MC-4R128FKE8S-840 [ELPIDA]
Direct Rambus DRAM SO-RIMM Module 128M-BYTE (64M-WORD x 18-BIT); 直接Rambus DRAM SO- RIMM模块128M字节（ 64M -字×18位）
| 型号： | MC-4R128FKE8S-840 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | Direct Rambus DRAM SO-RIMM Module 128M-BYTE (64M-WORD x 18-BIT) |
| 文件： | 总14页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R128FKE8S-840
Direct Rambus DRAM SO-RIMMTM Module
128M-BYTE (64M-WORD x 18-BIT)
Description
The Direct Rambus SO-RIMM module is a general-purpose high-performance memory module subsystem suitable
for use in a broad range of applications including computer memory, mobile personal computers, networking
systems, and other applications where high bandwidth and low latency are required.
MC-4R128FKE8S modules consists of four 288M Direct Rambus DRAM (Direct RDRAM) devices (µPD488588).
These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits 800MHz transfer rates while using conventional system and board design
technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per 16 bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield high bus efficiency. The Direct RDRAM's multi-bank architecture supports up to four simultaneous
transactions per device.
Features
• 160 edge connector pads with 0.65mm pad spacing
• 128 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 128 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0258N20 (Ver. 2.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4R128FKE8S-840
Order information
Part number
Organization I/O Freq. RAS access time
Package
Mounted devices
MHz
ns
160 edge connector pads
SO-RIMM with heat spreader
Edge connector: Gold plated
4 pieces of µPD488588FF
FBGA (µBGA ) package
MC-4R128FKE8S - 840
64M x 18
800
40
2
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Module Pad Configuration
GND
LDQA8
GND
LDQA6
GND
LDQA4
GND
LDQA2
GND
LDQA0
GND
LCTM
GND
LCTMN
GND
LROW1
GND
LCOL4
GND
LCOL2
GND
LCOL0
GND
LDQB0
GND
LDQB2
GND
LDQB4
GND
LDQB6
GND
B1
B2
GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB1
GND
LDQB3
GND
LDQB5
GND
LDQB7
GND
LDQB8
GND
A1
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
LSCK
GND
LCMD
GND
SIN
SOUT
V
DD
V
DD
NC
GND
NC
NC
GND
NC
LCFM, LCFMN,
V
CMOS
V
CMOS
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
NC
NC
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
LROW2 - LROW0,
Side B
Side A
NC
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
NC
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
V
REF
V
REF
SCL
SA0
V
DD
V
DD
SDA
DD
SA1
DD
RCOL4 - RCOL0 : Column bus
LDQA8 - LDQA0,
V
V
SWP
SVDD
GND
RSCK
GND
RDQB8
GND
RDQB7
GND
RDQB5
GND
RDQB3
GND
RDQB1
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
GND
RCMD
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL0
GND
RCOL2
GND
RCOL4
GND
RROW1
GND
RCTMN
GND
RCTM
GND
RDQA0
GND
RDQA2
GND
RDQA4
GND
RDQA6
GND
RDQA8
GND
RDQA8 - RDQA0 : Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0 : Data bus B
LSCK, RSCK : Clock input
SA0, SA1
SCL, SDA
: Serial Presence Detect Address
: Serial Presence Detect Clock
SIN, SOUT : Serial I/O
SVDD
SWP
VCMOS
VDD
: SPD Voltage
: Serial Presence Detect Write Protect
: Supply voltage for serial pads
: Supply voltage
VREF
GND
NC
: Logic threshold
RDQA5
GND
RDQA7
GND
: Ground reference
: These pads are not connected
3
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Module Pad Names
Pad
A1
Signal Name
Pad
B1
Signal Name
GND
Pad
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
Signal Name
NC
Pad
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
Signal Name
NC
GND
LDQA8
GND
A2
B2
LDQA7
GND
VREF
VREF
A3
B3
SCL
SA0
A4
LDQA6
GND
B4
LDQA5
GND
VDD
VDD
A5
B5
SDA
SA1
A6
LDQA4
GND
B6
LDQA3
GND
VDD
VDD
A7
B7
SVDD
SWP
A8
LDQA2
GND
B8
LDQA1
GND
GND
GND
A9
B9
RSCK
GND
RCMD
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
LDQA0
GND
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
LCFM
GND
RDQB8
GND
RDQB6
GND
LCTM
GND
LCFMN
GND
RDQB7
GND
RDQB4
GND
LCTMN
GND
LROW2
GND
RDQB5
GND
RDQB2
GND
LROW1
GND
LROW0
GND
RDQB3
GND
RDQB0
GND
LCOL4
GND
LCOL3
GND
RDQB1
GND
RCOL0
GND
LCOL2
GND
LCOL1
GND
RCOL1
GND
RCOL2
GND
LCOL0
GND
LDQB1
GND
RCOL3
GND
RCOL4
GND
LDQB0
GND
LDQB3
GND
RROW0
GND
RROW1
GND
LDQB2
GND
LDQB5
GND
RROW2
GND
RCTMN
GND
LDQB4
GND
LDQB7
GND
RCFMN
GND
RCTM
GND
LDQB6
GND
LDQB8
GND
RCFM
GND
RDQA0
GND
LSCK
GND
LCMD
GND
RDQA1
GND
RDQA2
GND
SOUT
VDD
SIN
VDD
RDQA3
GND
RDQA4
GND
NC
NC
GND
GND
RDQA5
GND
RDQA6
GND
NC
NC
VCMOS
NC
VCMOS
NC
RDQA7
GND
RDQA8
GND
4
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Module Connector Pad Description
(1/2)
Signal
I/O
–
Type
–
Description
GND
Ground reference for RDRAM core and interface.
LCFM
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN
I
RSL
VCMOS
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD
I
Serial Command used to read from and write to the control registers. Also used
for power management.
LCOL4..LCOL0
LCTM
I
I
Column bus. 5-bit bus containing control and address information for column
accesses.
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
LCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
LDQA8..LDQA0
LDQB8..LDQB0
I/O
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
RSL
LROW2..LROW0
LSCK
I
I
RSL
VCMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
NC
–
–
These pads are not connected. These 8 connector pads are reserved for future
use.
RCFM
I
RSL
RSL
VCMOS
RSL
RSL
RSL
RSL
RSL
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN
I
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
RCMD
I
Serial Command Input used to read from and write to the control registers. Also
used for power management.
RCOL4..RCOL0
RCTM
I
Column bus. 5-bit bus containing control and address information for column
accesses.
I
I
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RCTMN
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
RDQA8..RDQA0
RDQB8..RDQB0
RROW2..RROW0
I/O
I/O
I
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
5
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
(2/2)
Signal
I/O
I
Type
Description
RSCK
VCMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
SA0
SA1
SCL
SDA
SIN
I
I
SVDD
SVDD
SVDD
SVDD
VCMOS
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
I
Serial Presence Detect Clock.
I/O
I/O
Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control registers. Attaches to SIO0
of the first RDRAM on the module.
SOUT
I/O
VCMOS
Serial I/O for reading from and writing to the control registers. Attaches to SIO1
of the last RDRAM on the module.
SVDD
SWP
—
I
—
SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.
SVDD
Serial Presence Detect Write Protect (active high). When low, the SPD can be
written as well as read.
VCMOS
VDD
—
—
—
—
—
—
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
VREF
6
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Block Diagram
SIO 0
SIO 1
SCK
U1
CMD
V
REF
SIO 0
SIO 1
SCK
U2
CMD
V
REF
SIO 0
SIO 1
SCK
U3
CMD
V
REF
SIO 0
SIO 1
SCK
U4
CMD
V
REF
SVDD
V
CC
SCL
SCL
SDA
A2
SDA
U0
SWP
WP
A0
A1
47kΩ
SA0 SA1 SA2
SERIAL PD
Remarks 1. Rambus Channel signals form a loop through the SO-RIMM module, with the exception of the SIO
chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
7
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Electrical Specification
Absolute Maximum Ratings
Symbol
Parameter
MIN.
−0.3
−0.5
−50
MAX.
VDD + 0.3
VDD + 1.0
+100
Unit
V
VI,ABS
Voltage applied to any RSL or CMOS signal pad with respect to GND
Voltage on VDD with respect to GND
VDD,ABS
TSTORE
V
Storage temperature
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol
VDD
Parameter and conditions
Supply voltage
MIN.
2.50 − 0.13
VDD
MAX.
2.50 + 0.13
VDD
Unit
V
VCMOS
CMOS I/O power supply at pad
2.5V controllers
1.8V controllers
V
1.8 − 0.1
1.4 − 0.2
2.2
1.8 + 0.2
1.4 + 0.2
3.6
VREF
Reference voltage
V
V
VSPD
Serial presence detector-positive power supply
RSL input low voltage
VIL
VREF − 0.5
VREF + 0.2
−0.3
VREF − 0.2
VREF + 0.5
0.5VCMOS − 0.25
VCMOS + 0.3
0.3
V
VIH
RSL input high voltage
V
VIL,CMOS
VIH,CMOS
VOL,CMOS
VOH,CMOS
IREF
CMOS input low voltage
V
CMOS input high voltage
0.5VCMOS+0.25
—
V
CMOS output low voltage, IOL,CMOS = 1 mA
CMOS output high voltage, IOH,CMOS = −0.25 mA
VREF current, VREF,MAX
V
—
VCMOS − 0.3
−40.0
V
+40.0
µA
µA
µA
ISCK,CMD
ISIN,SOUT
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
−40.0
+40.0
−10.0
+10.0
8
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
25.2
23.8
TYP.
28.0
28.0
MAX.
30.8
32.2
1.06
Unit
Z
Module Impedance of RSL signals
Ω
Module Impedance of SCK and CMD signals
TPD
Average clock delay from finger to finger of all RSL clock nets
(CTM, CTMN,CFM, and CFMN)
ns
∆TPD
Propagation delay variation of RSL signals with respect to TPD Note1,2
-21
+21
ps
ps
∆TPD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay Note1
-250
+250
∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal
-200
+200
12.0
2.0
ps
%
%
%
Ω
Vα/VIN
VXF/VIN
VXB/VIN
RDC
Attenuation Limit
-840
-840
-840
-840
Forward crosstalk coefficient
Backward crosstalk coefficient
DC Resistance Limit
1.5
0.9
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the SO-RIMM module meets the following specification, then it is compliant to the specification.
If the SO-RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Adjusted ∆TPD Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
ps
MIN.
-30
MAX.
∆TPD
Propagation delay variation of RSL signals with respect to TPD +/− [17+(18*N*∆Z0)] Note
+30
Note N = Number of RDRAM devices installed on the SO-RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
9
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
SO-RIMM Module Current Profile
RIMM module power conditions Note1
IDD
MAX.
717.6
975
Unit
mA
mA
mA
mA
mA
mA
One RDRAM in Read Note2, balance in NAP mode
One RDRAM in Read Note2, balance in Standby mode
One RDRAM in Read Note2, balance in Active mode
One RDRAM in Write, balance in NAP mode
One RDRAM in Write, balance in Standby mode
One RDRAM in Write, balance in Active mode
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
-840
-840
-840
-840
-840
-840
1110
777.6
1035
1170
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
patterns. Power does not include Refresh Current.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA or 290
mA for x18 ECC module for the following : VDD = 2.5 V, VTERM = 1.8 V, VREF = 1.4 V and VDIL = VREF − 0.5 V.
10
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Package Drawings
160 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
EEPROM
A (AREA B)
288M Direct RDRAM x 4
R
M1 (AREA B)
P
S
O
N
M
G
Q
M2 (AREA A)
T
L
A
D
E
F
B
C
A1 (AREA A)
K
H
I
J
ITEM MILLIMETERS
A
67.60 TYP.
67.60 ± 0.15
30.00
A1
B
B1
C
C1
D
E
0.75 ± 0.10
4.00
4.00 ± 0.10
25.35
13.60
F
25.35
G
H
I
1.65
21.00
17.00
detail of A part
W
J
21.00
K
4.30
C1
L
0.65 TYP.
31.25 ± 0.15
8.75
R0.75
M
M1
M2
N
O
P
22.50
29.25
Y
B1
Z
20.00
X
5.00 ± 0.10
R1.00
Q
R
S
1.00 ± 0.10
φ2.00
T
1.0 ± 0.10
0.43 ± 0.03
2.55 MIN.
0.25 MAX.
1.50 ± 0.10
W
X
Y
Z
ECA-TS2-0034-02
11
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
160 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)
B
E
F
Pad A1
Pad A80
C
C
G
H
D
A1
DESCRIPTION
ITEM
A1
MIN.
TYP.
MAX.
67.75
UNIT
mm
PCB length
67.45
67.60
PCB height
B
C
D
E
F
31.10
31.25
25.35
30.00
20.00
1.00
31.40
mm
mm
mm
mm
mm
mm
mm
Center-center pad width from pad A1 to A40,
A41 to A80, B1 to B40 or B41 to B80
-
-
Spacing from PCB left edge to connector key notch
-
-
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
-
-
0.90
1.10
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
G
H
-
-
1.35
-
-
RIMM thickness
2.35
ECA-TS2-0034-02
12
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
13
Data Sheet E0258N20 (Ver. 2.0)
MC-4R128FKE8S-840
Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.
RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc.
µBGA is a registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
14
Data Sheet E0258N20 (Ver. 2.0)
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