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MC-458CB642XS-A75 [ELPIDA]

8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM); 8M - WORD 64位同步动态内存模块（ SO DIMM ）
MC-458CB642XS-A75
型号： MC-458CB642XS-A75
厂家： ELPIDA MEMORY    ELPIDA MEMORY
描述：

8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
8M - WORD 64位同步动态内存模块（ SO DIMM ）

存储 内存集成电路 动态存储器 时钟
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中文：  中文翻译
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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-458CB642XS  
8M-WORD BY 64-BIT  
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)  
Description  
The MC-458CB642XS is 8,388,608 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on  
which 4 pieces of 128M SDRAM: µPD45128163 are assembled.  
This module provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 8,388,608 words by 64 bits organization  
• Clock frequency and access time from CLK  
Part number  
/CAS latency  
CL = 3  
Clock frequency (MAX.)  
133 MHz  
Access time from CLK (MAX.)  
MC-458CB642XS-A75  
5.4 ns  
6 ns  
CL = 2  
100 MHz  
MC-458CB642XS-A75L  
CL = 3  
133 MHz  
5.4 ns  
6 ns  
CL = 2  
100 MHz  
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
• Pulsed interface  
• Possible to assert random column address in every cycle  
• Quad internal banks controlled by BA0, BA1 (Bank Select)  
• Programmable burst-length: 1, 2, 4, 8 and Full Page  
• Programmable wrap sequence (Sequential / Interleave)  
• Programmable /CAS latency (2, 3)  
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
• Single 3.3V ± 0.3V power supply  
• LVTTL compatible  
• 4,096 refresh cycles/64 ms  
• Burst termination by Burst Stop command and Precharge command  
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)  
• Unbuffered type  
• Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0115N20 (Ver. 2.0)  
Date Published September 2001 (K)  
Printed in Japan  
This product became EOL in March, 2004.  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  
MC-458CB642XS  
Ordering Information  
Part number  
Clock frequency  
MHz (MAX.)  
Package  
Mounted devices  
MC-458CB642XS-A75  
MC-458CB642XS-A75L  
133 MHz  
144-pin Small Outline DIMM  
(Socket Type)  
4 pieces of µPD45128163G5 (Rev. X)  
(10.16 mm (400) TSOP (II))  
133 MHz  
Edge connector: Gold plated  
25.4 mm height  
Data Sheet E0115N20  
2
MC-458CB642XS  
Pin Configuration  
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)  
2
4
Vss  
Vss  
DQ 0  
DQ 1  
DQ 2  
DQ 3  
1
DQ 32  
DQ 33  
DQ 34  
DQ 35  
Vcc  
3
/xxx indicates active low signal.  
6
5
8
7
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
9
VCC  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
DQ 36  
DQ 37  
DQ 38  
DQ 39  
Vss  
DQ 4  
DQ 5  
DQ 6  
DQ 7  
Vss  
DQMB4  
DQMB5  
Vcc  
DQMB0  
DQMB1  
V
CC  
A3  
A0  
A1  
A4  
A5  
A2  
Vss  
Vss  
DQ 40  
DQ 41  
DQ 42  
DQ 43  
Vcc  
DQ 8  
DQ 9  
DQ 10  
DQ 11  
V
CC  
DQ 44  
DQ 45  
DQ 46  
DQ 47  
Vss  
NC  
NC  
DQ 12  
DQ 13  
DQ 14  
DQ 15  
Vss  
NC  
NC  
62  
64  
CKE0  
Vcc  
CLK0  
Vcc  
/RAS  
/WE  
/CS0  
NC  
61  
63  
66  
/CAS  
NC  
65  
68  
67  
70  
NC  
NC  
69  
72  
71  
74  
CLK1  
Vss  
NC  
73  
A0 - A11  
: Address Inputs  
76  
Vss  
NC  
75  
78  
NC  
77  
[Row: A0 - A11, Column: A0 - A8]  
80  
NC  
NC  
79  
82  
Vcc  
VCC  
81  
BA0 (A13), BA1 (A12) : SDRAM Bank Select  
84  
DQ 48  
DQ 49  
DQ 50  
DQ 51  
Vss  
DQ 16  
DQ 17  
DQ 18  
DQ 19  
Vss  
83  
86  
85  
88  
87  
DQ0 - DQ63  
CLK0, CLK1  
CKE0  
: Data Inputs/Outputs  
: Clock Input  
90  
89  
92  
91  
94  
DQ 52  
DQ 53  
DQ 54  
DQ 55  
Vcc  
DQ 20  
DQ 21  
DQ 22  
DQ 23  
Vcc  
93  
96  
95  
98  
97  
: Clock Enable Input  
: Chip Select Input  
: Row Address Strobe  
: Column Address Strobe  
: Write Enable  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
99  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
/CS0  
A7  
A6  
BA0 (A13)  
Vss  
A8  
/RAS  
Vss  
BA1 (A12)  
A11  
A9  
A10  
/CAS  
Vcc  
Vcc  
DQMB6  
DQMB7  
Vss  
DQMB2  
DQMB3  
Vss  
/WE  
DQ 56  
DQ 57  
DQ 58  
DQ 59  
Vcc  
DQ 60  
DQ 61  
DQ 62  
DQ 63  
Vss  
SCL  
Vcc  
DQ 24  
DQ 25  
DQ 26  
DQ 27  
DQMB0 - DQMB7 : DQ Mask Enable  
SDA  
SCL  
VCC  
VSS  
: Serial Data I/O for PD  
: Clock Input for PD  
: Power Supply  
: Ground  
VCC  
DQ 28  
DQ 29  
DQ 30  
DQ 31  
Vss  
SDA  
VCC  
NC  
: No Connection  
Data Sheet E0115N20  
3
MC-458CB642XS  
Block Diagram  
/WE  
/CS0  
/CS  
/WE  
/WE  
/CS  
LDQM  
DQ 0  
LDQM  
DQ 0  
DQMB0  
DQMB4  
DQ 32  
DQ 0  
DQ 33  
DQ 34  
DQ 35  
DQ 36  
DQ 37  
DQ 38  
DQ 39  
DQ 1  
DQ 2  
DQ 3  
DQ 4  
DQ 5  
DQ 6  
DQ 7  
DQ 1  
DQ 1  
DQ 2  
DQ 2  
DQ 3  
DQ 3  
DQ 4  
DQ 4  
DQ 5  
DQ 5  
DQ 6  
DQ 6  
D0  
D2  
DQ 7  
DQ 7  
UDQM  
DQ 15  
DQ 14  
DQ 13  
DQ 12  
DQ 11  
DQ 10  
DQ 9  
UDQM  
DQ 15  
DQ 14  
DQ 13  
DQ 12  
DQ 11  
DQ 10  
DQ 9  
DQMB1  
DQMB5  
DQ 40  
DQ 41  
DQ 42  
DQ 43  
DQ 44  
DQ 45  
DQ 46  
DQ 47  
DQ 8  
DQ 9  
DQ 10  
DQ 11  
DQ 12  
DQ 13  
DQ 14  
DQ 15  
DQ 8  
DQ 8  
/CS  
/WE  
/WE  
/CS  
LDQM  
DQ 7  
LDQM  
DQ 7  
DQMB2  
DQMB6  
DQ 16  
DQ 17  
DQ 18  
DQ 19  
DQ 20  
DQ 21  
DQ 22  
DQ 23  
DQ 48  
DQ 49  
DQ 50  
DQ 51  
DQ 52  
DQ 53  
DQ 54  
DQ 55  
DQ 6  
DQ 6  
DQ 5  
DQ 5  
DQ 4  
DQ 4  
DQ 3  
DQ 3  
DQ 2  
DQ 2  
DQ 1  
DQ 1  
D1  
D3  
DQ 0  
DQ 0  
DQMB3  
UDQM  
DQ 8  
DQMB7  
UDQM  
DQ 8  
DQ 56  
DQ 57  
DQ 58  
DQ 59  
DQ 60  
DQ 61  
DQ 62  
DQ 63  
DQ 24  
DQ 25  
DQ 26  
DQ 27  
DQ 28  
DQ 29  
DQ 30  
DQ 31  
DQ 9  
DQ 9  
DQ 10  
DQ 11  
DQ 12  
DQ 13  
DQ 14  
DQ 15  
DQ 10  
DQ 11  
DQ 12  
DQ 13  
DQ 14  
DQ 15  
SERIAL PD  
V
CC  
D0 - D3  
D0 - D3  
C
V
SS  
SCL  
SDA  
10 Ω  
A0 A1 A2  
CLK1  
CLK0  
CLK : D0 - D3  
10 pF  
/RAS  
/CAS  
CKE0  
/RAS : D0 - D3  
/CAS : D0 - D3  
CKE : D0 - D3  
A0 - A11  
BA0  
A0 - A11 : D0 - D3  
A13 : D0 - D3  
BA1  
A12 : D0 - D3  
Remarks 1. D0 - D3: µPD45128163 (2M words x 16 bits x 4 banks)  
2. The value of all resistors is 10 Ω.  
Data Sheet E0115N20  
4
MC-458CB642XS  
Electrical Specifications  
• All voltages are referenced to VSS (GND).  
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper  
device operation is achieved.  
Absolute Maximum Ratings  
Parameter  
Voltage on power supply pin relative to GND  
Voltage on input pin relative to GND  
Short circuit output current  
Symbol  
VCC  
VT  
Condition  
Rating  
–0.5 to +4.6  
–0.5 to +4.6  
50  
Unit  
V
V
IO  
mA  
W
Power dissipation  
PD  
4
Operating ambient temperature  
Storage temperature  
TA  
0 to 70  
°C  
°C  
Tstg  
–55 to +125  
Caution  
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification. Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
Recommended Operating Conditions  
Parameter  
Supply voltage  
Symbol  
VCC  
VIH  
Condition  
MIN.  
3.0  
2.0  
–0.3  
0
TYP.  
3.3  
MAX.  
3.6  
Unit  
V
High level input voltage  
Low level input voltage  
Operating ambient temperature  
VCC + 0.3  
+0.8  
V
VIL  
V
TA  
70  
°C  
Capacitance (TA = 25 °C, f = 1 MHz)  
Parameter  
Symbol  
CI1  
Test condition  
MIN.  
15  
TYP.  
MAX.  
30  
Unit  
pF  
Input capacitance  
A0 - A11, BA0 (A13), BA1 (A12),  
/RAS, /CAS, /WE  
CLK0  
CI2  
CI3  
CI4  
CI5  
CI/O  
23  
15  
15  
5
37  
26  
26  
10  
12  
CKE0  
/CS0  
DQMB0 - DQMB7  
DQ0 - DQ63  
Data input/output capacitance  
5
pF  
Data Sheet E0115N20  
5
MC-458CB642XS  
DC Characteristics (Recommended Operating Conditions unless otherwise noted)  
Parameter  
Operating current  
Symbol  
Test condition  
MIN.  
MAX.  
440  
460  
4
Unit Notes  
ICC1  
Burst length = 1, tRC ≥ tRC (MIN.)  
/CAS latency = 2  
/CAS latency = 3  
mA  
mA  
mA  
1
Precharge standby current in  
power down mode  
ICC2P  
CKE ≤ VIL (MAX.), tCK = 15 ns  
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞  
ICC2N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),  
4
Precharge standby current in  
non power down mode  
80  
Input signals are changed one time during 30 ns.  
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.  
ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns  
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞  
ICC3N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),  
32  
20  
Active standby current in  
power down mode  
mA  
mA  
16  
Active standby current in  
non power down mode  
120  
Input signals are changed one time during 30 ns.  
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.  
80  
580  
740  
920  
960  
8
Operating current  
(Burst mode)  
ICC4  
ICC5  
ICC6  
tCK ≥ tCK (MIN.), IO = 0 mA  
/CAS latency = 2  
/CAS latency = 3  
/CAS latency = 2  
/CAS latency = 3  
-**  
mA  
mA  
2
3
CBR (Auto) refresh current  
tRC ≥ tRC (MIN.)  
Self refresh current  
CKE ≤ 0.2 V  
mA  
mA  
µA  
µA  
V
-**L  
3.2  
+4  
Input leakage current  
Output leakage current  
High level output voltage  
Low level output voltage  
II(L)  
IO(L)  
VOH  
VOL  
VI = 0 to 3.6 V, All other pins not under test = 0 V  
DOUT is disabled, VO = 0 to 3.6 V  
IO = –4.0 mA  
– 4  
–1.5  
2.4  
+1.5  
IO = +4.0 mA  
0.4  
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In  
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).  
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In  
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).  
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).  
Data Sheet E0115N20  
6
MC-458CB642XS  
AC Characteristics (Recommended Operating Conditions unless otherwise noted)  
Test Conditions  
Parameter  
Value  
2.4 / 0.4  
1.4  
Unit  
V
AC high level input voltage / low level input voltage  
Input timing measurement reference level  
Transition time (Input rise and fall time)  
Output timing measurement reference level  
V
1
ns  
V
1.4  
t
CK  
t
CH  
t
CL  
2.4 V  
CLK  
1.4 V  
0.4 V  
t
SETUP  
t
HOLD  
2.4 V  
1.4 V  
0.4 V  
Input  
t
AC  
t
OH  
Output  
Data Sheet E0115N20  
7
MC-458CB642XS  
Synchronous Characteristics  
Parameter  
Symbol  
-A75  
Unit  
Note  
MIN.  
7.5  
MAX.  
(133 MHz)  
(100 MHz)  
5.4  
Clock cycle time  
/CAS latency = 3  
/CAS latency = 2  
/CAS latency = 3  
/CAS latency = 2  
tCK3  
tCK2  
tAC3  
tAC2  
tCH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
Access time from CLK  
1
1
6
CLK high level width  
CLK low level width  
Data-out hold time  
2.5  
2.5  
3
tCL  
/CAS latency = 3  
/CAS latency = 2  
tOH3  
tOH2  
tLZ  
1
1
3
Data-out low-impedance time  
Data-out high-impedance time  
0
/CAS latency = 3  
/CAS latency = 2  
tHZ3  
tHZ2  
tDS  
3
5.4  
6
3
Data-in setup time  
Data-in hold time  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
1.5  
tDH  
Address setup time  
Address hold time  
CKE setup time  
tAS  
tAH  
tCKS  
tCKH  
tCKSP  
tCMS  
CKE hold time  
CKE setup time (Power down exit)  
Command (/CS0, /RAS, /CAS, /WE,  
DQMB0 - DQMB7) setup time  
Command (/CS0, /RAS, /CAS, /WE,  
DQMB0 - DQMB7) hold time  
tCMH  
0.8  
ns  
Note 1. Output load  
Z = 50 Ω  
Output  
50 pF  
Remark These specifications are applied to the monolithic device.  
Data Sheet E0115N20  
8
MC-458CB642XS  
Asynchronous Characteristics  
Parameter  
Symbol  
-A75  
Unit  
Note  
MIN.  
MAX.  
ACT to REF/ACT command period (Operation)  
REF to REF/ACT command period (Refresh)  
ACT to PRE command period  
tRC  
tRC1  
tRAS  
tRP  
67.5  
ns  
ns  
67.5  
45  
120,000  
ns  
PRE to ACT command period  
20  
ns  
Delay time ACT to READ/WRITE command  
ACT (one) to ACT (another) command period  
tRCD  
tRRD  
tDPL3  
tDPL2  
tDAL3  
tDAL2  
tRSC  
tT  
20  
ns  
15  
ns  
Data-in to PRE command  
period  
/CAS latency = 3  
/CAS latency = 2  
8
ns  
8
1CLK+22.5  
1CLK+20  
2
ns  
Data-in to ACT (REF) command /CAS latency = 3  
ns  
1
period (Auto precharge)  
Mode register set cycle time  
Transition time  
/CAS latency = 2  
ns  
CLK  
ns  
0.5  
30  
64  
Refresh time (4,096 refresh cycles)  
tREF  
ms  
Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.  
Data Sheet E0115N20  
9
MC-458CB642XS  
Serial PD  
Byte No.  
0
(1/2)  
Function Described  
Hex  
80H  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0  
Notes  
Defines the number of bytes written into  
serial PD memory  
1
0
0
0
0
0
0
0
128 bytes  
1
2
Total number of bytes of serial PD memory  
Fundamental memory type  
Number of rows  
08H  
04H  
0CH  
09H  
01H  
40H  
00H  
01H  
75H  
54H  
00H  
80H  
10H  
00H  
01H  
8FH  
04H  
06H  
01H  
01H  
00H  
0EH  
A0H  
60H  
00H  
14H  
0FH  
14H  
2DH  
10H  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
0
0
256 bytes  
SDRAM  
12 rows  
9 columns  
1 bank  
64 bits  
0
3
4
Number of columns  
5
Number of banks  
6
Data width  
7
Data width (continued)  
Voltage interface  
8
LVTTL  
7.5 ns  
5.4 ns  
None  
9
CL = 3 Cycle time  
-A75  
-A75  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25-26  
27  
28  
29  
30  
31  
CL = 3 Access time  
DIMM configuration type  
Refresh rate/type  
Normal  
×16  
SDRAM width  
Error checking SDRAM width  
Minimum clock delay  
Burst length supported  
None  
1 clock  
1, 2, 4, 8, F  
4 banks  
2, 3  
Number of banks on each SDRAM  
/CAS latency supported  
/CS latency supported  
0
/WE latency supported  
0
SDRAM module attributes  
SDRAM device attributes: General  
CL = 2 Cycle time  
CL = 2 Access time  
-A75  
10 ns  
6 ns  
-A75  
tRP (MIN.)  
-A75  
-A75  
-A75  
-A75  
20 ns  
tRRD (MIN.)  
15 ns  
tRCD (MIN.)  
20 ns  
tRAS (MIN.)  
45 ns  
Module bank density  
64M bytes  
Data Sheet E0115N20  
10  
MC-458CB642XS  
(2/2)  
Byte No.  
32  
Function Described  
Command and address  
Hex  
15H  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0  
Notes  
1.5 ns  
-A75  
-A75  
0
0
0
1
0
1
0
1
signal setup time  
33  
Command and address  
signal hold time  
08H  
0
0
0
0
1
0
0
0
0.8 ns  
34  
35  
Data signal input setup time  
Data signal input hold time  
-A75  
-A75  
15H  
08H  
00H  
12H  
A6H  
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1.5 ns  
0.8 ns  
36-61  
62  
SPD revision  
-A75  
-A75  
1.2 A  
63  
Checksum for bytes 0 - 62  
Manufacture’s JEDEC ID code  
Manufacturing location  
Manufacture’s P/N  
64-71  
72  
73-90  
91-92  
93-94  
95-98  
Revision code  
Manufacturing date  
Assembly serial number  
99-125 Mfg specific  
126  
127  
Intel specification frequency  
-A75  
-A75  
64H  
87H  
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
Intel specification /CAS  
latency support  
Timing Chart  
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).  
Data Sheet E0115N20  
11  
MC-458CB642XS  
Package Drawing  
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)  
A (AREA B)  
Y
M1 (AREA B)  
N
R
Q
L
M
M2 (AREA A)  
S
A
H
(OPTIONAL HOLES)  
U1  
U2  
C
B
T
I
E
D
A1 (AREA A)  
F
ITEM MILLIMETERS  
A
A1  
B
67.6  
67.6±0.15  
23.2  
C
29.0  
D
D1  
D2  
E
4.6  
detail of A part  
1.5±0.10  
4.0  
32.8  
D2  
W
F
3.7  
H
0.8 (T.P.)  
3.3  
I
L
20.0  
M
M1  
M2  
N
25.4±0.15  
3.4  
D1  
X
V
22.0  
3.8 MAX.  
R2.0  
Q
R
S
4.0±0.10  
φ
1.8  
T
1.0±0.1  
U1  
U2  
V
3.2 MIN.  
4.0 MIN.  
0.25 MAX.  
0.6±0.05  
2.55 MIN.  
2.0 MIN.  
W
X
Y
Data Sheet E0115N20  
12  
MC-458CB642XS  
CAUTION FOR HANDLING MEMORY MODULES  
When handling or inserting memory modules, be sure not to touch any components on the modules, such as  
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these  
components to prevent damaging them.  
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact  
with other modules may cause excessive mechanical stress, which may damage the modules.  
MDE0107  
NOTES FOR CMOS DEVICES  
1
PRECAUTION AGAINST ESD FOR MOS DEVICES  
Exposing the MOS devices to a strong electric field can cause destruction of the gate  
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop  
generation of static electricity as much as possible, and quickly dissipate it, when once  
it has occurred. Environmental control must be adequate. When it is dry, humidifier  
should be used. It is recommended to avoid using insulators that easily build static  
electricity. MOS devices must be stored and transported in an anti-static container,  
static shielding bag or conductive material. All test and measurement tools including  
work bench and floor should be grounded. The operator should be grounded using  
wrist strap. MOS devices must not be touched with bare hands. Similar precautions  
need to be taken for PW boards with semiconductor MOS devices on it.  
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES  
No connection for CMOS devices input pins can be a cause of malfunction. If no  
connection is provided to the input pins, it is possible that an internal input level may be  
generated due to noise, etc., hence causing malfunction. CMOS devices behave  
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed  
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected  
to VDD or GND with a resistor, if it is considered to have a possibility of being an output  
pin. The unused pins must be handled in accordance with the related specifications.  
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Power-on does not necessarily define initial status of MOS devices. Production process  
of MOS does not define the initial operation status of the device. Immediately after the  
power source is turned ON, the MOS devices with reset function have not yet been  
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or  
contents of registers. MOS devices are not initialized until the reset signal is received.  
Reset operation must be executed immediately after power-on for MOS devices having  
reset function.  
CME0107  
Data Sheet E0115N20  
13  
MC-458CB642XS  
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.  
No part of this document may be copied or reproduced in any form or by any means without the prior  
written consent of Elpida Memory, Inc.  
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights  
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or  
third parties by or arising from the use of the products or information listed in this document. No license,  
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property  
rights of Elpida Memory, Inc. or others.  
Descriptions of circuits, software and other related information in this document are provided for  
illustrative purposes in semiconductor product operation and application examples. The incorporation of  
these circuits, software and information in the design of the customer's equipment shall be done under  
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses  
incurred by customers or third parties arising from the use of these circuits, software and information.  
[Product applications]  
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.  
However, users are instructed to contact Elpida Memory's sales office before using the product in  
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,  
medical equipment for life support, or other such application in which especially high quality and  
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk  
of bodily injury.  
[Product usage]  
Design your application so that the product is used within the ranges and conditions guaranteed by  
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation  
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no  
responsibility for failure or damage when the product is used beyond the guaranteed ranges and  
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure  
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so  
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other  
consequential damage due to the operation of the Elpida Memory, Inc. product.  
[Usage environment]  
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be  
used in a non-condensing environment.  
If you export the products or technology described in this document that are controlled by the Foreign  
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance  
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by  
U.S. export control regulations, or another country's export control laws or regulations, you must follow  
the necessary procedures in accordance with such laws or regulations.  
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted  
license to use these products, that third party must be made aware that they are responsible for  
compliance with the relevant laws and regulations.  
M01E0107  

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