MC-4532CD647 [ELPIDA]
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE; 32M - WORD 64位的同步动态RAM模块UNBUFFERED TYPE
| 型号： | MC-4532CD647 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| 文件： | 总16页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CD647
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-4532CD647EF, MC-4532CD647PF and MC-4532CD647XF are 33,554,432 words by 64 bits synchronous
dynamic RAM module on which 16 pieces of 128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 64 bits organization
• Clock frequency and access time from CLK.
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
MC-4532CD647EF-A75
MC-4532CD647PF-A75
MC-4532CD647XF-A75
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
133 MHz
100 MHz
133 MHz
100 MHz
133 MHz
100 MHz
5.4 ns
6.0 ns
5.4 ns
6.0 ns
5.4 ns
6.0 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0054N20 (Ver. 2.0)
Date Published March 2001 CP (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532CD647
Ordering Information
Part number
Clock frequency
(MAX.)
Package
Mounted devices
MC-4532CD647EF-A75
MC-4532CD647PF-A75
MC-4532CD647XF-A75
133 MHz
168-pin Dual In-line Memory Module
(Socket Type)
16 pieces of µPD45128841G5 (Rev. E)
(10.16 mm (400) TSOP (II))
Edge connector: Gold plated
34.93 mm height
16 pieces of µPD45128841G5 (Rev. P)
(10.16 mm (400) TSOP (II))
16 pieces of µPD45128841G5 (Rev. X)
(10.16 mm (400) TSOP (II))
Data Sheet E0054N20
2
MC-4532CD647
Pin Configuration
168-pin Dual In-line MemoryModule Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
V
SS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
NC
DQ14
DQ15
NC
NC
NC
V
SS
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
SS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A8
A9
A10
BA0(A13)
A11
Vcc
BA1 (A12)
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
V
SS
VSS
CKE0
/CS3
DQMB6
DQMB7
NC
NC
/CS2
DQMB2
DQMB3
NC
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9]
BA0 (A13), BA1 (A12)
Vcc
Vcc
NC
NC
NC
NC
NC
NC
: SDRAM Bank Select
NC
NC
V
SS
VSS
DQ0 - DQ63
CLK0 - CLK3
CKE0, CKE1
/CS0 - /CS3
/RAS
: Data Inputs/Outputs
: Clock Input
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
DQ52
NC
DQ20
NC
NC
NC
NC
CKE1
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
/CAS
V
SS
VSS
/WE
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
SDA
SCL
VCC
: Address Input for EEPROM
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
V
SS
V
SS
CLK2
NC
CLK3
NC
WP
SA0
SA1
SA2
Vcc
VSS
SDA
SCL
Vcc
WP
: Write Protect
NC
: No Connection
Data Sheet E0054N20
3
MC-4532CD647
Block Diagram
/WE
/CS0
/CS1
/CS2
/CS3
DQMB0
DQMB2
DQM
DQM /CS /WE
/CS
/CS
/CS
/CS
DQM /CS /WE
DQM
/CS
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D0
D2
D8
D10
DQMB3
DQMB1
DQM
DQM
/CS /WE
/CS /WE
DQM /CS
DQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 8
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 3
DQ 0
DQ 1
DQ 2
DQ 4
DQ 5
DQ 6
DQ 7
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
D1
D3
D9
D11
DQMB6
DQMB4
DQM
/CS /WE
DQM
DQM
/CS /WE
DQM /CS
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 3
DQ 0
DQ 1
DQ 2
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D4
D6
D12
D14
DQMB5
DQMB7
/CS
DQM /CS /WE
DQM
/WE
DQM
/CS
DQM
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 5
DQ 7
DQ 6
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 2
DQ 0
DQ 1
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D5
D7
D13
D15
CLK0
CLK2
CLK3
C
LK: D0, D1, D4, D5
C
LK: D2, D3, D6, D7
SERIAL PD
3.3 pF
3.3 pF
SDA
WP
47kΩ
SCL
A0
A1
A2
CLK1
C
LK: D10, D11, D14, D15
C
LK: D8, D9, D12, D13
3.3 pF
3.3 pF
SA0 SA1 SA2
A0 - A11
A0 - A11: D0 - D15
A13, A12: D0 - D15
10kΩ
/RAS
/CAS
CKE0
/RAS: D0 - D15
/CAS: D0 - D15
CKE: D0 - D7
CKE1
CKE: D8-D15
BA0, BA1
VCC
VSS
D0 - D15
D0 - D15
C
Remarks 1. The value of all resistors is 10 Ω except CKE1 and WP.
2. D0 - D15: µPD45128841 (4M words × 8 bits × 4 banks)
Data Sheet E0054N20
4
MC-4532CD647
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
16
Operating ambient temperature
Storage temperature
TA
0 to 70
°C
°C
Tstg
–55 to +125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
VCC + 0.3
+0.8
V
Low level input voltage
VIL
V
Operating ambient temperature
TA
70
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
56
TYP.
MAX.
94
Unit
pF
Input capacitance
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0 - CLK3
CKE0, CKE1
/CS0 - /CS3
20
28
15
5
40
52
29
17
19
DQMB0 - DQMB7
DQ0 - DQ63
Data input/output capacitance
7
pF
Data Sheet E0054N20
5
MC-4532CD647
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
ICC1
Test condition
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2
/CAS latency = 3
1,040 mA
1,080
1
Burst length = 1
tRC ≥ tRC(MIN.), IO = 0 mA
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
power down mode ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
Precharge standby current in ICC2N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
16
16
mA
320
mA
non power down mode
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞ Input signals are stable.
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
128
80
Active standby current in
power down mode
mA
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
64
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
480
320
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.)
IO = 0 mA
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
1,200 mA
1,480
2
3
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
2,080 mA
2,160
Self refresh current
ICC6
II(L)
CKE ≤ 0.2 V
32
– 16 + 16
mA
Input leakage current
VI = 0 to 3.6 V, All other pins not under test = 0 V
µA
CKE1 – 500 +500
Output leakage current
High level output voltage
Low level output voltage
IO(L)
VOH
VOL
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 3
2.4
+ 3
µA
V
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0054N20
6
MC-4532CD647
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Value
2.4 / 0.4
1.4
Unit
V
V
1
ns
V
Output timing measurement reference level
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
Data Sheet E0054N20
7
MC-4532CD647
Synchronous Characteristics
Parameter
Symbol
-A75
Unit
Note
MIN.
7.5
MAX.
(133 MHz)
(100 MHz)
5.4
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
tCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
Access time from CLK
1
1
6.0
CLK high level width
2.5
2.5
3.0
0
CLK low level width
tCL
Data-out hold time
tOH
tLZ
1
Data-out low-impedance time
Data-out high-impedance time
/CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3.0
3.0
1.5
0.8
1.5
0.8
1.5
0.8
5.4
6.0
Data-in setup time
Data-in hold time
tDH
Address setup time
Address hold time
CKE setup time
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
1.5
1.5
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
tCMH
0.8
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
ns
Note 1. Output load
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet E0054N20
8
MC-4532CD647
Asynchronous Characteristics
Parameter
Symbol
-A75
Unit
Note
MIN.
MAX.
ACT to REF/ACT command period (operation)
REF to REF/ACT command period (refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
67.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
67.5
45
120,000
PRE to ACT command period
20
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC 2
tT
20
15
8
Data-in to ACT(REF) command
period (Auto precharge)
/CAS latency = 3
/CAS latency = 2
1CLK+22.5
1CLK+20
CLK
1
1
Mode register set cycle time
Transition time
0.5
30
64
ns
Refresh time (4,096 refresh cycles)
tREF
ms
Note This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
Data Sheet E0054N20
9
MC-4532CD647
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
0
Defines the number of bytes written into 80H
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0AH
02H
40H
00H
01H
75H
54H
00H
80H
08H
00H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
60H
00H
14H
0FH
14H
2DH
20H
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
0
256 bytes
SDRAM
12 rows
10 columns
2 banks
64 bits
0
3
4
Number of columns
5
Number of banks
6
Data width
7
Data width (continued)
Voltage interface
8
LVTTL
7.5 ns
5.4 ns
None
9
CL = 3 Cycle time
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25-26
27
28
29
30
31
CL = 3 Access time
DIMM configuration type
Refresh rate/type
Normal
×8
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General
CL = 2 Cycle time
None
1 clock
1, 2, 4, 8, F
4 banks
2, 3
0
0
10 ns
6 ns
CL = 2 Access time
tRP(MIN.)
20 ns
tRRD(MIN.)
15 ns
tRCD(MIN.)
20 ns
tRAS(MIN.)
45 ns
Module bank density
128M bytes
Data Sheet E0054N20
10
MC-4532CD647
(2/2)
Byte No.
32
Function Described
Hex
15H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
1.5 ns
Command and address signal input setup
time
0
0
0
1
0
1
0
1
33
Command and address signal input
hold time
08H
0
0
0
0
1
0
0
0
0.8 ns
34
35
Data signal input setup time
Data signal input hold time
15H
08H
00H
12H
B0H
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1.5 ns
0.8 ns
36-61
62
SPD revision
1.2
63
Checksum for bytes 0 - 62
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
64H
FFH
0
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
Intel specification /CAS latency support
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0054N20
11
MC-4532CD647
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Z1
Z2
Y1
N
Y2
R2
F2
F1
Q
M
R1
L
B
A
S
H
(OPTIONAL HOLES)
U2
U1
J
K
C
T
B
E
I
G
D
A1 (AREA A)
M2 (AREA A)
ITEM MILLIMETERS
A
133.35
133.35±0.13
11.43
A1
B
C
36.83
D
6.35
D1
D2
E
2.0
3.125
54.61
2.44
M1 (AREA B)
F1
F2
G
3.18
6.35
detail of A part
W
detail of B part
D2
H
1.27 (T.P.)
8.89
I
24.495
42.18
J
K
17.78
L
M
M1
M2
N
34.93±0.13
15.15
19.78
V
X
P
4.0 MAX.
1.0
P
D1
Q
R2.0
R1
R2
S
4.0±0.10
9.53
φ
3.0
T
1.27±0.1
4.0 MIN.
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
2.26
U1
U2
V
W
X
Y1
Y2
Z1
Z2
3.0 MIN.
2.26
M168S-50A78
Data Sheet E0054N20
12
MC-4532CD647
[ MEMO ]
Data Sheet E0054N20
13
MC-4532CD647
[ MEMO ]
Data Sheet E0054N20
14
MC-4532CD647
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet E0054N20
15
MC-4532CD647
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
•
The information in this document is current as of March, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data
books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
M8E 00. 4
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