MC-4532CC726XFA [ELPIDA]
32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE; 32M - WORD 72 - BIT同步动态RAM模块UNBUFFERED TYPE
| 型号： | MC-4532CC726XFA |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| 文件： | 总14页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CC726XFA
32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-4532CC726XFA is 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
MC-4532CC726XFA-A80
CL = 3
CL = 2
125 MHz
100 MHz
6 ns
6 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length: 1, 2, 4, 8 and full page
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0280N10 (Ver 1.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
This product became EOL in March, 2004.
Elpida Memory, Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532CC726XFA
Ordering Information
Part number
Clock frequency
Package
Mounted devices
MHz (MAX.)
125 MHz
MC-4532CC726XFA-A80
168-pin Dual In-line Memory Module 18 pieces of µPD45128841G5 (Rev. X)
(Socket Type)
(10.16 mm (400) TSOP (II))
Edge connector : Gold plated
34.93 mm height
Data Sheet E0280N10 (Ver 1.0)
2
MC-4532CC726XFA
Pin Configuration
168-pin Dual In-line MemoryModule Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
VSS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
V
SS
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
VSS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A8
A9
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
A0 - A11
: Address Inputs
CLK0
VSS
VSS
[Row: A0 - A11, Column: A0 - A9]
BA0 (A13), BA1 (A12)
CKE0
/CS3
DQMB6
DQMB7
NC
NC
/CS2
DQMB2
DQMB3
NC
: SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7
: Data Inputs/Outputs
Vcc
Vcc
NC
NC
NC
NC
CB6
CB2
CB7
CB3
V
SS
VSS
CLK0 - CLK3
CKE0, CKE1
/CS0 - /CS3
/RAS
: Clock Input
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
DQ52
NC
DQ20
NC
NC
NC
NC
CKE1
/CAS
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
/WE
V
SS
VSS
DQMB0 - DQMB7 : DQ Mask Enable
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
SA0 - SA2
SDA
SCL
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
VCC
VSS
V
SS
CLK2
NC
CLK3
NC
VSS
NC
SA0
SA1
SA2
Vcc
NC
: No Connection
SDA
SCL
Vcc
Data Sheet E0280N10 (Ver 1.0)
3
MC-4532CC726XFA
Block Diagram
/WE
/CS0
/CS1
/CS2
/CS3
DQMB0
DQMB2
DQM
DQM /CS /WE
/CS
/CS
/CS
/CS
DQM /CS /WE
DQM
/CS
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D0
D3
D9
D12
DQMB3
DQMB1
DQM
DQM
/CS /WE
/CS /WE
DQM /CS
DQM
DQ 8
DQ 9
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 3
DQ 0
DQ 1
DQ 2
DQ 4
DQ 5
DQ 6
DQ 7
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
D1
D4
D10
D13
DQMB6
DQMB5
DQM
/CS /WE
DQM
DQM /CS /WE
DQM /CS
CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
DQ 4
DQ 7
DQ 0
DQ 2
DQ 6
DQ 5
DQ 3
DQ 1
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 3
DQ 0
DQ 7
DQ 5
DQ 1
DQ 2
DQ 4
DQ 6
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D2
D7
D11
D16
DQMB4
DQMB7
/CS
DQM /CS /WE
DQM
/WE
DQM
/CS
DQM
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 3
DQ 0
DQ 1
DQ 2
DQ 4
DQ 5
DQ 6
DQ 7
D5
D8
D14
D17
DQMB5
DQM /CS /WE
DQM /CS
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 5
DQ 7
DQ 6
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 2
DQ 0
DQ 1
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D6
D15
SERIAL PD
CLK0
CLK2
CLK3
C
LK: D0, D1, D2, D5, D6
C
LK: D3, D4, D7, D8
SDA
3.3 pF
SCL
A0
A1
A2
CLK1
C
LK: D12, D13, D16, D17
C
LK: D9, D10, D11, D14, D15
SA0 SA1 SA2
3.3 pF
A0 - A11
BA0
A0 - A11: D0 - D17
A13: D0 - D17
10kΩ
/RAS
/RAS: D0 - D17
/CAS: D0 - D17
CKE: D0 - D8
CKE1
CKE: D9-D17
BA1
A12: D0 - D17
/CAS
V
CC
SS
D0 - D17
D0 - D17
C
CKE0
V
Remarks 1. The value of all resistors is 10 Ω except CKE1 and WP.
2. D0 - D17: µPD45128841 (4M words × 8 bits × 4 banks)
Data Sheet E0280N10 (Ver 1.0)
4
MC-4532CC726XFA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
PD
18
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
VCC + 0.3
+0.8
V
Low level input voltage
VIL
V
Operating ambient temperature
TA
70
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
60
TYP.
MAX.
102
Unit
pF
Input capacitance
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0 - CLK3
20
30
15
5
40
56
33
21
19
CKE0, CKE1
/CS0 - /CS3
DQMB0 - DQMB7
DQ0 - DQ63, CB0 - CB7
Data input/output capacitance
7
pF
Data Sheet E0280N10 (Ver 1.0)
5
MC-4532CC726XFA
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN. MAX. Unit Notes
Operating current
ICC1
/CAS latency = 2
/CAS latency = 3
1,170 mA
1,170
1
Burst length = 1
tRC ≥ tRC(MIN.), IO = 0 mA
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
power down mode ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
Precharge standby current in ICC2N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
18
18
mA
360
mA
non power down mode
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞
108
Input signals are stable.
Active standby current in
power down mode
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
90
72
mA
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
450
360
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.)
IO = 0 mA
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
1,350 mA
1,575
2
3
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
2,340 mA
2,340
Self refresh current
ICC6
II(L)
CKE ≤ 0.2 V
36
mA
Input leakage current
VI = 0 to 3.6 V, All other pins not under test = 0 V
– 18 + 18
µA
Input leakage current (CKE1)
Output leakage current
High level output voltage
Low level output voltage
–500 +500 µA
IO(L)
VOH
VOL
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 3
2.4
+ 3
µA
V
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0280N10 (Ver 1.0)
6
MC-4532CC726XFA
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
Value
2.4 / 0.4
1.4
Unit
V
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
V
1
ns
V
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
Data Sheet E0280N10 (Ver 1.0)
7
MC-4532CC726XFA
Synchronous Characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
MIN.
8
MAX.
Note
Clock cycle time
/CAS latency = 3
tCK3
tCK2
tAC3
tAC2
tCH
(125 MHz)
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
10
(100 MHz)
Access time from CLK
6
6
1
1
CLK high level width
CLK low level width
3
3
3
0
3
3
2
1
2
1
2
1
2
2
tCL
Data-out hold time
tOH
1
Data-out low-impedance time
tLZ
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
6
6
Data-in setup time
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1
ns
Note 1. Output load
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet E0280N10 (Ver 1.0)
8
MC-4532CC726XFA
Asynchronous Characteristics
Parameter
Symbol
tRC
MIN.
MAX.
Unit
ns
Note
ACT to REF/ACT command period (Operation)
REF to REF/ACT command period (Refresh)
ACT to PRE command period
70
tRC1
tRAS
tRP
70
ns
48
120,000
ns
PRE to ACT command period
20
ns
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC
tT
20
ns
16
ns
8
1CLK+20
1CLK+20
2
ns
Data-in to ACT(REF) command period /CAS latency = 3
ns
(Auto precharge)
/CAS latency = 2
ns
Mode register set cycle time
Transition time
CLK
ns
0.5
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
Data Sheet E0280N10 (Ver 1.0)
9
MC-4532CC726XFA
Serial PD
(1/2)
Byte No.
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
0
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0AH
02H
48H
00H
01H
80H
60H
02H
80H
08H
08H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
60H
00H
14H
10H
14H
30H
20H
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
10 columns
2 banks
72 bits
0
3
4
Number of columns
5
Number of banks
6
Data width
7
Data width (continued)
Voltage interface
8
LVTTL
8 ns
9
CL = 3 Cycle time
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25-26
27
28
29
30
31
CL =3 Access time
6 ns
DIMM configuration type
Refresh rate/type
ECC
Normal
×8
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General
CL = 2 Cycle time
×8
1 clock
1, 2, 4, 8, F
4 banks
2, 3
0
0
10 ns
6 ns
CL = 2 Access time
tRP(MIN.)
20 ns
tRRD(MIN.)
16 ns
tRCD(MIN.)
20 ns
tRAS(MIN.)
48 ns
Module bank density
128M bytes
Data Sheet E0280N10 (Ver 1.0)
10
MC-4532CC726XFA
(2/2)
Byte No.
32
Function Described
Hex
20H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
2 ns
Command and address signal input
setup time
0
0
1
0
0
0
0
0
33
Command and address signal input
hold time
10H
0
0
0
1
0
0
0
0
1 ns
34
35
Data signal input setup time
Data signal input hold time
20H
10H
00H
12H
03H
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
2 ns
1 ns
36-61
62
SPD revision
1.2
63
Checksum for bytes 0 - 62
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
64H
FFH
0
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
100 MHz
Intel specification /CAS latency support
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0280N10 (Ver 1.0)
11
MC-4532CC726XFA
Package Drawing
Front side
Unit: mm
3.00
(DATUM -A-)
4.80 Max
(63.67)
Component area
(Front)
1
84
B
A
C
11.43
1.27
36.83
54.61
133.35
Back side
2 – φ 3.00
127.35
8 5
1 6 8
Component area
(Back)
(DATUM -A-)
Detail A
Detail B
R FULL
Detail C
(DATUM -A-)
R FULL
6.35
1.27
0.050
1.00
6.35
2.00 ± 0.10
4.175
2.00 ± 0.10
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
ECA-TS2-0049-01
Data Sheet E0280N10 (Ver 1.0)
12
MC-4532CC726XFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0280N10 (Ver 1.0)
13
MC-4532CC726XFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
14
Data Sheet E0280N10 (Ver 1.0)
相关型号：
©2020 ICPDF网 联系我们和版权申明