EBE51ED8AEFA-5C-E [ELPIDA]
512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank); 512MB无缓冲DDR2 SDRAM DIMM （ 64M字× 72位，1个等级）
| 型号： | EBE51ED8AEFA-5C-E |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| 文件： | 总22页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
512MB Unbuffered DDR2 SDRAM DIMM
EBE51ED8AEFA (64M words × 72 bits, 1 Rank)
Description
Features
The EBE51ED8AEFA is 64M words × 72 bits, 1 rank
DDR2 SDRAM unbuffered module, mounting 9 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
• 240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
technology.
Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0585E20 (Ver. 2.0)
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
EBE51ED8AEFA
Ordering Information
Component
Data rate
Mbps (max.)
JEDEC speed bin
(CL-tRCD-tRP)
Contact
pad
Part number
Package
Mounted devices
EBE51ED8AEFA-5C-E 533
EBE51ED8AEFA-4A-E 400
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
EDE5108AESK-5C
EDE5108AESK-5C, -4A
240-pin DIMM
(lead-free)
Gold
Pin Configurations
Front side
1 pin
64 pin65 pin
120 pin
121 pin
184 pin 185 pin
240 pin
Back side
Pin name
A4
Pin No.
1
Pin name
VREF
VSS
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
Pin name
VSS
DQ4
DQ5
VSS
DM0
NC
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
Pin name
VDD
A3
2
VDD
A2
3
DQ0
A1
4
DQ1
VDD
VSS
VDD
CK0
5
VSS
6
/DQS0
DQS0
VSS
VSS
/CK0
VDD
A0
7
VDD
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
8
9
DQ2
VDD
A10
VDD
BA1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DQ3
VSS
BA0
VDD
/RAS
/CS0
VDD
ODT0
A13
DQ8
VDD
/WE
DQ9
VSS
/CAS
VDD
NC
/DQS1
DQS1
VSS
VSS
CK1
NC
VDD
VSS
DQ36
DQ37
VSS
DM4
NC
NC
VDD
VSS
/CK1
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
NC
VSS
DQ32
DQ33
VSS
DQ10
DQ11
VSS
/DQS4
DQS4
VSS
DQ16
DQ17
VSS
VSS
DQ38
DQ39
VSS
DQ44
DQ45
DQ34
DQ35
VSS
/DQS2
DQS2
VSS
VSS
DQ22
DQ40
Data Sheet E0585E20 (Ver. 2.0)
2
EBE51ED8AEFA
Pin No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin name
DQ18
DQ19
VSS
Pin No.
90
Pin name
DQ41
VSS
Pin No.
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pin name
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
Pin No.
Pin name
VSS
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
91
DM5
NC
92
/DQS5
DQS5
VSS
DQ24
DQ25
VSS
93
VSS
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
/DQS3
DQS3
VSS
96
97
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8
NC
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
SA2
/CK2
VSS
CB0
NC
CB1
VSS
DM6
NC
VSS
/DQS6
DQS6
VSS
/DQS8
DQS8
VSS
VSS
VSS
CB6
CB7
VSS
VDD
NC
DQ54
DQ55
VSS
DQ50
DQ51
VSS
CB2
CB3
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VDD
CKE0
VDD
NC
VDD
NC
DM7
NC
/DQS7
DQS7
VSS
NC
VSS
NC
VDD
A12
DQ62
DQ63
VSS
VDD
A11
DQ58
DQ59
VSS
A9
A7
VDD
A8
VDDSPD
SA0
VDD
A5
SDA
SCL
A6
SA1
Data Sheet E0585E20 (Ver. 2.0)
3
EBE51ED8AEFA
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A13
A0 to A13
A0 to A9
A10 (AP)
Auto precharge
BA0, BA1
Bank select address
Data input/output
DQ0 to DQ63
CB0 to CB7
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/RAS
/CAS
/WE
/CS0
Chip select
CKE0
Clock enable
CK0 to CK2
Clock input
/CK0 to /CK2
Differential clock input
Input and output data strobe
Input mask
DQS0 to DQS8, /DQS0 to /DQS8
DM0 to DM8
SCL
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
ODT0
ODT control
NC
No connection
Data Sheet E0585E20 (Ver. 2.0)
4
EBE51ED8AEFA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
device
256 bytes
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
08H
0EH
0AH
60H
48H
00H
05H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
10
1
72
Module data width continuation
0
Voltage interface level of this assembly 0
SSTL 1.8V
DDR SDRAM cycle time, CL = 5
9
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
3DH
50H
50H
3.75ns*1
5.0ns*1
0.5ns*1
-5C
-4A
0
0
SDRAM access from clock (tAC)
-5C
10
-4A
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
60H
02H
82H
08H
08H
00H
0.6ns*1
ECC
7.8µs
× 8
11
12
13
14
15
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
× 8
0
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH
04H
38H
4,8
SDRAM device attributes: Number of
banks on SDRAM device
4
SDRAM device attributes:
/CAS latency
3, 4, 5
19
20
21
22
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
00H
02H
00H
01H
0
DIMM type information
SDRAM module attributes
SDRAM device attributes: General
Unbuffered
Normal
Weak Driver
Minimum clock cycle time at CL = 4
-5C
23
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH
50H
3.75ns*1
5.0ns*1
-4A
Maximum data access time (tAC) from
clock at CL = 4
-5C
24
0
1
0
1
0
0
0
0
50H
0.5ns*1
-4A
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H
50H
0.6ns*1
5.0ns*1
Minimum clock cycle time at CL = 3
-5C, -4A
25
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
0.6ns*1
-5C, -4A
Data Sheet E0585E20 (Ver. 2.0)
5
EBE51ED8AEFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
15ns
27
28
29
Minimum row precharge time (tRP)
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
3CH
1EH
3CH
Minimum row active to row active
delay (tRRD)
7.5ns
15ns
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
30
(tRAS)
-5C
0
0
1
0
1
1
0
1
2DH
45ns
-4A
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
28H
80H
40ns
31
32
Module rank density
512M bytes
Address and command setup time
before clock (tIS)
-5C
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H
35H
38H
48H
10H
0.25ns*1
0.35ns*1
0.38ns*1
0.48ns*1
0.10ns*1
-4A
Address and command hold time after
clock (tIH)
-5C
33
-4A
Data input setup time before clock
(tDS)
-5C
34
35
-4A
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H
23H
0.15ns*1
0.23ns*1
Data input hold time after clock (tDH)
-5C
-4A
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H
3CH
0.28ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-5C
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe characteristics 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H
00H
TBD
Extension of Byte 41 and 42
0
0
0
0
1
0
0
0
Undefined
Active command period (tRC)
-5C
41
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
3CH
37H
69H
80H
1EH
23H
28H
60ns*1
-4A
55ns*1
Auto refresh to active/
42
43
44
105ns*1
8ns*1
Auto refresh command cycle (tRFC)
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-5C
0.30ns*1
0.35ns*1
0.40ns*1
-4A
Data hold skew (tQHS)
-5C
45
-4A
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
2DH
00H
00H
0.45ns*1
46
PLL relock time
Undefined
47 to 61
Data Sheet E0585E20 (Ver. 2.0)
6
EBE51ED8AEFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
Rev. 1.0
62
63
SPD Revision
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
10H
C4H
3EH
7FH
Checksum for bytes 0 to 62
-5C
-4A
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
66
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH
00H
Elpida Memory
67 to 71
(ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
75
76
77
78
79
80
81
82
83
84
85
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
0
1
1
0
1
1
45H
42H
45H
35H
31H
45H
44H
38H
41H
45H
46H
41H
2DH
E
B
E
5
1
E
D
8
A
E
F
A
—
Module part number
-5C
86
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
1
0
1
35H
34H
41H
5
4
A
-4A
Module part number
-4A
87
-5C
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
43H
2DH
45H
20H
30H
20H
C
88
89
90
91
92
Module part number
Module part number
Module part number
Revision code
—
E
(Space)
Initial
(Space)
Revision code
Year code
(BCD)
93
Manufacturing date
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
××
××
Week code
(BCD)
94
Manufacturing date
95 to 98
Module serial number
99 to 127 Manufacture specific data
Note: These specifications are defined based on component specification, not module.
Data Sheet E0585E20 (Ver. 2.0)
7
EBE51ED8AEFA
Block Diagram
/CS0
R
S1
R
S1
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
R
R
S1
S1
S1
R
R
S1
/CS DQS /DQS
/CS DQS /DQS
DM
DM
8
8
8
8
R
S1
8
8
8
R
D0
D4
S1
DQ0
to DQ7
DQ0
to DQ7
DQ0 to DQ7
DQ32 to DQ39
R
R
S1
R
S1
S1
S1
/DQS1
/DQS5
DQS5
S1
R
DQS1
DM1
R
R
S1
R
R
/CS DQS /DQS
/CS DQS /DQS
DM5
DM
DM
S1
S1
DQ0
to DQ7
DQ0
to DQ7
D1
DQ8 to DQ15
DQ40 to DQ47
D5
R
R
S1
R
S1
/DQS2
DQS2
/DQS6
DQS6
S1
R
S1
R
R
R
R
S1
/CS DQS /DQS
S1
/DQS
/CS DQS
DM2
DM
DM6
DM
S1
S1
DQ0
to DQ7
DQ0
to DQ7
D6
D2
DQ48 to DQ55
DQ16 to DQ23
R
R
S1
R
S1
/DQS3
DQS3
/DQS7
DQS7
S1
R
S1
R
S1
/CS DQS /DQS
R
R
/CS DQS /DQS
S1
DM
DM3
DM
DM7
8
S1
R
S1
D3
DQ0
to DQ7
DQ0
to DQ7
D7
DQ56 to DQ63
DQ24 to DQ31
R
S1
R
/DQS8
S2
S2
S2
S2
S2
BA0 to BA1
A0 to A13
/RAS
BA0 to BA1: SDRAMs (D0 to D8)
A0 to A13: SDRAMs (D0 to D8)
R
S1
R
R
R
R
DQS8
R
R
S1
/CS DQS /DQS
/RAS: SDRAMs (D0 to D8)
/CAS: SDRAMs (D0 to D8)
DM8
DM
8
S1
DQ0
to DQ7
D8
CB0 to CB7
/CAS
/WE
CKE0
ODT0
/WE: SDRAMs (D0 to D8)
CKE: SDRAMs (D0 to D8)
ODT:SDRAMs (D0 to D8)
Serial PD
SDA
SDA
SCL
SA0
SA1
SA2
SCL
VDDSPD
VREF
SPD
A0
A1
A2
U0
SDRAMs (D0 to D8)
WP
SDRAMs (D0 to D8)
VDD
VSS
SDRAMs (D0 to D8)
Notes :
1. DQ wiring maybe changed within a byte.
* D0 to D7 : 512M bits DDR2 SDRAM
U0 : 2k bits EEPROM
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be meintained as shown.
Rs1 : 22
Ω
3. Refer to the appropriate clock wiring topology
under the DIMM wiring details section of this document.
Rs2 : 5.1
Ω
Data Sheet E0585E20 (Ver. 2.0)
8
EBE51ED8AEFA
Logical Clock Net Structure
3DRAM loads
R = 200Ω
C1
C1
DRAM
DRAM
DIMM
connector
R = 200Ω
DRAM
C1
R = 200Ω
Data Sheet E0585E20 (Ver. 2.0)
9
EBE51ED8AEFA
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
Note
1
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +2.3
–0.5 to +2.3
50
V
VDD
IOS
PD
V
mA
W
°C
°C
1
9
Operating case temperature
Storage temperature
TC
0 to +85
–55 to +100
1
1
Tstg
Note: 1. DDR2 SDRAM component specification.
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TC = 0 to +85°C) (DDR2 SDRAM Component Specification)
Parameter
Symbol
VDD, VDDQ
VSS
min.
typ.
1.8
0
max.
1.9
0
Unit
V
Notes
4
Supply voltage
1.7
0
V
VDDSPD
VREF
1.7
—
3.6
V
Input reference voltage
Termination voltage
DC input logic high
DC input low
0.49 × VDDQ
VREF − 0.04
VREF + 0.125
−0.3
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
3
VTT
VREF
VREF + 0.04
VDDQ + 0.3V
VREF – 0.125
V
VIH (DC)
VIL (DC)
VIH (AC)
VIL (AC)
V
V
AC input logic high
AC input low
VREF + 0.250
V
VREF − 0.250
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ must be equal to VDD.
Data Sheet E0585E20 (Ver. 2.0)
10
EBE51ED8AEFA
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol
IDD0
Grade
max.
Unit
mA
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-PRE)
-5C
-4A
990
855
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(ACT-READ-PRE)
-5C
-4A
1125
990
IDD1
mA
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-5C
-4A
90
72
Precharge power-down
standby current
IDD2P
IDD2Q
IDD2N
mA
mA
mA
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-5C
-4A
225
180
Precharge quiet standby
current
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-5C
-4A
270
225
Idle standby current
all banks open;
Fast PDN Exit
-5C
-4A
360
315
IDD3P-F
IDD3P-S
mA
mA
tCK = tCK (IDD);
MRS(12) = 0
Active power-down
standby current
CKE is L;
Other control and address bus
inputs are STABLE;
Data bus inputs are FLOATING
-5C
-4A
225
180
Slow PDN Exit
MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-5C
-4A
585
540
Active standby current
IDD3N
IDD4R
mA
mA
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
1710
1350
Operating current
-5C
-4A
(Burst read operating)
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
1710
1350
Operating current
-5C
-4A
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4W
IDD5
mA
mA
(Burst write operating)
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-5C
-4A
2250
2070
Auto-refresh current
Data Sheet E0585E20 (Ver. 2.0)
11
EBE51ED8AEFA
Parameter
Symbol
IDD6
Grade
max.
54
Unit
mA
Test condition
Self Refresh Mode;
CK and /CK at 0V;
CKE ≤ 0.2V;
Self-refresh current
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Operating current
(Bank interleaving)
-5C
-4A
2880
2700
IDD7
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
CL(IDD)
4-4-4
4
3-3-3
3
Unit
tCK
ns
tRCD(IDD)
tRC(IDD)
15
15
60
55
ns
tRRD(IDD)
tCK(IDD)
7.5
3.75
45
7.5
5
ns
ns
tRAS(min.)(IDD)
tRAS(max.)(IDD)
tRP(IDD)
40
ns
70000
15
70000
15
ns
ns
tRFC(IDD)
105
105
ns
Data Sheet E0585E20 (Ver. 2.0)
12
EBE51ED8AEFA
DC Characteristics 2 (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
ILI
Value
Unit
Notes
Input leakage current
Output leakage current
2
5
µA
µA
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
ILO
Minimum required output pull-up under AC
test load
VOH
VOL
VTT + 0.603
VTT – 0.603
V
V
5
5
Maximum required output pull-down under
AC test load
Output timing measurement reference level VOTR
0.5 × VDDQ
+13.4
V
1
Output minimum sink DC current
Output minimum source DC current
IOL
mA
mA
3, 4, 5
2, 4, 5
IOH
-13.4
Notes: 1. The VDDQ of the device under test is referenced.
2. VDDQ = 1.7V; VOUT = 1.42V.
3. VDDQ = 1.7V; VOUT = 0.28V.
4. The DC value of VREF applied to the receiving device is expected to be set to VTT.
5. After OCD calibration to 18Ω at TA = 25°C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit
V
Notes
AC differential input voltage
AC differential cross point voltage
AC differential cross point voltage
VID (AC)
VIX (AC)
VOX (AC)
0.5
VDDQ + 0.6
1
2
3
0.5 × VDDQ − 0.175
0.5 × VDDQ − 0.125
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
V
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true
input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as
/CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) − VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX(AC)
is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals
must cross.
3. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and
VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential
output signals must cross.
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
Differential Signal Levels*1, 2
Data Sheet E0585E20 (Ver. 2.0)
13
EBE51ED8AEFA
ODT DC Electrical Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
∆VM
min.
60
typ.
75
max.
90
Unit
Ω
Note
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω
Deviation of VM with respect to VDDQ/2
1
1
1
1
120
40
150
50
180
60
Ω
Ω
−6
+6
%
Note: 1. Test condition for Rtt measurements.
Measurement Definition for Rtt(eff)
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.
VIH(AC), and VDDQ values defined in SSTL_18.
VIH(AC) − VIL(AC)
Rtt(eff) =
I(VIH(AC)) − I(VIL(AC))
Measurement Definition for ∆VM
Measure voltage (VM) at test pin (midpoint) with no load.
2 × VM
VDDQ
× 100%
∆VM =
− 1
OCD Default Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
min.
12.6
0
typ.
18
max.
23.4
4
Unit
Ω
Notes
1
Output impedance
Pull-up and pull-down mismatch
Output slew rate
Ω
1, 2
3, 4
1.5
5
V/ns
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and
voltage.
3. Slew rate measured from VIL(AC) to VIH(AC).
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate
as measured from AC to AC. This is guaranteed by design and characterization.
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol Pins
min.
1.0
1.0
2.5
max.
2.0
Unit
pF
Note
Address, /RAS, /CAS, /WE,
Input capacitance
CI1
CI2
CO
/CS, CKE, ODT
Input capacitance
CK, /CK
2.0
pF
Data and DQS input/output
capacitance
DQ, DQS, /DQS, DM, CB
4.0
pF
Data Sheet E0585E20 (Ver. 2.0)
14
EBE51ED8AEFA
AC Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-5C
533
min.
4
-4A
Frequency (Mbps)
400
min.
3
Parameter
Symbol
CL
max.
5
max.
5
Unit
tCK
ns
Notes
/CAS latency
Active to read or write command delay
Precharge command period
tRCD
tRP
15
15
15
15
ns
Active to active/auto refresh command time tRC
60
55
ns
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
−500
−450
0.45
0.45
+500
+450
0.55
0.55
−600
−500
0.45
0.45
+600
+500
0.55
0.55
ps
tDQSCK
tCH
ps
tCK
tCK
CK low-level width
tCL
min.
(tCL, tCH)
min.
(tCL, tCH)
CK half period
tHP
ps
Clock cycle time
tCK
tDH
tDS
3750
225
8000
5000
275
8000
ps
ps
ps
DQ and DM input hold time
DQ and DM input setup time
5
4
100
150
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK,/CK tHZ
0.35
0.35
tCK
ps
tAC max.
tAC max.
tAC max.
tAC max.
Data-out low-impedance time from CK,/CK
tLZ
tAC min.
tAC min.
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
300
400
350
450
ps
DQ hold skew factor
tQHS
tQH
ps
ps
DQ/DQS output hold time from DQS
tHP – tQHS
tHP – tQHS
Write command to first DQS latching
transition
tDQSS
WL − 0.25
WL + 0.25
WL − 0.25
WL + 0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
0.35
0.35
0.2
0.35
0.35
0.2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
0.2
0.2
2
2
0.4
0.6
0.4
0.6
Write preamble
0.35
375
250
0.9
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
5
4
tIS
ps
tRPRE
tRPST
tRAS
tRAP
1.1
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
0.4
0.6
Active to precharge command
Active to auto-precharge delay
45
70000
40
70000
tRCD min.
tRCD min.
ns
Data Sheet E0585E20 (Ver. 2.0)
15
EBE51ED8AEFA
-5C
533
min.
-4A
400
min.
Frequency (Mbps)
Parameter
Symbol
tRRD
tWR
max.
max.
Unit
ns
Notes
Active bank A to active bank B command
period
7.5
15
7.5
15
Write recovery time
ns
Auto precharge write recovery + precharge
time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
tCK
1
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
10
ns
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
tCK
Exit precharge power down to any non-read
command
tXP
2
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
2
2
3
Exit active power down to read command
(slow exit/low power mode)
6 − AL
6 − AL
2, 3
CKE minimum pulse width (high and low
pulse width)
tCKE
tOIT
3
3
tCK
ns
Output impedance test driver delay
0
12
0
12
Auto refresh to active/auto refresh command
time
tRFC
tREFI
tDELAY
105
105
ns
Average periodic refresh interval
7.8
7.8
µs
Minimum time clocks remains ON after CKE
asynchronously drops low
tIS + tCK +
tIH
tIS + tCK +
tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0585E20 (Ver. 2.0)
16
EBE51ED8AEFA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Unit Notes
tCK
Parameter
Symbol
tAOND
tAON
min.
max.
ODT turn-on delay
2
2
ODT turn-on
tAC(min)
tAC(max) + 1000
ps
1
ODT turn-on (power down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min) + 2000
2tCK + tAC(max) + 1000
ps
2.5
2.5
tCK
ps
ODT turn-off
tAC(min)
tAC(max) + 600
2
ODT turn-off (power down mode)
ODT to power down entry latency
ODT power down exit latency
tAOFPD
tANPD
tAXPD
tAC(min) + 2000
2.5tCK + tAC(max) + 1000
ps
3
8
3
8
tCK
tCK
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
2. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
AC Input Test Conditions
Parameter
Symbol
Value
0.5 × VDDQ
1.0
Unit
V
Notes
1
Input reference voltage
VREF
Input signal maximum peak to peak swing
Input signal maximum slew rate
VSWING(max.)
SLEW
V
1
1.0
V/ns
2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)
(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in
the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive
transitions and VIH(AC) to VIL(AC) on the negative transitions.
Start of rising edge input timing
Start of falling edge input timing
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VSWING(max.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
∆TF
∆TR
VIH (DC)(min.)
−
VIL (AC)(max.)
VIH (AC) min.
−
VIL (DC)(max.)
Falling slew =
Rising slew =
∆TF
∆TR
AC Input Test Signal Wave forms
Measurement point
DQ
VTT
RT =25 Ω
Output Load
Data Sheet E0585E20 (Ver. 2.0)
17
EBE51ED8AEFA
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A13 (input pins)
Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address
becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ and CB (input and output pins)
Data are input to and output from these pins.
DQS and /DQS (input and output pin)
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
Data Sheet E0585E20 (Ver. 2.0)
18
EBE51ED8AEFA
DM (input pins)
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.
VDD (power supply pins)
1.8V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
1.8V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDE5104AESK, EDE5108AESK datasheet (E0562E).
Data Sheet E0585E20 (Ver. 2.0)
19
EBE51ED8AEFA
Physical Outline
Unit: mm
4.00 max
0.5 min
(DATUM -A-)
Component area
(Front)
1
120
B
A
1.27 ± 0.10
63.00
55.00
133.35
121
240
Component area
(Back)
FULL R
3.00
Detail A
Detail B
1.00
(DATUM -A-)
FULL R
4.00
2.50
5.00
1.50 ± 0.10
0.80 ± 0.05
ECA-TS2-0093-01
Data Sheet E0585E20 (Ver. 2.0)
20
EBE51ED8AEFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0585E20 (Ver. 2.0)
21
EBE51ED8AEFA
µBGA is a registered trademark of Tessera, Inc.
All other trademarks are the intellectual property of their respective owners.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0585E20 (Ver. 2.0)
22
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