EBD52UC8AKDA-7B [ELPIDA]
512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks); 512MB DDR SDRAM SO DIMM （ 64M字× 64位， 2级）
| 型号： | EBD52UC8AKDA-7B |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks) |
| 文件： | 总19页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
512MB DDR SDRAM SO DIMM
EBD52UC8AKDA (64M words × 64 bits, 2 Ranks)
Description
Features
The EBD52UC8AKDA is 64M words × 64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 16 pieces of 256M
bits DDR SDRAM sealed in TCP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TCP on the module board.
• 200-pin socket type small outline dual in line memory
module (SO DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0367E20 (Ver. 2.0)
Date Published March 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2003
EBD52UC8AKDA
Ordering Information
Component
JEDEC speed bin
(CL-tRCD-tRP)
Data rate
Mbps (max.)
Contact
pad
Part number
Package
Mounted devices
256M bits DDR SDRAM TCP*1
EBD52UC8AKDA-6B
EBD52UC8AKDA-7A
EBD52UC8AKDA-7B
333
266
266
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
200-pin SO DIMM Gold
Note: Please refer to 256Mb DDR TSOP product datasheet for electrical characteristics.
Pin Configurations
Front side
1 pin
2 pin
39 pin 41 pin
199 pin
42 pin
200 pin
40 pin
Back side
Pin No.
1
Pin name
VREF
VSS
Pin No.
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Pin name
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
NC
Pin No.
2
Pin name
VREF
VSS
Pin No.
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Pin name
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
NC
3
4
5
DQ0
6
DQ4
7
DQ1
8
DQ5
9
VDD
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
VDD
DM0
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS0
DQ2
DQ6
VSS
VSS
DQ3
DQ7
DQ8
DQ12
VDD
DQ13
DM1
VDD
DQ9
NC
NC
DQS1
VSS
VSS
NC
VSS
NC
VSS
DQ10
DQ11
VDD
NC
DQ14
DQ15
VDD
VDD
VSS
NC
VDD
NC
VDD
NC
CK0
NC
NC
/CK0
VSS
VSS
CK2
/CK2
VDD
CKE1
NC
VSS
VSS
VDD
VDD
CKE0
NC
VSS
DQ16
DQ17
VDD
DQ20
DQ21
VDD
DM2
DQS2
DQ18
A12
DQ22
A11
Preliminary Data Sheet E0367E20 (Ver. 2.0)
2
EBD52UC8AKDA
Pin No.
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Pin name
A9
Pin No.
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Pin name
DQ42
DQ43
VDD
Pin No.
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Pin name
A8
Pin No.
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Pin name
DQ46
DQ47
VDD
/CK1
CK1
VSS
A7
VSS
A6
A5
VDD
A4
A3
VSS
A2
A1
VSS
A0
VSS
VDD
A10/AP
BA0
DQ48
DQ49
VDD
VDD
BA1
DQ52
DQ53
VDD
DM6
/RAS
/CAS
/CS1
NC
/WE
DQS6
DQ50
VSS
/CS0
NC
DQ54
VSS
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ51
DQ56
VDD
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ55
DQ60
VDD
DQ61
DM7
DQ57
DQS7
VSS
VSS
DQ58
DQ59
VDD
DQ62
DQ63
VDD
SA0
SDA
SCL
SA1
VDDSPD
VDDID
SA2
NC
Preliminary Data Sheet E0367E20 (Ver. 2.0)
3
EBD52UC8AKDA
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A12
A0 to A12
A0 to A9
BA0, BA1
DQ0 to DQ63
/RAS
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7
SCL
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
VDD identification flag
No connection
NC
Preliminary Data Sheet E0367E20 (Ver. 2.0)
4
EBD52UC8AKDA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
256 bytes
device
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
0
0
0
0
07H
0DH
0AH
02H
40H
00H
04H
DDR SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
10
2
64 bits
0
Module data width continuation
Voltage interface level of this assembly
SSTL2
DDR SDRAM cycle time, CL = X
-6B
-7A, -7B
SDRAM access from clock (tAC)
-6B
-7A, -7B
9
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
60H
75H
70H
CL = 2.5*1
10
0.7ns*1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H
00H
0.75ns*1
None
7.8µs
Self refresh
11
12
DIMM configuration type
Refresh rate/type
1
0
0
0
0
0
1
0
82H
13
14
Primary SDRAM width
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
08H
00H
× 8
Error checking SDRAM width
Not used
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
16
17
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0EH
04H
2,4,8
4
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
18
19
20
21
22
SDRAM device attributes: /CAS latency 0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0CH
01H
02H
20H
C0H
2, 2.5
SDRAM device attributes: /CS latency
SDRAM device attributes: /WE latency
SDRAM module attributes
0
0
0
1
0
1
Unbuffered
VDD ± 0.2V
SDRAM device attributes: General
Minimum clock cycle time at
CL = X –0.5
23
0
1
0
1
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
75H
A0H
70H
CL = 2*1
-6B, -7A
-7B
Maximum data access time (tAC) from
clock at CL = X –0.5
-6B
24
0.7ns*1
-7A, -7B
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H
00H
0.75ns*1
25 to 26
27
Minimum row precharge time (tRP)
-6B
-7A, -7B
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H
50H
18ns
20ns
Minimum row active to row active delay
28
(tRRD)
-6B
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
0
30H
3CH
12ns
15ns
-7A, -7B
Preliminary Data Sheet E0367E20 (Ver. 2.0)
5
EBD52UC8AKDA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
18ns
Minimum /RAS to /CAS delay (tRCD)
-6B
29
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H
50H
-7A, -7B
20ns
Minimum active to precharge time
(tRAS)
-6B
30
0
0
1
0
1
0
1
0
2AH
42ns
-7A, -7B
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
2DH
40H
45ns
2 ranks
256MB
31
32
Module rank density
Address and command setup time
before clock (tIS)
-6B
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
1
0
0
0
1
0
1
75H
90H
75H
0.75ns*1
0.9ns*1
-7A, -7B
Address and command hold time after
clock (tIH)
-6B
33
0.75ns*1
-7A, -7B
1
0
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
90H
45H
50H
45H
0.9ns*1
0.45ns*1
0.5ns*1
0.45ns*1
Data input setup time before clock (tDS)
-6B
-7A, -7B
Data input hold time after clock (tDH)
-6B
-7A, -7B
34
35
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
50H
00H
0.5ns*1
36 to 40 Superset information
Future use
Active command period (tRC)
41
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
3CH
41H
60ns*1
65ns*1
-6B
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
42
0
1
0
0
1
0
0
0
48H
72ns*1
-7A, -7B
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
4BH
30H
75ns*1
12ns*1
43
44
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
2DH
32H
55H
0.45ns*1
0.5ns*1
45
0.55ns*1
-7A, -7B
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
75H
00H
00H
0.75ns*1
46 to 61 Superset information
Future use
62
SPD Revision
Checksum for bytes 0 to 62
-6B
63
0
0
0
0
0
0
0
1
01H
-7A
1
1
0
1
1
1
1
0
1
0
0
0
0
1
0
1
B8H
E3H
-7B
Continuation
code
Elpida Memory
64 to 65 Manufacturer’s JEDEC ID code
66 Manufacturer’s JEDEC ID code
67 to 71 Manufacturing location
0
1
1
1
1
1
1
1
7FH
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH
00H
(ASCII-8bit
code)
72
Module part number
×
×
×
×
×
×
×
×
××
73
74
Module part number
Module part number
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
45H
42H
E
B
Preliminary Data Sheet E0367E20 (Ver. 2.0)
6
EBD52UC8AKDA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
75
76
77
78
79
80
81
82
83
84
85
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
1
44H
35H
32H
55H
43H
38H
41H
4BH
44H
41H
2DH
D
5
2
U
C
8
A
K
D
A
—
Module part number
-6B
-7A, -7B
Module part number
-6B, -7B
86
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
1
1
1
0
1
0
36H
37H
42H
6
7
B
87
-7A
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
41H
20H
30H
20H
A
88 to 90 Module part number
(Space)
Initial
(Space)
91
92
Revision code
Revision code
Year code
93
94
Manufacturing date
Manufacturing date
×
×
×
×
×
×
×
×
××
(HEX)
Week code
(HEX)
×
×
×
×
×
×
×
×
××
95 to 98 Module serial number
99 to 127 Manufacture specific data
Note: These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
7
EBD52UC8AKDA
Block Diagram
/CS1
/CS0
R
R
S
S
/CS
/CS
/CS
/CS
DQS0
DQS4
DQS
DM
DQS
DM
DQS
DM
DQS
DM
R
R
R
S
R
S
R
S
S
DM0
DM4
D0
D8
D4
D12
8
8
8
8
S
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
DQ0 to DQ7
DQ32 to DQ39
R
S
DQS1
DQS5
DQS
DM
DQS
DM
DQS
DM
DQS
DM
/CS
/CS
/CS
/CS
R
R
R
R
S
S
DM1
DM5
D5
D13
D1
D9
S
S
DQ8 to DQ15
DQ40 to DQ47
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
R
S
R
S
/CS
/CS
/CS
/CS
DQS2
DQS6
DQS
DQS
DQS
DQS
R
R
R
R
R
S
S
S
S
DM
DM
DM2
DM
DM
DM6
D6
D14
D2
D10
8
8
8
8
S
I/O0 to I/O7
I/O0 to I/O7
DQ16 to DQ23
I/O0 to I/O7
I/O0 to I/O7
DQ48 to DQ55
R
S
/CS
/CS
DQS3
DQS7
/CS
/CS
DQS
DM
DQS
DM
DQS
DQS
R
R
R
R
S
S
DM3
DM7
DM
DM
D3
D7
D15
D11
S
S
DQ24 to DQ31
DQ56 to DQ63
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
Serial PD
SDA
SCL
SDA
SCL
SA0
SA1
SA2
A0
A1
A2
U0
BA0 to BA1
A0 to AN
/RAS
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D7)
SDRAMs (D8 to D15)
WP
/CAS
/WE
CK0
CKE0
CKE1
8 loads
/CK0
CK1
8 loads
0 loads
VDDSPD
VREF
SPD
SDRAMs (D0 to D15)
/CK1
CK2
/CK2
VDD
SDRAMs (D0 to D15), VDD and VDDQ
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
VSS
SDRAMs (D0 to D15), SPD
SDRAMs (D0 to D15), SPD
VDDID
Open
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
* D0 to D15 : 256M bits DDR SDRAM
U0 : 2k bits EEPROM
Rs : 22Ω
Strap in (closed): VDD ≠ VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
8
EBD52UC8AKDA
Logical Clock Net Structure
4DRAM loads
DRAM1
DRAM2
120Ω
DIMM
connector
DRAM3
DRAM4
Preliminary Data Sheet E0367E20 (Ver. 2.0)
9
EBD52UC8AKDA
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +3.6
–1.0 to +3.6
50
V
VDD
IO
V
mA
W
°C
°C
PD
8
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
1
Tstg
Note: DDR SDRAM component specification.
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)
Parameter
Symbol
VDD, VDDQ
VSS
Min
Typ
2.5
0
Max
2.7
0
Unit
V
Notes
1
Supply voltage
2.3
0
V
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
VREF
0.49 × VDDQ
VREF – 0.04
VREF + 0.15
–0.3
0.50 × VDDQ 0.51 × VDDQ
V
VTT
VREF
—
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
V
VIH (DC)
VIL (DC)
V
2
3
—
V
Input voltage level,
VIN (DC)
VIX (DC)
VID (DC)
–0.3
—
VDDQ + 0.3
V
V
V
4
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
0.5 × VDDQ − 0.2V 0.5 × VDDQ
0.36
0.5 × VDDQ + 0.2V
VDDQ + 0.6
—
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
10
EBD52UC8AKDA
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
IDD0
Grade
max.
Unit
mA
Test condition
Notes
1, 2, 9
-6B
-7A, -7B
1320
1200
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACTV-PRE)
CKE ≥ VIH, BL = 4,
Operating current
(ACTV-READ-PRE)
-6B
-7A, -7B
1560
1440
IDD1
mA
CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current
Floating idle standby current
IDD2P
IDD2F
48
560
480
mA
mA
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4
-6B
-7A, -7B
4, 5
-6B
480
400
CKE ≥ VIH, /CS ≥ VIH,
Quiet idle standby current
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
mA
mA
mA
mA
mA
mA
mA
mA
4, 10
-7A, -7B
DQ, DQS, DM = VREF
Active power down
standby current
320
CKE ≤ VIL
3
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
880
800
2080
1840
2080
1840
3200
2800
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 2.5
CKE ≥ VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Active standby current
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Self refresh current
IDD6
48
Operating current
(4 banks interleaving)
-6B
-7A, -7B
3240
2800
IDD7A
BL = 4
5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
ILI
min.
–32
max.
32
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDD ≥ VOUT ≥ VSS
VOUT = 1.95V
ILO
–10
10
µA
IOH
IOL
–15.2
15.2
—
mA
mA
1
1
—
VOUT = 0.35V
Note: 1. DDR SDRAM component specification.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
11
EBD52UC8AKDA
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
TBD
TBD
Unit
pF
Notes
Input capacitance
Input capacitance
Address, /RAS, /CAS, /WE
CK, /CK, CKE, /CS
CI2
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
TBD
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol
tCK
min.
max.
12
min.
max.
12
min.
max
12
Unit
Notes
10
Clock cycle time
(CL = 2)
7.5
7.5
10
ns
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
0.45
0.55
0.55
0.45
0.55
0.55
tCK
tCK
0.45
0.45
0.45
min
min
min
CK half period
tHP
tAC
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from
CK, /CK
–0.7
0.7
–0.75
0.75
–0.75
0.75
2, 11
DQS output access time from CK,
tDQSCK –0.6
0.6
–0.75
—
0.75
0.5
–0.75
—
0.75
0.5
ns
ns
ns
ns
ns
2, 11
3
/CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data hold skew factor
Data-out high-impedance time from
CK, /CK
tDQSQ
tQH
—
0.45
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
tQHS
tHZ
—
0.55
—
0.75
—
0.75
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
tLZ
–0.7
–0.75
–0.75
ns
Read preamble
tRPRE
tRPST
tDS
0.9
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.45
0.45
1.75
0
8
8
7
tDH
—
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
—
ns
—
—
—
ns
0.25
0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from
CK
tDQSS
0.75
0.2
1.25
—
0.75
0.2
1.25
—
0.75
0.2
1.25
—
tCK
tCK
tCK
tDSH
0.2
—
0.2
—
0.2
—
DQS input high pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
DQS input low pulse width
Address and control input setup
time
Address and control input hold time tIH
Address and control input pulse
width
tIS
0.75
0.75
2.2
—
—
—
0.9
0.9
2.2
—
—
—
0.9
0.9
2.2
—
—
—
ns
ns
ns
8
8
7
tIPW
Preliminary Data Sheet E0367E20 (Ver. 2.0)
12
EBD52UC8AKDA
-6B
-7A
-7B
Parameter
Symbol
tMRD
min.
max.
—
min.
max.
—
min.
max
—
Unit
tCK
Notes
Mode register set command cycle
time
2
2
2
Active to Precharge command
tRAS
tRC
42
60
120000 45
120000 45
120000 ns
period
Active to Active/Auto refresh
command period
—
65
—
65
—
ns
Auto refresh to Active/Auto refresh
tRFC
tRCD
tRP
72
18
18
—
—
—
75
20
20
—
—
—
75
20
20
—
—
—
ns
ns
ns
command period
Active to Read/Write delay
Precharge to active command
period
Active to Autoprecharge delay
Active to active command period
Write recovery time
tRAP
tRRD
tWR
tRCD min.
—
—
—
tRCD min.
—
—
—
tRCD min.
—
—
—
ns
ns
ns
12
15
15
15
15
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
—
tCK
13
Internal write to Read command
delay
Average periodic refresh interval
tWTR
tREF
1
—
1
—
1
—
tCK
µs
—
7.8
—
7.8
—
7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Preliminary Data Sheet E0367E20 (Ver. 2.0)
13
EBD52UC8AKDA
Timing Parameter Measured in Clock Cycle for unbuffered DIMM
Number of clock cycle
6ns
min.
tCK
7.5ns
Parameter
Symbol
max.
min.
max.
Unit
Write to pre-charge command delay (same bank) tWPD
Read to pre-charge command delay (same bank) tRPD
4 + BL/2
BL/2
3 + BL/2
BL/2
tCK
tCK
tCK
tCK
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
(CL = 2)
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
2 + BL/2
2 + BL/2
2
2
tCK
tCK
3
3
2
2
2
2
tCK
tCK
(CL = 2.5)
2.5
2.5
2.5
2.5
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
2 + BL/2
tCK
tCK
(CL = 2.5)
Pre-charge command to High-Z
(CL = 2)
tRWD
tHZP
3 + BL/2
2
3 + BL/2
2
2
2
tCK
tCK
tCK
tCK
tCK
(CL = 2.5)
tHZP
2.5
1
2.5
1
2.5
1
2.5
1
Write command to data in latency
Write recovery
tWCD
tWR
3
2
DM to data in latency
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
0
0
0
0
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
2
2
12
200
1
10
200
1
tCK
tCK
tCK
tCK
1
1
Power down exit to command input
1
1
Preliminary Data Sheet E0367E20 (Ver. 2.0)
14
EBD52UC8AKDA
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address
becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0, BA1 (input pin)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
L
Bank 2
H
H
Bank 3
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ (input and output pins)
Data are input to and output from these pins.
DQS (input and output pin)
DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0367E20 (Ver. 2.0)
15
EBD52UC8AKDA
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of
DQS and VREF
VDD (power supply pins)
2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output buffer.)
VDDSPD (power supply pin)
2.5V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDD2508AKTA datasheet.
Preliminary Data Sheet E0367E20 (Ver. 2.0)
16
EBD52UC8AKDA
Physical Outline
Unit: mm
3.80 Max
Front side
11.55
18.45
(DATUM -A-)
4x Full R
Component area
(Front)
A
B
11.40
2.45
2.15
47.40
1.00 ± 0.10
67.60
Back side
2.45
2.15
R0.50 ± 0.20
C
R0.50 ± 0.20
Component area
(Back)
(DATUM -A-)
Detail B
Detail A
Detail C
FULL R
0.60
1.80
4.20
1.50
4.20
1.00 ± 0.10
0.45 ± 0.03
ECA-TS2-0085-01
Preliminary Data Sheet E0367E20 (Ver. 2.0)
17
EBD52UC8AKDA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0367E20 (Ver. 2.0)
18
EBD52UC8AKDA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0367E20 (Ver. 2.0)
19
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