PI6C49X0204AWIE [DIODES]
Low Skew Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8;
| 型号： | PI6C49X0204AWIE |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Low Skew Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Features
Description
ꢀÎLow skew outputs (250 ps)
ꢀÎPackaged in 8-pin SOIC
The PI6C49X0204A is a low skew, single input to four output,
clock buffer. Perfect for fanning out multiple clock outputs.
ꢀÎLow power CMOS technology
ꢀÎOperating Voltages of 1.5 V to 3.3 V
ꢀÎOutput Enable pin tri-states outputs
ꢀÎ3.6 V tolerant input clock
ꢀÎIndustrial temperature ranges
Block Diagram
Pin Assignment
Q0
OE
CLK
Q1
1
2
3
4
8
7
6
5
Q1
Q2
CLK
VDD
Q2
GND
Q3
Q4
Q3
Output Enable
PI6C49X0204A
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Pin Descriptions
Pin#
Pin Name
CLK
Pin Type
Input
Pin Description
Clock Input. 3.3 V tolerant input.
1
2
3
4
5
6
7
Q1
Output
Output
Output
Output
Power
Clock Output 1.
Q2
Clock Output 2.
Q3
Clock Output 3.
Q4
Clock Output 4.
GND
VDD
Connect to ground.
Power
Connect to 1.5 V, 1.8V, 2.5V or 3.3V.
Output Enable. Tri-states outputs when low. Connect to VDD for
normal operation.
8
OE
Input
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 μF should be connected
between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 Ω series terminating resistor may be used on each
clock output if the trace is longer than 1 inch.
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Low Skew 1 TO 4 Clock Buffer
Maximum Ratings
Note:
Stresses above the ratings listed below can cause
permanent damage to the PI6C49X0204A. Functional
operation of the device at these or any other conditions
above those indicated in the operational sections of the
specifications is not implied.
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6V
Output Enable and All Outputs . . . . . . . . . . . .-0.5 V to VDD+0.5 V
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V (VDD > 0V)
Ambient Operating Temperature (industrial) . . . . . . . -40 to +85 °C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C
Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C
ESD Protection (HBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended
operating temperature range.
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (industrial)
-40
+85
°C
V
Power Supply Voltage (measured in respect to GND)
+3.6
+1.425
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
DC ELECTRICAL CHARACTERISTICS
VDD=1.5 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
1.425
1.17
Typ.
Max.
Units
VDD
Operating Voltage
1.5
1.575
V
VIH
VIL
IIH
Input High Voltage
Note 1, CLK
3.6
0.575
40
V
Input Low Voltage
Note 1, CLK
V
Input High Current
Input Low Current
Note 1, CLK, OE
Note 1, CLK, OE
IOH = -6 mA
µA
µA
V
IIL
1
VOH
VOL
IDD
ZO
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
0.95
IOL = 6 mA
0.45
9
V
No load, 133 MHz
mA
Ω
20
5
CIN
IOS
CLK, OE pin
pF
mA
Short Circuit Current
±12
Notes: 1. Nominal switching threshold is VDD/2
VDD=1.8 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
1.7
Typ.
Max.
Units
VDD
Operating Voltage
1.8
1.89
V
VIH
VIL
IIH
Input High Voltage
Note 1, CLK
1.7
3.6
0.6
50
1
V
Input Low Voltage
Note 1, CLK
V
Input High Current
Input Low Current
Note 1, CLK, OE
Note 1, CLK, OE
IOH = -8 mA
µA
µA
V
IIL
VOH
VOL
IDD
ZO
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
1.4
IOL = 8 mA
0.4
11
V
No load, 133 MHz
mA
Ω
20
5
CIN
IOS
CLK, OE pin
pF
mA
Short Circuit Current
±20
Notes: 1. Nominal switching threshold is VDD/2
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Low Skew 1 TO 4 Clock Buffer
VDD=2.5 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
2.375
1.7
Typ.
Max.
Units
VDD
Operating Voltage
2.5
2.625
V
VIH
VIL
IIH
Input High Voltage
Note 1, CLK
3.6
0.7
60
3
V
Input Low Voltage
Note 1, CLK
V
Input High Current
Input Low Current
Note 1, CLK, OE
Note 1, CLK, OE
IOH = -8 mA
µA
µA
V
IIL
VOH
VOL
IDD
ZO
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
2
IOL = 8 mA
0.4
15
V
No load, 133 MHz
mA
Ω
20
5
CIN
IOS
CLK, OE pin
pF
mA
Short Circuit Current
±50
Notes: 1. Nominal switching threshold is VDD/2
VDD=3.3 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
3.0
Typ.
Max.
Units
VDD
Operating Voltage
3.3
3.6
V
VIH
VIL
IIH
Input High Voltage
Note 1, CLK
2.1
3.6
0.7
85
1
V
Input Low Voltage
Note 1, CLK
V
Input High Current
Input Low Current
Note 1, CLK, OE
Note 1, CLK, OE
IOH = -8 mA
µA
µA
V
IIL
VOH
VOL
IDD
ZO
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
2.8
IOL = 8 mA
0.2
21
V
No load, 133 MHz
mA
Ω
20
5
CIN
IOS
CLK, OE pin
pF
mA
Short Circuit Current
±50
Notes: 1. Nominal switching threshold is VDD/2
AC ELECTRICAL CHARACTERISTICS
VDD=1.5 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output Frequency
0
166
MHz
tOR
tOF
TPD
TSK
Output Rise Time
20% to 80%
20% to 80%
1.0
1.0
3
1.5
1.5
5
ns
ns
ns
ps
Output Fall Time
Propagation Delay (Note1)
Output to Output Skew (Note2)
2
Rising edges at VDD/2
0
±250
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Low Skew 1 TO 4 Clock Buffer
AC ELECTRICAL CHARACTERISTICS
VDD=1.8 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output Frequency
0
166
MHz
tOR
tOF
TPD
TSK
Output Rise Time
20% to 80%
20% to 80%
1.0
1.0
2
1.5
1.5
4
ns
ns
ns
ps
Output Fall Time
Propagation Delay (Note1)
Output to Output Skew (Note2)
1.3
Rising edges at VDD/2
0
±250
@156.25MHz, 12k to
20MHz
JADD
Additive Jitter
0.1
ps
VDD=2.5 V ±5%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output Frequency
0
200
MHz
tOR
tOF
TPD
TSK
Output Rise Time
20% TO 80%
20% TO 80%
1.0
1.0
1.5
0
1.5
1.5
3
ns
ns
ns
ps
Output Fall Time
Propagation Delay (Note1)
Output to Output Skew (Note2)
0.8
Rising edges at VDD/2
±250
@156.25MHz, 12k to
20MHz
JADD
Additive Jitter
0.05
ps
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
VDD=3.3 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output Frequency
0
200
MHz
tOR
tOF
TPD
TSK
Output Rise Time
20% TO 80%
20% TO 80%
1.0
1.0
1.0
0
1.5
ns
ns
ns
ps
Output Fall Time
1.5
Propagation Delay (Note1)
Output to Output Skew (Note2)
0.8
2.5
Rising edges at VDD/2
±250
@156.25MHz, 12k to
20MHz
JADD
Additive Jitter
0.05
ps
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θJA
θJC
Still air
157
42
°C/W
°C/W
Thermal Resistance Junction to Case
PI6C49X0204A
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Phase Noise Plot
PI6C49X0204A
Rev D
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Application information
CMOS Output Termination
Suggest for Unused Inputs and Outputs
Popular CMOS Output Termination
LVCMOS Input Control Pins
e most popular CMOS termination is a serial resitor close to
the output pin (<=200mil). It is simple and balances the drive
strength. e resistor's value can be fine tuned for best perfor-
mance during board bring-up based on VDDO voltage used.
It is suggested to add pull-up=4.7k and pull-down=1k for LVC-
MOS pins even though they have internal pull-up/down but
with much higher value (>=50k) for higher design reliability.
Outputs
All unused outputs are suggested to be leꢀ open and not con-
nected to any trace. is can lower the IC power consumption.
Power Decoupling & Routing
VDD Pin Decoupling
Each VDD pin must have a 0.1uF decoupling capacitor. For
better decoupling, 1uF can be used. Locating the decoupling
capacitor on the component side has better decoupling filter
result as shown.
Combining Serial and Parallel Termination
14
Designers can also use a parallel termination for CMOS outputs.
For example, a 50 ohm pull-down resistor can be used at the
Rx side to reduce signal reflection, but it reduces the signals
V_swing in half. is pull-down can be combined with a serial
resitor to form a smaller clock voltage difference. e following
diagram shows how to transition a 2.5V clock into 1.8V clock.
13
GND
0.1uF
12
VDD
GND
11
10
9
0.1uF
VDD
GND
VDD
8
Decouple cap.
on comp. side
Clock IC Device
Placement of Decoupling caps
CMOS Clock Trace Routing
Please ensure that there is a sufficent keep-out area to the adja-
cent trace (>20mil.). In an example using a 125MHz XO driving
a buffer IC, it is better to route the clock trace on the component
side with a 33 ohm termination resistor.
Rs = 33 ohm with Rn = 100 ohm, to transition 3.3V CMOS to
2.5V
Rs= 43 ohm with Rn =70 ohm to transition 3.3V CMOS to 1.8V
PI6C49X0204A
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Clock Jitter Definitions
Total jitter= RJ + DJ
Device Thermal Calculation
e JEDEC thermal model in a 4-layer PCB is shown below.
Random Jitter (RJ) is unpredictable and unbounded timing noise
that can fit in a Gaussian math distribution in RMS. RJ test val-
ues are directly related with how long or how many test samples
are available. Deterministic Jitter (DJ) is timing jitter that is pre-
dictable and periodic in fixed interference frequency. Total Jitter
(TJ) is the combination of random jitter and deterministic jitter:
, where is a factor based on total test sample count. JEDEC std.
specifies digital clock TJ in 10k random samples.
JEDEC IC ermal Model
Phase Jitter
Phase noise is short-term random noise attached on the clock
carrier and it is a function of the clock offset from the car-
rier, for example dBc/Hz@10kHz which is phase noise power
in 1-Hz normalized bandwidth vs. the carrier power @10kHz
offset. Integration of phase noise in plot over a given frequency
band yields RMS phase jitter, for example, to specify phase jitter
<=1ps at 12k to 20MHz offset band as SONET standard specifi-
cation.
Important factors to influence device operating temperature are:
1) e power dissipation from the chip (P_chip) is aꢀer subtract-
ing power dissipation from external loads. Generally it can be
the no-load device Idd
2) Package type and PCB stack-up structure, for example, 1oz
4 layer board. PCB with more layers and are thicker has better
heat dissipation
3) Chassis air flow and cooling mechanism. More air flow M/s
and adding heat sink on device can reduce device final die junc-
tion temperature Tj
e individual device thermal calculation formula:
Tj =Ta + Pchip x Ja
Tc = Tj - Pchip x Jc
Ja ___ Package thermal resistance from die to the ambient air
in C/W unit; is data is provided in JEDEC model simulation.
An air flow of 1m/s will reduce Ja (still air) by 20~30%
Jc ___ Package thermal resistance from die to the package case
in C/W unit
Tj ___ Die junction temperature in C (industry limit <125C
max.)
Ta ___ Ambiant air température in C
Tc ___ Package case temperature in C
Pchip___ IC actually consumes power through Iee/GND cur-
rent
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PI6C49X0204A
Low Skew 1 TO 4 Clock Buffer
Note:
•
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6C49X0204AWIE
W
W
8-pin, Pb-free & Green, SOIC
PI6C49X0204AWIEX
8-pin, Pb-free & Green, SOIC, Tape & Reel
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PI6C49X0204A
Rev D
5/4/2016
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All trademarks are property of their respective owners.
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