PI6C20800BIAEX [DIODES]
Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, GREEN, MO-153FE, TSSOP-48;
| 型号： | PI6C20800BIAEX |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, GREEN, MO-153FE, TSSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C20800B
PCI Express® 3.0 1:8
HCSL Clock Buffer
Features
Description
ꢀÎPhase jitter filter for PCIe 3.0 application
ꢀÎEight Pairs of Differential Clocks
ꢀÎLow skew < 50ps (PI6C20800B), <60ps (PI6C20800BI)
ꢀÎLow Cycle-to-cycle jitter < 60ps
ꢀÎOutput Enable for all outputs
ꢀÎOutputs Tristate control via SMBus
ꢀÎPower Management Control
PI6C20800B is a PCIe 3.0 compliant, high-speed, low-noise
differential clock buffer designed to be a companion to PCI
Express 3.0 clock generator for Intel server chipsets. The device
distributes the differential SRC clock from PCIe clock generator
to eight differential pairs of clock outputs either with or without
PLL. The input SRC clock can be divided by 2 when SRC_DIV#
is LOW. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is LOW, the output
clocks are Tristated. When PWRDWN# is LOW, the SDA and
SCLK inputs must be Tristated.
ꢀÎProgrammable PLL Bandwidth
ꢀÎPLL or Fanout operation
ꢀÎ3.3V Operation
ꢀÎIndustrial Temperature Option - PI6C20800BI
ꢀÎPackaging (Pb-Free & Green):
— 48-Pin TSSOP (A)
Block Diagram
Pin Configuration (48-Pin TSSOP)
OE_INV
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
SRC_DIV#
VDD
VDD_A
VSS_A
IREF
LOCK
OE_7
OE [0:7]
SRC_STOP#
PWRDWN#
Output
Control
VSS
SRC
OUT0
OUT0#
SRC#
OE_0
OE_3
OUT0
OUT0#
VSS
OUT1
OE_4
OUT1#
SCLK
SDA
SMBus
OUT7
OUT7#
OE_INV
VDD
OUT6
OUT6#
OE_6
Controller
OUT2
9
OUT2#
10
11
12
13
14
15
16
17
18
PLL/BYPASS#
SRC_DIV#
OUT3
VDD
OUT3#
OUT1
OUT1#
OE_1
OE_2
OUT2
OUT2#
VSS
OUT4
SRC
OUT4#
OE_5
SRC#
OUT5
OUT5#
VSS
OUT5
OUT5#
OUT6
VDD
OUT6#
DIV
VDD 19
OUT3 20
OUT3# 21
OUT4
OUT4#
PLL_BW#
SRC_STOP#
PWRDWN#
VSS
PLL_BW#
PLL
OUT7
OUT7#
PLL/BYPASS# 22
SCLK 23
LOCK
SDA 24
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Pinout Table
Pin Name
Type
Pin #
Descriptions
3.3V LVTTL input for selecting input frequency divide by 2, active
LOW.
SRC_DIV#
SRC & SRC#
OE [0:7]
Input
Input
Input
1
4, 5
0.7V Differential SRC input from PI6C410 clock synthesizer
6, 7, 14, 15, 35, 36,
43, 44
3.3V LVTTL input for enabling outputs, active HIGH.
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
OE_INV
Input
40
When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
8, 9, 12, 13, 16 17, 20,
21, 29, 30, 33, 34, 37,
38, 41, 42
OUT[0:7] & OUT[0:7]# Output
0.7V Differential outputs
PLL/BYPASS#
SCLK
Input
Input
I/O
22
23
24
46
27
28
26
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SDA
SMBus compatible SDATA
IREF
Input
Input
Input
Input
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active LOW
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active LOW
SRC_STOP#
PLL_BW#
PWRDWN#
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
LOCK
Output
Power
45
VDD
2, 11, 19, 31, 39
3.3V Power Supply for Outputs
Ground for Outputs
VSS
Ground 3, 10, 18, 25, 32
Ground 47
VSS_A
VDD_A
Ground for PLL
Power
48
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
is part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address
and read/write bit as shown below.
Address assignment
A6
A5
A4
0
A3
1
A2
1
A1
1
A0
0
W/R
0/1
1
1
Data Write Protocol(1)
1 bit 7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Data
Byte
Offset
Data
Byte N
- 1
Start
bit
Register
offset
Byte Count
= N
Slave Addr
W
Ack
Ack
Ack
Ack
Ack Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Data Read Protocol(2)
7
1 bit 7 bits
Start Slave
1
1
8 bits
1
1
bits
1
1
8 bits
Byte
1
8 bits
1
8 bits
Data
1
1 bit
Data
Byte
Offset
Register
offset
Repeat Slave
Start Addr
Not Stop
Ack
W
Ack
Ack
R
Ack Count Ack
= N
Ack Byte
N - 1
bit
Addr
bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read.
Data Byte 0: Control Register
Bit Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
SRC_DIV#
0
1
2
0 = Divide by 2
1 = Normal
RW
1 = x1
OUT[0:7], OUT[0:7]#
NA
PLL/BYPASS#
0 = Fanout
RW
RW
1 = PLL
1 = Low
OUT[0:7], OUT[0:7]#
OUT[0:7], OUT[0:7]#
NA
NA
1 = PLL
PLL Bandwidth
0 = HIGH Bandwidth,
1 = LOW Bandwidth
RESERVED
3
4
5
RESERVED
RESERVED
SRC_STOP#
6
7
0 = Driven when stopped
1 = Tristate
RW
RW
0 = Driven when stopped
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
OUT[0:7], OUT[0:7]#
PWRDWN#
0 = Driven when stopped
1 = Tristate
NA
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Data Byte 1: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
RW
RW
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
NA
NA
NA
NA
NA
NA
NA
NA
OUTPUTS enable
1 = Enabled
0 = Disabled
Data Byte 2: Control Register
Bit Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
1
RW
RW
RW
RW
RW
RW
RW
RW
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
NA
NA
NA
NA
NA
NA
NA
NA
2
3
4
5
6
7
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
Data Byte 3: Control Register
Bit Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
1
2
RW
RW
RW
RW
RW
RW
RW
RW
3
RESERVED
4
5
6
7
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Data Byte 4: Pericom ID Register
Bit Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
1
2
R
R
R
R
R
R
R
R
0
0
0
0
0
1
0
0
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
3
Pericom ID
4
5
6
7
Functionality
PWRDWN# OUT
OUT#
SRC_Stop#
OUT
OUT#
1
0
Normal
REF × 2 or Float
Normal
LOW
1
0
Normal
REF × 6 or Float
Normal
LOW
I
I
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]#
VDD
(3.3V 5ꢀ%
Slope ~ 1/Rs
RO
IOUT
ROS
Iout
0V
0.85V
VOUT = 0.85V max
Differential Clock Buffer Characteristics
Symbol
Minimum
Maximum
RO
3000Ω
N/A
ROS
VOUT
unspecified
N/A
unspecified
850mV
Current Accuracy
Symbol
Conditions
Configuration
Load
Min.
Max.
R
REF = 475Ω 1%
Nominal test load for given
configuration
IOUT
VDD = 3.30 5%
-12% INOMINAL +12% INOMINAL
IREF = 2.32mA
Note:
1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
100Ω
Reference R, Iref = VDD/(3xRr) Output Current VOH @ Z
RREF = 475Ω 1%,
IOH = 6 x IREF
0.7V @ 50
(100Ω differential ≈ 15% coupling ratio)
IREF = 2.32mA
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Absolute Maximum Ratings(1) (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
Units
VDD_A
VDD
VIH
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Storage Temperature
ESD Protection
-0.5
-0.5
4.6
4.6
4.6
V
VIL
-0.5
-65
Ts
150
°C
V
VESD
2000
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol Parameters
Condition
Min.
Max.
Units
VDD_A
VDD
VIH
VIL
3.3V Core Supply Voltage
3.135
3.135
2.0
3.465
3.465
VDD + 0.3
0.8
3.3V I/O Supply Voltage
3.3V Input HIGH Voltage
3.3V Input LOW Voltage
Input Leakage Current
V
VSS – 0.3
-5
IIK
0 < VIN < VDD
IOH = -1mA
IOL = 1mA
+5
µA
V
VOH
VOL
3.3V Output HIGH Voltage
3.3V Output LOW Voltage
2.4
0.4
IOH = 6 x IREF
,
12.2
1.5
IOH
Output HIGH Current
mA
IREF = 2.32mA
15.6
5
CIN
COUT
LPIN
IDD
ISS
Logic Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
pF
6
7
nH
Power Supply Current
Power Down Current
Power Down Current
VDD = 3.465V, FCPU = 100MHz
Driven outputs
250
80
12
70
85
mA
°C
ISS
Tristate outputs
Commercial (PI6C20800B)
Industrial (PI6C20800BI)
0
TA
Ambient Temperature
-40
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
AC Switching Characteristics(1,2,3) (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Parameters
Min
Typ.
Max.
Units Notes
SRC/SRC# Input Frequency PLL Mode
SRC/SRC# Input Frequency Bypass Mode
95
95
105
400
MHz
MHz
6
6
Fin
Rise and Fall Time (measured between 0.175V to
0.525V)
Trise / Tfall
175
700
2
2
ps
ΔTrise / ΔTfall
Rise and Fall Time Variation
125
250
450
7.5
PI6C20800B
-250
PLL Mode
ps
ns
ps
PI6C20800BI -450
Input to Output
Tpd
Propagation Delay
PI6C20800B
-7.5
Bypass Mode
PI6C20800BI -8
8
Output-to-Output Skew (PI6C20800B)
Output-to-Output Skew (PI6C20800BI)
50
3
3
2
Tskew
65
VHIGH
VOVS
Voltage HIGH (Measured at 100MHz @ 3.3V)
Max. Voltage
600
900
1150
VUDS
VLOW
Min. Voltage
-300
-150
250
mV
Voltage LOW
+150
550
140
55
2
2
2
3
V
Absolute crossing poing voltages
Total Variation of Vcross over all edges
Duty Cycle (Measured at 100 MHz)
cross
ΔV
cross
TDC
45
%
Jitter, Cycle-to-cycle (PLL Mode, Measurement for dif-
ferential waveform)
Tjcyc-cyc
Jadd
60
ps
ps
4
5
Jitter, Cycle-to-cycle (BYPASS mode as additive jitter)
Additive RMS phase jitter for PCIe 2.0
PLL L-BW @ 2M & 5M 1st H3
<0
1
3
3
3
3
1
1
1
1
1.115
1.211
1.116
1.425
0.646
0.644
0.646
0.579
PLL L-BW @ 2M & 4M 1st H3
PLL L-BW @ 2M & 5M 1st H3
PLL L-BW @ 2M & 4M 1st H3
RMS phase jitter for
PCIe 3.0
Jadd
ps
PLL H-BW @ 2M & 5M 1st H3
PLL H-BW @ 2M & 4M 1st H3
PLL H-BW @ 2M & 5M 1st H3
PLL H-BW @ 2M & 4M 1st H3
Notes:
1. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.
2. Measurement taken from Single Ended waveform.
3. Measurement taken from Differential waveform.
4. Measured using M1 timing analyzer from Amherst.
5. Additive jitter is calculated from input and output RMS phase jitter by using PCIe 2.0 filter. (Jadd = √ (output jitter)2 – (input jitter)2 )
6. –0.5% downnspread input
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Configuration Test Load Board Termination
Rs
33Ω
5%
OUT
TLA
TLB
PI6C20800B
or
Rs
33Ω
5%
PI6C20800BI
OUT#
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
475Ω
1%
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PI6C20800B
PCI Express® 3.0 1:8 HCSL Clock Buffer
Packaging Mechanical: 48-Pin TSSOP (A)
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
See Note 3
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.007
.010
.0197
BSC
.006
0.05
0.15
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Ordering Information(1,2)
Ordering Code
Package Code
Package Description
PI6C20800BAE
PI6C20800BIAE
AE
AE
48-pin, 240-mil wide, TSSOP, Pb-Free and Green
48-pin, 240-mil wide, TSSOP, Pb-Free and Green (Industrial)
Notes:
1. ermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336
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PCIe® , and the PCI EXPRESS design mark® are trademarks of PCI-SIG® (www.pcisig.com)
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