PI3EQX1204-CZHE [DIODES]
IC REDRIVER SAS SATA 42TQFN;
| 型号： | PI3EQX1204-CZHE |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | IC REDRIVER SAS SATA 42TQFN 驱动 接口集成电路 |
| 文件： | 总17页 (文件大小：847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A product Line of
Diodes Incorporated
PI3EQX1204-C
12.5Gbps 4-channel, SAS3 ReDriver with Linear Equalization
Features
Description
ꢀÎ1-12.5Gbps serial link with linear equalizer
ꢀÎSupport SATA Gen1/Gen2/Gen3, SAS2/3, and XAUI protocol
ꢀÎSupporting 4 differential channels
e PI3EQX1204-C is a SAS3, 4 differential channels ReDriver.
e device provides programmable linear equalization, output
2
swing and flat gain, by either pin strapping option or I C Control,
to optimize performance over a variety of physical mediums by
reducing Inter-symbol interference.
ꢀÎHandle up to 34dB channel loss (42" FR4 trace or 10 meters
or SAS3 cable)
PI3EQX1204-C supports four 100-Ohm Differential CML data
I/O’s and extends the signals across other distant data pathways
on the user’s platform.
ꢀÎIndependent channel configuration of receiver equalization,
output swing and flat gain
ꢀÎRate and Coding Agnostic
ꢀÎTransparent to link training, OOB, Idle
ꢀÎ260mW per channel power dissipation with 700 mVpp
e integrated equalization circuitry provides flexibility with
signal integrity of the signal before the ReDriver, whereas the
integrated linear amplifier/buffer circuitry provides flexibility
with signal integrity of the signal aꢀer the ReDriver.
output swing
ꢀÎPin strap and I C selectable device programming
ꢀÎ4-bit selectable address bit for I C
2
2
Application
Rack Server, JBOD storage
ꢀÎSupply Voltage: 3.3V 0.3V
ꢀÎIndustrial Temperature Range: -40 C to 85 C
ꢀÎPackaging (Pb-free & Green):
o
o
à 42-contact TQFN (9mm x3.5mm)
Pin Configuration (Top-Side View)
Block Diagram
Conditional
pullup, 50-Ohm
or HIZ
Input threshold
Detection
VCC
39
42 41 40
SW1
SW0
1
2
3
4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
FG1/I2C_RESET#
FG0
CML Input buffer
VCC
O+
O-
VCC
I+
I-
Linear
Amp
Equalizer
Buffer
A0RX+
A0RX-
VCC
A0TX+
A0TX-
VCC
5
6
7
CML output
amplifier
Conditional input
Load: 50-Ohm or
200K-ohm
Equalization
control (4-bits)
A1RX+
A1RX-
VCC
A1TX+
A1TX-
VCC
V
CC
Flat
gain
8
Swing
control
9
10
control
A2RX+
A2TX+
A2TX-
VCC
Flat gain
control (2-bits)
Output Swing
control (2-bits)
A2RX-
VCC
11
12
13
14
15
16
17
Power
management
PRSNT#
A3RX+
A3RX-
VCC
A3TX+
A3TX-
VCC
^^ Repeats 4x ^^
DNC
DNC
DNC
I2C_DONE
21
18 19 20
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® Diodes Incorporated
PI3EQX1204-C
Document number: DS40033 Rev.1-2
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A product Line of
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PI3EQX1204-C
Pin Description
Pin #
Pin Name
Type Description
Data Signals
4
A0RX+
A0RX-
A0TX+
A0TX-
A1RX+
A1RX-
A1TX+
A1TX-
A2RX+
A2RX-
A2TX+
A2TX-
A3RX+
A3RX-
A3TX+
A3TX-
I
CML inputs for Channel A0, with internal 50-Ohm pull-up and ~200K-Ohm
pull-up otherwise.
5
I
35
O
O
I
CML outputs for Channel A0, with internal 50-Ohm pull-up and high
impedance otherwise.
34
7
CML inputs for Channel A1, with internal 50-Ohm pull-up and ~200K-Ohm
otherwise.
8
I
32
O
O
I
CML outputs for Channel A1, with internal 50-Ohm pull-up and high
impedance otherwise.
31
10
CML inputs for Channel A2, with internal 50-Ohm pull-up and ~200K-Ohm
otherwise.
11
I
29
O
O
I
CML outputs for Channel A2, with internal 50-Ohm pull-up and high
impedance otherwise.
28
13
CML inputs for Channel A3, with internal 50-Ohm pull-up and ~200K-Ohm
otherwise.
14
I
26
O
O
CML outputs for Channel A3, with internal 50-Ohm pull-up and high
impedance otherwise.
25
Control Signals
2
I C SCL Clock. In Master mode (ENI2C floating), SCL is an output.
Otherwise it is an input.
I/O
19
SCL
2
I/O
I C SDA data input/output.
18
SDA
2
42, 41, 40, 39
AD[3:0]
I
I C programmable address bits, with internal 100k-Ohm pull-up.
2
is pin is active in both PIN mode(ENI2C=LOW) and I C mode
(ENI2C=HIGH). Cable present detect input. is pin has internal 100K-ohm
pull-up. When High, a cable is not present, and the device is put in lower power
mode. When LOW, the device is enabled and in normal operation.
20
PRSNT#
I
When LOW, each channel is programmed by the external pin voltage.
2
21
ENI2C
I
When HIGH, each channel is programmed by the data stored in the I C bus.
When floating, master mode (Read External EEPROM)
Inputs with internal 100k-Ohm pull-up. is pins set the amount of Equalizer
42, 41, 40, 39
EQ[3:0]
SW[1:0]
FG[1:0]
I
I
I
I
Boost in all channel when ENI2C is LOW.
Inputs with internal 100k-Ohm pull-up. is pin sets the output Voltage
Level in all channel when ENI2C is LOW.
1, 2
Inputs with internal 100KΩ pull up resistor. Sets the output flat gain level
on all channels when ENI2C is low.
38, 37
38
2
Inputs with internal 100KΩ pull up resistor. Reset pin for I C.
2
I C_RESET#
When set low will reset the registers to default state.
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® Diodes Incorporated
PI3EQX1204-C
Document number: DS40033 Rev.1-2
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A product Line of
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PI3EQX1204-C
Pin #
Pin Name
Type Description
Valid register load status output, use for daisy chain master
LOW = External EEPROM load failed
22
I2C_DONE
DNC
O
HIGH = External EEPROM load passed
Do Not Connect
16, 17, 23
Power Pins
3, 6, 9, 12, 15, 24,
27, 30, 33, 36
V
PWR 3.3V Supply Voltage
CC
EP
GND
PWR Exposed pad. Supply Ground
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
Description of Operation
Power Enable function:
One pin control or I2C control, when PRSNT# is set to HIGH, the IC goes into power down mode, both input and output
termination set to 200K and High impedance respectively. Individual Channel Enabling is done through the I2C register
programming.
Equalization Setting:
EQ[3:0] are the selection pins for the equalization selection for each channel.
Table 1. Equalization Setting
Equalizer setting
EQ3
EQ2
EQ1
EQ0
@ 3GHz
@ 4GHz
@ 5GHz
@ 6GHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3.6
4
4.5
5.1
5.6
6.1
6.6
7.1
7.6
8
5.5
6.8
6.2
7.6
4.4
4.7
5.1
5.5
5.9
6.2
6.6
6.9
7.3
7.6
8
6.9
8.4
7.5
9.1
8.1
9.8
8.7
10.4
11
9.2
9.7
11.5
12
8.5
8.9
9.3
9.7
10.1
10.5
10.8
11.1
10.2
10.7
11.1
11.5
11.9
12.3
12.7
13
12.5
12.9
13.3
13.7
14.1
14.4
14.7
8.2
8.6
8.9
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
Flat Gain Setting:
FG[1:0] are the selection bits for the DC value.
Table 2. Flat Gain Setting
Flat Gain Setting
FG1
FG0
dB
0
0
1
1
0
1
0
1
-3.5
-1.5
0.5
2.5
Swing Setting:
Swing Setting: SW[1:0] are the selection bits for the output swing value.
Table 3. Swing Setting
SW1
SW0
mVp-p
0
0
1
1
0
1
0
1
700
800
900
1000
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
I2C Programming
Address assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
1
AD3
AD2
AD1
AD0
1=R, 0=W
BYTE 0 Reserved
BYTE 1 Reserved
BYTE 2
Bit
7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power up condition
Control affected
A3 Power down
A2 Power down
A1 Power down
A0 Power down
Comment
0
0
0
0
0
0
0
0
6
5
4
1 = Power down
3
2
1
0
BYTE 3
Comment
Bit
7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power up condition
Control affected
0
0
0
0
0
0
0
0
EQ3
EQ2
EQ1
EQ0
FG1
FG0
SW1
SW0
6
Equalizer
5
4
Channel A0 configuration
3
Flat gain
Swing
2
1
0
BYTE 4
Comment
Bit
7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power up condition
Control affected
0
0
0
0
0
0
0
0
EQ3
EQ2
EQ1
EQ0
FG1
FG0
SW1
SW0
6
Equalizer
5
4
Channel A1 configuration
3
Flat gain
Swing
2
1
0
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
I2C Programming cont.
BYTE 5
Comment
Bit
7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power up condition
Control affected
EQ3
EQ2
EQ1
EQ0
FG1
FG0
SW1
SW0
0
0
0
0
0
0
0
0
6
Equalizer
5
4
Channel A2 configuration
3
Flat gain
Swing
2
1
0
BYTE 6
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power up condition
Control affected
Comment
7
EQ3
EQ2
EQ1
EQ0
FG1
FG0
SW1
SW0
0
0
0
0
0
0
0
0
6
Equalizer
5
4
Channel A3 configuration
3
Flat gain
Swing
2
1
0
BYTE 7-15 with '0' power up condition Reserved
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
Reset and I2CM Timing Diagram
I2C Operation
2
The integrated I C interface operates as a master or slave device depending on the pin ENI2C being HIZ or HIGH respectively.
Standard mode (100Kbps) is supported with 7-bit addressing. The data byte format is 8-bit bytes, and supports the format of index-
ing to be compatible with other bus devices. In the Slave mode (ENI2C = HIGH), the device supports Read/Write. The bytes must be
accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred.
Address bits A3 to A0 are programmable to support multiple chips environment. The Data is loaded until a Stop sequence is issued.
2
In the master mode (ENI2C = HIZ), PI3EQX1204-C supports up to 16 masters connected in daisy chain through connecting I C_
2
DONE pin to I C_RESET# pin of the next part.
Master EEPROM data starting address for device address:
2
I C address:
AD3, AD2, AD1, AD0
Data starting location
0000
0001
0010
0011
00H
10H
20H
30H
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
40H
50H
60H
70H
80H
90H
A0H
B0H
C0H
D0H
E0H
F0H
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PI3EQX1204-C
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PI3EQX1204-C
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the
2
most significant bit (MSB) first (see the I C Data Transfer diagram). The PI3EQX1204-C will never hold the clock line SCL LOW to
force the master into a wait state.
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge
clock pulse, the PI3EQX1204-C will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
2
during the HIGH period of this clock pulse as indicated in the I C Data Transfer diagram. The PI3EQX1204-C will generate an
acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI3EQX1204-C will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the first data byte following the address byte is an index byte that is used by the PI3EQX1204-C. Data is trans-
ferred with the most significant bit (MSB) first.
I2C Data Transfer
Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the
SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
I2C Data Transfer
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Supply Voltage to Ground Potential . . . . . . . . . . . . . . –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
is is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to V +0.5V
CC
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–25mA to +25mA
Power Dissipation Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1W
Junction Temperature Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
ESD, HBM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2kV to +2kV
Electrical characteristics:
LVCMOS I/O DC Specifications (V
= 3.3 ± 0.3V, T = -40 to 85°C)
A
CC
Symbol
Parameter
Conditions
Min.
Typ.
Typ.
Max
Units
V
V
V
CC
/2 + 0.7
IH
IL
DC input logic high
At IOH = -200µA
At IOL = -200µA
V C + 0.3
V
V
V
V
-0.3
V
OH
V
CC
+ 0.2
V
OL
0.2
V
0.8
= 3.3 ± 0.3V, T = -40 to 85°C)
Hysteresis of Schmitt trigger input
hys
SDA and SCL I/O for I2C-bus (V
CC
A
Symbol
Parameter
Conditions
Min.
Max.
V + 0.3
CC
Units
V
DC input logic high
DC input logic low
V
V
V
CC
/2 + 0.7
IH
V
-0.3
V
CC
/2 - 0.7
IL
V
OL
DC output logic low
I
OL
= 3mA
V
V
0.4
V
hys
Hysteresis of Schmitt trigger input
0.8
Output fall time from VIHmin to
VILmax with bus cap. 10-400pF
t
f
of
SCLK
ns
250
100
SCLK clock frequency
kHz
High speed I/O AC/DC Specifications (V
= 3.3 ± 0.3V, T = -40 to 85°C)
A
CC
Symbol
Parameter
Conditions
Min. Typ. Max. Units
C
RX AC coupling capacitance
220
11.0
5.0
nF
RX
10MHz to 6GHz differential
1GHz to 6GHz common mode
10MHz to 6GHz differential
1GHz to 6GHz common mode
S
11
Input return loss
dB
11.5
4.8
S
22
Output return loss
dB
Ω
DC single-ended input impedance
DC Differential Input Impedance
50
R
IN
100
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PI3EQX1204-C
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PI3EQX1204-C
High speed I/O AC/DC Specifications cont.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
DC single-ended output impedance
DC Differential output Impedance
50
R
Z
Ω
OUT
100
DC input CM input impedance during
reset or power down
200
kΩ
RX-HIZ
Differential Input Peak-to-peak Volt-
age
V
Operational
1.2
150
8
Vppd
mVpp
ns
RX-DIFF-PP
Input source common-mode noise
DC – 200MHz
T
Max time to electrical idle aꢀer send-
ing an EIOS
TX-IDLE-SET-TO-
4
IDLE
T
DATA
Max time to valid diff signal aꢀer leav-
ing electrical idle
TX-IDLE-TO-DIFF-
4
8
ns
Vcc
Power supply voltage
Max Supply power
Max Supply current
Supply power
3
3.3
3.6
1.3
V
W
P
PRSNT#=0
max
I
360
14.4
mA
mW
ns
max
P
PRSNT#=1
idle
t
Latency
From input to output
EQ<3:0> = 1111
EQ<3:0> = 1000
EQ<3:0> = 0000
Variation around typical
FG<1:0> = 11
0.5
15.4
12.5
7.1
pd
Peaking gain (Compensation at 6GHz,
relative to 100MHz, 100mVp-p sine
wave input)
dB
dB
G
G
P
-3
-3
+3
+3
2
0
FG<1:0> = 10
dB
dB
Flat gain (100MHz, EQ<3:0> = 1000,
SW<1:0> = 10)
FG<1:0> = 01
-2
-4
F
FG<1:0> = 00
Variation around typical
SW<1:0> = 11
1370
1280
1040
920
SW<1:0> = 10
-1dB compression point of output
swing (at 100MHz)
V
V
mVppd
1dB_100M
SW<1:0> = 01
SW<1:0> = 00
SW<1:0> = 11
1000
940
SW<1:0> = 10
-1dB compression point of output
swing (at 6GHz)
mVppd
dB
1dB_6G
SW<1:0> = 01
700
SW<1:0> = 00
600
100MHz to 6GHz, Figure 1
(Note 1)
V
Coup
Channel isolation
25
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PI3EQX1204-C
Document number: DS40033 Rev.1-2
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PI3EQX1204-C
High speed I/O AC/DC Specifications cont.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
100MHz to 6GHz, FG<1:0> =
11, EQ<3:0> = 0000, Figure 2
0.5
Vnoise_input
Input-referred noise
mV
mV
RMS
100MHz to 6GHz, FG<1:0> =
11, EQ<3:0> = 1010, Figure 2
0.4
0.7
0.8
100MHz to 6GHz, FG<1:0> =
11, EQ<3:0> = 0000, Figure 2
Vnoise_output
Output-referred noise (Note 2)
RMS
100MHz to 6GHz, FG<1:0> =
11, EQ<3:0> = 1010, Figure 2
1.6
Note: (1) Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. e VNA detects the signal at the output of the
victim channel. All other inputs and outputs are terminated with 50Ω.
(2) Guaranteed by design and characterization.
PI3EQX1204-C
Figure 1. Channel-isolation test configuration
PI3EQX1204-C
Figure 2. Noise test configuration
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ESD Specification
•
•
2000V HBM
500V CDM
Application Diagram
VCC
50 ohm
50 ohm
220nF
220nF
220nF
AXRX+
AXRX-
AXTX+
0-48in
0-48in
AXTX-
220nF
PI3EQX1204-C
AGND
PRSNT#
SCL
VCC
3.3V
0V
SCL
SDA
AGND
SDA
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AC/DC Specifications - SCL/SDA for I2C BUS
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
V
/2 +
CC
0.7
V
IH
DC input logic high
V
CC
+ 0.3
V
V
DC input logic low
-0.3
V
/2 - 0.7
V
V
IL
CC
V
OL
DC output logic low
I
OL
= 3mA
0.4
Current rough Pull-Up Resistor
or Current Source
High Power
specification
Ipullup
3.0
3.6
mA
VDD
Nominal Bus Voltage
3.0
3.6
V
Ileak-bus Input leakage per bus segment
Ileak-pin Input leakage per device pin
-200
200
uA
uA
pF
Hz
-15
CI
Capacitance for SDA/SCL
Bus Operation Frequency
10
Freq
100k
"Bus Free Time
TBUF
1.3
us
us
Between Stop and Start condition"
Hold time aꢀer (Repeated) Start condition.
Aꢀer this period, the first clock is generated.
THD:STA
At Ipull-up, Max 0.6
TSU:STA Repeated start conidtion setup time
TSU:STO Stop condition setup time
THD:DAT Data hold time
0.6
0.6
0
us
us
ns
ns
us
us
ns
ns
TSU:DAT Data setup time
100
1.3
Tlow
igh
tF
Clock low period
Clock high period
Clock/Data fall time
Clock/Data rise time
50
0.6
300
300
tR
"Time in which a device must be operation
aꢀer power-on reset"
tpor
500
ms
Note: (1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Compliant to I2C physical layer specification.
(4) Ensured by Design. Parameter not tested in production.
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May 2017
® Diodes Incorporated
PI3EQX1204-C
Document number: DS40033 Rev.1-2
15
A product Line of
Diodes Incorporated
PI3EQX1204-C
Package Mechanical: 42-Contact TQFN (ZH)
17-0266
Note: For latest package info, please check: https://www.diodes.com/design/support/packaging/pericom-packaging/
Ordering Information
Ordering Number
Package Code
Package Description
PI3EQX1204-CZHE
PI3EQX1204-CZHEX
ZH
ZH
42-Contact, in Fine Pitch Quad Flat No-Lead (TQFN)
42-Contact, in Fine Pitch Quad Flat No-Lead (TQFN), Tape & Reel
Notes:
• ermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
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May 2017
® Diodes Incorporated
PI3EQX1204-C
Document number: DS40033 Rev.1-2
16
A product Line of
Diodes Incorporated
PI3EQX1204-C
IMPORTANT NOTICE
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER
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tice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or
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native format released by Diodes Incorporated.
LIFE SUPPORT
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of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge
and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated
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Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
www.diodes.com
May 2017
® Diodes Incorporated
PI3EQX1204-C
Document number: DS40033 Rev.1-2
17
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