AP9050FDB-7 [DIODES]
PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL; 保护接口的PMIC，带有集成OVP控制
| 型号： | AP9050FDB-7 |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL |
| 文件： | 总9页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Description
Pin Assignments
(Top View)
AP9050 is designed to protect the latest generation of PMICs
for portable applications such as UMPCs, smartphones and
others utilizing battery power.
1
2
3
6
5
4
8
The integrated LDO allows the PMIC to power up and
determine whether the connected power supply (USB or
AC-DC wall adapter) is valid and a safe operation can be
performed.
7
The PMIC controls the operation of the integrated n-channel
MOSFET to either pass the line voltage or disconnect the line
from the PMIC to protect its internal circuits in the event of an
over-voltage.
U-DFN2020-6
The AP9050 is available in a low-profile U-DFN2020-6
package.
Features
Applications
•
•
•
•
•
•
Power Interface for New Generation PMICs
Charger Front End Protection
Smartphone
•
•
Input Supply Range from 3V to 30V
Lower Power Dissipation and Higher Efficiency as
compared to a Zener Shunt Regulator
•
•
LDO is stable without a bypass capacitor on the output
and operates across the temperature range
Cell Phone
Ultra Mobile PC
Available in a U-DFN2020-6 package with a typical
height of 0.575mm
Tablets
Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at
http://www.diodes.com/products/lead_free.html.
Typical Application Circuit
Figure 1. Typical Application Circuit
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March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Pin Descriptions
Pin #
1
Name
Source
Gate
Description
Source of the n-channel power FET. Pass-switch’s output pin.
Gate of the FET switch. Pass-switch’s control pin.
Input voltage to the internal LDO.
2
3, 7
4
VIN
Ground
VOUT
LDO ground connection.
5
Output of the LDO.
6, 8
Drain
Drain of the power FET. Pass-switch’s input pin.
Functional Block Diagram
Figure 2. Functional Block Diagram
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March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Absolute Maximum Ratings (Note 2, 3)
Symbol
VIN
Parameter
Rating
−0.3 to 30
±12
Unit
V
Supply Voltage
VGS
Gate-to-Source Voltage
Drain Current, Peak (10µs pulse)
Drain Current, Continuous
(Note 4, Steady-State)
TA = 25ºC
V
IDpk
19
A
3.7
2.7
ID
A
TA = 85ºC
Total Power Dissipation @ TA = 25°C
(Note 3, 4)
Pmax
750
mW
TJ
TJ
Junction Temperature Range
Non-operating Temperature Range
−40 to +125
−55 to +150
°C
°C
Maximum Lead Temperature for Soldering
Purposes
TL
260
°C
Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and
transporting these devices.
Notes:
2. Exceeding these ratings may damage the device.
2
3. Mounted on FR4 Board using 30 mm , 2 oz Cu.
4. Dual die operation (equally−heated).
Thermal Resistance
Symbol
Parameter
Rating
132
Unit
°C/W
°C/W
θJA
θJC
Junction to Ambient (Note 5)
Junction to Case
13
2
Note: 5. Test condition for DFN2020-6: Mounted on FR4 Board using 30 mm , 2 oz Cu.
Recommended Operating Conditions (Note 6)
Symbol
VIN
Parameter
Min
3
Max
30
Unit
V
Supply Voltage
Operating Ambient Temperature Range
TA
+85
°C
−40
Note: 6. The device function is not guaranteed outside of the recommended operating conditions.
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www.diodes.com
March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Electrical Characteristics (VIN (OVP_SENSE) = 5.0V, TJ = +25°C, unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ.
Max
Unit
Power FET
VDS = 24V, VGS = 0V
TJ = 85°C
1.0
10
IDSS
Zero Gate Voltage Drain Current
µA
IGSS
Gate-to-Source Leakage Current
Gate Threshold Voltage
VDS = 0V, VGS = ±8V
VGS = VDS, ID = 250µA
VGS = 4.5V, ID = 2.0A
80
nA
V
VGS(th)
0.62
0.9
1.2
41
55
53
68
Drain-to-Source On-Resistance
(Note 7)
RDS(on)
gFS
mΩ
S
V
GS = 2.5V, ID = 2.0A
Forward Transconductance
VDS = 5V, ID = 2.0A
VDS = 15V, VGS = 0V,
f = 1MHz
8
CISS
Input Capacitance
500
pF
VDS = 15V, VGS = 0V,
f = 1MHz
COSS
CRSS
Output Capacitance
65
50
pF
pF
VDS = 15V, VGS = 0V,
f = 1MHz
Reverse Transfer Capacitance
LDO (unless otherwise noted, TJ = 25ºC, VIN = 5.0V)
VOUT
Regulated Output Voltage
VIN = 5.5V, IOUT = 1mA
4.6
5.0
5.3
V
VIN − VOUT, IOUT = 1.2mA,
150
mV
V
IN = 4.6V
Vhead
Headroom
VIN − VOUT, IOUT = 10mA,
1000
mV
VIN = 4.8V, TJ = −40 to +125°C
Response to Input Transient
tpulse
Time signal is above 5.5V
Vpk
VIN 0 to 30V, < 1µs rise time,
5.0kΩ resistive load (Note 8)
VIN 0 to 30V, < 1µs rise time,
5.0kΩ resistive load (Note 8)
5.0
9.0
µs
V
Peak Voltage
Total Device
Ibias
Input Bias Current
VIN = 5.5V
110
850
3.0
µA
V
VIN_min
Minimum Operating Voltage
Notes:
7. Pulse test width 300µs, duty cycle 2%
8. Guaranteed by design
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www.diodes.com
March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Typical Performance Characteristics
1.6
1.5
VGS=4.5V
1.4
1.3
1.2
1.1
1
ID=2A
0.9
0.8
0.7
0.6
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ºC)
Figure 3. RDS(ON) variation over junction temperature
20
VGS=10V
VGS=2.5V
18
16
14
12
10
8
VGS=3V
VGS=2V
6
4
2
VGS=1.5V
0
0
1
2
3
4
5
Drain-Source Voltage (V)
Figure 4. RDS(ON) Characteristics
5.2
5.15
5.1
5.05
5
4.95
4.9
4.85
4.8
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ºC)
Figure 5. Output voltage variation over junction temperature
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March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Applications Information
Theory of Operation
External Capacitors
The AP9050 was designed to work in close relationship
with a PMIC (Power Management IC). To protect the
PMIC from an overvoltage situation the AP9050 powers up
a detection circuit within the connected PMIC. (See Figure
2 as reference)
AP9050 was specified to reduce board space and external
component count, by designing the LDO to be stable
without an external bypass capacitor.
A low ESR 1nF to 10nF external capacitor can be used to
improve behavior with fast ac transients or other switching
currents that might be present.
This detection circuit determines if a valid input source is
connected (ex. VIN < 8V). If a valid input source is detected
the power MOSFET will be turned on and the supply
current to the PMIC will be turned on. The overvoltage
detection is continuous, if an overvoltage occurs at a later
state the Power MOSFET will be turned off.
To improve noise immunity and ac impedance from long
input traces a 1nF capacitor can be added to the input VIN
of the LDO.
PCB Layout
The AP9050 was designed utilizing two process
technologies to provide best performance and a cost
effective solution.
1
2
3
6
5
4
8
7
Figure 6. Package Pin Out
Both die are packaged side by side in the U-DFN2020-6
package and are mounted on two separate exposed pads.
These pads are not required for electrical functionality, but
to aid with the thermal performance of AP9050.
Attention should be paid in the layout of the PCB (Printed
Circuit Board) that PAD7 is connected to VIN of the LDO,
pin 3, while PAD8 is connected to the Drain of the Power
MOSFET, pin 6 of the package. For best thermal
performance large copper areas connected to the two
exposed pads should be used to transfer heat away from
the AP9050.
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www.diodes.com
March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Ordering Information
AP9050FDB-7
Package
Packing
FDB
U-DFN2020-6
7” Tape and Reel
Packaging
(Note 10)
Package
Code
Device
Quantity
3000/Tape & Reel
Part Number Suffix
AP9050FDB-7
FDB
U-DFN2020-6
-7
Note: 10. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
Marking Information
U-DFN2020-6
( Top View )
XX : Identification Code
Y : Year : 0~9
X X
Y X
W : Week : A~Z : 1~26 week;
W
a~z : 27~52 week; z represents
52 and 53 week
X : A~Z : Internal code
Device
AP9050FDB
Package
Identification Code
U-DFN2020-6
BZ
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March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Package Outline Dimensions (All Dimensions in mm)
U-DFN2020-6
Marking
0.05 C
0.08 C
(Active area depth)
Seating plane
1.05
2x-0.70
C
C
L
1.95/2.075
2x-0.5/0.7 0.45
A
B
C
L
0.65
6x-0.3
Top View
Land Pattern Recommendation
unit:mm
0.15 C
2x-
0.65nom.
0.2/0.3
0.05
M C A B
Bottom View
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March 2011
© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS
DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other
changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability
arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any
license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described
herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies
whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized
sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall
indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names
and markings noted herein may also be covered by one or more United States, international or foreign trademarks.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without
the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided
in the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements
concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems,
notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further,
Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2011, Diodes Incorporated
www.diodes.com
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© Diodes Incorporated
AP9050
Document number: DS35283 Rev. 1 - 2
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