AM24LC16S_技术文档

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Features

ꢀ General Description

• State- of- the- Art Architecture

- Non-volatile data storage

The AM24LC16 is a non-volatile, 16384-bit serial

EEPROM with enhanced security device and

conforms to all specifications in I²C 2 wire protocol.

The whole memory can be disabled (Write Protected)

by connecting the WP pin to Vcc. This section of

memory then becomes unalterable unless WP is

switched to Vss. The AM24LC16's communication

protocol uses CLOCK (SCL) and DATA I/O (SDA)

lines to synchronously clock data between the

master (for example: a microcomputer)and the slave

EEPROM devices (s).

- Full range Vcc = 2.7V to 5.5V

• 2 wire I²C serial interface

- Provides bi-directional data transfer protocol

• Hard-ware Write Protection

- With WP PIN to disable programming command

• 16 bytes page write mode

- Minimizes total write time per word

• Self-timed write-cycle(including auto-erase)

• Durable and Reliable

- 40 years data retention

Anachip EEPROMs are designed and tested for

application requiring high endurance, high reliability,

and low power consumption.

- Minimum of 1M write/erase cycles per word

- Unlimited read cycles

- ESD protection

• Low standby current

• Package: PDIP-8L, SOP-8L

ꢀ Pin Assignments

ꢀ Connection Diagram

Name

NC

Description

No connect

Ground

NC

1

2

3

4

8

7

6

5

VCC

WP

VSS

SDA

SCL

WP

Data I/O

NC

SCL

SDA

Clock input

Write protect

Power pin

VSS

VCC

PDIP / SOP

ꢀ Ordering Information

16 X X X

AM 24 LC

Type

16 =16K

Temp. grade

o

Packing

Operating Voltage

Package

o

Blank : Tube

A: Taping

0 C ~ +70 C

S : SOP-8L

N: PDIP-8L

Blank :

LC: 2.7~5.5V, CMOS

o

I

:

− 40 C ~ +85 C

o

V

− 40 C ~ +125 C

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of

this product. No rights under any patent accompany the sale of the product.

Rev.A1 Oct 20, 2003

1/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Block Diagrams

WP

start cycle

H.V.

GENERATION

TIMING

CONTROL

LOGIC

START

STOP

SDA

SCL

LOGIC

&

ck

CONTROL

load

inc

SLAVE

WORD

ADDRESS

REGISTER

&

ADDRESS

COUNTER

EEPROM

ARRAY

COMPARATOR

XDEC

128x16x8

R/W ~ , device address bit A0

YDEC

DATA

Din

REGISTER

VCC

VSS

Dout

DOUT

ACK

ꢀ Absolute Maximum Ratings

Characteristics

Symbol

T_S

Values

Unit

Storage Temperature

-65 to + 125

°C

Voltage with Respect to Ground

-0.3 to + 6.5

V

NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage

the part. Prolonged exposure to maximum ratings may affect device reliability.

ꢀ Operating Conditions

Temperature under bias

Values

Unit

AM24LC16

AM24LC16I

AM24LC16V

0 to + 70

-40 to + 85

-40 to +125

°C

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

2/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Electrical Characteristics

o

(Vcc =2.7~5.5V, Ta = 25 C )

DC Electrical Characteristics

Parameter

AM24LC16

Symbol

Conditions

Units

Min

—

Max

Operating Current (Program) **

Operating Current (Read) **

Standby Current

Input Leakage

SCL = 100KHZ CMOS Input Levels

SCL=SDA=0V, Vcc=5V

SCL=SDA=0V, Vcc=3V

VIN = 0 V to VCC

3

200

10

mA

µA

V

I_CC1

I_CC2

I_SB1

I_SB2

I_IL

—

1

-1

+1

Output Leakage

I_OL

V_IL

V_IH

V_OL1

V_OL2

VOUT = 0 V to Vcc

Input Low Voltage**

Input High Voltage**

Output Low Voltage

-0.1

Vcc x 0.3

Vcc x 0.7 V_CC+ 0.2

V

IOL = 2.1mA TTL

IOL = 10uA CMOS

—

0.4

0.2

Programming Command Can Be

Executed

VCC Lockout Voltage

V_LK

Default

—

V

Note ** : I_CC1, I_CC2, V_ILmin and V_IHmax are for reference only and are not tested.

ꢀ Switching Characteristics ^{(Under Operating Conditions)}

AC Electrical Characteristics (Vcc =2.7~5.5V)

AM24LC16

Parameter

Symbol

Units

Min

0

Max

Clock frequency

Fscl

Thigh

Tlow

100

—

kHz

ns

ms

Clock high time

4000

4700

—

Clock low time

—

SDA and SCL rise time**

SDA and SCL fall time**

START condition hold time

START condition setup time

Data input hold time

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time **

Tr

1000

300

—

Tf

—

Thd:Sta

Tsu:Sta

Thd:Dat

Tsu:Dat

Tsu:Sto

Taa

4000

4700

0

—

250

4000

300

4700

300

—

3500

—

Tbuf

Data out hold time

Tdh

—

Write cycle time

Twr

10

5V, 25ºC, Byte Mode

Endurance**

1M

—

write cycles

Note **: This parameter is characterized and is not 100% tested.

Capacitance TA= 25°C , f=250KHz

Parameter

Output capacitance

Input capacitance

Symbol

C_OUT

Max

5

Units

pF

C_IN

5

pF

AC. Conditions of Test

Input Pulse Levels

Vcc x 0.1 to Vcc x 0.9

Input Rise and Fall times

Input and Output Timming level

Output Load

10 ns

Vcc x 0.5

1 TTL Gate and CL = 100pf

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

3/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Pin Descriptions

Table A

Device

Serial Clock (SCL)

The SCL input is used to clock all data into and out

of the device.

A0

ADR

XP

A1

ADR

XP

A2

ADR

XP

AM24LC02

AM24LC04

AM24LC08

AM24LC16

Serial Data (SDA)

XP

SDA is a bidirection pin used to transfer data or

security bit into and out of the device.

XP

ADR indicates the device address pin.

It is an open drain output and may be wire-ORed

with any number of open drain or open collector

outputs. Thus, the SDA bus requires a pull-up

resistor to Vcc (typical 4.7KΩ for 100KHz, 1 KΩ

for 400KHz).

XP indicates that device address pin don’t care but

refers to an internal PAGE BLOCK memory

segment.

Write Protection (WP)

If WP is connected to Vcc, PROGRAM operation

onto the whole memory will not be executed. READ

operations are possible. If WP is connected to Vss,

normal memory operation is enabled, READ/WRITE

over the entire memory is possible.

Device Address Inputs (A0, A1, A2)

The following table (Table A) shows the active pins

across the AM24LCXX device family.

ꢀ Functional Description

are reserved for indicating start and stop conditions.

(Shown in Figures 1 and 2)

Applications

ATC’s electrically erasable programmable read only

memories (EEPROMs) offer valuable security

features including write protect function , two write

modes ,three read modes, and a wide variety of

Start Condition

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START

condition. (Shown in Figure 2)

memory size. Typical applications for the I²C bus

and AM24LCXX memories are included in

SANs(small-area-networks), stereos, televisions,

automobiles and other scaled-down systems that

don't require tremendous speeds but instead cost

efficiency and design simplicity.

Stop Condition

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition.

All operations must be ended with a STOP condition.

(Shown in Figure 2)

Endurance and Data Retention

The AM24LC16 is designed for applications

requiring up to 1KK programming cycles (BYTE

WRITE and PAGE WRITE). It provides 40 years of

secure data retention without power.

Acknowledge

Each receiving device, when addressed, is obliged

to generate an acknowledge after the reception of

each byte. The master device must generate an

extra clock pulse which is associated with this

acknowledge bit. The device that acknowledges,

has to pull down the SDA line during the

acknowledge clock pulse in such a way that the

SDA line is stable LOW during the HIGH period of

the acknowledge related clock pulse. Of course,

setup and hold times must be taken into account. A

master must signal an end of data to the slave by

not generating an acknowledge bit on the last byte

that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable

the master to generate the STOP condition. (Shown

in Figure 3)

Device Operation

The AM24LC16 supports

a

bidirectional bus

oriented protocol. The protocol defines any device

that sends data onto the bus as a transmitter and

the receiving device as the receiver. The device

controlling the transfer is the master and the device

that is controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

AM24LC16 is considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

4/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Functional Description (Continued)

The AM24LC16 monitors the bus for its

corresponding slave address all the time. It

generates an acknowledge bit if the slave address

was true and it is not in a programming mode.

Devices Addressing

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit

device code (1010) for the AM24LC16, 3-bit page

address (A2 A1 A0) and 1-bit value indicating the

Table B

2

read or write mode. All I C EEPROMs use and

Chip

internal protocol that defines a PAGE BLOCK size of

16K bits. The eighth bit of slave address determines

if the master device wants to read or write to the

AM24LC16. (Refer to table B).

Operation Control Code

R/W

Select

Read

Write

1010

A2 A1 A0

1

0

A0, A1, A2 is no connect

ꢀ Write Operations

Byte Write

Acknowledge Polling

Following the start signal from the master, the slave

address is placed onto the bus by the master

transmitter. This indicates to the addressed slave

receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle.

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle

is complete (this feature can be used to maximize

bus throughout). Once the stop condition for a write

command has been issued from the master, the

device initiates the internally timed write cycle. ACK

polling can be initiated immediately. This involves

the master sending a start condition followed by the

control byte for a write command (R/W = 0). If the

device is still busy with the write cycle, then no ACK

will returned. If the cycle is complete then the device

will return the ACK and the master can then proceed

with the next read or write commands.

Therefore the next byte transmitted by the master is

the word address and will be written into the address

pointer of the AM24LC16. After receiving another

acknowledge signal from the AM24LC16 the master

device will transmit the data word to be written into

the addressed memory location. The AM24LC16

acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this period the AM24LC16 will not

generate acknowledge signals. (Shown in Figure 4)

Page Write

Write Protection

Programming will not take place if the WP pin of the

AM24LC16 is connected to Vcc. The AM24LC16 will

accept slave and byte addresses; but if the memory

accessed is write protected by the WP pin, the

AM24LC16 will not generate an acknowledge after

the first byte of data has been received, and thus the

programming cycle will not be started when the stop

condition is asserted.

The write control byte, word address and the first

data byte are transmitted to the AM24LC16 in the

same way as in a byte write. But instead of

generating a stop condition the master transmit up

to 16 data bytes to the AM24LC16 which are

temporarily stored in the on-chip page buffer and will

be written into the memory after the master has

transmitted a stop condition. If the master transmits

more than 16 bytes prior to generating the stop

condition, the address counter will roll over and the

previously received data will be overwritten. As with

the byte write operation, once the stop condition is

received an internal write cycle will begin. (Shown in

Figure 5).

Read Operations

Read operations are initiated in the same way as

write operations with the exception that the R/W bit

of the slave address is set to one. There are three

basic types of read operations: current address read,

random read, and sequential read.

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

2/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Write Operations (Continued)

Then the master issues the control byte again but

with R/W bit set to a one. The AM24LC16 will then

issue an acknowledge and transmit the eight bit data

word. The master will not acknowledge the transfer

but does generate a stop condition and the

AM24LC16 discontinues transmission. (Shown in

Figure 7)

Current Address Read

The AM24LC16 contains an address counter that

maintains the address of the last accessed word,

internally incremented by one. Therefore if the

previous access (either a read or write operation )

was to address n, the next current address read

operation would access data from address n + 1.

Upon receipt of the slave address with R/W bit set to

one, the AM24LC16 issues an acknowledge and

transmits the eight bit data word . The master will

not acknowledge the transfer but does generate a

stop condition and the AM24LC16 discontinues

transmission. (Shown in Figure 6)

Sequential Read

Sequential read is initiated in the same way as a

random read except that after the AM24LC16

transmits the first data byte, the master issues an

acknowledge as opposed to a stop condition in a

random read. This directs the AM24LC16 to transmit

the next sequentially addressed 8 bit byte (Shown in

Figure 8). To provide sequential read the

AM24LC16 contains an internal address pointer

which is incremented by one at the completion of

each operation.

Random Read

Random read operations allow the master to access

any memory location in a random manner. To

perform this type of read operation, first the word

address must be set. This is done by sending the

word address to the AM24LC16 as part of a write

operation. After the word address is sent, the master

Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operation even on a noisy bus.

generates

a

start condition following the

acknowledge. This terminates the write operation,

but not before the internal address pointer is set.

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

6/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Timing Diagram

Bus Timing

Thigh

Tf

Tr

Tlow

SCL

Thd:Sta

Tsu:Dat

Tsu:Sta

Thd:Dat

Tsu:Sta

SDA

IN

Tbuf

Taa

Tdh

SDA

OUT

SDA

SCL

DATA

DATA STABLE

CHANGE

Figure 1. Data Validity

SDA

SCL

START

BIT

STOP

BIT

Figure 2. Definition of Start and Stop

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

7/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

SCL FROM MASTER

1

8

9

DATA OUTPUT FROM

TRANSMITTER

DATA OUTPUT FROM

RECEIVER

ACKNOWLEDGE

START

Figure 3. Acknowledge Response from Receiver

SLAVE

BYTE

BUS ACTIVITY

MASTER

START

S

DATA n

ADDRESS

STOP

SDA

LINE

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

SLAVE

Figure 4. Byte Write for Data

SLAVE

ADDRESS

BYTE

START

S

DATA n

DATA n+15

BUS ACTIVITY

MASTER

ADDRESS n

STOP

P

SDA

LINE

A

C

K

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

SLAVE

Figure 5. Page Write for Data

SLAVE

START

BUS ACTIVITY

MASTER

ADDRESS

STOP

SDA

LINE

s

P

NO

A

C

K

BUS ACTIVITY

SLAVE

A

C

K

DATA

Figure 6. Current Address Read for Data

SLAVE

BYTE

SLAVE

BUS ACTIVITY

START

S

STOP

P

ADDRESS

ADDRESS n

ADDRESS

MASTER

SDA

S

LINE

A

C

K

A

C

K

A

C

K

NO

BUS ACTIVITY

SLAVE

A

C

K

DATA n

Figure 7. Random Read for Data

SLAVE

ADDRESS

START

A

C

K

BUS ACTIVITY

MASTER

A

C

K

STOP

P

SDA

S

LINE

A

C

K

NO

BUS ACTIVITY

SLAVE

DATA n+1

DATA n

DATA n+x

A

C

K

Figure 8. Sequential Read for Data

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

8/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

ꢀ Package Diagrams

(1)Plastic Dual-in-line package: PDIP-8L

D

E-PIN O0.118 inch

E

(4X)

15

PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch

C

7

(4X)

eB

B

B1

e

S

B2

Dimensions in millimeters

Dimensions in inches

Symbol

Min.

-

Nom.

-

Max.

5.33

-

Min.

Nom.

-

Max.

A

A1

A2

B

B1

B2

C

D

E

E1

e

L

-

0.210

-

0.38

3.1

0.36

1.4

0.81

0.20

9.02

7.62

6.15

-

2.92

8.38

0.71

-

0.015

0.122

0.014

0.055

0.032

0.008

0.355

0.300

0.242

-

3.30

0.46

1.52

0.99

0.25

9.27

7.94

6.35

2.54

3.3

3.5

0.130

0.018

0.060

0.039

0.010

0.365

0.313

0.250

0.100

0.130

0.350

0.033

0.138

0.022

0.065

0.045

0.014

0.375

0.325

0.258

-

0.56

1.65

1.14

0.36

9.53

8.26

6.55

-

3.81

9.40

0.97

0.115

0.330

0.028

0.150

0.370

0.038

eB

S

8.89

0.84

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

9/10

ATC

2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM

AM24LC16

(2) JEDEC Small Outline Package: SOP-8L

L

VIEW "A"

D

0.015x45

(4X)

e

(4X)

7

B

VIEW "A"

y

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min.

1.40

0.10

1.30

0.33

0.19

4.80

3.70

-

Nom.

1.60

-

Max.

1.75

0.25

1.50

0.51

0.25

5.30

4.10

-

6.20

1.27

0.10

8^O

Min.

Nom.

0.063

-

Max.

0.069

A

A1

A2

B

C

D

E

e

H

L

0.055

0.040

0.051

0.013

0.0075

0.189

0.146

-

0.100

0.059

0.020

0.010

0.209

0.161

-

0.244

0.050

0.004

8^O

1.45

0.41

0.20

5.05

3.90

1.27

5.99

0.71

-

0.057

0.016

0.008

0.199

0.154

0.050

0.236

0.028

-

5.79

0.38

-

0.228

0.015

-

y

θ

0^O

-

0^O

-

ꢀ Marking Information

Top view

Logo

ATC

Part Number & grade

X = Blank ( 0 ~ + 70 C)

24LC16 X

o

XX

XX X

o

=

I

V

( - 40 ~ +85 C)

( - 40 ~ +125 C)

ID code: internal

Nth week: 01~52

o

Year: "01" = 2001

"02" = 2002

PDIP/SOP

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

10/10


型号：	AM24LC16S
厂家：	DIODES INCORPORATED
描述：	EEPROM, 2KX8, Serial, CMOS, PDSO8, SOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
文件：	总10页 (文件大小：203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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