74LVC574AQ20-13 [DIODES]
Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, 2.50 X 4.50 MM, 0.95 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFN-20;
| 型号： | 74LVC574AQ20-13 |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, 2.50 X 4.50 MM, 0.95 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFN-20 驱动 逻辑集成电路 |
| 文件： | 总11页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC574A
OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS
Description
Pin Assignments
The 74LVC574A provides eight edge-triggered D-type flip-flops
featuring 3-state outputs designed specifically for driving highly
capacitive or relatively low-impedance loads. These devices are
particularly suitable for implementing buffer registers, input/output (I/O)
ports, bidirectional bus drivers, and working registers. On the positive
transition of the clock (CLK) input, the Q outputs are set to the logic
levels set up at the data (D) inputs. A buffered output-enable (OE)
input can be used to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be
retained or new data can be entered while the outputs are in the high-
impedance state.
Applications
These devices feature inputs and outputs on opposite sides of the
package that facilitate printed circuit board layout.
•
•
•
•
General Purpose Logic
Bus Driving
The device is designed for operation with a power supply range of
1.65V to 3.6V. The device is fully specified for partial power down
Power Down Signal Isolation
Wide Array of Products Such as:
applications using IOFF
.
PCs, Notebooks, Netbooks, Ultrabooks
Networking Computer Peripherals, Hard Drives, CD/DVD
ROM
Features
•
•
•
•
•
•
Supply Voltage Range from 1.65V to 3.6V
TV, DVD, DVR, set top box
Sinks or Sources 24mA at VCC = 3V
CMOS Low Power Consumption
I
OFF Supports Partial-Power Down Operation
Inputs or Outputs Accept Up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage
Applications
•
•
Schmitt Trigger Action at All Inputs
Typical VOLP (Quiet Output Ground Bounce) less than 0.8V with
VCC = 3.3V and TA = +25°C
•
•
Typical VOHV (Quiet Output Dynamic VOH) greater than 2.0V
with VCC = 3.3V and TA = +25°C
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
•
•
Latch-Up Exceeds 250mA per JESD 78, Class I
All devices are:
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free,
"Green" and Lead-Free.
3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
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74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Ordering Information
74 LVC 574A xxx -13
Logic Device
Function
Package
Packing
74 : Logic Prefix
574 :
Octal D-Type
Flip-Flop with 3
State Outputs
T20 : TSSOP-20
Q20 : QFN-20
-13 : 13” Tape & Reel
Package
Size
13” Tape and Reel
Package
(Note 4 & 5)
Package
Part Number
Code
Quantity
Part Number Suffix
6.4mm X 6.5mm X 1.2mm
0.65 mm lead pitch
74LVC574AT20-13
74LVC574AQ20-13
T20
Q20
TSSOP-20
2500/Tape & Reel
2500/Tape & Reel
-13
2.5mm X 4.5mm X 0.95mm
0.50 mm lead pitch
V-QFN4525-20
-13
Notes:
4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
5. V-QFN4525-20 is a JEDEC recognized naming convention that specifies the package thickness category as V and the number 4525 describes the
package as 4.5mm X 2.5mm.
Pin Descriptions
Logic Diagram
Function Table
(Each Latch)
INPUTS
Pin
Number
Pin
Name
Description
OUTPUT
Q
CLK
D
H
L
OE
1
Output Enable
OE
D1
L
H
L
2
3
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Data Input
Ground
↑
↑
H or L
X
D2
L
4
D3
L
H
X
X
Q0
Z
5
D4
6
D5
7
D6
8
D7
9
D8
10
11
12
13
14
15
16
17
18
19
20
GND
CLK
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Vcc
Clock
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Latch Output
Supply Voltage
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74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Absolute Maximum Ratings (Notes 6 & 7)
Symbol
ESD HBM
ESD CDM
ESD MM
VCC
Description
Rating
Unit
kV
kV
V
Human Body Model ESD Protection
Charged Device Model ESD Protection
Machine Model ESD Protection
Supply Voltage Range
2
1
200
-0.5 to +7.0
-0.5 to +7.0
V
Input Voltage Range
V
VI
-20
-50
mA
mA
mA
mA
mA
°C
IIK
Input Clamp Current VI < 0V
IOK
Output Clamp Current VO < 0V
Continuous Output Current -0.5V < VO VCC +0.5V
Continuous Current Through VCC
Continuous Current Through GND
Operating Junction Temperature
Storage Temperature
±50
IO
100
ICC
-100
IGND
TJ
-40 to +150
-65 to +150
500
°C
TSTG
PTOT
Total Power Dissipation
mW
Notes:
6. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values.
7. Forcing the maximum allowed voltage could cause a condition exceeding the maximum current or conversely forcing the maximum current could
cause a condition exceeding the maximum voltage. The ratings of both current and voltage must be maintained within the controlled range.
Recommended Operating Conditions (Note 8)
Symbol
Parameter
Conditions
Min
1.65
1.5
0
Max
3.6
—
Unit
V
Operating
Supply Voltage
VCC
Data Retention Only
V
—
—
Input Voltage
5.5
V
VI
Output Voltage
0
—
—
—
—
—
—
—
—
—
-40
V
VO
VCC
-4
VCC = 1.65V
-8
VCC = 2.3V
VCC = 2.7V
VCC = 3.0V
VCC = 1.65V
VCC = 2.3V
VCC = 2.7V
VCC = 3.0V
High-Level Output Current
Low-Level Output Current
mA
IOH
-12
-24
4
8
mA
IOL
12
24
10
+125
∆t/∆V
Input Transition Rise or Fall Rate
Operating Free-Air Temperature
ns/V
°C
TA
Note:
8. Unused inputs should be held at VCC or Ground.
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74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Electrical Characteristics
TA = -40°C to +85°C
TA = -40°C to +125°C
Symbol
Parameter
Test Conditions
Unit
VCC
Min
Max
—
Min
VCC X 0.65
1.7
Max
1.65V to 1.95V
2.3V to 2.7V
3.0V to 3.6V
1.65V to 1.95V
2.3V to 2.7V
3.0V to 3.6V
1.65V to 3.6V
1.65V
—
V
CC X 0.65
High-Level Input
Voltage
V
V
VIH
1.7
2
—
—
—
2
—
—
—
—
—
V
CC X 0.35
0.7
0.8
—
VCC X 0.35
Low-Level Input
Voltage
VIL
—
0.7
0.8
—
—
IOH = -50μA
IOH = -4mA
IOH = -8mA
VCC -0.2
1.2
VCC -0.3
1.05
1.65
2.05
2.48
2.0
—
—
2.3V
1.7
—
—
High-Level
Output Voltage
VOH
2.7V
2.2
—
—
V
V
IOH = -12mA
IOH = -24mA
3.0V
2.4
—
—
3.0V
2.3
—
—
1.65V to 3.6V
—
0.2
—
0.3
I
OL = 100μA
IOL = 4mA
IOL = 8mA
1.65V
2.3V
2.7V
3.0V
—
—
—
—
0.45
0.60
0.40
0.55
—
—
—
—
0.65
0.80
0.60
0.80
Low-Level Output
Voltage
VOL
IOL = 12mA
IOL = 24mA
Power Down
Leakage Current
0V
—
—
±10
±5
—
—
20
μA
μA
IOFF
II
VI or VO = 0 or 5.5V
VI = GND or 5.5V
Input Current
Control Pins
0 to 3.6V
±20
Z-State Current
including Input
Current
VI = GND or 5.5V
VO = 0 to 5.5V
3.6V
—
±5
—
±20
µA
IOZ
I/O Pins
Supply Current
3.6V
—
—
10
—
—
40
μA
μA
ICC
VI = GND or VCC, IO = 0
Additional Supply
Current
2.7V to 3.6V
500
5000
ꢀICC
One Input at VCC -0.6V IO = 0A
Control Pins
VI = GND or VCC
I/O Pins
4.0 typical
5.5 typical
4.0 typical
5.5 typical
Input
Capacitance
0V to 3.6V
pF
Ci
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74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Switching Characteristics
TA = -40°C to
+85°C
TA = -40°C to
+125°C
TA = +25°C
Test
Conditions
Symbol
Parameter
Unit
VCC
Min
35
Typ
40
Max
Min
35
Max
Min
30
Max
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
50
60
50
45
Figure 1
Maximum
Frequency
Mhz
fMAX
80
100
125
2.5
2.0
1.7
1.5
2.0
1.5
1.0
1.0
1.5
1.0
1.0
1.0
6.0
3.9
4.2
3.8
7.8
4.0
4.4
4.1
7.8
4.0
4.4
4.1
7.8
4.0
4.4
4.1
80
64
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
100
5.0
4.0
3.3
3.0
4.0
3.0
2.0
2.0
3.0
2.0
1.5
1.5
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
100
5.0
4.0
3.3
3.0
4.0
3.0
2.0
2.0
3.0
2.0
1.5
1.5
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
80
5.5
4.5
3.5
3.5
4.5
3.5
2.5
2.5
3.5
2.5
2.0
2.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
1.0
1.0
1.0
1.7
Pulse Width
CLK
Figure 1
Figure 1
Figure 1
Figure 1
ns
ns
ns
ns
ns
ns
tW
tSU
tH
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
Set-up Time DN
to CLK
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
Hold Time
DN to CLK
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
15.1
8.8
15.7
9.0
16.9
10.5
10.0
8.1
Propagation
Delay
tPD
tEN
tDIS
8.1
9.4
CLK to QN
3.3V ± 0.3V
1.8V ± 0.15
2.5V ± 0.2V
2.7V
7.1
7.6
16.5
9.0
17.0
9.5
18.4
10.5
10.0
9.0
Enable Time
OE to QN
Figure 1
Figure 1
Figure 1
8.3
8.5
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
7.3
7.5
16.5
9.0
17.0
9.5
18.4
10.5
10.0
9.0
Disable Time
OE to QN
8.3
8.5
3.3V ± 0.3V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
7.3
7.5
16.5
9.0
17.0
9.5
18.4
10.5
10.0
9.0
Disable Time
OE to QN
ns
ns
tDIS
8.3
8.5
3.3V ± 0.3V
7.3
7.5
Output Skew
Time
tsk(0)
3.3V ± 0.3V
1.0
1.5
Operating Characteristics
TA = +25°C
Symbol
Parameter
Test Conditions
Typ
Unit
VCC
1.8V ± 0.15V
2.5V ± 0.2V
3.3V ± 0.3V
9.9
Power dissipation
capacitance per gate
F = 10 MHz
10.2
10.6
pF
Cpd
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© Diodes Incorporated
74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Package Characteristics
Symbol
Parameter
Package
Test Conditions
Min
Typ
Max
Unit
Thermal Resistance
Junction-to-Ambient
TSSOP-20
(Note 9)
—
74
—
°C/W
θJA
Thermal Resistance
Junction-to-Case
TSSOP-20
(Note 9)
(Note 9)
(Note 9)
—
—
—
15
67
20
—
—
—
°C/W
°C/W
°C/W
θJC
θJA
θJC
Thermal Resistance
Junction-to-Ambient
V-QFN4525-20
V-QFN4525-20
Thermal Resistance
Junction-to-Case
Note:
9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended
pad layout per JESD 51-7.
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Document number: DS35898 Rev. 1 - 2
74LVC574A
Parameter Measurement Information
VLOAD
S1
Open
GND
RL
From Output
Under Test
CL
RL
(see Note A)
Inputs
VCC
VM
VLOAD
CL
RL
V∆
VI
tr/tf
VCC
VCC
2.7V
2.7V
VCC/2
VCC/2
1.5V
2 x VCC
2 x VCC
6V
1.8V ± 0.15V
2.5V ± 0.2V
2.7V
≤ 2ns
≤ 2ns
30pF
30pF
50pF
50pF
1KΩ
500Ω
500Ω
500Ω
0.15V
0.15V
0.3V
≤ 2.5ns
≤ 2.5ns
3.3V ± 0.3V
1.5V
6V
0.3V
Voltage Waveform Pulse Duration
Voltage Waveform Enable and Disable Times
Low and High Level Enabling
Voltage Waveform Propagation Delay Times
Inverting and Non Inverting Outputs
Notes:
A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10 MHz.
C. Inputs are measured separately one transition per measurement.
D. tPLZ and tPHZ are the same as tdis.
E. tPZL and tPZH are the same as tEN0
F. tPLH and tPHL are the same as tPD.
Figure 1 Load Circuit and Voltage Waveforms
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74LVC574A
Document number: DS35898 Rev. 1 - 2
74LVC574A
Marking Information
(1) TSSOP20
74LVC574A
Part Number
Package
74LVC574AT20
TSSOP-20
(2) QFN-20 (V-QFN4525-20)
74LVC574A
Part Number
Package
74LVC574AQ20
V-QFN4525-20
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74LVC574A
Package Outline Dimensions
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version.
(1) TSSOP-20
D
TSSOP-20
Dim
A
A1
A2
b
c
D
E
E1
e
Min
-
Max
1.20
0.15
1.05
0.30
0.20
6.60
6.60
4.50
Typ
-
-
-
-
-
6.50
6.40
4.40
0.05
0.80
0.19
0.09
6.40
6.20
4.30
θ2
E1
E
0.25
Gauge Plane
θ3
PIN 1
ID MARK
0.65 BSC
0.75
Seating Plane
L
0.45
0.60
θ1
e
L
L1
θ1
θ2
θ3
1.0 REF
8°
DETAIL
0°
10°
10°
-
L1
14°
14°
12°
12°
A2
A
All Dimensions in mm
b
A1
(2) QFN-20 (V-QFN4525-20)
A1
A3
A
V-QFN4525-20
Seati ng Pl ane
Dim
A
A1
A3
b
D
D2
E
E2
e
L
Z
Z1
Min
0.75
0.00
-
0.18
4.45
2.85
2.45
0.85
Max
0.85
0.05
-
0.30
4.55
3.15
2.55
1.15
0.50BSC
0.50
-
Typ
0.80
0.02
0.15
0.23
4.50
3.00
2.50
1.00
Pi n #1I D
D
e
Z1 4x
E
E2
0.30
-
-
0.40
0.385
0.885
D2
-
L
20x
All Dimensions in mm
b
20x
Z
4x
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Document number: DS35898 Rev. 1 - 2
74LVC574A
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
(1) TSSOP-20
X (20x)
C
Dimensions
Value (in mm)
0.650
C
X
0.420
X1
Y
6.270
1.789
Y1
Y2
Y1
Y2
4.160
7.720
Y (20x)
X1
(2) QFN-20 (V-QFN4525-20)
X4
X3
Dimensions
Value (in mm)
0.500
C
X
0.330
0.600
3.200
3.830
4.800
0.600
X1
X1
X2
X3
X4
Y
X2
Y3
Y1
Y1
Y2
Y3
1.200
0.830
2.800
Y2
Y
X
C
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Document number: DS35898 Rev. 1 - 2
74LVC574A
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
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labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and
any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or
systems.
Copyright © 2014, Diodes Incorporated
www.diodes.com
11 of 11
www.diodes.com
July 2014
© Diodes Incorporated
74LVC574A
Document number: DS35898 Rev. 1 - 2
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