SLG46620-AG [DIALOG]
Auto Grade GreenPAK Programmable Mixed-signal Matrix;
| 型号： | SLG46620-AG |
| 厂家： | 
Dialog Semiconductor |
| 描述： | Auto Grade GreenPAK Programmable Mixed-signal Matrix |
| 文件： | 总186页 (文件大小：2253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
General Description
The SLG46620-A provides a small, low power component for commonly used mixed-signal functions. The user creates their
circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect
logic, the IO Pins and the macrocells of the SLG46620-A. This highly versatile device allows a wide variety of mixed-signal
functions to be designed within a very small, low power single integrated circuit.
Key Features
8-bit Successive Approximation Register Analog-to-Digital
Converter (SAR ADC)
ADC 3-bit Programmable Gain Amplifier (PGA)
Two Digital-to-Analog Converters (DAC)
Six Analog Comparators (ACMP)
Power-On Reset (POR)
Two Bandgaps
Slave SPI
Read Back Protection (Read Lock)
Power Supply
1.8 V (±5 %) to 3.3 V (±10 %)
Operating Temperature Range: -40°C to 105°C
RoHS Compliant / Halogen-Free
Available Package
Two Voltage References (Vref)
Twenty Five Combinatorial Look Up Tables (LUTs)
Eight 2-bit LUTs
Sixteen 3-bit LUTs
One 4-bit LUT
20-pin TSSOP: 6.5 mm x 6.4 mm x 1.2 mm, 0.65 mm
pitch
One Combination Function Marcocells
Pattern Generator or 4-bit LUT
AEC-Q100 Grade 2 Qualified
Three Digital Comparators/Pulse Width Modulators
(DCMPs /PWMs) w/ Selectable Deadband
Ten Counters/Delays (CNT/DLY)
Two 14-bit Delay/Counter
One 14-bit Delay/Counter (Wake-Sleep Control)
One 14-bit Delay/Counter/Finite State Machine
Five 8-bit Delay/Counter
One 8-bit Delay/Counter/Finite State Machine
Twelve D Flip-Flops/Latches
Two Pipe Delays – 16 stage/ 2 output
Two Programmable Delays w/ Edge Detection
Three Internal Oscillators
Low-Frequency
Ring
RC 25 kHz and 2 MHz
Applications
Infotainment
Navigation
Advanced Driver Assistance Systems (ADAS)
Automotive Display Clusters
Body Electronics
Datasheet
16-Mar-2020
Revision 3.3
1 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ....................................................................................................................................................................10
2 Pinout ..................................................................................................................................................................................11
2.1 Pin Configuration - TSSOP-20 .............................................................................................................................11
3 Characteristics ...................................................................................................................................................................13
3.1 Absolute Maximum Ratings .................................................................................................................................13
3.2 Electrostatic Discharge Ratings ...........................................................................................................................13
3.3 Recommended Operating Conditions .................................................................................................................13
3.4 Electrical Characteristics ......................................................................................................................................14
3.5 Timing Characteristics ..........................................................................................................................................24
3.6 Oscillator Characteristics .....................................................................................................................................27
3.7 ACMP Characteristics ..........................................................................................................................................29
3.8 Vref OUT Characteristics .....................................................................................................................................32
3.9 ADC Characteristics Including PGA .....................................................................................................................33
3.10 PGA Specifications ............................................................................................................................................37
4 User Programmability ........................................................................................................................................................41
5 IO Pins .................................................................................................................................................................................42
5.1 Input Modes .........................................................................................................................................................42
5.2 Output Modes .......................................................................................................................................................42
5.3 Pull-Up/Down Resistors .......................................................................................................................................42
5.4 GPI Structure .......................................................................................................................................................42
5.5 Matrix OE IO Structure .........................................................................................................................................43
5.6 Register OE IO Structure .....................................................................................................................................45
5.7 IO Typical Performance .......................................................................................................................................47
6 Connection Matrix ..............................................................................................................................................................49
6.1 Matrix Input 0 Table ............................................................................................................................................52
6.2 Matrix 0 Output Table ..........................................................................................................................................54
6.3 Matrix Input 1 Table ............................................................................................................................................57
6.4 Matrix 1 Output Table ..........................................................................................................................................59
7 8-bit SAR ADC Analog-to-Digital Converter ....................................................................................................................62
7.1 ADC Functional Diagram ....................................................................................................................................63
7.2 ADC Operation Modes .........................................................................................................................................63
7.3 ADC 3-bit Programmable Gain Amplifier .............................................................................................................63
7.4 ADC Input Voltage Definition ...............................................................................................................................68
7.5 ADC Reference Voltage .......................................................................................................................................69
7.6 ADC Power-Down Select Mode ...........................................................................................................................69
7.7 ADC Clock Source ...............................................................................................................................................69
7.8 ADC Outputs ........................................................................................................................................................70
7.9 ADC Interrupt Output Timing Diagram ................................................................................................................71
8 8-bit Digital-to-Analog Converter ......................................................................................................................................72
8.1 DAC0 Functional Diagram ...................................................................................................................................73
8.2 DAC1 Functional Diagram ...................................................................................................................................73
8.3 DAC Typical Performance ...................................................................................................................................74
9 Combinatorial Logic ...........................................................................................................................................................75
9.1 2-Bit LUT ..............................................................................................................................................................75
9.2 3-Bit LUT ..............................................................................................................................................................79
9.3 4-Bit LUT ..............................................................................................................................................................84
10 Combination Function Macrocells ..................................................................................................................................86
11 Analog Comparators ........................................................................................................................................................88
11.1 ACMP Master Architecture ................................................................................................................................89
11.2 ACMP0 Block Diagram .....................................................................................................................................90
11.3 ACMP1 Block Diagram .....................................................................................................................................91
11.4 ACMP2 Block Diagram ......................................................................................................................................92
Datasheet
16-Mar-2020
Revision 3.3
2 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
11.5 ACMP3 Block Diagram ......................................................................................................................................93
11.6 ACMP4 Block Diagram .....................................................................................................................................94
11.7 ACMP5 Block Diagram .....................................................................................................................................95
11.8 ACMP Typical Performance ...............................................................................................................................96
12 Digital Storage Elements .................................................................................................................................................97
12.1 Initial Polarity Operations ................................................................................................................................103
13 Counters/Delay Generators ...........................................................................................................................................106
13.1 CNT/DLY Timing Diagrams ..............................................................................................................................112
14 Digital Comparator/Pulse Width Modulator .................................................................................................................116
14.1 DCMP Input Modes ..........................................................................................................................................116
14.2 DCMP Output Modes .......................................................................................................................................116
14.3 PWM Input Modes ............................................................................................................................................117
14.4 PWM Output Modes .........................................................................................................................................117
14.5 DCMP0/PWM0 Functional Diagram ................................................................................................................118
14.6 DCMP1/PWM1 Functional Diagram ................................................................................................................118
14.7 DCMP2/PWM2 Functional Diagram ................................................................................................................119
14.8 PWM Dead Band Control .................................................................................................................................119
14.9 PWM Dead Band Control Timing Diagram ......................................................................................................119
14.10 DCMP/PWM Power-down Control .................................................................................................................119
14.11 DCMP/PWM Clock Invert Control ..................................................................................................................120
15 Slave SPI - Serial to Parallel/Parallel to Serial Converter (SPI) ..................................................................................121
15.1 SPI Functional Diagram ...................................................................................................................................121
15.2 Clock Polarity and Phase .................................................................................................................................121
15.3 SPI Clock Synchronization ...............................................................................................................................124
15.4 SPI Data Buffer Function .................................................................................................................................125
16 Pipe Delay .......................................................................................................................................................................126
17 Programmable Delay/Edge Detector ............................................................................................................................128
17.1 Programmable Delay Timing Diagram - Edge Detector Output .....................................................................129
17.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output ........................................130
18 Voltage Reference ..........................................................................................................................................................131
18.1 Voltage Reference Overview ...........................................................................................................................131
18.2 Vref Selection Table ........................................................................................................................................131
18.3 Vref Block Diagram .........................................................................................................................................132
18.4 Vref Out Typical Performance .........................................................................................................................133
19 Clocking ..........................................................................................................................................................................134
19.1 Oscillators General Description ........................................................................................................................134
19.2 Oscillators Power-On Delay .............................................................................................................................136
19.3 Oscillators Accuracy .........................................................................................................................................138
20 Power-On Reset ..............................................................................................................................................................141
20.1 General Operation ............................................................................................................................................141
20.2 POR Sequence ................................................................................................................................................142
20.3 Macrocells Output States During POR Sequence ...........................................................................................142
20.4 Initialization ......................................................................................................................................................143
20.5 Power-Down ....................................................................................................................................................144
20.6 External Reset ..................................................................................................................................................144
21 Power Detector ...............................................................................................................................................................148
22 Additional Logic Functions ...........................................................................................................................................148
22.1 INV_0 Gate .....................................................................................................................................................148
22.2 INV_1 Gate .....................................................................................................................................................148
23 Register Definitions .......................................................................................................................................................149
23.1 Register Map ....................................................................................................................................................149
24 Package Top Marking Definitions .................................................................................................................................179
24.1 TSSOP-20 ........................................................................................................................................................179
25 Package Information ......................................................................................................................................................180
25.1 Package outlines for TSSOP 20L 173 MIL Green Package ............................................................................180
25.2 TSSOP Handling ..............................................................................................................................................181
25.3 Soldering Information .......................................................................................................................................181
Datasheet
16-Mar-2020
Revision 3.3
3 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
26 Ordering Information .....................................................................................................................................................181
26.1 Tape and Reel Specifications ..........................................................................................................................181
26.2 Carrier Tape Drawing and Dimensions ............................................................................................................181
26.3 TSSOP- 20 .......................................................................................................................................................182
27 Layout Guidelines ..........................................................................................................................................................182
27.1 TSSOP-20 ........................................................................................................................................................182
Glossary................................................................................................................................................................................183
Revision History...................................................................................................................................................................185
Datasheet
16-Mar-2020
Revision 3.3
4 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Figures
Figure 1: Steps to Create a Custom GreenPAK Device...........................................................................................................41
Figure 2: PIN 2 GPI Structure Diagram....................................................................................................................................42
Figure 3: Matrix OE IO Structure Diagram...............................................................................................................................43
Figure 4: Matrix OE IO 4x Drive Structure Diagram.................................................................................................................44
Figure 5: Register IO Structure Diagram..................................................................................................................................45
Figure 6: Register OE 4x Drive Structure Diagram ..................................................................................................................46
Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.......................................................47
Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .........................................47
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .........................................48
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C .......................................48
Figure 11: Matrix Cross Connection Block Diagram ................................................................................................................49
Figure 12: Connection Matrix 0................................................................................................................................................50
Figure 13: Connection Matrix 1................................................................................................................................................50
Figure 14: Connection Matrix Example....................................................................................................................................51
Figure 15: ADC Functional Diagram ........................................................................................................................................63
Figure 16: ADC 2-Channel Selection.......................................................................................................................................64
Figure 17: PGA Input Offset Distribution, Single-Ended Mode, G = 0.5 ..................................................................................65
Figure 18: PGA Input Offset Distribution, Single-Ended Mode, G = 1 .....................................................................................65
Figure 19: PGA Input Offset Distribution, Single-Ended Mode, G = 2 .....................................................................................66
Figure 20: PGA Input Offset Distribution, Single-Ended Mode, G = 4 .....................................................................................66
Figure 21: PGA Input Offset Distribution, Single-Ended Mode, G = 8 .....................................................................................66
Figure 22: Typical Input Common Mode Voltage Range vs. Linear Output Voltage Range, Differential Mode, All Gains.......67
Figure 23: Typical Negative Input Voltage Range vs. Linear Output Voltage, Pseudo-Differential Mode, G = 1.....................67
Figure 24: Typical Negative Input Voltage Range vs. Linear Output Voltage, Pseudo-Differential Mode, G = 2.....................67
Figure 25: ADC Reference Voltage..........................................................................................................................................69
Figure 26: ADC Clock Source..................................................................................................................................................70
Figure 27: ADC Interrupt Output Timing Diagram....................................................................................................................71
Figure 28: DAC0 Functional Diagram ......................................................................................................................................73
Figure 29: DAC1 Functional Diagram ......................................................................................................................................73
Figure 30: DAC Typical Load Regulation, T = 25°C, VDD = 3.3 V............................................................................................74
Figure 31: 2-bit LUTs................................................................................................................................................................76
Figure 32: 3-bit LUTs................................................................................................................................................................79
Figure 33: 3-bit LUTs................................................................................................................................................................80
Figure 34: 4-bit LUT_1 .............................................................................................................................................................84
Figure 35: 4-bit LUT1 or PGEN................................................................................................................................................86
Figure 36: PGEN Timing Diagram............................................................................................................................................87
Figure 37: Maximum Power-On Delay vs. VDD, BG = 550 µs, Regulator and Charge Pump set to automatic ON/OFF.........88
Figure 38: Maximum Power-On Delay vs. VDD, BG = 100 µs, Regulator and Charge Pump set to automatic ON/OFF.........88
Figure 39: ACMP Master Architecture Diagram.......................................................................................................................89
Figure 40: ACMP0 Block Diagram ...........................................................................................................................................90
Figure 41: ACMP1 Block Diagram ...........................................................................................................................................91
Figure 42: ACMP2 Block Diagram ...........................................................................................................................................92
Figure 43: ACMP3 Block Diagram ...........................................................................................................................................93
Figure 44: ACMP4 Block Diagram ...........................................................................................................................................94
Figure 45: ACMP5 Block Diagram ...........................................................................................................................................95
Figure 46: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 105 °C, VDD = 3.3 V.............................................96
Figure 47: DFF/Latch0 .............................................................................................................................................................97
Figure 48: DFF/Latch1 .............................................................................................................................................................98
Figure 49: DFF/Latch2 .............................................................................................................................................................98
Figure 50: DFF/Latch3 .............................................................................................................................................................99
Figure 51: DFF/Latch4 .............................................................................................................................................................99
Figure 52: DFF/Latch5 .............................................................................................................................................................99
Figure 53: DFF/Latch6 ...........................................................................................................................................................100
Figure 54: DFF/Latch7 ...........................................................................................................................................................100
Figure 55: DFF/Latch8 ...........................................................................................................................................................101
Datasheet
16-Mar-2020
Revision 3.3
5 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Figure 56: DFF/Latch9 ...........................................................................................................................................................101
Figure 57: DFF/Latch10 .........................................................................................................................................................102
Figure 58: DFF/Latch11 .........................................................................................................................................................102
Figure 59: DFF Polarity Operations........................................................................................................................................103
Figure 60: DFF Polarity Operations with nRST......................................................................................................................104
Figure 61: DFF Polarity Operations with nSet........................................................................................................................105
Figure 62: CNT/DLY0.............................................................................................................................................................107
Figure 63: CNT/DLY1.............................................................................................................................................................107
Figure 64: CNT/DLY2/FSM0..................................................................................................................................................108
Figure 65: CNT/DLY3.............................................................................................................................................................108
Figure 66: CNT/DLY4/FSM0..................................................................................................................................................109
Figure 67: CNT/DLY5.............................................................................................................................................................109
Figure 68: CNT/DLY6.............................................................................................................................................................110
Figure 69: CNT/DLY7.............................................................................................................................................................110
Figure 70: CNT/DLY8/PWM_RAMP.......................................................................................................................................111
Figure 71: CNT/DLY9/PWM_RAMP.......................................................................................................................................111
Figure 72: Timing (Rising Edge) for Count Data = 3..............................................................................................................112
Figure 73: Timing (Falling Edge) for Count Data = 3 .............................................................................................................112
Figure 74: Timing (Reset Rising Edge Mode, Oscillator is Forced on) for Count Data = 3....................................................113
Figure 75: Timing (Reset Falling Edge Mode, Oscillator is Forced on) for Count Data = 3 ...................................................113
Figure 76: Timing (Reset High Level Mode, Oscillator is Autopowered on (Controlled by Reset)) for Count Data = 3 .........113
Figure 77: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP=0) for Counter Data = 3 .....114
Figure 78: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced on, UP=0) for Counter Data = 3..........114
Figure 79: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced on, UP=1) for Counter Data = 3......115
Figure 80: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced on, UP=1) for Counter Data = 3..........115
Figure 81: DCMP Timing Diagram.........................................................................................................................................117
Figure 82: DCMP0/PWM0 Functional Diagram......................................................................................................................118
Figure 83: DCMP1/PWM1 Functional Diagram......................................................................................................................118
Figure 84: DCMP2/PWM2 Functional Diagram......................................................................................................................119
Figure 85: PWM Dead Band Control Timing Diagram ...........................................................................................................119
Figure 86: SPI Functional Diagram........................................................................................................................................121
Figure 87: Timing Diagram showing Clock Polarity and Phase, CPHA=0 .............................................................................122
Figure 88: Timing Diagram showing Clock Polarity and Phase, CPHA = 1 ...........................................................................123
Figure 89: Timing Diagram showing SPI Clock synchronization............................................................................................125
Figure 90: The SPI used as ADC data buffer diagram...........................................................................................................125
Figure 91: Pipe Delay 0..........................................................................................................................................................126
Figure 92: Pipe Delay 1..........................................................................................................................................................127
Figure 93: Programmable Delay ............................................................................................................................................128
Figure 94: Programmable Delay ............................................................................................................................................128
Figure 95: Edge Detector Output ...........................................................................................................................................129
Figure 96: Delayed Edge Detector Output.............................................................................................................................129
Figure 97: Glitch Filtering for Edge Detector Output..............................................................................................................130
Figure 98: Voltage Reference Block Diagram........................................................................................................................132
Figure 99: Typical Load Regulation, T = 25°C, VDD = 3.3 V ..................................................................................................133
Figure 100: Oscillator Block Diagram.....................................................................................................................................135
Figure 101: Oscillator Startup Diagram..................................................................................................................................136
Figure 102: LF Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, OSC = 1.73 kHz ...............................................136
Figure 103: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, RC OSC = 2 MHz............................................137
Figure 104: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, RC OSC = 25 kHz ...........................................137
Figure 105: Ring Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, OSC = 27 MHz..............................................138
Figure 106: RC Oscillator Frequency vs. VDD, RC OSC = 25 kHz, T = 25 °C .......................................................................138
Figure 107: RC Oscillator Frequency vs. VDD, RC OSC = 25 kHz, T = -40 °C to 105 °C ......................................................139
Figure 108: Ring Oscillator Frequency vs. VDD, OSC = 27 MHz, T = 25 °C ..........................................................................139
Figure 109: Ring Oscillator Frequency vs. VDD, OSC = 27 MHz, T = -40 °C to 105 °C.........................................................140
Figure 110: POR sequence....................................................................................................................................................142
Figure 111: Internal Macrocell States during POR sequence................................................................................................143
Figure 112: Power-Down........................................................................................................................................................144
Datasheet
16-Mar-2020
Revision 3.3
6 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Figure 113: External Reset Sequence (High Active)..............................................................................................................145
Figure 114: External Reset Sequence (Rising Edge Detect).................................................................................................146
Figure 115: External Reset Sequence (Falling Edge Detect).................................................................................................147
Figure 116: INV_0 Gate .........................................................................................................................................................148
Figure 117: INV_1 Gate .........................................................................................................................................................148
Datasheet
16-Mar-2020
Revision 3.3
7 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Tables
Table 1: Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . 14
Table 7: Input Leakage Current at T = -40 °C to +105 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C . . . . . . . . . . . . . . . 22
Table 9: Typical Delay Estimated for Each Macrocell at T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C . . . . . . . . . . . . . . . . . . . . 25
Table 11: Oscillators Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12: Oscillators Power-On Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13: ACMP Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted. . . . . . . . . . 29
Table 14: Vref OUT Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted . . . . . . . 32
Table 15: Delay Estimated for Each ACMP at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted . . . 32
Table 16: Single-Ended ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . . . . 33
Table 17: Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . . . . . . 34
Table 18: Pseudo-Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . 35
Table 19: Single-Ended PGA Operation, T = -40°C to +105°C, VDD = 1.71 V to 3.6V, Unless Otherwise Noted . . . . . . 37
Table 20: Differential PGA Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . . . . . . 38
Table 21: Pseudo-Differential PGA Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted . . 39
Table 22: Differential/Pseudo-Differential PGA Mode, T = -40°C to +105°C, VDD = 1.71V to 3.6V, Unless Otherwise Noted 40
Table 23: Matrix 0 Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24: Matrix 0 Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 25: Matrix 1 Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 26: Matrix 1 Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 28: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 30: 2-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31: 2-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 32: 2-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 33: 2-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 34: 2-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 35: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 36: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 37: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 38: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 39: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 40: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 42: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 43: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 44: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 45: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 46: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 47: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 48: 3-bit LUT12 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 49: 3-bit LUT13 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 50: 3-bit LUT14 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 51: 3-bit LUT15 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 52: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 53: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 54: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 55: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 56: Gain Divider Input Resistance (typical). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 57: Gain Divider typical Accuracy at T = (-40 to +105°C), VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 58: Counter/Delay Macrocell Functions Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 59: CPHA = 0 Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 60: CPHA = 1 Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 61: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Datasheet
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Revision 3.3
8 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 62: Vref Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 63: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Datasheet
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
1
Block Diagram
Counters/Delay Generators
Pin 1
VDD
Pin 20
GPIO
CNT0
CNT5
CNT1
CNT2
CNT7
CNT3
CNT4
CNT9
Programmable
Delay0
ACMP0
Pin 2
GPI
CNT6
CNT8
Pin 19
GPIO
Programmable
Delay1
DFF/Latches
Pin 18
GPIO
Pin 3
DFF0
DFF1
DFF2
DFF3
DFF9
DFF4
DFF5
ACMP1
GPIO
DFF6
DFF7
DFF8
DFF10
DFF11
Pipe
Delay0
Vref
Pin 17
GPIO
Pin 4
GPIO
ACMP2
Look Up Tables (LUTs)
2-bit
LUT2_0
2-bit
LUT2_1
2-bit
LUT2_2
2-bit
LUT2_3
2-bit
LUT2_4
Pipe
Delay1
POR
Pin 16
GPIO
Pin 5
GPIO
2-bit
LUT2_5
2-bit
LUT2_6
2-bit
LUT2_7
3-bit
LUT3_0
3-bit
LUT3_1
ACMP3
3-bit
LUT3_2
3-bit
LUT3_3
3-bit
LUT3_4
3-bit
LUT3_5
3-bit
LUT3_6
Additional
Logic Functions
Pin 15
GPIO
Pin 6
GPIO
3-bit
LUT3_7
3-bit
LUT3_8
3-bit
LUT3_9
3-bit
LUT3_10
3-bit
LUT3_11
INV_0
INV_1
ACMP4
3-bit
LUT3_12
3-bit
LUT3_13
3-bit
LUT3_14
3-bit
LUT3_15
4-bit
LUT4_0
Pin 14
GPIO
Pin 7
GPIO
Combination Function
Macrocell
8-bit SAR
ADC
4-bit LUT4_1
or PGEN
DAC0
DAC1
Pin 13
GPIO
Pin 8
ACMP5
GPIO
DCMP/PWM
LF Oscillator
Pin 9
GPIO
Pin 12
GPIO
PWR DET
SPI
PGA
Ring Oscillator
RC Oscillator
Pin 11
GND
Pin 10
GPIO
Datasheet
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Revision 3.3
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
2
Pinout
2.1 PIN CONFIGURATION - TSSOP-20
6.4 mm
1
2
20
19
18
17
16
15
14
13
12
11
3
4
5
6
7
8
9
10
TSSOP-20
(Top View)
Table 1: Functional Pin Description
Pin #
Pin Name Function
1
VDD
Power Supply
General Purpose Input
External Reset
ADC CLK
2
GPI
General Purpose IO with OE
ACMP4(+)
3
4
5
6
7
8
9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
General Purpose IO
ACMP5(+)
General Purpose IO with OE
ACMP5 (-)
General Purpose IO
ACMP0(+) / ACMP1(+) / ACMP2(+) / ACMP3(+) / ACMP4(+)
General Purpose IO with OE
ACMP0(-) / ACMP1(-) / PGA_OUT
General Purpose IO
PGA(+)
General Purpose IO with OE
PGA(-)
General Purpose IO with OE
ACMP0(-) / ACMP1(-) / ACMP2(-) / ACMP3(-) / ACMP4(-)
Super Drive IO
10
11
12
GPIO
GND
GPIO
Ground
General Purpose IO
ACMP1(+)
Super Drive IO
General Purpose IO with OE
ACMP2(+) / ACMP3(+)
13
14
GPIO
GPIO
General Purpose IO with OE
ACMP2(-)
Datasheet
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Revision 3.3
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 1: Functional Pin Description(Continued)
Pin #
Pin Name Function
General Purpose IO
ACMP3(+) / ACMP4(+)
15
GPIO
GPIO
GPIO
GPIO
General Purpose IO with OE
16
17
18
General Purpose IO
General Purpose IO with OE
Vref OUT 1
General Purpose IO with OE
Vref OUT 0
19
20
GPIO
GPIO
General Purpose IO
Table 2: Pin Type Definitions
Pin Type
VDD
Description
Power Supply
GPI
General Purpose Input
General Purpose Input/Output
General Purpose Output
Ground
GPIO
GPO
GND
Datasheet
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Supply Voltage on VDD relative to GND
DC Input Voltage
Min
Max
7
Unit
V
-0.5
GND - 0.5 V
VDD + 0.5 V
1.98/G
V
Single-ended
--
--
V
Differential
(1.98 - 0.55)/G
V
PGA Input voltage (Note 1)
Pseudo-
--
(1.98 - 0.18)/G
V
differential
Maximum Average or DC
Current Through VDD Pin
(Per chip side, (Note 2))
TJ = 85°C
TJ = 110°C
TJ = 85°C
TJ = 110°C
--
--
--
--
45
21
69
33
mA
mA
mA
mA
Maximum Average or DC
Current Through GND Pin
(Per chip side, (Note 2))
Push-Pull 1x
Push-Pull 2x
Push-Pull 4x
OD 1x
--
--
10
14
--
28
Maximum Average or DC Current
(Through pin)
mA
--
14
OD 2x
--
27
OD 4x
--
46
Current at Input Pin
-1.0
-65
--
1.0
150
150
1
mA
°C
Storage Temperature Range
Junction Temperature
°C
Moisture Sensitive Level
Note 1 IN+ relative to GND in Single-ended mode, IN+ and IN- relative to each other in Differential and Pseudo-differential
modes.
Note 2 The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7, 8, 9 and 10 are connected to one side, pins
12, 13, 14, 15, 16, 17, 18, 19 and 20 to another.
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
750
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model), corner pins
ESD Protection (Charged Device Model), other pins
--
V
500
--
V
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions
Parameter
Condition
Min
1.71
-40
Max
3.6
Unit
V
Supply Voltage (VDD
)
Operating Temperature
105
°C
Datasheet
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 5: Recommended Operating Conditions(Continued)
Parameter
Condition
Min
Max
Unit
Maximal Voltage Applied to any PIN in High
Impedance State
VDD
0.3
+
--
V
Capacitor Value at VDD
0.1
0
--
µF
Analog Input Common Mode Range
Allowable Input Voltage atAnalog Pins
VDD
V
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
3.6
Unit
VDD
VPP
Supply Voltage
1.71
7.25
0
3.3
7.50
--
V
V
V
V
Programming Voltage
7.75
VDD
1.2
Positive Input
Negative Input
VACMP
ACMP Input Voltage Range
0
--
0.7x
VDD
VDD
0.3
+
Logic Input (Note 3)
--
--
V
V
V
V
V
V
V
V
V
V
V
V
0.8x
VDD
VDD
0.3
+
VIH
HIGH-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 3)
Logic Input (Note 3)
VDD
0.3
+
1.25
--
GND-
0.3
0.3x
VDD
--
GND-
0.3
0.2x
VDD
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
--
GND-
0.3
Low-Level Logic Input (Note 3)
--
0.5
Logic Input with Schmitt Trigger,
0.174
0.181
0.187
0.253
0.266
0.271
0.342
0.346
0.346
0.405
0.421
0.432
0.530
0.530
0.530
0.630
0.643
0.681
V
DD = 1.71 V
Logic Input with Schmitt Trigger,
DD = 1.8 V
V
Logic Input with Schmitt Trigger,
VDD = 1.89 V
Schmitt Trigger Hysteresis
Voltage
VHYS
Logic Input with Schmitt Trigger,
VDD = 3 V
Logic Input with Schmitt Trigger,
VDD = 3.3 V
Logic Input with Schmitt Trigger,
VDD = 3.6 V
PMOS OD, 1x Drive, IOH = 0.1 mA,
VDD = 1.71 V
1.677
2.678
3.011
3.337
1.697
2.773
3.092
3.408
--
--
--
--
V
V
V
V
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3 V
VOH
HIGH-Level Output Voltage
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3.3 V
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3.6 V
Datasheet
16-Mar-2020
Revision 3.3
14 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
PMOS OD, 2x Drive, IOH = 0.1 mA,
VDD = 1.71 V
1.69
1.704
--
V
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3 V
2.843
3.156
3.467
1.702
2.918
3.225
3.53
2.887
3.196
3.503
1.707
2.941
3.245
3.549
1.703
2.772
3.091
3.408
1.704
2.886
3.196
3.503
1.707
2.941
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3.3 V
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3.6 V
PMOS OD, 4x Drive, IOH = 0.1 mA,
VDD = 1.71 V
PMOS OD, 4x Drive, IOH = 3 mA,
VDD = 3 V
PMOS OD, 4x Drive, IOH = 3 mA,
VDD = 3.3 V
PMOS OD, 4x Drive, IOH = 3 mA,
VDD = 3.6 V
Push-Pull, 1x Drive, IOH = 0.1 mA,
VDD = 1.71 V
1.677
2.675
3.009
3.336
1.69
VOH
HIGH-Level Output Voltage
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3 V
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.3 V
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.6 V
Push-Pull, 2x Drive, IOH = 0.1 mA,
VDD = 1.71 V
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3 V
2.842
3.156
3.466
1.702
2.918
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.3 V
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.6 V
Push-Pull, 4x Drive, IOH = 0.1 mA,
VDD = 1.71 V
Push-Pull, 4x Drive, IOH = 3 mA,
VDD = 3 V
Datasheet
16-Mar-2020
Revision 3.3
15 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 4x Drive, IOH = 3 mA,
VDD = 3.3 V
3.225
3.246
--
V
VOH
HIGH-Level Output Voltage
Push-Pull, 4x Drive, IOH = 3 mA,
VDD = 3.6 V
3.53
--
3.549
0.003
0.064
0.06
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NMOS OD, 1x Drive, IOL = 0.1 mA,
VDD = 1.71 V
0.007
0.094
0.088
0.083
0.004
0.051
0.048
0.046
0.002
0.026
0.025
0.024
0.017
0.232
0.216
0.201
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3 V
--
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3.3 V
--
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3.6 V
--
0.056
0.002
0.035
0.033
0.031
0.001
0.018
0.017
0.016
0.008
0.153
0.144
0.133
NMOS OD, 2x Drive, IOL = 0.1 mA,
VDD = 1.71 V
--
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3 V
--
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3.3 V
--
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3.6 V
--
VOL
LOW-Level Output Voltage
NMOS OD, 4x Drive, IOL = 0.1 mA,
VDD = 1.71 V
--
NMOS OD, 4x Drive, IOL = 3 mA,
VDD = 3 V
--
NMOS OD, 4x Drive, IOL = 3 mA,
VDD = 3.3 V
--
NMOS OD, 4x Drive, IOL = 3 mA,
VDD = 3.6 V
--
Push-Pull, 1x Drive, IOL = 0.1 mA,
VDD = 1.71 V
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3 V
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.3 V
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.6 V
--
Datasheet
16-Mar-2020
Revision 3.3
16 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, IOL = 0.1 mA,
VDD = 1.71 V
--
0.004
0.009
V
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3 V
--
--
--
--
--
--
--
0.079
0.074
0.069
0.002
0.04
0.117
0.109
0.103
0.004
0.057
0.053
0.050
V
V
V
V
V
V
V
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3.3 V
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3.6 V
VOL
LOW-Level Output Voltage
Push-Pull, 4x Drive, IOL = 0.1 mA,
VDD = 1.71 V
Push-Pull, 4x Drive, IOL = 3 mA,
VDD = 3 V
Push-Pull, 4x Drive, IOL = 3 mA,
VDD = 3.3 V
0.037
0.035
Push-Pull, 4x Drive, IOL = 3 mA,
VDD = 3.6 V
PMOS OD, 1x Drive,
VOH = VDD - 0.2
0.888
1.327
--
mA
VDD = 1.71 V
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 3 V
5.014
7.602
10.22
6.862
10.292
13.661
--
--
--
mA
mA
mA
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 3.3 V
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 3.6 V
PMOS OD, 2x Drive,
VOH = VDD - 0.2
HIGH-Level Output Pulse
Current (Note 1)
IOH
1.784
2.602
--
mA
VDD = 1.71 V
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 3 V
9.758
14.765
19.786
13.325
19.961
26.453
--
--
--
mA
mA
mA
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 3.3 V
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 3.6 V
PMOS OD, 4x Drive,
VOH = VDD - 0.2
3.467
4.940
--
mA
VDD = 1.71 V
Datasheet
16-Mar-2020
Revision 3.3
17 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
PMOS OD, 4x Drive,
VOH = 2.4 V, VDD = 3 V
18.41
24.709
--
mA
PMOS OD, 4x Drive,
27.793
37.08
36.972
48.908
--
--
mA
mA
V
OH = 2.4 V, VDD = 3.3 V
PMOS OD, 4x Drive,
VOH = 2.4 V, VDD = 3.6 V
Push-Pull, 1x Drive,
VOH = VDD - 0.2
0.886
1.328
--
mA
VDD = 1.71 V
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3 V
4.988
7.57
6.850
10.274
13.642
--
--
--
mA
mA
mA
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.3 V
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.6 V
10.186
Push-Pull, 2x Drive,
VOH = VDD - 0.2
HIGH-Level Output Pulse
Current (Note 1)
IOH
1.772
2.602
--
mA
VDD = 1.71 V
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3 V
9.73
13.308
19.934
26.407
--
--
--
mA
mA
mA
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.3 V
14.727
19.742
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.6 V
Push-Pull, 4x Drive,
VOH = VDD - 0.2
3.474
4.967
--
mA
VDD = 1.71 V
Push-Pull, 4x Drive,
VOH = 2.4 V, VDD = 3 V
18.371
27.716
36.955
2.605
24.763
37.017
48.951
3.747
--
--
--
--
mA
mA
mA
mA
Push-Pull, 4x Drive,
VOH = 2.4 V, VDD = 3.3 V
Push-Pull, 4x Drive,
VOH = 2.4 V, VDD = 3.6 V
NMOS OD, 1x Drive, VOL = 0.15 V
VDD = 1.71 V
LOW-Level Output Pulse
Current (Note 1)
IOL
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 3 V
11.731
17.144
--
mA
Datasheet
16-Mar-2020
Revision 3.3
18 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 3.3 V
12.68
18.499
--
mA
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 3.6 V
13.405
4.973
21.614
23.323
24.348
10.026
43.796
45.48
49.417
1.053
4.903
5.266
5.67
20.055
7.184
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NMOS OD, 2x Drive, VOL = 0.15 V
VDD = 1.71 V
NMOS OD, 2x Drive, VOL = 0.4 V
VDD = 3 V
32.171
34.195
37.261
14.124
62.595
65.776
72.104
1.521
NMOS OD, 2x Drive, VOL = 0.4 V
VDD = 3.3 V
NMOS OD, 2x Drive, VOL = 0.4 V
VDD = 3.6 V
NMOS OD, 4x Drive, VOL = 0.15 V
VDD = 1.71 V
NMOS OD, 4x Drive, VOL = 0.4 V
VDD = 3 V
NMOS OD, 4x Drive, VOL = 0.4 V
VDD = 3.3 V
LOW-Level Output Pulse
Current (Note 1)
IOL
NMOS OD, 4x Drive, VOL = 0.4 V
VDD = 3.6 V
Push-Pull, 1x Drive, VOL = 0.15 V
VDD = 1.71 V
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3 V
7.109
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3.3 V
7.734
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3.6 V
8.393
Push-Pull, 2x Drive, VOL = 0.15 V
VDD = 1.71 V
2.091
9.54
3.020
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 3 V
13.867
15.013
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 3.3 V
10.285
Datasheet
16-Mar-2020
Revision 3.3
19 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 6: EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 3.6 V
10.928
16.260
--
mA
Push-Pull, 4x Drive, VOL = 0.15 V
VDD = 1.71 V
4.213
19.57
20.916
22.726
--
6.012
27.791
29.449
32.030
--
--
--
mA
mA
mA
mA
V
Push-Pull, 4x Drive, VOL = 0.4 V
VDD = 3 V
LOW-Level Output Pulse
Current (Note 1)
IOL
Push-Pull, 4x Drive, VOL = 0.4 V
VDD = 3.3 V
--
Push-Pull, 4x Drive, VOL = 0.4 V
VDD = 3.6 V
--
Maximal Voltage Applied to
any PIN in High-Impedance
State
VO
VDD
Tramp = 3 ms (Note 4)
--
--
1.448
1.567
1.464
3.229
7.458
1.700
ms
ms
V
Startup Time (Note 2)
From VDD rising past PONTHR
TSU
Tramp = 10 ms (Note 4)
PONTHR Power-On Threshold
POFFTHR Power-Off Threshold
VDD Level Required to Start Up the Chip
0.921
V
DD Level Required to Switch Off the
0.836
1.107
1.390
V
Chip
1 M Pull-up
809.136 1047.55 1455.16
632.228 1054.76 2574.69
83.717 104.885 143.777
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
1 M Pull-up (PINs 17, 18, 19)
100 k Pull-up
10 k Pull-up
RPUP
Pull-up Resistance
8.945
11.0738 16.687
1 M Pull-down
100 k Pull-down
10 k Pull-down
410.19 1047.35 1448.22
81.555 104.798 143.277
RPDWN
Pull-down Resistance
Input Capacitance
8.740
--
10.9851 17.198
2.49 2.97
CIN
Note 1 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2 VDD ramp rising speed must be less than 0.6 V/µs after Power-on. Violating this specification may cause chip to restart.
Note 3 No hysteresis
Note 4 Tramp - linear voltage ramp duration 0 V to VDD on PIN1 relative to GND.
Note 5 Typical value is given for T = 25 °C, maximum value is given for T = -40 °C to 105 °C
Datasheet
16-Mar-2020
Revision 3.3
20 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 7: Input Leakage Current at T = -40 °C to +105 °C
Parameter Description
Condition
IN- = 0 V, VDD = 1.71 V
Ext.Vref/2
Min
Typ
Max
Unit
V
--
0.32
6.49
nA
VIN- = 0 V, VDD = 1.71 V
Ext.Vref
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.09
1.30
7.76
5.90
1.69
0.81
12.61
1489
5.16
2078
7.84
7.10
8.19
6.78
1.99
0.95
12.39
1493
10.06
4389
14.35
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
VIN+ = 0 V, VDD = 1.71 V
Buffer Disable, Gain = 0.25, 0.33, 0.5
VIN+ = 0 V, VDD = 1.71 V
Buffer Disable, Gain = 1
0.009
0.005
0.05
VIN+ = 0 V, VDD = 1.71 V
Buffer Enable
VIN- = 1.2 V, VDD = 1.71 V
Ext.Vref
VIN- = 1.2 V, VDD = 1.71 V
Ext.Vref/2
1198
0.003
1649
0.006
0.31
V
IN+ = VDD, VDD = 1.71 V
Buffer Enable
V
IN+ = VDD, VDD = 1.71 V
Buffer Disable, Gain = 0.25, 0.33, 0.5
V
IN+ = VDD, VDD = 1.71 V
Buffer Disable, Gain = 1
ACMP Input Leakage
V
IN- = 0 V, VDD = 3.3 V ± 10%
Ext.Vref/2
ILKG
(Absolute
Value)
V
IN- = 0 V, VDD = 3.3 V ± 10%
0.1
Ext.Vref
V
IN+ = 0 V, VDD = 3.3 V ± 10%
1.36
Buffer Disable, Gain = 0.25, 0.33, 0.5
V
IN+ = 0 V, VDD = 3.3 V ± 10%
0.018
0.005
0.048
1200
0.007
3483
0.016
Buffer Disable, Gain = 1
V
IN+ = 0 V, VDD = 3.3 V ± 10%
Buffer Enable
VIN- = 1.2 V, VDD = 3.3 V ± 10%
Ext.Vref
VIN- = 1.2 V, VDD = 3.3 V ± 10%
Ext.Vref/2
VIN+ = VDD, VDD = 3.3 V ± 10%
Buffer Enable
VIN+ = VDD, VDD = 3.3 V ± 10%
Buffer Disable, Gain = 0.25, 0.33, 0.5
VIN+ = VDD, VDD = 3.3 V ± 10%
Buffer Disable, Gain = 1
VIN = 0 V, VDD = 1.71 V
--
--
--
--
0.005
0.008
0.004
0.004
1
nA
nA
nA
nA
VIN = VDD, VDD = 1.71 V
4.75
0.84
3.92
PGA Input Leakage
ADC Mode = DI, PD, SE
VIN = 0 V, VDD = 3.3 V ± 10%
VIN = VDD, VDD = 3.3 V ± 10%
Datasheet
16-Mar-2020
Revision 3.3
21 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 7: Input Leakage Current at T = -40 °C to +105 °C(Continued)
Parameter Description
Condition
Min
--
Typ
Max
1.09
5.46
2.94
Unit
nA
VIN = 0 V, VDD = 1.71 V to 3.6 V
0.003
0.007
0.004
Logic Input without Schmitt
Trigger (Floating) Leakage
V
IN = VDD, VDD = 1.71 V to 3.6 V
--
nA
Logic Input without Schmitt
Trigger (Floating) Leakage
(pin 17, 18, 19)
VIN = 0 V, VDD = 1.71 V to 3.6 V
VIN = VDD, VDD = 1.71 V to 3.6 V
--
nA
--
2.56
445.77
nA
VIN = 0 V, VDD = 1.71 V to 3.6 V
VIN = VDD, VDD = 1.71 V to 3.6 V
VIN = 0 V, VDD = 1.71 V to 3.6 V
--
--
--
0.003
0.007
0.004
1.06
5.43
2.90
nA
nA
nA
Logic Input with Schmitt
Trigger (Floating) Leakage
ILKG
(Absolute
Value)
Logic Input with Schmitt
Trigger (Floating) Leakage
(pin 17, 18, 19)
V
IN = VDD, VDD = 1.71 V to 3.6 V
--
2.56
442.87
nA
VIN = 0 V, VDD = 1.71 V to 3.6 V
VIN = VDD, VDD = 1.71 V to 3.6 V
VIN = 0 V, VDD = 1.71 V to 3.6 V
--
--
--
0.003
0.007
0.004
1.04
5.39
2.85
nA
nA
nA
Low-Level Logic Input
(Floating) Leakage
Low-Level Logic Input
(Floating) Leakage
(pin 17, 18, 19)
VIN = VDD, VDD = 1.71 V to 3.6 V
--
2.57
439.75
nA
Table 8: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C
Condition
VDD = 1.71 V VDD = 3.3 V VDD = 3.6 V Unit
Quiescent current
0.29
35.56
0.29
0.47
0.46
0.39
29.24
0.38
0.52
0.49
0.4
29.89
0.40
0.53
0.49
µA
µA
µA
µA
µA
BG Force On, Output Delay = 550 us
Charge Pump Mode - Any
LF OSC Force PWR On; Matrix PWR Down Dis; Pre-Divider = 1
LF OSC Force PWR On; Matrix PWR Down Dis; Pre-Divider = 16
RC OSC (25 kHz) Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 1; Second Divider = 1
µA
µA
µA
µA
µA
µA
4.52
4.30
5.19
4.73
5.31
4.80
RC OSC (25 kHz) Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 8; Second Divider = 1
RC OSC (2 MHz) Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 1; Second Divider = 1
34.18
16.92
80.11
57.28
59.68
23.22
112.34
62.06
64.61
24.43
120.23
64.75
RC OSC (2 MHz) Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 8; Second Divider = 1
RING OSC Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 1; Second Divider = 1
RING OSC Force PWR On; Matrix PWR Down Dis;
Pre-Divider = 16; Second Divider = 1
µA
µA
µA
µA
µA
µA
µA
Internal Vref
77.63
47.86
97.63
100
77.3.
41.90
94
77.95
42.56
94.67
99.04
63.06
99.41
99.69
DAC0 Force On
DAC0+DAC1 Force On
PGA Force On; Gain = 0.5; ADC SE; Ext_OUT Dis
PGA Force On; Gain = 1; ADC SE; Ext_OUT Dis/En
PGA Force On; Gain = 2; ADC SE; Ext_OUT Dis
PGA Force On; Gain = 4; ADC SE; Ext_OUT Dis
98.13
62.44
98.51
98.88
67.84
100.58
101.15
Datasheet
16-Mar-2020
Revision 3.3
22 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 8: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C(Continued)
Condition
VDD = 1.71 V VDD = 3.3 V VDD = 3.6 V Unit
µA
PGA Force On; Gain = 8; ADC SE; Ext_OUT Dis
101.87
46.09
99.59
40.10
100.47
40.75
ACMP0; Hyst Disable or Hyst = 25 mV; IN PIN6;
Buff Bandwidth = 1 kHz; Gain = 1; Vref = 1 V
µA
ACMP0; Hyst Disable; IN Buffered PIN6;
BUF Bandwidth = 1 kHz; Gain = 0.25, 0.33, 0.5; Vref = 1 V
µA
µA
µA
µA
µA
µA
µA
47.68
51.19
56.49
68.11
89.69
42.72
80.52
45.07
45.83
51.63
64.36
88.07
41.95
76.08
45.99
46.53
52.34
65.15
89.07
42.61
76.83
ACMP0; Hyst Disable; IN Buffered PIN6;
BUF Bandwidth = 1 kHz; Gain = 1; Vref = 1 V
ACMP0; Hyst Disable; IN Buffered PIN6;
BUF Bandwidth = 5 kHz; Gain = 1; Vref = 1 V
ACMP0; Hyst Disable; IN Buffered PIN6;
BUF Bandwidth = 20 kHz; Gain = 1; Vref = 1 V
ACMP0; Hyst Disable; IN Buffered PIN6;
BUF Bandwidth = 50 kHz; Gain = 1; Vref = 1 V
ACMP0; Hyst Disable; IN VDD; BUF Bandwidth = 1 kHz;
Gain = 1; Vref = 1 V
ACMP0; Hyst Disable; IN PIN6; BUF Bandwidth = 1 kHz;
100uA En; Gain = 1; Vref = 1 V
ACMP0,1,2,3,4,5; Hyst Disable; IN PIN6,12,13,15,3,4; BUF Bandwidth =
1 kHz; Gain = 1; Vref = 1 V
µA
µA
µA
70.90
4.69
65.73
4.19
66.36
4.26
ACMP0 WS En; Force Sleep Low; CNT Data = 10
ADC PD; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider = 1; WS En; Force Sleep Low; CNT Data = 10
35.23
37.45
37.56
ADC PD; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider = 1
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
368.32
379.01
36.28
387.98
400.05
38.58
389.54
401.65
38.75
ADC DI; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider = 1
ADC DI; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider = 1; WS En; Force Sleep Low; CNT Data = 10
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider - Any
168.86
16.57
168.06
16.64
168.84
16.75
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (25 kHz);
CLK Divider = 1; WS En; Force Sleep Low; CNT Data = 10
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (2 MHz);
CLK Divider = 1
204.74
198.20
18.96
239.56
223.08
21.86
247.46
228.91
22.52
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (2 MHz);
CLK Divider = 16
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RC OSC (2 MHz);
CLK Divider = 1; WS En; Force Sleep Low; CNT Data = 10
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RING OSC;
CLK Divider = 1
273.88
246.19
162.09
425.84
332.03
165.18
499.10
349.54
166.51
ADC SE; Vref = 1.2 V; Analog Force En; CLK Source: RING OSC;
CLK Divider = 16
ADC SE; Vref = PWR Div(0.25xVDD); Analog Force En; CLK Source:
RC OSC (25 kHz); CLK Divider = 1
Datasheet
16-Mar-2020
Revision 3.3
23 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 8: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C(Continued)
Condition
VDD = 1.71 V VDD = 3.3 V VDD = 3.6 V Unit
ADC SE; Vref = PWR Div(0.25xVDD); Analog Force En; CLK Source:
RC OSC (25k kHz); CLK Divider = 1; WS En; Force Sleep Low;
CNT Data = 10
µA
15.87
16.37
16.53
3.5 TIMING CHARACTERISTICS
Table 9: Typical Delay Estimated for Each Macrocell at T = 25°C
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6V
Note
Parameter Description
Unit
Rising Falling Rising Falling Rising Falling
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
19
21
28
23
27
27
33
--
17
18
26
19
25
23
--
6
7
6
6
6
6
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Both Matrix 2-bit LUT
Both Matrix 3-bit LUT
Matrix 0 4-bit LUT
9
9
9
8
8
7
7
6
Matrix 1 4-bit LUT
9
10
10
--
8
9
Both Matrix DFF Q
10
11
--
9
9
Both Matrix DFF nQ
Both Matrix DFF nSET Q
Both Matrix DFF nSET nQ
Both Matrix DFF nRST Q
10
--
--
9
--
10
9
30
28
--
11
10
--
--
--
31
10
--
Both Matrix DFF nRST nQ
Matrix 0 Digital Input to 1x 3-State
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
--
47
--
42
--
--
17
--
16
--
--
16
--
15
--
ns
ns
ns
ns
(Hi-Z to 0)
Matrix 0 Digital Input to 1x 3-State
(Hi-Z to 1)
Matrix 1 Digital Input to 1x 3-State
(Hi-Z to 0)
36
--
14
--
13
--
Matrix 1 Digital Input to 1x 3-State
(Hi-Z to 1)
41
15
14
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
44
36
--
42
34
40
32
16
13
--
17
14
16
12
15
12
--
16
13
15
11
ns
ns
ns
ns
Matrix 0 Digital Input to PP 1x
Matrix 1 Digital Input to PP 1x
Matrix 0 Digital Input to NMOS 1x
--
--
--
Matrix 1 Digital Input to NMOS 1x
Matrix 0 Digital Input to PP 2x 3-State
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
--
45
--
41
--
--
17
--
16
--
--
16
--
14
--
ns
ns
ns
ns
(Hi-Z to 0)
Matrix 0 Digital Input to PP 2x 3-State
(Hi-Z to 1)
Matrix 1 Digital Input to PP 2x 3-State
(Hi-Z to 0)
35
--
13
--
12
--
Matrix 1 Digital Input to PP 2x 3-State
(Hi-Z to 1)
39
15
14
tpd
tpd
tpd
Delay
Delay
Delay
42
34
--
41
32
39
16
13
--
16
13
15
15
12
--
15
12
14
ns
ns
ns
Matrix 0 Digital Input to PP 2x
Matrix 1 Digital Input to PP 2x
Matrix 0 Digital Input to NMOS 2x
Datasheet
16-Mar-2020
Revision 3.3
24 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 9: Typical Delay Estimated for Each Macrocell at T = 25°C(Continued)
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6V
Note
Parameter Description
Unit
Rising Falling Rising Falling Rising Falling
tpd
tpd
Delay
Delay
--
31
43
--
12
18
--
11
17
ns
ns
Matrix 1 Digital Input to NMOS 2x
Matrix 0 Digital Input to PP 1x With
Schmitt Trigger
44
17
16
Matrix 1 Digital Input to PP 1x With
Schmitt Trigger
tpd
Delay
38
35
14
15
13
14
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
51
41
19
25
27
30
--
564
392
16
24
22
--
18
15
6
187
134
7
17
14
5
168
121
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Matrix 0 Digital Input Low Voltage
Matrix 1 Digital Input Low Voltage
Both Matrix INV
9
9
8
8
Both Matrix LATCH Q
8
9
7
8
Both Matrix LATCH nQ
10
--
--
9
--
Both Matrix LATCH nSET Q
Both Matrix LATCH nSET nQ
Both Matrix LATCH nRST Q
Both Matrix LATCH nRST nQ
Matrix Ports P0 - P9
26
30
--
10
11
--
--
9
--
--
--
10
--
33
15
22
31
--
11
5
10
4
13
20
32
33
--
4
4
8
7
7
7
Matrix Ports P10 - P19
12
--
12
13
--
11
--
11
12
--
PGen CLK
PGen Hi-Z to 0
37
37
--
13
13
--
11
12
--
PGen Hi-Z to 1
35
40
38
--
14
16
15
--
13
15
14
--
Both Matrix Pipe Delay CLK Q
Both Matrix Pipe Delay CLK nQ
Both Matrix Pipe Delay CLK nRST Q
Both Matrix Pipe Delay CLK nRST nQ
--
--
--
45
16
15
Table 10: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C
Parameter
Description
Note
VDD = 1.71V VDD = 3.3V VDD = 3.6V Unit
Mode: (any) edge detector,
Output mode: Non-delayed
time 1
Pulse Width, 1 cell
401
798
1196
1592
37
160
316
473
630
13
148
292
437
582
12
ns
ns
ns
ns
ns
ns
ns
ns
Mode: (any) edge detector,
Output mode: Non-delayed
time 1
time 1
time 1
tpd
Pulse Width, 2 cell
Pulse Width, 3 cell
Pulse Width, 4 cell
Delay, 1 cell
Mode: (any) edge detector,
Output mode: Non-delayed
Mode: (any) edge detector,
Output mode: Non-delayed
Mode: (any) edge detector,
Output mode: Non-delayed
Mode: (any) edge detector,
Output mode: Non-delayed
tpd
Delay, 2 cell
37
13
12
Mode: (any) edge detector,
Output mode: Non-delayed
tpd
Delay, 3 cell
37
13
12
Mode: (any) edge detector,
Output mode: Non-delayed
tpd
Delay, 4 cell
37
13
12
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Table 10: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C (Continued)
Parameter
Description
Note
VDD = 1.71V VDD = 3.3V VDD = 3.6V Unit
Mode: (any) edge detector,
Output mode: Delayed
time 1
Pulse Width, 1 cell
393
790
157
312
466
621
78
145
288
430
573
71
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mode: (any) edge detector,
Output mode: Delayed
time 1
time 1
time 1
time 2
time 2
time 2
time 2
Pulse Width, 2 cell
Pulse Width, 3 cell
Pulse Width, 4 cell
Delay, 1 cell
Mode: (any) edge detector,
Output mode: Delayed
1179
1578
226
Mode: (any) edge detector,
Output mode: Delayed
Mode: (any) edge detector,
Output mode: Delayed
Mode: (any) edge detector,
Output mode: Delayed
Delay, 2 cell
407
143
207
271
172
328
485
641
128
186
244
158
303
447
592
Mode: (any) edge detector,
Output mode: Delayed
Delay, 3 cell
591
Mode: (any) edge detector,
Output mode: Delayed
Delay, 4 cell
772
time 2 +
time 1
Delay, 1 cell
Mode: Both edge delay
Mode: Both edge delay
Mode: Both edge delay
Mode: Both edge delay
438
time 2 +
time 1
Delay, 2 cell
835
time 2 +
time 1
Delay, 3 cell
1233
1631
time 2 +
time 1
Delay, 4 cell
Note: See Timing Diagram Section 17.1
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3.6 OSCILLATOR CHARACTERISTICS
See Section 19 Clocking
Table 11: Oscillators Frequency Limits
Temperature Range
Error, %
Power
Supply
Range
(VDD), V
+25 °C
-40 °C to +105 °C
Minimum Maximum
OSC
Minimum
Value, kHz
Maximum
Value, kHz
Error, %
Value, kHz Value, kHz
-16.2
+20.9
-16.2
+20.6
-15.8
+20.9
-15.8
-21.2
+23.3
-21.2
+23.2
-20.6
+23.3
-20.6
1.71 V to 3.6 V
1.449
2.092
2.087
2.092
1.364
1.364
1.373
2.133
2.132
2.133
1.8 V ± 5%
1.450
1.457
3.3 V ± 10%
LF OSC
(1.73 kHz)
3.3 V ± 10%
over lifetime at 105 °C
(Note 2)
1.457
1.454
2.161
2.092
1.373
1.371
2.202
2.133
+24.9
+27.3
-16
+20.9
-16
-20.8
+23.3
-20.8
2.3 V to 3.6 V
2.3 V to 3.6 V
over lifetime at 105 °C
(Note 2)
1.454
2.161
1.371
2.202
+24.9
-8.4
+27.3
-9.9
52.3
(Note 1)
1.71 V to 3.6 V
1.8 V ± 5%
22.888
31.065
22.527
38.073
+24.3
-6.6
+7.8
-1
-19.3
23.343
24.741
26.946
25.344
20.176
23.490
37.500
26.450
50 (Note 1)
-6
+5.8
-6
3.3 V ± 10%
3.3 V ± 10%
+1.4
-1
RC OSC
(25 kHz)
24.741
24.432
24.433
26.544
26.066
27.266
23.490
23.353
23.353
27.650
27.063
28.263
over lifetime at 105 °C
(Note 2)
+6.2
+10.6
-2.3
+4.3
-2.3
-6.6
+8.3
-6.6
2.3 V to 3.6 V
2.3 V to 3.6 V
over lifetime at 105 °C
(Note 2)
+9.1
+13.1
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Table 11: Oscillators Frequency Limits(Continued)
Temperature Range
Error, %
Power
Supply
Range
(VDD), V
+25 °C
-40 °C to +105 °C
Minimum Maximum
OSC
Minimum
Value, kHz
Maximum
Value, kHz
Error, %
Value, kHz Value, kHz
-13.7
+5.5
-2.9
+2.7
-1.6
+2
-16.2
+9
1.71 V to 3.6 V
1726.1
2110.3
2053
1676
2179.1
2117.4
2121.8
-6.5
+5.9
-7.9
+6.1
-7.9
1.8 V ± 5%
1942.4
1967.8
1869.8
1842.4
3.3 V ± 10%
3.3 V ± 10%
2039.9
RC OSC
(2 MHz)
-1.6
1967.8
1908.3
1908.3
2119.9
2095.6
2175.6
1842.4
1842.4
1842.4
2201.8
2158
over lifetime at 105 °C
(Note 2)
+6
+10.1
-4.6
+4.8
-4.6
-7.9
+7.9
-7.9
2.3 V to 3.6 V
2.3 V to 3.6 V
2238
over lifetime at 105 °C
(Note 2)
+11.9
+8.8
-19.3
+12.7
-18.8
+12.7
-12.3
+11.9
-12.3
-24.4
+12.7
-23.8
+12.7
-16.5
+11.9
-16.5
1.71 V to 3.6 V
1.8 V ± 5%
21787.1
21920
30437.8
30424.3
30224
20418
20579.6
22551.8
30437.8
30424.3
30224
3.3 V ± 10%
3.3 V ± 10%
23687.7
Ring OSC
(27 MHz)
23687.7
23679.8
23679.8
31304
30224.7
31304.7
22551.8
22548.5
22548.5
31304
30224.7
31304.7
over lifetime at 105 °C
(Note 2)
+15.9
+15.9
-12.3
+11.9
-12.3
-16.5
+11.9
-16.5
2.3 V to 3.6 V
2.3 V to 3.6 V
over lifetime at 105 °C
(Note 2)
+15.9
+15.9
Note 1 Based on characterization data and is not guaranteed. Due to the large frequency error of this device at 1.8V, the
SLG46620-A is not recommended for applications requiring accurate frequency at VDD below 2.2V. This maximum
frequency value is documented only to provide designers guidance on the part's expected performance at these condi-
tions.
Note 2 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
3.6.1 OSC Power-On Delay
Table 12: Oscillators Power-On Delay
Power
Supply
Range
LF OSC (1.73 kHz)
RC OSC (2 MHz)
RC OSC (25 kHz)
Ring OSC (27MHz)
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
(VDD), V
Value, µs
Value, ns
Value, µs
Value, ns
1.71
575.10
722.19
886.5
1335.33
41.55
45.16
134
283.46
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Table 12: Oscillators Power-On Delay(Continued)
Power
Supply
Range
LF OSC (1.73 kHz)
RC OSC (2 MHz)
RC OSC (25 kHz)
Ring OSC (27MHz)
Typical
Value, µs
Maximum
Value, µs
Typical
Maximum
Value, ns
Typical
Value, µs
Maximum
Value, µs
Typical
Value, ns
Maximum
Value, ns
(VDD), V
Value, ns
695.5
677.5
662
3
566.94
564.91
562.19
709.98
900.10
849.62
810.79
40.56
43.36
43.11
43.19
88.5
87
150.98
155.79
150.40
3.3
3.6
706.96
40.51
706.39
40.46
82.75
Note 1 Typical value is given for T = 25 °C, maximum value is given for T = -40 °C to 105 °C
Note 2 RC OSC Power Setting: "Auto Power-On", RC OSC Clock to Matrix Input: “Enable”
3.7 ACMP CHARACTERISTICS
Table 13: ACMP Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
0
Typ
--
Max
Unit
V
Positive Input
Negative Input
VDD
1.2
ACMP Input Voltage
VACMP
Range
0
--
V
T = 25°C
-8.09
-11.77
-9.34
-9.35
-17.43
-23.30
-17.59
-23.76
-39.29
-74.22
--
20.71 mV
20.71 mV
Vhys = 0 mV, Gain =1,
Vref = 1200 mV
--
ACMP Input Voltage
Offset
Voffset
T = 25°C
T = 25°C
T = 25°C
T = 25°C
--
5.96
6.36
mV
mV
Vhys = 0 mV, Gain =1,
Vref = 100 mV
--
--
13.39 mV
19.34 mV
13.15 mV
19.71 mV
20.62 mV
36.09 mV
Vhys = 0 mV, Gain =1,
Vref = 100 mV
--
--
ACMP Buffer Input
Voltage Offset
Vhys = 0 mV, Gain =1,
Vref = 600 mV
VBUF_offset
--
--
Vhys = 0 mV, Gain =1,
Vref = 1200 mV
--
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Table 13: ACMP Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Force BG on - Disable,
Output Delay - 100 µs,
VDD = 1.71 V
--
89.1
696.2
µs
Force BG on - Disable,
Output Delay - 100 µs,
VDD ≥ 3 V
--
--
--
84.2
732.6
µs
Force BG on - Disable,
Output Delay - 550 µs,
VDD = 1.71 V
421.7 3381.8 µs
418.6 3349.8 µs
Force BG on - Disable,
Output delay - 550 µs,
VDD ≥ 3 V
Force BG on - Enable,
ACMP0,1, 2, 3, 4,
Vref = 50 mV to 600 mV,
--
--
--
--
--
--
--
--
290.7
194.9
401.1
280
ns
ns
V
DD = 1.71 V
Force BG on - Enable,
ACMP0,1, 2, 3, 4,
Vref = 50 mV to 600 mV,
V
DD ≥ 3 V
ACMP Power-On
delay, Minimal
requiredwaketimefor
the “Wake and Sleep
function”
Force BG on - Enable,
ACMP0,1, 2, 3, 4,
Vref = 1200 mV,
tstart
ACMP Startup Time
469.1 1040.4 ns
V
DD = 1.71 V
Force BG on - Enable,
ACMP0,1, 2, 3, 4,
Vref = 1200 mV,
221.3
405.6
291.4
289.1
514.7
389.2
ns
ns
ns
V
DD ≥ 3 V
Force BG on - Enable,
ACM5,
Vref = 50 mV to 600 mV,
V
DD = 1.71 V
Force BG on - Enable,
ACMP5,
Vref = 50 mV to 600 mV,
VDD ≥ 3 V
Force BG on - Enable,
ACMP5,
Vref = 1200 mV,
718.6 1653.6 ns
VDD = 1.71 V
Force BG on - Enable,
ACMP5,
Vref = 1200 mV,
335.7
449.4
ns
VDD ≥ 3 V
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Table 13: ACMP Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
VHYS = 25 mV
VIL = Vref - VHYS/2
VIH = Vref + VHYS/2
T = 25°C
10.59
--
36.5
mV
VHYS = 50 mV
VIL = Vref - VHYS
VIH = Vref
T = 25°C
T = 25°C
45.57
193.38
3.35
--
--
--
--
--
59.75 mV
210.47 mV
37.75 mV
VHYS = 200 mV
VIL = Vref - VHYS
VIH = Vin
VHYS
Built-in Hysteresis
VHYS = 25 mV
VIL = Vref - VHYS/2
VIH = Vref + VHYS/2
V
HYS = 50 mV
VIL = Vref - VHYS
VIH = Vref
45.45
193.06
64
mV
VHYS = 200 mV
V
IL = Vref - VHYS
214.68 mV
VIH = Vin
Gain = 1x
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
G = 1
--
100.0
1.0
0.8
1.0
1
--
ΜΩ
ΜΩ
ΜΩ
ΜΩ
--
--
Rsin
Series Input Resistance
--
--
--
--
Vref = 50…1200 mV
Vref = 100 mV
Vref = 600 mV
Vref = 100 mV
Vref = 600 mV
Vref = 1200 mV
--
--
-1.98
-1.14
-2.39
-0.91
-0.72
-1.01
-1.28
-0.37
-2.06
-2.32
-1.03
--
2.65
1.10
2.69
1.24
0.92
3.82
3.92
2.56
3.11
3.08
1.47
%
%
%
%
%
%
%
%
%
%
%
G = 0.5, VDD = 1.71 V
--
--
G = 0.5,
--
V
DD = 3.3 V ±10 %
Gain error (including
threshold and internal
Vref error),
--
G
G = 0.33, VDD = 1.71 V Vref = 100 mV
--
T = (-40…+105)°C
Vref = 100 mV
G = 0.33,
--
V
DD = 3.3 V ±10 %
Vref = 600 mV
--
G = 0.25, VDD = 1.71 V Vref = 100 mV
--
Vref = 100 mV
G = 0.25,
VDD = 3.3 V ±10 %
--
Vref = 600 mV
--
Note Typical value is given at T = 25 °C
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3.8 VREF OUT CHARACTERISTICS
Table 14: Vref OUT Specifications at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted
Parameter Description
Note
Conditions
T = 25 °C
Min
-10.47
-13.92
-1.64
-2.35
-0.85
-1.49
Typ
--
Max
12.72
11.97
2.26
2.70
1.24
1.48
Unit
%
Vref = 100 mV
--
%
T = 25 °C
T = 25 °C
--
%
Vref OUT Vref OUT through PINs
Vref = 600 mV
Vref = 1200 mV
Error
18 or 19
--
%
--
%
--
%
Table 15: Delay Estimated for Each ACMP at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V Unless Otherwise Noted
Typ
Max
Note
Parameter Description
Propagation Delay,
Unit
Rising Falling Rising Falling
VDD = 1.71 V
VDD = 3.3 V
0.98
0.82
0.83
0.53
0.36
0.35
14.7
8.81
8.92
5.52
3.27
3.27
1.17 3.7181 4.4846 µs
Response Time
for ACMP 0
VIN+ Source - Buffered PIN
Overdrive = 10 mV
0.72
0.75
0.61
0.37
0.36
1.62
1.67
3.19
0.69
0.67
1.49
1.56
3.13
0.78
0.76
µs
µs
µs
µs
µs
V
DD = 3.6 V
VDD = 1.71 V
VDD = 3.3 V
Overdrive = 100 mV
Overdrive = 10 mV
Overdrive = 100 mV
Overdrive = 10 mV
Overdrive = 100 mV
V
DD = 3.6 V
VDD = 1.71 V
DD = 3.3 V
Propagation Delay,
Response Time
for ACMP 0 to 4
VIN+ Source - PIN
13.92 283.55 269.09 µs
8.85 116.97 104.27 µs
8.92 117.28 106.04 µs
4.79 144.40 120.16 µs
V
VDD = 3.6 V
VDD = 1.71 V
VDD = 3.3 V
2.91
2.92
49.47 42.87 µs
50.99 43.57 µs
V
DD = 3.6 V
Propagation Delay,
Response Time
for ACMP 5
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6 V
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6 V
26.59 25.02 438.23 301.34 µs
15.99 16.29 177.78 132.07 µs
16.24 16.34 184.23 133.69 µs
VIN+ Source - PIN
PROP
10.17
5.75
5.77
7.78 226.93 153.63 µs
4.76
4.76
78.08 57.31 µs
78.15 57.61 µs
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3.9 ADC CHARACTERISTICS INCLUDING PGA
Note: PGA input voltage should not exceed values given in Table 3.
Table 16: Single-Ended ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
60
Max
2060
1030
520
Unit
mV
G = 0.5
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
VDD = 2.5 to 3.6 V
30
mV
Input Voltage Range
(bit 0 to bit 255),
Vinp
20
mV
relative to GND
15
265
mV
12
137
mV
T = 25°C, VDD = 3.3 V to 3.6 V
-2.6
-4.9
-2.2
-1.7
-2.6
-4.0
-4.6
-5.7
-8.5
-14.3
-4.4
-5.8
-4.7
-4.5
-3.9
-4.7
-6.8
-6.3
-5.1
-5.2
-2.8
-6.1
-2.9
-6.4
-2.8
-6.2
-2.3
-5.9
-2.3
-5.3
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
+3.8
+4.2
+4.3
+3.3
+3.7
+5.0
+6.4
+6.3
+7.7
+12.7
T = 25°C
Offset Zero Error
(Note 2)
ZE
VDD = 3.3 to 3.6 V
T = 25°C, VDD = 3.3 V to 3.6 V
+5.1
+4.2
+4.0
+4.0
+3.8
+6.4
+5.3
+6.1
+5.9
+6.5
+2.1
+2.1
+2.4
+2.3
+2.1
+2.4
+2.0
+2.3
+2.2
+2.5
T = 25°C
GE
Gain Error
VDD = 3.3 to 3.6 V
T = 25°C, VDD = 3.3 to 3.6 V
VDD = 3.3 to 3.6 V
T = 25°C
G = 0.5
G = 1
G = 2
G = 4
G = 8
T = 25°C
T = 25°C
T = 25°C
Integral Non-Linearity
Error
INL
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Table 16: Single-Ended ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
-1.5
-1.6
-1.7
-1.7
-1.3
-1.5
-1.3
-1.4
-1.4
-1.4
Max
+0.3
+0.3
+0.3
+0.3
+0.3
+0.4
+0.4
+0.4
+0.6
+0.6
Unit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
T = 25°C, VDD = 3.3 to 3.6 V
VDD = 3.3 to 3.6 V
T = 25°C
G = 0.5
G = 1
G = 2
G = 4
G = 8
T = 25°C
T = 25°C
T = 25°C
Differential Non-
DNL
Linearity
Note 1 To ensure linear operation, absolute input voltage on each pin should not exceed VDD - 0.5
Note 2 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
Table 17: Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
-500
Max
500
Unit
mV
mV
mV
mV
mV
mV
G = 1
G = 2
-250
-125
250
125
Input Voltage Range
Vind
(bit 0 to bit 255),
Differential
G = 4
G = 8
-62.5
-31.25
400
62.5
31.25
550
G = 16
G = 1, 2, 4, 8, 16
Typical Input
Common Voltage
(Note 2)
VDD = 1.8 V ±5%
VDD = 3.3 V ±10%
Vcm
400
950
mV
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
-2.4
-2.4
-2.4
-3.1
-6.8
-6.3
-6.3
-8.1
-10.3
-18.3
+3.9
+3.6
+3.7
+4.1
+6.3
+4.8
+5.9
+5.9
+9.0
+17.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
T = 25°C
Offset Zero Error
(Note 4)
ZE
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Table 17: Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
-5.3
Max
+2.9
Unit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
-5.1
-4,0
-3.6
-5.8
-6.4
-6.1
-6.3
-5.1
-6.9
-2.4
-5.5
-2.4
-5.3
-2.5
-5.5
-2.4
-5.6
-3.2
-5.6
-1.3
-1.3
-1.2
-1.2
-1.0
-1.2
-1,0
-1.1
-1.3
-1.3
+3.6
+3.3
+3.1
+4.3
+5.0
+6.2
+6.7
+5.2
+7.5
+1.9
+2.0
+1.9
+2,0
+1.8
+2.1
+2.2
+2.4
+3.3
+3.4
+0.5
+0.5
+0.5
+0.5
+0.5
+0.5
+0.6
+0.7
+1.1
+1.1
T = 25°C
GE
Gain Error
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
Integral Non-Linearity
Error
INL
Differential Non-
Linearity
DNL
Note 1 Vcm = 500 mV
Note 2 Vcm range is given for stable CMRR > 34 dB.
Note 3 To ensure linear operation, absolute input voltage on each pin should not exceed VDD - 0.5.
Note 4 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
Table 18: Pseudo-Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Input Voltage Range
Note
Conditions
Min
Max
980
Unit
G = 1
0
mV
Vind
(bit 0 to bit 255),
Differential
G = 2
0
490
mV
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Table 18: Pseudo-Differential ADC Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise
Parameter Description
Note
Conditions
Min
500
Max
500
Unit
VDD = 1.8 V ±5%
G = 1, 2
mV
Typical Negative input
Vinn
voltage range
VDD = 3.3 V ±10%
500
1250
mV
T = 25°C, VDD = 3.3 to 3.6 V
G = 1
G = 2
G = 1
G = 2
G = 1
G = 2
G = 1
G = 2
-3.1
-2.5
-5.3
-6.5
-3.5
-5.0
-4.8
-6.8
-2.2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
+2.9
+2.7
+4.5
+4.4
T = 25°C
Offset Zero Error
(Note 4)
ZE
VDD = 3.3 to 3.6 V
T = 25°C, VDD = 3.3 to 3.6 V
+3.5
+4.1
+6.2
+5.9
T = 25°C
GE
INL
Gain Error
VDD = 3.3 to 3.6 V
T = 25°C, VDD = 3.3 to 3.6 V
+1.8
G = 1
G = 2
G = 1
G = 2
V
DD = 3.3 to 3.6 V
-3.2
-2.3
-3.2
-1.1
LSB
LSB
LSB
LSB
Integral Non-Linearity
Error
+1.9
+2.6
+3.1
T = 25°C
T = 25°C, VDD = 3.3 to 3.6 V
+0.4
V
DD = 3.3 to 3.6 V
-1.1
-1.1
-1.1
LSB
LSB
LSB
Differential Non-
Linearity
+0.4
+0.4
+0.4
DNL
T = 25°C
Note 1 Vcm = 500 mV
Note 2 Vinn is given for convenience instead of Vcm.
Note 3 To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5.
Note 4 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
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3.10 PGA SPECIFICATIONS
Note 1 PGA input voltage should not exceed values given in Section 3.1.
Table 19: Single-Ended PGA Operation, T = -40°C to +105°C, VDD = 1.71 V to 3.6V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
T = 25°C,
G = 0.5
-24.65
1.15
+27.61
mV
VDD = 3.3 V to 3.6 V
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
G = 0.5
G = 1
G = 2
G = 4
G = 8
T = 25°C
-9.59
-14.76
-13.74
-13.47
-34.49
-12.83
-20.13
-18.42
-18.57
-0.8
0.95
-0.80
-1.02
-1.31
1.20
0.91
0.77
1.04
1.23
+13.52
+12.45
+10.38
+10.48
+33.34
+15.37
+14.77
+11.53
+12.25
mV
mV
mV
mV
mV
mV
mV
mV
mV
%
T = 25°C
T = 25°C
Offset Voltage
(RTI (Note 1))
(Note 3)
T = 25°C
Vos
VDD = 3.3 V to 3.6 V
VDD = 3.3 V to 3.6 V
0.2
0
1.1
0.1
1.0
0.9
0.8
-0.2
%
ΔG
Vsw
Gain Error
-1.5
-0.3
-0.6
-1.3
%
-2.3
%
-4.0
%
Output Voltage
Swing
50 to
1380
--
--
mV
VDD 3.3 V to 3.6 V
G = 0.5
G = 1
G = 2
G = 4
G = 8
56.65
80.10
97.83
108.5
144.1
--
--
--
--
--
1257
1155
1159
1156
1143
mV
mV
mV
mV
mV
Linear Output
Voltage Range
(Note 2)
VOUT_LIN
Note 1 RTI - referred to input.
Note 2 Gain Error < 10%
Note 3 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
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Table 20: Differential PGA Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Offset Voltage
Vos
Vid = 0
(RTO,
All gains
--
550
--
mV
(Note 2))
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
G = 1
G = 2
G = 4
G = 8
G = 16
T = 25°C
T = 25°C
T = 25°C
T = 25°C
T = 25°C
-3.07
-4.01
-5.84
-9.83
-21.57
-15.07
-16.99
-23.44
-38.27
-70.14
-1.4
0.86
0.80
0.57
0.28
-0.26
0.14
0.18
0.18
0.13
-0.06
-0.2
-0.5
-0.9
-1.5
-1.8
57
+5.64
+5.96
+8.10
+12.05
+23.96
+12.38
+14.37
+20.45
+35.20
+70.15
0.9
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
%
Offset Voltage
Error (RTO)
(Note 4)
ΔVos
-2.0
0.9
%
ΔG
Gain Error
-2.5
0.6
%
-3.9
0.4
%
-4.3
0.6
%
--
--
dB
dB
dB
dB
dB
--
57
--
Common-Mode
Rejection Rate
CMRR
--
56
--
--
55
--
--
51
--
Input Common
Mode Range
ICMR
Vsw
All gains
See Figure 22
Output Voltage
Swing
50 to
1380
--
--
mV
G = 1
G = 2
G = 4
G = 8
G = 16
101.5
102.8
109.8
156.6
156.6
--
--
--
--
--
1262
1262
1266
1327
1327
mV
mV
mV
mV
mV
Linear Output
Voltage Range
(Note 3)
VOUT_LIN
Note 1 ADC - Power-On, Vcm = 500 mV
Note 2 RTO - referred to output.
Note 3 Gain Error < 10%.
Note 4 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
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Table 21: Pseudo-Differential PGA Operation, T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Offset Voltage
Vos
Vid = 0
(RTO,
All gains
--
180
--
mV
(Note 2))
G = 1
G = 2
G = 1
G = 2
G = 1
G = 2
G = 1
G = 2
T = 25°C,
T = 25°C
-2.53
-3.78
-12.75
-16.04
-3.0
0.68
0.64
0.50
0.43
-0.3
-0.5
56
+5.43
+7.19
+13.70
+17.09
1.1
mV
mV
mV
mV
%
Offset Voltage
Error (RTO)
(Note 4)
ΔVos
ΔG
Gain Error
-2.2
0.9
%
--
--
dB
dB
Common-Mode
Rejection Rate
CMRR
--
57
--
Negative Input
Voltage Range
See Figure 23
and Figure 24
Vinn
Vsw
All gains
Output Voltage
Swing
50 to
1380
--
--
mV
Linear Output
Voltage Range
(Note 3)
G = 1
G = 2
83.75
96.38
--
--
1252
1155
mV
mV
VOUT_LIN
Note 1 ADC - Power-On, Vinn = 500 mV
Note 2 RTO - Referred to output
Note 3 Gain Error < 10%.
Note 4 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
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Table 22: Differential/Pseudo-Differential PGA Mode, T = -40°C to +105°C, VDD = 1.71V to 3.6V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
T = 25°C,
VDD = 3.3 V
Offset Voltage
Vos
All gains
--
±1.9
--
mV
(RTI (Note 2))
G = 1
G = 2
G = 4
G = 8
G = 16
--
--
--
--
--
-0.2
-0.5
-0.9
-1.5
-1.8
--
--
--
--
--
%
%
%
%
%
ΔG
Gain Error
Note 1 ADC - Power-down, Vcm = 500 mV
Note 2 RTI - referred to input.
Note 3 WhenADC is powered down, PGAoperation in Differential or Pseudo-Differential mode is not recommended. Parameters
in Table 22 are for reference only.
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4
User Programmability
The SLG46620-A is a user programmable device with One-Time-Programmable (OTP) memory elements that are able to
configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial
devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a
production process.
Product
Definition
Customer creates their own design in
E-mail Product Idea, Definition, Drawing or
GreenPAK Designer
Schematic to
CMBUGreenPAK@diasemi.com
Emulate design to verify behavior
Dialog Semiconductor Applications
Engineers will review design specifications
with customer
Program Engineering Samples with
GreenPAK Development Tools
Samples, Design and Characterization
Report send to customer
Customer verifies GreenPAK in system
design
GreenPAK Design
approved
GreenPAK Design
approved
Customers verifies GreenPAK design
E-mail .gpx to
CMBUGreenPAK@diasemi.com
GreenPAK Design
Approved in system test
Custom GreenPAK part enters production
Figure 1: Steps to Create a Custom GreenPAK Device
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5
IO Pins
The SLG46620-A has a total of 18 multi-function IO pins which can function as either a user defined Input or Output, as well as
serving as a special function (such as outputting the voltage reference), or serving as a signal for programming of the on-chip
Non Volatile Memory (NVM). Refer to Section 2 for normal and programming mode pin definitions
Of the 18 user defined IO pins on the SLG46620-A, all but one of the pins (Pin 2) can serve as both digital input and digital output.
Pin 2 can only serve as a digital input pin or external reset.
5.1 INPUT MODES
Each IO pin can be configured as a digital input pin with/without buffered Schmitt trigger, or can also be configured as a low voltage
digital input. Pins 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 and 17 can also be configured to serve as analog inputs to the on-chip
comparators. Pins 18 and 19 can also be configured as analog reference voltage outputs.
5.2 OUTPUT MODES
Pins 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, and 20 can all be configured as digital output pins.
5.3 PULL-UP/DOWN RESISTORS
All IO pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ and 1 MΩ. In the case of Pin 2, the resistors are fixed to a Pull-down configuration. In the case of all other IO
pins, the internal resistors can be configured as either Pull-up or Pull-downs.
5.4 GPI STRUCTURE
5.4.1 GPI Structure (for Pin 2)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0
01: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0
10: Low Voltage Digital IN mode, LV_EN = 1, OE = 0
11: Reserved
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Note 1: OE cannot be selected by user
Note 2: OE is Matrix output, Digital IN is Matrix input
Low Voltage
Input
LV_EN
OE
Floating
PAD
s0
s1
s2
s3
VDD
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Figure 2: PIN 2 GPI Structure Diagram
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5.5 MATRIX OE IO STRUCTURE
5.5.1 Matrix OE IO Structure (for Pins 3, 5, 7, 9, 13, 14, 16, 18, 19)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1
01: Digital IN with Schmitt Trigger, SMT_EN = 1
10: Low Voltage Digital IN mode, LV_EN = 1
11: Analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Output Mode [1:0]
00: 1x Push-Pull mode, PP1x_EN = 1
01: 2x Push-Pull mode, PP2x_EN = 1, PP1x_EN = 1
10: 1x NMOS Open-DRAIN mode, OD1x_EN = 1
11: 2x NMOS Open-DRAIN mode, OD2x_EN = 1, OD1x_EN = 1
Low Voltage
Input
Note 1: Digital OUT and OE are Matrix output, Digital IN is Matrix input
Note 2: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
Digital OUT
OE
OE
OD1x_EN
PP1x_EN
VDD
PAD
VDD
Digital OUT
Digital OUT
OE
OE
OD2x_EN
PP2x_EN
Figure 3: Matrix OE IO Structure Diagram
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5.5.2 Matrix OE 4x Drive Structure (for Pin 10)
Trigger Input
Input Mode [1:0]
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1
01: Digital IN with Schmitt Trigger, SMT_EN = 1
10: Low Voltage Digital IN mode, LV_EN = 1
11: Analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Output Mode [1:0]
00: 1x Push-Pull mode, PP1x_EN = 1
01: 2x Push-Pull mode, PP2x_EN = 1, PP1x_EN = 1
10: 1x NMOS Open-DRAIN mode, OD1x_EN =1, ODn_EN = 1
11: 2x NMOS Open-DRAIN mode, OD2x_EN =1, OD1x_en=1, ODn_EN = 1
Low Voltage
Input
Note 1: Digital OUT and OE are Matrix output, Digital IN is Matrix input
Note 2: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
VDD
Digital OUT
OE
OD2x_EN
4x_EN
PAD
VDD
ODn_EN
Digital OUT
OE
Digital OUT
OE
4x_EN
ODn_EN
PP2x_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 4: Matrix OE IO 4x Drive Structure Diagram
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5.6 REGISTER OE IO STRUCTURE
5.6.1 Register OE IO Structure (for Pins 4, 6, 8, 15, 17, 20)
Trigger Input
Mode [2:0]
WOSMT_EN
SMT_EN
000: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0
001: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0
010: Low Voltage Digital IN mode, LV_EN = 1, OE = 0
011: Analog IO mode
OE
OE
Schmitt
Trigger Input
Digital IN
100: Push-Pull mode, PP_EN = 1, OE = 1
101: NMOS Open-DRAIN mode, ODn_EN = 1, OE = 1
110: PMOS Open-DRAIN mode, ODp_EN = 1, OE = 1
111: Analog IO and NMOS Open-DRAIN mode, ODn_EN = 1 and AIO_EN = 1
Low Voltage
Input
Note 1: OE cannot be selected by user
Note 2: Can be varied over PVT, for reference only
Note 3: Digital OUT and OE are Matrix output, Digital IN is Matrix input
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
s1
s0
172 Ω
(Note 2)
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
VDD
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
ODp_EN
Digital OUT
OE
Digital OUT
OE
ODn_EN
2x_EN
PP_EN
VDD
PAD
VDD
ODp_EN
Digital OUT
OE
Digital OUT
OE
2x_EN
PP_EN
2x_EN
ODn_EN
Figure 5: Register IO Structure Diagram
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5.6.2 Register OE 4x Drive Structure (for Pin 12)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0
001: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0
010: Low Voltage Digital IN mode, LV_EN = 1, OE = 0
011: Analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
100: Push-Pull mode, PP_EN = 1, OE = 1
101: NMOS Open-DRAIN mode, ODn_EN = 1, OE = 1
110: PMOS Open-DRAIN mode, ODp_EN = 1, OE = 1
111: Analog IO and NMOS Open-DRAIN mode, odn_EN = 1 and AIO_EN = 1
Digital IN
Note 1: OE cannot be selected by user
Note 2: Digital OUT and OE are Matrix output, Digital IN is Matrix input
Note 3: Can be varied over PVT, for reference only
Low Voltage
Input
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 3)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
Pull-up_EN
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
VDD
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
Digital OUT
OE
VDD
OD2x_EN
4x_EN
ODn_EN
PAD
VDD
Digital OUT
OE
Digital OUT
OE
4x_EN
PP2x_EN
ODn_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 6: Register OE 4x Drive Structure Diagram
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5.7 IO TYPICAL PERFORMANCE
Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C
45
40
35
30
25
20
15
10
5
NMOS 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 3.3 V
NMOS 1x @ VDD = 1.71 V
Push-Pull 1x @ VDD = 1.71 V
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VOL (V)
Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C
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80
NMOS 2x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 3.3 V
NMOS 2x @ VDD = 1.71 V
Push-Pull 2x @ VDD = 1.71 V
70
60
50
40
30
20
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VOL (V)
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C
160
150
140
130
120
110
100
90
NMOS 4x @ VDD = 3.3 V
Push-Pull 4x @ VDD = 3.3 V
NMOS 4x @ VDD = 1.71 V
Push-Pull 4x @ VDD = 1.71 V
80
70
60
50
40
30
20
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VOL (V)
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
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6
Connection Matrix
The SLG46620-A has two Connection Matrices, which are used to create the internal routing for internal digital signals inside the
device, once it is programmed. The registers are programmed from the one-time NVM cells during Test Mode Operation. All of
the connection points for each logic cell within the SLG46620-A have a specific digital bit code assigned to it that is either set to
active “High” or inactive “Low” based on the design that is created. Once the 2048 register bits within the SLG46620-A are
programmed, a fully custom circuit will be created.
Each Connection Matrix within the device has 64 inputs and 95 outputs. Each of the 64 inputs to each Connection Matrix is hard-
wired to the digital output of a particular source macrocell, including I/O pins, LUTs, ADC, analog comparators, other digital
macrocells and VDD and VSS. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. All
macrocells associated with a particular matrix has both its inputs and outputs connected to that matrix. To make connections to
macrocells associated with the other matrix, the user can select the Matrix Cross Connection lines (see Figure 11).
Each matrix has 10 dedicated output connections for connecting to the other matrix, known as the “Cross Connection “outputs.
When using these cross connections, any macrocell can be connected to any other macrocell in the device by first going through
the other matrix. As there is fixed number of the Matrix Cross Connections, it is important when making connections of the outputs
of macrocells to the inputs of other macrocells that this is done within the same matrix whenever possible. This will leave the
Matrix Cross Connection lines free for digital connections to resources associated with the other matrix.
For a complete list of the SLG46620-A’s register table, see Section 23.
Matrix 0
Matrix 1
Matrix 0 to Matrix 1 Cross Connection
Matrix 1 to Matrix 0 Cross Connection
Figure 11: Matrix Cross Connection Block Diagram
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Matrix Input Signal
N
Functions
GROUND
0
1
2
3
LUT2_0 Output
LUT2_1 Output
LUT2_2 Output
Cross Connection In-
61
62
63
put[9] from Matrix 1
nRESET_matrix
VDD
Matrix Inputs
N
0
1
2
94
Registers
[5:0]
[11:6]
[17:12]
[569:564]
IN0 of LUT2_0
IN0 of LUT2_1
IN0 of LUT2_1
Cross Connection
Output[9] to Matrix 1
Function
Matrix Outputs
Figure 12: Connection Matrix 0
Matrix Input Signal
N
0
1
2
3
Functions
GROUND
LUT2_4 Output
LUT2_5 Output
LUT2_6 Output
Cross Connection In-
61
62
63
put[9] from Matrix 0
nRESET_matrix
VDD
Matrix Inputs
N
0
1
2
94
Registers
register[1029:1024] register[1035:1030] register[1041:1036]
IN0 of LUT2_4 IN0 of LUT2_4 IN0 of LUT2_5
registers 1593:1588]
Cross Connection
Output[9] to Matrix 0
Function
Matrix Outputs
Figure 13: Connection Matrix 1
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Function
Connection Matrix
Pin 13
LUT
Pin 12
Pin 13
Pin 14
Pin 12
LUT
Pin 14
Figure 14: Connection Matrix Example
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6.1 MATRIX INPUT 0 TABLE
Table 23: Matrix 0 Input Table
Matrix Decode
N
Matrix 0 Input Signal Function
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GROUND
1
LUT2_0 Output
2
LUT2_1 Output
3
LUT2_2 Output
4
LUT2_3 Output
5
LUT3_0 Output
6
LUT3_1 Output
7
LUT3_2 Output
8
LUT3_3 Output
9
LUT3_4 Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
LUT3_5 Output
LUT3_6 Output
LUT3_7 Output
LUT4_0/PGEN Output
DFF0/LATCH0 Output
DFF1/LATCH1 Output
DFF2/LATCH2 Output
DFF3/LATCH3 Output
DFF4/LATCH4 Output
DFF5/LATCH5 Output
Pipe Delay 0 Out0
Pipe Delay 0 Out1
Edge Detect Programmable Delay 0 Output
Inverter 0 Output
Pin2 Digital Output
Pin3 Digital Output
Pin4 Digital Output
Pin5 Digital Output
Pin6 Digital Output
Pin7 Digital Output
Pin8 Digital Output
Pin9 Digital Output
Pin10 Digital Output
ACMP0 Output
ACMP4 Output
ACMP5 Output
DLY0/CNT0 Output
DLY2/CNT2 Output
Datasheet
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Table 23: Matrix 0 Input Table
Matrix Decode
N
Matrix 0 Input Signal Function
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DLY5/CNT5 Output
DLY6/CNT6 Output
DLY9/CNT9 Output
Sig_BG_OK
Power Detector Output
ADC interrupt
SPI interrupt
GROUND
GROUND
GROUND
Ring Oscillator Output
RC Oscillator Output
Low Frequency Oscillator Output
GROUND
Cross Connection Input from Matrix 1 [0]
Cross Connection Input from Matrix 1 [1]
Cross Connection Input from Matrix 1 [2]
Cross Connection Input from Matrix 1 [3]
Cross Connection Input from Matrix 1 [4]
Cross Connection Input from Matrix 1 [5]
Cross Connection Input from Matrix 1 [6]
Cross Connection Input from Matrix 1 [7]
Cross Connection Input from Matrix 1 [8]
Cross Connection Input from Matrix 1 [9]
nReset_Matrix
VDD
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6.2 MATRIX 0 OUTPUT TABLE
Table 24: Matrix 0 Output Table
Register Bit
Matrix Output
Number
Matrix 0 Output Signal Function
Address
[5:0]
Matrix 0 OUT: In0 of LUT2_0
Matrix 0 OUT: In1 of LUT2_0
Matrix 0 OUT: In0 of LUT2_1
Matrix 0 OUT: In1 of LUT2_1
Matrix 0 OUT: In0 of LUT2_2
Matrix 0 OUT: In1 of LUT2_2
Matrix 0 OUT: In0 of LUT2_3
Matrix 0 OUT: In1 of LUT2_3
Matrix 0 OUT: In0 of LUT3_0
Matrix 0 OUT: In1 of LUT3_0
Matrix 0 OUT: In2 of LUT3_0
Matrix 0 OUT: In0 of LUT3_1
Matrix 0 OUT: In1 of LUT3_1
Matrix 0 OUT: In2 of LUT3_1
Matrix 0 OUT: In0 of LUT3_2
Matrix 0 OUT: In1 of LUT3_2
Matrix 0 OUT: In2 of LUT3_2
Matrix 0 OUT: In0 of LUT3_3
Matrix 0 OUT: In1 of LUT3_3
Matrix 0 OUT: In2 of LUT3_3
Matrix 0 OUT: In0 of LUT3_4
Matrix 0 OUT: In1 of LUT3_4
Matrix 0 OUT: In2 of LUT3_4
Matrix 0 OUT: In0 of LUT3_5
Matrix 0 OUT: In1 of LUT3_5
Matrix 0 OUT: In2 of LUT3_5
Matrix 0 OUT: In0 of LUT3_6
Matrix 0 OUT: In1 of LUT3_6
Matrix 0 OUT: In2 of LUT3_6
Matrix 0 OUT: In0 of LUT3_7
Matrix 0 OUT: In1 of LUT3_7
Matrix 0 OUT: In2 of LUT3_7
Matrix 0 OUT: In0 of LUT4_0
Matrix 0 OUT: In1 of LUT4_0
Matrix 0 OUT: In2 of LUT4_0 or PGEN CLK
Matrix 0 OUT: In3 of LUT4_0 or PGEN nRST
Matrix 0 OUT: nSET or nRST of DFF0/Latch0
Matrix 0 OUT: Data of DFF0/Latch0
0
[11:6]
1
[17:12]
2
[23:18]
3
[29:24]
4
[35:30]
5
[41:36]
6
[47:42]
7
[53:48]
8
[59:54]
9
[65:60]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
[71:66]
[77:72]
[83:78]
[89:84]
[95:90]
[101:96]
[107:102]
[113:108]
[119:114]
[125:120]
[131:126]
[137:132]
[143:138]
[149:144]
[155:150]
[161:156]
[167:162]
[173:168]
[179:174]
[185:180]
[191:186]
[197:192]
[203:198]
[209:204]
[215:210]
[221:216]
[227:222]
Datasheet
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SLG46620-A
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Programmable Mixed-signal Matrix
Table 24: Matrix 0 Output Table
Register Bit
Matrix Output
Number
Matrix 0 Output Signal Function
Address
[233:228]
[239:234]
[245:240]
[251:246]
[257:252]
[263:258]
[269:264]
[275:270]
[281:276]
[287:282]
[293:288]
[299:294]
[305:300]
[311:306]
[317:312]
[323:318]
[329:324]
[335:330]
[341:336]
[347:342]
[353:348]
[359:354]
[365:360]
[371:366]
[377:372]
[383:378]
[389:384]
[395:390]
[401:396]
[407:402]
[413:408]
[419:414]
[425:420]
[431:426]
[437:432]
[443:438]
[449:444]
[455:450]
[461:456]
Matrix 0 OUT: Clock of DFF0/Latch0
Matrix 0 OUT: nSET or nRST of DFF1/Latch1
Matrix 0 OUT: Data of DFF1/Latch1
Matrix 0 OUT: Clock of DFF1/Latch1
Matrix 0 OUT: nSET or nRST of DFF2/LatcOUTh2
Matrix 0 OUT: Data of DFF2/Latch2
Matrix 0 OUT: Clock of DFF2/Latch2
Matrix 0 OUT: Data of DFF3/Latch3
Matrix 0 OUT: Clock of DFF3/Latch3
Matrix 0 OUT: Data of DFF4/Latch4
Matrix 0 OUT: Clock of DFF4/Latch4
Matrix 0 OUT: Data of DFF5/Latch5
Matrix 0 OUT: Clock of DFF5/Latch5
Matrix 0 OUT: Clock of Pipe Delay 0
Matrix 0 OUT: Input Data of Pipe Delay 0
Matrix 0 OUT: Reset of Pipe Delay 0
Matrix 0 OUT: Input of Edge Detector and Programmable Delay 0
Matrix 0 OUT: Input of Inverter 0
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Matrix 0 OUT: Digital Output of Pin3
Matrix 0 OUT: OE of Pin3
Matrix 0 OUT: Digital Output of Pin4
Matrix 0 OUT: Digital Output of Pin5
Matrix 0 OUT: OE of Pin5
Matrix 0 OUT: Digital Output of Pin6
Matrix 0 OUT: Digital Output of Pin7
Matrix 0 OUT: OE of Pin7
Matrix 0 OUT: Digital Output of Pin8
Matrix 0 OUT: Digital Output of Pin9
Matrix 0 OUT: OE of Pin9
Matrix 0 OUT: Digital Output of Pin10
Matrix 0 OUT: OE of Pin10
Matrix 0 OUT: PDB (Power-down) for ACMP0
Matrix 0 OUT: PDB (Power-down) for ACMP4
Matrix 0 OUT: PDB (Power-down) for ACMP5
Matrix 0 OUT: CNT0/CNT2/CNT9/ External Clock(CLK_Matrix0)
Matrix 0 OUT: CNT5/CNT6 External Clock (CLK_Matrix1)
Matrix 0 OUT: Input of DLY/CNT0
Matrix 0 OUT: Input of DLY/CNT2
Matrix 0 OUT: Keep of DLY/CNT2
Datasheet
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Programmable Mixed-signal Matrix
Table 24: Matrix 0 Output Table
Register Bit
Matrix Output
Number
Matrix 0 Output Signal Function
Address
[467:462]
[473:468]
[479:474]
[485:480]
[491:486]
[497:492]
[503:498]
[509:504]
[515:510]
[521:516]
[527:522]
[533:528]
[539:534]
[545:540]
[551:546]
[557:552]
[563:558]
[569:564]
Matrix 0 OUT: Up of DLY/CNT2
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Matrix 0 OUT: Input of DLY/CNT5
Matrix 0 OUT: Input of DLY/CNT6
Matrix 0 OUT: Input of DLY/CNT9
Matrix 0 OUT: ADC Power-down
Matrix 0 OUT: CSB of SPI
Matrix 0 OUT: SCLK of SPI
Matrix 0 OUT: Oscillator Power-down
Matrix 0 OUT: Cross Connection Output to Matrix 1 [0]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [1]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [2]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [3]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [4]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [5]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [6]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [7]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [8]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [9]
Datasheet
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Programmable Mixed-signal Matrix
6.3 MATRIX INPUT 1 TABLE
Table 25: Matrix 1 Input Table
Matrix Decode
N
Matrix 1 Input Signal Function
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GROUND
1
LUT2_4 Output
2
LUT2_5 Output
3
LUT2_6 Output
4
LUT2_7 Output
5
LUT3_8 Output
6
LUT3_9 Output
7
LUT3_10 Output
8
LUT3_11 Output
9
LUT3_12 Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
LUT3_13 Output
LUT3_14 Output
LUT3_15 Output
LUT4_1 Output
DFF6/LATCH6 Output
DFF7/LATCH7 Output
DFF8/LATCH8 Output
DFF9/LATCH9 Output
DFF10/LATCH10 Output
DFF11/LATCH11 Output
Pipe Delay 1 Out0
Pipe Delay 1 Out1
Edge Detect Programmable Delay 1 Output
Inverter 1 Output
Pin12 Digital Output
Pin13 Digital Output
Pin14 Digital Output
Pin15 Digital Output
Pin16 Digital Output
Pin17 Digital Output
Pin18 Digital Output
Pin19 Digital Output
Pin20 Digital Output
ACMP1 Output
ACMP2 Output
ACMP3 Output
DLY1/CNT1 Output
DLY3/CNT3 Output
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Table 25: Matrix 1 Input Table
Matrix Decode
N
Matrix 1 Input Signal Function
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DLY4/CNT4 Output
DLY7/CNT7 Output
DLY8/CNT8 Output
Sig_BG_OK
PWM0_DCMP0_Out_negative
PWM0_DCMP0_Out_positive
PWM1_DCMP1_Out_negative/SPI_Out[0]
PWM1_DCMP1_Out_positive/SPI_Out[1]
PWM2_DCMP2_Out_negative/SPI_Out[2]
PWM2_DCMP2_Out_positive/SPI_Out[3]
Ring Oscillator Output/SPI_Out[4]
RC Oscillator Output/SPI_Out[5]
Low Frequency Oscillator Output/SPI_Out[6]
GROUND/SPI_Out[7]
Cross Connection Input from Matrix 0 [0]
Cross Connection Input from Matrix 0 [1]
Cross Connection Input from Matrix 0 [2]
Cross Connection Input from Matrix 0 [3]
Cross Connection Input from Matrix 0 [4]
Cross Connection Input from Matrix 0 [5]
Cross Connection Input from Matrix 0 [6]
Cross Connection Input from Matrix 0 [7]
Cross Connection Input from Matrix 0 [8]
Cross Connection Input from Matrix 0 [9]
nRESET_Matrix
VDD
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6.4 MATRIX 1 OUTPUT TABLE
Table 26: Matrix 1 Output Table
Register Bit
Matrix Output
Number
Matrix 1 Output Signal Function
Address
[1029:1024]
[1035:1030]
[1041:1036]
[1047:1042]
[1053:1048]
[1059:1054]
[1065:1060]
[1071:1066]
[1077:1072]
[1083:1078]
[1089:1084]
[1095:1090]
[1101:1096]
[1107:1102]
[1113:1108]
[1119:1114]
[1125:1120]
[1131:1126]
[1137:1132]
[1143:1138]
[1149:1144]
[1155:1150]
[1161:1156]
[1167:1162]
[1173:1168]
[1179:1174]
[1185:1180]
[1191:1186]
[1197:1192]
[1203:1198]
[1209:1204]
[1215:1210]
[1221:1216]
[1227:1222]
[1233:1228]
[1239:1234]
[1245:1240]
[1251:1246]
Matrix 1 OUT: In0 of LUT2_4
Matrix 1 OUT: In1 of LUT2_4
Matrix 1 OUT: In0 of LUT2_5
Matrix 1 OUT: In1 of LUT2_5
Matrix 1 OUT: In0 of LUT2_6
Matrix 1 OUT: In1 of LUT2_6
Matrix 1 OUT: In0 of LUT2_7
Matrix 1 OUT: In1 of LUT2_7
Matrix 1 OUT: In0 of LUT3_8
Matrix 1 OUT: In1 of LUT3_8
Matrix 1 OUT: In2 of LUT3_8
Matrix 1 OUT: In0 of LUT3_9
Matrix 1 OUT: In1 of LUT3_9
Matrix 1 OUT: In2 of LUT3_9
Matrix 1 OUT: In0 of LUT3_10
Matrix 1 OUT: In1 of LUT3_10
Matrix 1 OUT: In2 of LUT3_10
Matrix 1 OUT: In0 of LUT3_11
Matrix 1 OUT: In1 of LUT3_11
Matrix 1 OUT: In2 of LUT3_11
Matrix 1 OUT: In0 of LUT3_12
Matrix 1 OUT: In1 of LUT3_12
Matrix 1 OUT: In2 of LUT3_12
Matrix 1 OUT: In0 of LUT3_13
Matrix 1 OUT: In1 of LUT3_13
Matrix 1 OUT: In2 of LUT3_13
Matrix 1 OUT: In0 of LUT3_14
Matrix 1 OUT: In1 of LUT3_14
Matrix 1 OUT: In2 of LUT3_14
Matrix 1 OUT: In0 of LUT3_15
Matrix 1 OUT: In1 of LUT3_15
Matrix 1 OUT: In2 of LUT3_15
Matrix 1 OUT: In0 of LUT4_1
Matrix 1 OUT: In1 of LUT4_1
Matrix 1 OUT: In2 of LUT4_1
Matrix 1 OUT: In3 of LUT4_1
Matrix 1 OUT: nSET or nRST of DFF6/Latch6
Matrix 1 OUT: Data of DFF6/Latch6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
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Table 26: Matrix 1 Output Table
Register Bit
Matrix Output
Number
Matrix 1 Output Signal Function
Address
[1257:1252]
[1263:1258]
[1269:1264]
[1275:1270]
[1281:1276]
[1287:1282]
[1293:1288]
[1299:1294]
[1305:1300]
[1311:1306]
[1317:1312]
[1323:1318]
[1329:1324]
[1335:1330]
[1341:1336]
[1347:1342]
[1353:1348]
[1359:1354]
[1365:1360]
[1371:1366]
[1377:1372]
[1383:1378]
[1389:1384]
[1395:1390]
[1401:1396]
[1407:1402]
[1413:1408]
[1419:1414]
[1425:1420]
[1431:1426]
[1437:1432]
[1443:1438]
[1449:1444]
[1455:1450]
[1461:1456]
[1467:1462]
[1473:1468]
[1479:1474]
[1485:1480]
Matrix 1 OUT: Clock of DFF6/Latch6
Matrix 1 OUT: nSET or nRST of DFF7/Latch7
Matrix 1 OUT: Data of DFF7/Latch7
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Matrix 1 OUT: Clock of DFF7/Latch7
Matrix 1 OUT: nSET or nRST of DFF8/Latch8
Matrix 1 OUT: Data of DFF8/Latch8
Matrix 1 OUT: Clock of DFF8/Latch8
Matrix 1 OUT: Data of DFF9/Latch9
Matrix 1 OUT: Clock of DFF9/Latch9
Matrix 1 OUT: Data of DFF10/Latch10
Matrix 1 OUT: Clock of DFF10/Latch10
Matrix 1 OUT: Data of DFF11/Latch11
Matrix 1 OUT: Clock of DFF11/Latch11
Matrix 1 OUT: Clock of Pipe Delay 1
Matrix 1 OUT: Input Data of Pipe Delay 1
Matrix 1 OUT: Reset of Pipe Delay 1
Matrix 1 OUT: Input of Edge Detector and Programmable Delay 1
Matrix 1 OUT: Input of Inverter 1
Matrix 1 OUT: Digital Output of PIN 12
Matrix 1 OUT: Digital Output of PIN 13
Matrix 1 OUT: OE of PIN 13
Matrix 1 OUT: Digital Output of PIN 14
Matrix 1 OUT: OE of PIN 14
Matrix 1 OUT: Digital Output of PIN 15
Matrix 1 OUT: Digital Output of PIN 16
Matrix 1 OUT: OE of PIN 16
Matrix 1 OUT: Digital Output of PIN 17
Matrix 1 OUT: Digital Output of PIN 18
Matrix 1 OUT: OE of PIN 18
Matrix 1 OUT: Digital Output of PIN 19
Matrix 1 OUT: OE of PIN 19
Matrix 1 OUT: Digital Output of PIN 20
Matrix 1 OUT: PDB (Power-down) for ACMP1
Matrix 1 OUT: PDB (Power-down) for ACMP2
Matrix 1 OUT: PDB (Power-down) for ACMP3
Matrix 1 OUT: CNT7/CNT8/PWM/ADC External Clock (CLK_Matrix2)
Matrix 1 OUT: CNT1/CNT3/CNT4 External Clock (CLK_Matrix3)
Matrix 1 OUT: Input of DLY/CNT1
Matrix 1 OUT: Input of DLY/CNT3
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Table 26: Matrix 1 Output Table
Register Bit
Matrix Output
Number
Matrix 1 Output Signal Function
Address
[1491:1486]
[1497:1492]
[1503:1498]
[1509:1504]
[1515:1510]
[1521:1516]
Matrix 1 OUT: Input of DLY/CNT4
Matrix 1 OUT: Keep of DLY/CNT4
Matrix 1 OUT: Up of DLY/CNT4
Matrix 1 OUT: Input of DLY/CNT7
Matrix 1 OUT: Input of DLY/CNT8
Matrix 1 OUT: PWM Power-down
77
78
79
80
81
82
83
Matrix 1 OUT: PWM/DCMP0 Positive Input and PWM/DCMP1 Negative Input Reg-
ister Selection Bit 0
[1527:1522]
[1533:1528]
Matrix 1 OUT: PWM/DCMP0 Positive Input and PWM/DCMP1 Negative Input Reg-
ister Selection Bit 1
84
[1539:1534]
[1545:1540]
[1551:1546]
[1557:1552]
[1563:1558]
[1569:1564]
[1575:1570]
[1581:1576]
[1587:1582]
[1593:1588]
[1599:1594]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [0]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [1]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [2]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [3]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [4]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [5]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [6]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [7]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [8]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [9]
Reserved
85
86
87
88
89
90
91
92
93
94
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7
8-bit SAR ADC Analog-to-Digital Converter
The Analog to Digital Converter (ADC) in the SLG46620-A is an 8-bit Successive Approximation Register Analog to Digital
Converter (SAR ADC) which operates at a sampling speed of 100 kHz. The ADC’s DNL < ± 0.5 LSB and INL < ± 3.4 LSB and
has a ADC Vref accuracy of ± 50 mV. The ADC consists of two parts: PGA which provides signal amplification and conditioning
and SAR ADC which handles analog to digital conversion. PGA can be used as amplifier when ADC is disabled. Please see
Section 7.3.2 PGA Output for more details. User controlled inputs and outputs of the ADC are listed below:
Inputs:
CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input MUX Control Signal (PIN 16, VDD
IN+: Single-Ended Mode Input (PIN8 or PIN9) and Differential Mode Positive Input (PIN8)
IN-: Differential Mode Negative Input (PIN 9 or DAC0)
Vref: ADC Voltage Reference Input (ADC Vref, VDD/4, none)
CLK or CLK/16: ADC Clock Input (Ring OSC, Ext. CLK2 (Matrix1_OUT73), RC OSC, SPI SCLK)
)
Wake/Sleep
Outputs:
PGA_Out: Output of the PGA to PIN7
PGA_Out: Output of the PGA to ACMP1
SER DATA: ADC serial output (SPI)
PAR DATA: 8-bit ADC parallel data to either the SPI, PWM, or DCMP
INT_ OUT: ADC Interrupt Output (Matrix0_OUT43)
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7.1 ADC FUNCTIONAL DIAGRAM
VDD
PGAOUT_en register [886]
0
PGA OUT
to ACMP
CH Select (PIN 16)
1
ADC Programmable
Gain Amplifier
register [816]
Pin 9
Gain Selection
register [820:818]
0
1
SER DATA
PAR DATA
INT OUT
Pin 8
ADC
PGA
PGA Power register [821]
0
1
/16
0
ADC Vref
CLK
00
01
10
Vref
Reserved
1
DAC_in_en register [815]
VDD * (0.25)
register [1639]
DAC 0
registers [842:841]
Ring OSC
8-bit registers [851:844]
DCMP1_Neg.IN
Diff_mode_en register [817]
pseudo_en register [822]
0
1
00
Wake/Sleep En register [884]
Wake/Sleep Signal
Ext. CLK2
01
10
11
(matrix1_out73)
RC OSC
SPI CLK
register [843]
ADC CLK SRC registers [1629:1628]
Figure 15: ADC Functional Diagram
7.2 ADC OPERATION MODES
The ADC has three operating modes:
Single-Ended ADC operation using IN+ from PIN 8 or 9, when ADC_sel (register [817]) is “0”
Differential ADC operation using IN+ from PIN 8 and IN- from PIN 9, when ADC_sel (register [817]) is “1”
Pseudo-Differential ADC operation using IN+ from PIN 8 and IN- from PIN 9, when ADC_sel (register [817]) and
ADC_pseudodiff_en (register [822]) bits are both set to “1”.
7.3 ADC 3-BIT PROGRAMMABLE GAIN AMPLIFIER
The front end of the ADC is a PGA with 3 bits for setting gain. The PGA buffers the ADC in all cases. The PGA gain is set by the
ADC_gain_control (registers [820:818]). See ADC Register Settings Table.
Available gain settings depending on PGA mode selected (when used as ADC front-end):
Single-ended: 0.5x, 1x, 2x, 4x, 8x;
Differential: 1x, 2x, 4x, 8x, 16x;
Pseudo-Differential: 1x, 2x.
PGA inputs:
CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input MUX Control Signal (PIN16, VDD
IN+: Single-Ended Mode Input (PIN8 or PIN9) and Differential Mode Positive Input (PIN8)
IN-: Differential Mode Negative Input (PIN9 or DAC0)
)
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PGA output is connected directly to ADC input. Also, it is possible to connect PIN7 to PGA output (register [886]), when ADC is
not in use only. The output of PGA has an offset when used as ADC front-end. Please see section 7.3.2 for more details.
7.3.1 PGA 2-Channel Selection
When ADC_channel_sel (register [816]) is set to “1”, the PGA of the ADC will sample either PIN 8 or PIN 9 on the IN+ input,
where the selection is controlled by PIN 16.
When PIN 16 is set to “0”, the ADC will sample PIN 9
When PIN 16 is set to “1”, the ADC will sample PIN 8
When ADC_channel_sel (register [816]) is set to “0”, the PGA of the ADC will sample PIN 8 on the IN+ input.
Logic “1”
0
CH Selector (Pin 16)
1
register [816]
IN+ CH#2 (Pin 9)
0
IN+
IN+ CH#1 (Pin 8)
1
Figure 16: ADC 2-Channel Selection
7.3.2 PGA Output
PGA can be used either in standalone mode or as ADC font-end / ACMP input buffer.
In PGA standalone mode (ADC in POWER-DOWN mode) PGA output is always referenced to GND. When ADC is powered on,
it powers also the PGA output reference macrocell, so that the output voltage is referenced to one of predefined output offset
voltages Vos(RTO) which can be found in PGA specifications. This offset is required for correct ADC operation and it does not
affect output code calculation.
PGA output reference (when ADC is on):
Single-ended mode: Vos(RTO) = GND
Differential mode: Vos(RTO) = 550 mV
Pseudo-Differential mode: Vos(RTO) = 180 mV
Note that the reference voltage macrocell is controlled by ADC, therefore if ADC is in POWER-DOWN mode, the reference
macrocell is OFF and PGA output is referenced to GND. In this case both Differential and Pseudo-Differential modes provide the
same output. Typical PGA specifications in Differential/Pseudo-Differential mode with ADC in POWER-DOWN state are given in
specifications section for information only.
Note 1: PGA operation in Differential/Pseudo-Differential mode with ADC in POWER-DOWN state is not recommended to use.
Note 2: Toggling ADC POWER-DOWN mode will also toggle the PGA output reference macrocell, that will influence the ACMP
input voltage.
PGA has a few output connection possibilities: to ACMP1 and/or ADC, and to external output on PIN7. Connection to external
output is possible only when ADC is powered down.
PGA output connection options:
•
Single-Ended mode:
• ADC
• ACMP
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• External output
•
•
Differential mode:
• ADC
• ACMP (Note 2)
• External output (Operation in this mode is not recommended)
Pseudo-Differential mode:
• ADC
• ACMP (Note 2)
• External output (Operation in this mode is not recommended)
7.3.3 PGA Power-On Signal
Whenever ADC is enabled, PGA is powered on automatically. However, it is possible to use PGA separately. In this case, Power-
On function must be enabled, register [821] = 1.
Note 1 In ADC Wake/Sleep dynamic ON/OFF mode, must be set to 0
7.3.4 PGA Typical Performance
30
25
20
15
10
5
30
25
20
15
10
5
200 samples
VDD = 3.3 V
T = 25°C
200 samples
VDD = 3.3 V
T = 25°C
0
0
Vos, mV
Vos, mV
Figure 18: PGA Input Offset Distribution, Single-Ended
Mode, G = 1
Figure 17: PGA Input Offset Distribution, Single-Ended
Mode, G = 0.5
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18
20
18
16
14
12
10
8
200 samples
200 samples
VDD = 3.3 V
T = 25°C
16
14
12
10
8
VDD = 3.3 V
T = 25°C
6
6
4
4
2
2
0
0
Vos, mV
Vos, mV
Figure 19: PGA Input Offset Distribution, Single-Ended
Mode, G = 2
Figure 20: PGA Input Offset Distribution, Single-Ended
Mode, G = 4
20
200 samples
18
VDD = 3.3 V
16
T = 25°C
14
12
10
8
6
4
2
0
Vos, mV
Figure 21: PGA Input Offset Distribution, Single-Ended
Mode, G = 8
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1300
1200
1100
1000
900
1300
1200
1100
1000
900
800
800
700
700
600
600
500
500
400
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6 V
400
VDD = 1.71 V
VDD = 3.3 V
VDD = 3.6 V
300
200
100
300
200
100
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Vcm, V
Vinn, V
Figure 22: Typical Input Common Mode Voltage Range vs.
Linear Output Voltage Range, Differential Mode, All Gains
Figure 23: Typical Negative Input Voltage Range vs.
Linear Output Voltage, Pseudo-Differential Mode, G = 1
1300
1200
1100
1000
900
800
700
600
500
400
300
VDD = 1.71 V
200
100
VDD = 3.3 V
VDD = 3.6 V
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Vinn, V
Figure 24: Typical Negative Input Voltage Range vs.
Linear Output Voltage, Pseudo-Differential Mode, G = 2
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7.4 ADC INPUT VOLTAGE DEFINITION
The ADC’s input voltage (VIN_ADC) is calculated based on either the single-ended or differential operation modes the logic cell is
set to. In single-ended mode VIN_ADC is the positive input voltage multiplied by the gain of the PGA. While in differential mode
the VIN_ADC is the difference between the positive and negative input voltages multiplied by the gain of the PGA plus one half of
the reference voltage.
VOUT(PGA) = VIN(ADC) = G
·
(Vinp + Vos(RTI)) - for SE mode
VOUT(PGA) = VIN(ADC) = G Vind + Vos(RTO) - for DI and PD mode
·
Vos - PGA offset voltage. RTI and RTO denotes referred to input and referred to output Vos.
Vos(RTO)
----------------------
G
Vos(RTI)
=
G - PGA nominal gain
Vind - PGA input voltage (differential):
Vind = Vinp - Vinn
Vind
----------
2
Vinp = Vcm
+
Vind
----------
2
Vinn = Vcm
–
Vinn and Vinp - absolute voltage at negative and positive PGA input correspondingly
Vcm - common mode PGA voltage:
Vinn + Vinp
----------------------------
=
Vcm
2
Note: In Pseudo-Differential mode Vcm is replaced by Vinn voltage for convenience
ADC code for PGA differential input voltage Vind can be calculated as follows:
•
Single-ended mode:
V
ind = Vinp
255
ADC
= -----------------------------------------------------------------(V
– V
)
code
inp
inp[min]
V
– V
inp[max]
inp[min]
Vinp[min] and Vinp[max] - positive input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications)
Differential and Pseudo-Differential mode:
•
255
ADC
= -----------------------------------------------------------------(Vind – Vind[min])
code
V
– V
ind[max]
ind[min]
Vind[min] and Vind[max] - differential input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications)
Least significant bit size (LSB) calculates as follows:
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FS
LSB = ---------
255
where FS is full-scale range:
FS = Vind[max] - Vind[min]
7.5 ADC REFERENCE VOLTAGE
The ADC’s reference voltage (Vref) is controlled by ADC_Vref_sel (registers [842:841]). The two reference voltage inputs are
chosen from the following:
ADC Vref from Internal Source (ADC Vref = 1.2 V)
Power Divider of (0.25) * VDD
ADC Vref
00
01
10
Vref
Reserved
V
DD * (0.25)
registers [842:841]
Figure 25: ADC Reference Voltage
7.6 ADC POWER-DOWN SELECT MODE
The ADC’s power-down source is selected by Matrix0_Out81 registers [491:486]. A value of “1” will drive the ADC and the PGA
to power-down mode. The SLG46620-A also has a slow/fast power-on mode feature controlled by register [885]. When register
[885] = 0, the ADC is in slow power-on mode and the entire analog macrocell is controlled by connection matrix output0 81. When
register [885] = 1, ADC is in fast power-on mode, where only the ADC will be controlled by connection matrix output0 81 and the
analog macrocell will remain on. With this feature, the first ADC power-on (with the rest of the analog macrocell) will be
approximately 500 µs; the next power cycle the ADC power-on (ADC only) time is < 5 µs.
7.7 ADC CLOCK SOURCE
TheADC clock source comes from either the internal RC Oscillator, Matrix1_Out73, Ring Oscillator, or SPI CLK. TheADC requires
16 clock cycles to sample the analog voltage and output the sampled data.
Note: Sampling rate should not exceed approximately 100 kbps.
The selection is made from the ADC_clk_sel signal via registers [1629:1628] where:
00: Ring Oscillator
01: Matrix1_Out 73
10: RC Oscillator
11: SPI CLK
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Note: It is not recommended to design in high frequency signals (input our output) on pins adjacent to the following pins: Pin7,
Pin8, Pin9 as this may affect ADC performance.
/16
0
1
CLK
register [1639]
Ring OSC
00
Matrix1 OUT [73]
RC OSC
01
10
11
SPI CLK
ADC CLK SRC registers [1629:1628]
Figure 26: ADC Clock Source
7.8 ADC OUTPUTS
The ADC’s output can be shifted out through the SPI logic cell. Both SER DATA and PAR DATA produce an 8-bit data string over
16 clock cycles. See Figure 27.
7.8.1 ADC Serial Output
The 8-bit serial data can be output from the SLG46620-A device on PIN 10. The individual 8 serial data bits can be read into an
external device within the larger system design.
To initialize the SER DATA the ADC needs a Power-down signal, which can be configured through the connection matrix. After 6
ADC_CLK cycles the ADC will start to output the 8-Bit Serial Data. This PD signal needs to be held for at least 16 ADC_CLK
cycles. The ADC_CLK is determined by either the RC OSC, RingOSC OSC, Matrix1_Out73, or SPI CLK.OSC
7.8.2 ADC Parallel Output
The 16-bit parallel data can be output from the ADC logic cell to either the DCMP/PWM or FSM logic cells within the SLG46620-
A device.
To initialize the PAR DATA the ADC needs a Power-down signal, which can be configured through the connection matrix. After
tenADC_CLK cycles theADC will start to output the 16-Bit Parallel Data. This PD signal needs to be held for at least 32 ADC_CLK
cycles. The ADC_CLK is determined by either the RC OSC, Ring OSC, Matrix1_Out73, or SPI CLK.
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7.9 ADC INTERRUPT OUTPUT TIMING DIAGRAM
Power_Down
T_ADC_startup > 500µs (force analog disable)
T_ADC_startup > 5 µs (force analog enable)
CLK case 1
CLK case 2
1
1
2
3
4
5
6
7
8
9
10
10
11
11
12 13
14 15 16
1
1
16
16
2
3
4
5
6
7
8
9
12 13
14 15
16
SER DATA
D7
D0
SER DATA
Input Signal case 1
PAR DATA
Input Signal case 2
PAR DATA
ADC_int
First pulse
Bandgap OK
Figure 27: ADC Interrupt Output Timing Diagram
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8
8-bit Digital-to-Analog Converter
There are two Digital-to-Analog Converters (DACs) in the SLG46620-A (DAC0 and DAC1), they are 8-bit Digital to Analog
Converters which operate at a maximum sampling speed of 100 kbps. The DAC's DNL is less than 1 LSB and INL is less than
1LSB. DAC output to PIN resistance is 1 kΩ. Load resistance is recommended to be no less than 10 kΩ; load capacitance is
recommended to be no more than 100 pF.
User controlled inputs and outputs of the DAC are listed below:
DAC0 Inputs:
Registers
CNT9_Q[7:0]
8LSBs SPI
FSM0[7:0]
DAC0 Outputs:
PIN19
PGA negative input (00: 0 V; FF: 1 V)
ACMP0 negative input
ACMP1 negative input
ACMP2 negative input
ACMP3 negative input
ACMP4 negative input
ACMP5 negative input
DAC1 Inputs:
Registers
CNT9_Q[7:0]
8LSBs SPI
FSM0[7:0]
DAC1 Outputs:
PIN18
ACMP0 negative input
ACMP1 negative input
ACMP2 negative input
ACMP3 negative input
ACMP4 negative input
ACMP5 negative input
If a DAC output is connected to one of SLG46620-A's external pins (Pin19 for DAC0 and Pin18 for DAC1), it is necessary to
enable those external pins as analog input/output. Register [840]: 0 - DAC0 power-off, 1 - DAC0 power-on. Register [834]: 0 -
DAC1 power-off, 1 - DAC1 power-on.
DAC0 output range: 0 V…1 V
DAC1 output range: 50 mV…1.05 V
Please note that DAC1 is shared with ADC macrocell. Therefore it is impossible to use DAC1, when ADC is used. Also to activate
DAC1, DAC0 must be enabled (register [840] = 1 and register [834] = 1). In addition, DAC0 is used as a part of pseudo-differential
mode of PGA macrocell. Therefore DAC0 is not available when PGA is in pseudo-differential mode.
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8.1 DAC0 FUNCTIONAL DIAGRAM
register [843]
Pin19_aio_en
registers [1962:1961]=11
Register
0
01
10
11
Vref Out_0 (Pin19)
DAC0
DCMP1's neg. input
1
PWR DOWN
registers [879:878]
register [840]
PGA negative input
ACMP0 negative input
ACMP5 negative input
Figure 28: DAC0 Functional Diagram
8.2 DAC1 FUNCTIONAL DIAGRAM
register [883]
Pin19_aio_en
registers [1955:1954]=11
Register
01
10
11
Vref Out_1 (Pin18)
1
0
DAC1
DCMP1's neg. input
PWR DOWN
registers [877:876]
register [834]
ACMP0 negative input
ACMP5 negative input
Figure 29: DAC1 Functional Diagram
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8.3 DAC TYPICAL PERFORMANCE
ꢂꢃꢀꢀ
ꢂꢂꢁꢀ
ꢂꢂꢀꢀ
ꢂꢀꢁꢀ
ꢂꢀꢀꢀ
ꢉꢁꢀ
ꢉꢀꢀ
ꢈꢁꢀ
ꢈꢀꢀ
ꢇꢁꢀ
ꢇꢀꢀ
ꢆꢁꢀ
ꢆꢀꢀ
ꢁꢁꢀ
ꢁꢀꢀ
ꢅꢁꢀ
ꢅꢀꢀ
ꢄꢁꢀ
ꢄꢀꢀ
ꢃꢁꢀ
ꢃꢀꢀ
ꢂꢁꢀ
ꢂꢀꢀ
ꢁꢀ
8-bit register control = 255
8-bit register control = 200
8-bit register control = 160
8-bit register control = 100
8-bit register control = 20
ꢀ
ꢀ8ꢀꢃ ꢀ8ꢀꢅ ꢀ8ꢀꢆ ꢀ8ꢀꢈ ꢀ8ꢂ ꢀ8ꢃ ꢀ8ꢅ ꢀ8ꢆ ꢀ8ꢈ
ꢂ
ꢃ
ꢅ
ꢆ
ꢈ
ꢂꢀ ꢃꢀ ꢅꢀ ꢆꢀ ꢈꢀ ꢂꢀꢀ ꢃꢀꢀ ꢅꢀꢀ ꢆꢀꢀ ꢈꢀꢀ ꢂꢀꢀꢀ ꢃꢀꢀꢀ
Load, uA
Figure 30: DAC Typical Load Regulation, T = 25°C, VDD = 3.3 V
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9
Combinatorial Logic
Combinatorial logic is supported via twenty five Lookup Tables (LUTs) within the SLG46620-A. There are eight 2-bit LUTs, sixteen
3-bit LUTs, and one 4-bit LUT. The device also includes one Combination Function Macrocell that can be used as a 4-bit LUT.
For more details, please see Section 10.
Inputs/Outputs for the twenty five LUTs are configured from one of the connection matrices with specific logic functions being
defined by the state of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following
standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
9.1 2-BIT LUT
The eight 2-bit LUTs each take in two input signals from one of the two connection matrices and produce a single output, which
goes back into the same connection matrix that the inputs came from. The output state of each 2-bit LUT is defined by four register
bits, the output state is based on the appropriate bit selected by the value of the two inputs to the LUT.
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registers [579:576]
registers [583:580]
From Connection
Matrix Output 0 [0]
IN0
From Connection
Matrix Output 0 [2]
IN0
To Connection
Matrix Input 0[1]
To Connection
Matrix Input 0 [2]
OUT
OUT
OUT
OUT
OUT
2-bit LUT0
2-bit LUT1
From Connection
Matrix Output 0 [1]
IN1
From Connection
Matrix Output 0 [3]
IN1
registers [587:584]
registers [591:588]
From Connection
Matrix Output 0 [4]
IN0
From Connection
Matrix Output 0 [6]
IN0
To Connection
To Connection
Matrix Input 0 [4]
Matrix Input 0[3]
OUT
2-bit LUT2
2-bit LUT3
From Connection
Matrix Output 0 [5]
IN1
From Connection
Matrix Output 0 [7]
IN1
registers [701:698]
registers [705:702]
From Connection
Matrix Output 1 [0]
IN0
From Connection
Matrix Output 1 [2]
IN0
To Connection
Matrix Input 1 [1]
To Connection
Matrix Input 1 [2]
OUT
2-bit LUT4
2-bit LUT5
From Connection
Matrix Output 1 [1]
IN1
From Connection
Matrix Output 1 [3]
IN1
registers [709:706]
registers [713:710]
From Connection
Matrix Output 1 [4]
IN0
From Connection
Matrix Output 1 [6]
IN0
To Connection
Matrix Input 1 [3]
To Connection
Matrix Input 1 [4]
OUT
2-bit LUT6
2-bit LUT7
From Connection
Matrix Output 1 [5]
IN1
From Connection
Matrix Output 1 [7]
IN1
Figure 31: 2-bit LUTs
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Table 27: 2-bit LUT0 Truth Table
Table 31: 2-bit LUT4 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [576]
register [577]
register [578]
register [579]
register [698]
register [699]
register [700]
register [701]
0
1
0
1
1
0
1
0
1
1
1
1
Table 28: 2-bit LUT1 Truth Table
Table 32: 2-bit LUT5 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [580]
register [581]
register [582]
register [583]
register [702]
register [703]
register [704]
register [705]
0
1
0
1
1
0
1
0
1
1
1
1
Table 29: 2-bit LUT2 Truth Table
Table 33: 2-bit LUT6 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [584]
register [585]
register [586]
register [587]
register [706]
register [707]
register [708]
register [709]
0
1
0
1
1
0
1
0
1
1
1
1
Table 30: 2-bit LUT3 Truth Table
Table 34: 2-bit LUT7 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [588]
register [589]
register [590]
register [591]
register [710]
register [711]
register [712]
register [713]
0
1
0
1
1
0
1
0
1
1
1
1
Each Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function;
2-Bit LUT0 is defined by registers [579:576]
2-Bit LUT1 is defined by registers [583:580]
2-Bit LUT2 is defined by registers [587:584]
2-Bit LUT3 is defined by registers [591:588]
2-Bit LUT4 is defined by registers [701:698]
2-Bit LUT5 is defined by registers [705:702]
2-Bit LUT6 is defined by registers [709:706]
2-Bit LUT7 is defined by registers [713:710]
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The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the 2-bit LUT logic cells.
Table 35: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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9.2 3-BIT LUT
The sixteen 3-bit LUTs each take in three input signals from one of the two connection matrices and produce a single output,
which goes back into the same connection matrix that the inputs came from. The output state of each 3-bit LUT is defined by eight
register bits, the output state is based on the appropriate bit selected by the value of the three inputs to the LUT.
registers [599:592]
registers [607:600]
From Connection
Matrix Output 0 [8]
From Connection
Matrix Output 0 [11]
IN0
IN1
IN0
IN1
To Connection
To Connection
Matrix Input 0 [6]
From Connection
Matrix Output 0 [9]
From Connection
Matrix Output 0 [12]
Matrix Input 0 [5]
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
3-bit LUT0
3-bit LUT1
From Connection
Matrix Output 0 [10]
From Connection
Matrix Output 0 [13]
IN2
IN2
registers [615:608]
registers [623:616]
From Connection
Matrix Output 0 [14]
From Connection
Matrix Output 0 [17]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 0 [7]
To Connection
From Connection
Matrix Output 0 [15]
From Connection
Matrix Output 0 [18]
Matrix Input 0 [8]
3-bit LUT2
3-bit LUT3
From Connection
Matrix Output 0 [16]
From Connection
Matrix Output 0 [19]
IN2
IN2
registers [631:624]
registers [639:632]
From Connection
Matrix Output 0 [20]
From Connection
Matrix Output 0 [23]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 0 [9]
To Connection
Matrix Input 0 [10]
From Connection
Matrix Output 0 [21]
From Connection
Matrix Output 0 [24]
3-bit LUT4
3-bit LUT5
From Connection
Matrix Output 0 [22]
From Connection
Matrix Output 0 [25]
IN2
IN2
registers [647:640]
registers [655:648]
From Connection
Matrix Output 0 [26]
From Connection
Matrix Output 0 [29]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 0 [11]
To Connection
Matrix Input 0 [12]
From Connection
Matrix Output 0 [27]
From Connection
Matrix Output 0 [30]
3-bit LUT6
3-bit LUT7
From Connection
Matrix Output 0 [28]
From Connection
Matrix Output 0 [31]
IN2
IN2
Figure 32: 3-bit LUTs
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registers [721:714]
registers [729:722]
From Connection
From Connection
Matrix Output 1 [8]
Matrix Output 1 [11]
IN0
IN0
IN1
To Connection
To Connection
From Connection
Matrix Output 1 [9]
From Connection
Matrix Output 1 [12]
Matrix Input 1 [5]
Matrix Input 1 [6]
IN1
IN2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
3-bit LUT8
3-bit LUT9
From Connection
Matrix Output 1[10]
From Connection
Matrix Output 1 [13]
IN2
registers [737:730]
registers [745:738]
From Connection
Matrix Output 1 [14]
From Connection
Matrix Output 1 [17]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 1 [7]
To Connection
Matrix Input 1 [8]
From Connection
Matrix Output 1 [15]
From Connection
Matrix Output 1 [18]
3-bit LUT10
3-bit LUT11
From Connection
Matrix Output 1 [16]
From Connection
Matrix Output 1 [19]
IN2
IN2
registers [753:746]
registers [761:754]
From Connection
Matrix Output 1 [20]
From Connection
Matrix Output 0 [23]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 1 [9]
To Connection
Matrix Input 1 [10]
From Connection
Matrix Output 1 [21]
From Connection
Matrix Output 0 [24]
3-bit LUT12
3-bit LUT13
From Connection
Matrix Output 1 [22]
From Connection
Matrix Output 0 [25]
IN2
IN2
registers [769:762]
registers [777:770]
From Connection
Matrix Output 1 [26]
From Connection
Matrix Output 1 [29]
IN0
IN1
IN0
IN1
To Connection
Matrix Input 1 [11]
To Connection
Matrix Input 1 [12]
From Connection
Matrix Output 1 [27]
From Connection
Matrix Output 1 [30]
3-bit LUT14
3-bit LUT15
From Connection
Matrix Output 1 [28]
From Connection
Matrix Output 1 [31]
IN2
IN2
Figure 33: 3-bit LUTs
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Table 36: 3-bit LUT0 Truth Table
Table 40: 3-bit LUT4 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [592]
register [593]
register [594]
register [595]
register [596]
register [597]
register [598]
register [599]
register [624]
register [625]
register [626]
register [627]
register [628]
register [629]
register [630]
register [631]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 37: 3-bit LUT1 Truth Table
Table 41: 3-bit LUT5 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [600]
register [601]
register [602]
register [603]
register [604]
register [605]
register [606]
register [607]
register [632]
register [633]
register [634]
register [635]
register [636]
register [637]
register [638]
register [639]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 38: 3-bit LUT2 Truth Table
Table 42: 3-bit LUT6 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [608]
register [609]
register [610]
register [611]
register [612]
register [613]
register [614]
register [615]
register [640]
register [641]
register [642]
register [643]
register [644]
register [645]
register [646]
register [647]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 39: 3-bit LUT3 Truth Table
Table 43: 3-bit LUT7 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [616]
register [617]
register [618]
register [619]
register [620]
register [621]
register [622]
register [623]
register [648]
register [649]
register [650]
register [651]
register [652]
register [653]
register [654]
register [655]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
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Table 44: 3-bit LUT8 Truth Table
Table 48: 3-bit LUT12 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
reg <714>
register [746]
register [747]
register [748]
register [749]
register [750]
register [751]
register [752]
register [753]
0
0
1
register [715]
register [716]
register [717]
register [718]
register [719]
register [720]
register [721]
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 45: 3-bit LUT9 Truth Table
Table 49: 3-bit LUT13 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [722]
register [723]
register [724]
register [725]
register [726]
register [727]
register [728]
register [729]
register [754]
register [755]
register [756]
register [757]
register [758]
register [759]
register [760]
register [761]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 46: 3-bit LUT10 Truth Table
Table 50: 3-bit LUT14 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [730]
register [731]
register [732]
register [733]
register [734]
register [735]
register [736]
register [737]
register [762]
register [763]
register [764]
register [765]
register [766]
register [767]
register [768]
register [769]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 47: 3-bit LUT11 Truth Table
Table 51: 3-bit LUT15 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [738]
register [739]
register [740]
register [741]
register [742]
register [743]
register [744]
register [745]
register [770]
register [771]
register [772]
register [773]
register [774]
register [775]
register [776]
register [777]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
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Each 3-bit LUT uses an 8-bit register signal to define their output functions;
3-Bit LUT0 is defined by registers [599:592]
3-Bit LUT1 is defined by registers [607:600]
3-Bit LUT2 is defined by registers [615:608]
3-Bit LUT3 is defined by registers [623:616]
3-Bit LUT4 is defined by registers [631:624]
3-Bit LUT5 is defined by registers [639:632]
3-Bit LUT6 is defined by registers [647:640]
3-Bit LUT7 is defined by registers [655 648]
3-Bit LUT8 is defined by registers [721:714]
3-Bit LUT9 is defined by registers [729:722]
3-Bit LUT10 is defined by registers [737:730]
3-Bit LUT11 is defined by registers [745:738]
3-Bit LUT12 is defined by registers [753:746]
3-Bit LUT13 is defined by registers [761:754]
3-Bit LUT14 is defined by registers [769:762]
3-Bit LUT15 is defined by registers [777:770]
The Table 52 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the 3-bit LUT logic cells.
Table 52: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
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9.3 4-BIT LUT
The one 4-bit LUT (LUT4_1) takes in four input signals from connection matrix 1 and produces a single output, which goes back
into connection matrix 1. The output state of the 4-bit LUT is defined by sixteen register bits, the output state is based on the
appropriate bit selected by the value of the four inputs to the LUT.
registers [793:778]
From Connection
Matrix Output 1 [32]
IN0
From Connection
Matrix Output 1 [33]
To Connection
Matrix Input 1 [13]
IN1
IN2
IN2
From Connection
Matrix Output 1 [34]
OUT
4-bit LUT1
From Connection
Matrix Output 1 [35]
Figure 34: 4-bit LUT_1
The device also includes one Combination Function Macrocell that can be used as a 4-bit LUT. For more details, please see
Section 10.
Table 53: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [778]
register [779]
register [780]
register [781]
register [782]
register [783]
register [784]
register [785]
register [786]
register [787]
register [788]
register [789]
register [790]
register [791]
register [792]
register [793]
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Each 4-bit LUT uses an 16-bit register signal to define their output functions;
4-Bit LUT1 is defined by registers [793:778]
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The Table 54 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within the 4-bit LUT logic cell.
Table 54: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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10 Combination Function Macrocells
The SLG46620-A has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve
as a Look Up Table (LUT), or Programmable Function Generator (PGEN).
When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix 0 and produce a
single output, which goes back into the connection matrix 0. When used as a LUT to implement combinatorial logic functions, the
outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND,
NAND, OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any
selectable function.
When operating as a Programmable Function Generator, the output of the macrocell with clock out a sequence of two to sixteen
bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the
pattern repeats. See Figure 36.
From Connection Matrix Output 0 [32]
From Connection Matrix Output 0 [33]
From Connection Matrix Output 0 [34]
From Connection Matrix Output 0 [35]
In0
In1
In2
In3
OUT
4-bit LUT1
LUT Truth
Table
0
1
To Connection Matrix 0 Input [13]
registers [671:656]
0: 4-bit LUT1 OUT
1: PGEN OUT
PGEN
Data
nRST
clk
PGEN
OUT
Pattern
size
register [676]
registers [675:672]
Figure 35: 4-bit LUT1 or PGEN
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VDD
t
t
t
t
nRST
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
OUT
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D0
Figure 36: PGEN Timing Diagram
When this macrocell is used to implement LUT function, the 4-bit LUT uses a 16-bit register signal to define its output function;
4-Bit LUT0 is defined by registers [671:656]
Table 55: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [656]
register [657]
register [658]
register [659]
register [660]
register [661]
register [662]
register [663]
register [664]
register [665]
register [666]
register [667]
register [668]
register [669]
register [670]
register [671]
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
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11 Analog Comparators
There are six Analog Comparator (ACMP) macrocells in the SLG46620-A. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMPx_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is
possible to have each ACMP be always on, always off, or power cycled based on a digital signal coming from the Connection
Matrix. When ACMP is powered down, output is low.
PWR UP = 1 → ACMP is powered up.
PWR UP = 0 → ACMP is powered down.
During ACMP power up, its output will remain low, and then becomes valid 2.08 ms (max) after ACMP power up signal goes high,
see Figure 37. If VDD is greater or equal to 2.7 V, it is possible to decrease turn-on time by setting the BG ok delay to 100
see Figure 38. To ensure proper chip startup operation, it is recommended to enable the ACMPs with the POR signal, and not
the VDD signal.
µ
s,
Figure 38: Maximum Power-On Delay vs. V , BG = 100 µs,
DD
Figure 37: Maximum Power-On Delay vs. V , BG = 550 µs,
DD
Regulator and Charge Pump set to automatic ON/OFF
Regulator and Charge Pump set to automatic ON/OFF
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources. There is also a selectable
gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The Gain divider is unbuffered and consists of
250 kΩ (typ.) resistors, see Table 56. For gain divider accuracy refer to Table 57. IN- voltage range: 0 - 1.2 V. Can use Vref selection
V
DD/4 and VDD/3 to maintain this input range.
Input bias current < 1 nA (typ).
Table 56: Gain Divider Input Resistance (typical)
Gain
x1
x0.5
x0.33
x0.25
1 MΩ
Input Resistance
100 GΩ
1 MΩ
0.75 MΩ
Table 57: Gain Divider typical Accuracy at T = (-40 to +105°C), VDD = 3.3 V
Gain
x0.5
x0.33
x0.25
±0.25%
Accuracy
±0.50%
±0.33%
Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. The 50 mV and 200 mV hysteresis
options can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external
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voltage reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be
Vref (high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is
within threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will
be Vref + hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).
Note: Any ACMP powered on enables the Bandgap internal circuit as well. An analog voltage will appear on Vref even when the
Force Bandgap option is set as Disabled.
For high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer (except ACMP5).
However, this will add an offset.
Note 1 When VDD < 1.8 V voltage reference should not exceed 1100 mV.
Note 2 For electrical specification refer to Section 3.7.
11.1 ACMP MASTER ARCHITECTURE
PIN 19
VDD
DAC0
selectable gain will be 1.0x, 0.5x, 0.333x, 0.25x
ACMP Buffer
Vref OUT
selectable
+
-
ACMP0
ACMP1
gain 2-bit
PIN 6
PIN 7
Internal Vref
27 values
5-bit
selectable gain will be 1.0x, 0.5x, 0.333x, 0.25x
From ADC PGA
selectable
gain 2-bit
+
-
PIN 12
PIN 10
Internal Vref
27 values
5-bit
selectable gain will be 1.0x, 0.5x, 0.333x, 0.25x
selectable
gain 2-bit
+
-
ACMP2
PIN 13
PIN 14
Internal Vref
27 values
5-bit
selectable gain will be 1.0x, 0.5x, 0.333x, 0.25x
selectable
gain 2-bit
+
-
ACMP3
PIN 15
Internal Vref
27 values
PIN 18
5-bit
DAC1
selectable gain will be 1.0x, 0.5x, 0.333x, 0.25x
selectable
gain 2-bit
+
-
ACMP4
ACMP5
PIN 3
Internal Vref
27 values
5-bit
PIN 4
PIN 5
no selectable gain on ACMP5
+
-
Internal Vref
27 values
5-bit
Figure 39: ACMP Master Architecture Diagram
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11.2 ACMP0 BLOCK DIAGRAM
to ACMP1, ACMP2, ACMP3,
ACMP4’s MUX input
registers [935:934]
register [832]
Hysteresis
Selection
registers [854:853]
ACMP Buffer*
100 µA
Current
Source
01
00
10
PIN6: ACMP0(+)
External VDD 1.71 V ~ 3.6 V
Selectable
Gain
To Connection
Matrix 0 Input[33]
+
-
L/S
pdb
Vref
registers [856:855]
ON after
BG on Delay
DAC0 OUT
DAC1 OUT
ACMP0 /2
ACMP1 /2
ACMP0
11111
11110
11101
11100
11011
11010
ACMP1
From Connection
Matrix 0 Output [69]
11001-
00000
Internal
Vref
*External VDD
2.7 V ~ 3.6 V
=
registers [896:892]
Figure 40: ACMP0 Block Diagram
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11.3 ACMP1 BLOCK DIAGRAM
registers [933:932]
register [831]
Hysteresis
Selection
100 µA
Current
Source
registers [858:857]
Pin 12: ACMP1(+)
00
ADC PGA OUT
Selectable
Gain
+
-
01
To Connection
Matrix 1 Input [33]
L/S
ACMP0 Input (before gain)
pdb
10
Vref
registers [860:859]
ON after
BG on Delay
DAC0 OUT
11111
DAC1 OUT
11110
ACMP0 /2
11101
ACMP1 /2
11100
ACMP0
11011
ACMP1
11010
From Connection
Matrix 1 Output [70]
11001-
00000
Internal
Vref
registers [901:897]
Figure 41: ACMP1 Block Diagram
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11.4 ACMP2 BLOCK DIAGRAM
registers [931:930]
Hysteresis
Selection
registers [865:864]
Pin 13 ACMP2(+)
0
Selectable
Gain
+
-
To Connection
Matrix 1 Input [34]
L/S
ACMP0 Input (before gain)
pdb
1
Vref
register [863]
ON after
BG on Delay
DAC0 OUT
11111
DAC1 OUT
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
ACMP1
11010
From Connection
Matrix 1 Output [71]
11001-
00000
Internal
Vref
registers [906:902]
Figure 42: ACMP2 Block Diagram
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11.5 ACMP3 BLOCK DIAGRAM
registers [929:928]
Hysteresis
Selection
registers [868:867]
PIN15: ACMP3(+)
00
PIN13: ACMP2(+)
Selectable
Gain
+
-
To Connection
Matrix 1 Input [35]
01
L/S
ACMP0 Input (before gain)
pdb
10
Vref
registers[870:869]
ON after
BG on Delay
DAC0 OUT
11111
DAC1 OUT
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
ACMP1
11010
From Connection
Matrix 1 Output [72]
11001-
00000
Internal
Vref
registers [911:907]
Figure 43: ACMP3 Block Diagram
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11.6 ACMP4 BLOCK DIAGRAM
registers [927:926]
Hysteresis
Selection
registers [872:871]
PIN3: ACMP4(+)
00
PIN15: ACMP3(+)
Selectable
Gain
+
-
To Connection
Matrix 0 Input [34]
01
L/S
ACMP0 Input (before gain)
pdb
10
Vref
registers[874:873]
ON after
BG on Delay
DAC0 OUT
11111
DAC1 OUT
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
ACMP1
11010
From Connection
Matrix 0 Output [70]
11001-
00000
Internal
Vref
registers [916:912]
Figure 44: ACMP4 Block Diagram
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11.7 ACMP5 BLOCK DIAGRAM
registers [925:924]
Hysteresis
Selection
Pin4 ACMP5(+)
+
-
To Connection
Matrix 0 Input [35]
L/S
pdb
Vref
ON after
BG on Delay
DAC0 OUT
11111
DAC1 OUT
11110
ACMP5 /2
11101
ACMP1 /2
11100
ACMP5
11011
ACMP1
11010
From Connection
Matrix 0 Output [71]
11001-
00000
Internal
Vref
registers [921:917]
Figure 45: ACMP5 Block Diagram
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11.8 ACMP TYPICAL PERFORMANCE
180
160
140
120
100
80
Max
Typ
Min
60
40
20
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Input Voltage (V)
Figure 46: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 105 °C, VDD = 3.3 V
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12 Digital Storage Elements
There are twelve D Flip-Flop/Latches (DFF/LATCH) logic cells within the SLG46620-A available for design. The source and
destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/LATCH macrocells
have user selection for initial state. The macrocells DFF0, DFF1, DFF2, DFF6, DFF7, and DFF8 have an additional input from
the matrix that can serve as a nSet or nRST function to the macrocell.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High).
DFF or LATCH Select
register [677]
Initial Polarity Select
register [680]
From Connection Matrix 0 Output [37]
From Connection Matrix 0 Output [38]
To Connection Matrix 0 Input [14]
D
Q/nQ
DFF/Latch0
CLK
nRST
nSET
From Connection Matrix 0 Output [36]
0
1
Output Select (Q or nQ)
register [678]
0
1
register [679]
Figure 47: DFF/Latch0
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DFF or LATCH Select
Initial Polarity Select
register [684]
register [681]
From Connection Matrix 0 Output [40]
From Connection Matrix 0 Output [41]
To Connection Matrix 0 Input [15]
D
Q/nQ
DFF/Latch1
CLK
nRST
nSET
From Connection Matrix 0 Output [39]
0
1
Output Select (Q or nQ)
register [682]
0
1
register [683]
Figure 48: DFF/Latch1
DFF or LATCH Select
register [685]
Initial Polarity Select
register [688]
From Connection Matrix 0 Output [43]
From Connection Matrix 0 Output [44]
To Connection Matrix 0 Input [16]
D
Q/nQ
DFF/Latch2
CLK
nRST
nSET
From Connection Matrix 0 Output [42]
0
1
Output Select (Q or nQ)
register [686]
0
1
register [687]
Figure 49: DFF/Latch2
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DFF or LATCH Select
register [689]
Initial Polarity Select
register [691]
From Connection Matrix 0 Output [45]
To Connection Matrix 0 Input [17]
D
Q/nQ
DFF/Latch3
From Connection Matrix 0 Output [46]
CLK
Output Select (Q or nQ)
register [690]
Figure 50: DFF/Latch3
DFF or LATCH Select
register [692]
Initial Polarity Select
register [694]
From Connection Matrix 0 Output [47]
From Connection Matrix 0 Output [48]
To Connection Matrix 0 Input [18]
D
Q/nQ
DFF/Latch4
CLK
Output Select (Q or nQ)
register [693]
Figure 51: DFF/Latch4
DFF or LATCH Select
register [695]
Initial Polarity Select
register [697]
From Connection Matrix 0 Output [49]
To Connection Matrix 0 Input [19]
D
Q/nQ
DFF/Latch5
From Connection Matrix 0 Output [50]
CLK
Output Select (Q or nQ)
register [709]
Figure 52: DFF/Latch5
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DFF or LATCH Select
Initial Polarity Select
register [797]
register [794]
From Connection Matrix 1 Output [37]
From Connection Matrix 1 Output [38]
To Connection Matrix 1 Input [14]
D
Q/nQ
DFF/Latch6
CLK
nRST
nSET
From Connection Matrix 1 Output [36]
0
1
Output Select (Q or nQ)
register [795]
0
1
register [796]
Figure 53: DFF/Latch6
DFF or LATCH Select
register [798]
Initial Polarity Select
register [801]
From Connection Matrix 1 Output [40]
From Connection Matrix 1 Output [41]
To Connection Matrix 1 Input [15]
D
Q/nQ
DFF/Latch7
CLK
nRST
nSET
From Connection Matrix 1 Output [39]
0
1
Output Select (Q or nQ)
register [799]
0
1
register [800]
Figure 54: DFF/Latch7
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DFF or LATCH Select
Initial Polarity Select
register [805]
register [802]
From Connection Matrix 1 Output [43]
From Connection Matrix 1 Output [44]
To Connection Matrix 1 Input [16]
D
Q/nQ
DFF/Latch8
CLK
nRST
nSET
From Connection Matrix 1 Output [42]
0
1
Output Select (Q or nQ)
register [803]
0
1
register [804]
Figure 55: DFF/Latch8
DFF or LATCH Select
register [806]
Initial Polarity Select
register [808]
From Connection Matrix Output [45]
From Connection Matrix Output [46]
To Connection Matrix Input [17]
D
Q/nQ
DFF/Latch9
CLK
Output Select (Q or nQ)
register [807]
Figure 56: DFF/Latch9
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DFF or LATCH Select
register [809]
Initial Polarity Select
register [811]
From Connection Matrix 1 Output [47]
To Connection Matrix 1 Input [18]
D
Q/nQ
DFF/Latch10
From Connection Matrix 1 Output [48]
CLK
Output Select (Q or nQ)
register [810]
Figure 57: DFF/Latch10
DFF or LATCH Select
register [812]
Initial Polarity Select
register [814]
From Connection Matrix 1 Output [49]
From Connection Matrix 1 Output [50]
To Connection Matrix 1 Input [19]
D
Q/nQ
DFF/Latch11
CLK
Output Select (Q or nQ)
register [813]
Figure 58: DFF/Latch11
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12.1 INITIAL POLARITY OPERATIONS
Figure 59: DFF Polarity Operations
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Figure 60: DFF Polarity Operations with nRST
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Figure 61: DFF Polarity Operations with nSet
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13 Counters/Delay Generators
There are ten configurable counters/delay (CNT/DLY) generators in the SLG46620-A. Four of these counters/delay generators
(CNT/DLY 0, 1, 2 and 3) are 14-bit, and six of the counters/delay generators (CNT/DLY 4, 5, 6, 7, 8 and 9) are 8-bit. Each macrocell
has a dedicated matrix input connection, some of the macrocells have additional matrix connections to support optional functions,
as listed below. For flexibility, each of these macrocells has a large selection of internal and external clock sources, as well as the
option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits.
The delay time and counter output equation is as follows:
Delay time = ((counter data + 1) + variable) / Clock
Variable = (0 or 1) * period
Counter period = (counter data + 1) / Clock
Note: Variable can be negative, since OSC can operate while Delay input changes. In this case it might be possible that we will
not see first period, if OSC rising edge appears immediately after input change.
Counter/delay macrocells (0, 2, 5, 6, 9) are connected to Matrix 0 with both inputs and outputs, counter/delay macrocells (1, 3, 4
7, 8) are connected to Matrix 1 with both inputs and outputs.
Four of the counter/delay generator macrocells (CNT/DLY 0,1,2,3) have an optional Edge Detector function.
Two of the counter/delay generator macrocells (CNT/DLY 2,4) have an optional Finite State Machine (FSM) function.These two
macrocells each have two additional matrix inputs for Up and Keep to support FSM functionality.
Two of the counter/delay generator macrocells (CNT/DLY 8,9) have an optional PWM Ramp function.
One of the counter/delay generator macrocells (CNT/DLY 0) can optionally serve as a Wake/Sleep Counter.
Please see Table 58 for a summary of all optional functions:
Table 58: Counter/Delay Macrocell Functions Summary
Finite State
Machine
(FSM)
Edge
Detector
Wake/Sleep
Counter
Macrocell
Bit-Width
Counter
Delay
PWM Ramp
CNT/DLY0
CNT/DLY1
CNT/DLY2
CNT/DLY3
CNT/DLY4
CNT/DLY5
CNT/DLY6
CNT/DLY7
CNT/DLY8
CNT/DLY9
14-bit
14-bit
14-bit
14-bit
8-bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8-bit
8-bit
8-bit
8-bit
X
X
8-bit
Note: Counters initialize with counter data after POR.
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Mode Select: registers [1749:1748]
Connection Matrix 0 Output [74]
Macrocell Function Select: registers [1751:1750]
Wake/Sleep Output State: register [1752]
Clock Source Select: registers [1747:1745]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 0 Input [36]
1
CNT/DLY0
RC OSC/24
2
Counter_end
RC OSC/64
3
clk
LF OSC
4
CNT_END9
5
RING OSC
6
Matrix 0 Output [72]
7
Counter Control Data
registers [1744:1731]
Figure 62: CNT/DLY0
Mode Select: registers [1771:1770]
Connection Matrix 1 Output [75]
Macrocell Function Select: registers [1773:1772]
Clock Source Select: registers [1769:1767]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 1 Input [36]
1
CNT/DLY1
RC OSC/24
2
Counter_end
RC OSC/64
3
CLK
LFOSC
4
CNT_END0
5
RING OSC
6
Matrix 1 Output [74]
7
Counter Control Data
registers [1766:1753]
Figure 63: CNT/DLY1
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Mode Select: registers [1793:1792]
Macrocell Function Select: registers [1795:1794]
FSM Input Source Select:
registers [1797:1796]
Connection Matrix 0 Output [77]
UP
FSM0
KEEP
Connection Matrix 0 Output [76]
Connection Matrix 0 Output [75]
Clock Source Select: registers [1791:1788]
RC OSC
0
RC OSC/4
1
IN
RC OSC/12
2
RC OSC/24
3
To Connection
Matrix 0 Input [37]
RC OSC/64
4
CNT/DLY2
CNT_END1
5
Counter_end
Matrix 0 Output [72]
Matrix 0 Output [72] /8
RING OSC
6
7
8
CLK
Matrix 0 Output [83]
9
LFOSC
CLK_FSM/256
CLK_PWM
10
11
12
13
14
15
Reserved
Reserved
Reserved
Counter Control Data
registers [1787:1774]
CNT2 Value Control: register [1798]
Figure 64: CNT/DLY2/FSM0
Mode Select: registers [1817:1816]
Connection Matrix 1 Output [76]
Macrocell Function Select: registers [1819:1818]
Clock Source Select: registers [1815:1813]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 1 Input [37]
1
CNT/DLY3
RC OSC/24
2
Counter_end
RC OSC/64
3
clk
LF OSC
4
CNT_END2
5
Ring OSC
6
Matrix 1 Output [74]
7
Counter Control Data
registers [1812:1799]
Figure 65: CNT/DLY3
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Mode Select: registers [1833:1832]
Macrocell Function Select: register [1834]
FSM Input Source Select:
registers [1836:1835]
Connection Matrix 1 Output [79]
UP
FSM1
KEEP
Connection Matrix 1 Output [78]
Connection Matrix 1 Output [77]
Clock Source Select: registers [1831:1828]
RC OSC
0
RC OSC/4
1
IN
RC OSC/12
2
RC OSC/24
3
To Connection
Matrix 1 Input [38]
RC OSC/64
4
CNT/DLY4
CNT_END3
5
Counter_end
Matrix 1 Output [74]
Matrix 0 Output [72] /8
RING OSC
6
7
8
CLK
Matrix 0 Output [83]
9
LF OSC
CLK_FSM/256
CLK_PWM
10
11
12
13
14
15
Reserved
Reserved
Reserved
Counter Control Data
registers [1827:1820]
CNT4 Value Control register [1837]
Figure 66: CNT/DLY4/FSM0
Mode Select: registers [1850:1849]
Connection Matrix 0 Output [78]
Macrocell Function Select: register [1851]
Clock Source Select: registers [1848:1846]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 0 Input [38]
1
CNT/DLY5
RC OSC/24
2
Counter_end
RC OSC/64
3
clk
LF OSC
4
CNT_END4
5
Ring OSC
6
Matrix 0 Output [73]
7
Counter Control Data
registers [1845:1838]
Figure 67: CNT/DLY5
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Mode Select: registers [1864:1863]
Connection Matrix 0 Output [79]
Macrocell Function Select: register [1865]
Clock Source Select: registers [1862:1860]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 0 Input [39]
1
CNT/DLY6
RC OSC/24
2
Counter_end
RC OSC/64
3
clk
LF OSC
4
CNT_END5
5
Ring OSC
6
Matrix 0 Output [73]
7
Counter Control Data
registers [1859:1852]
Figure 68: CNT/DLY6
Mode Select: registers [1878:1877]
Connection Matrix 1 Output [80]
Macrocell Function Select: registers [1879]
Clock Source Select: registers [1876:1874]
RC OSC
IN
0
RC OSC/4
To Connection
Matrix 1 Input [39]
1
CNT/DLY7
RC OSC/24
2
Counter_end
RC OSC/64
3
clk
LF OSC
4
CNT_END6
5
Ring OSC
6
Matrix 1 Output [73]
7
Counter Control Data
registers [1873:1866]
Figure 69: CNT/DLY7
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Mode Select: registers [1893:1892]
Connection Matrix 1 Output [81]
Macrocell Function Select: registers [1894]
Clock Source Select: registers [1891:1888]
RC OSC
0
RC OSC/4
1
IN
RC OSC/12
2
RC OSC/24
3
To Connection
Matrix 1 Input [40]
RC OSC/64
4
CNT/DLY8
CNT_END7
5
Counter_end
Matrix 1 Output [73]
Matrix 0 Output [72] /8
RING OSC
6
7
8
CLK
Matrix 0 Output [83]
9
LF OSC
CLK_FSM/256
CLK_PWM
10
11
12
13
14
15
Reserved
Reserved
Reserved
Counter Control Data
registers [1887:1880]
Figure 70: CNT/DLY8/PWM_RAMP
Mode Select: registers [1908:1907]
Connection Matrix 0 Output [80]
Macrocell Function Select: registers [1909]
Clock Source Select: registers [1906:1903]
RC OSC
0
RC OSC/4
1
IN
RC OSC/12
2
RC OSC/24
3
To Connection
Matrix 0 Input [40]
RC OSC/64
4
CNT/DLY9
CNT_END8
5
Counter_end
Matrix 0 Output [72]
Matrix 0 Output [72] /8
RING OSC
Matrix 0 Output [83]
LF OSC
6
7
8
CLK
9
10
11
12
13
14
15
CLK_FSM/256
CLK_PWM
Reserved
Reserved
Reserved
Counter Control Data
registers [1902:1895]
Figure 71: CNT/DLY9/PWM_RAMP
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13.1 CNT/DLY TIMING DIAGRAMS
13.1.1 Delay Mode (Counter Data: 3) CNT/DLY0...CNT/DLY9
DLYIN
offset
period
1
2
3
4
5
CLK (OSC force on)
DLYOUT
delay = offset + period x (count_data + 1)
offset = (0 or 1) * period
DLYIN
offset
1
2
3
4
5
CLK (single DLY usage,
OSC is autopower-on)
DLYOUT
delay = offset + period x (count_data + 1)
offset = (0 or 1) * period (25 kHz)
offset = (0, 1 or 2) * period (2 MHz)
Figure 72: Timing (Rising Edge) for Count Data = 3
DLYIN
offset
period
1
2
3
4
5
CLK (OSC force on)
DLYOUT
delay = offset + period x (count_data + 1)
offset = (0 or 1) * period
DLYIN
offset
1
2
3
4
5
CLK (single DLY usage,
OSC is autopower-on)
DLYOUT
delay = offset + period x (count_data + 1)
offset = (0 or 1) * period (25 kHz)
offset = (0, 1 or 2) * period (2 MHz)
Figure 73: Timing (Falling Edge) for Count Data = 3
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13.1.2 Counter Mode (Counter Data: 3) CNT/DLY0...CNT/DLY9
RESETIN
The pulse width is about 10 ns, depending on PVT
EDGE DETECT OUT
CLK
OUT
Q
4 clk period pulse
1
0
3
2
1
0
3
2
1
0
3
2
3
2
1
0
3
2
0
Note: Q = current counter value
Figure 74: Timing (Reset Rising Edge Mode, Oscillator is Forced on) for Count Data = 3
RESETIN
From Matrix
The pulse width is about 10 ns, depending on PVT
EDGE DETECT OUT
CLK
OUT
Q
4 clk period pulse
1
0
3
2
1
0
3
2
1
0
3
2
3
2
1
0
3
2
0
Note: Q = current counter value
Figure 75: Timing (Reset Falling Edge Mode, Oscillator is Forced on) for Count Data = 3
RESETIN
From Matrix
one clock cycle time + offset
CLK ENABLE
the offset value is the same as the DLYs auto on case
CLK
COUNTEND
1
0
3
2
1
0
3
0
3
2
0
3
2
Q
Note: Q = current counter value
Figure 76: Timing (Reset High Level Mode, Oscillator is Autopowered on (Controlled by Reset)) for Count Data = 3
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13.1.3 CNT/FSM Mode CNT/DLY2, CNT/DLY4
RESETIN
KEEP
COUNT_END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 77: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP=0) for Counter Data = 3
RESETIN
KEEP
COUNTEND
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 78: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced on, UP=0) for Counter Data = 3
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RESETIN
KEEP
COUNTEND
CLK
5
6
7
8
9
253 254 255
3
4
5
3
4
5
1
2
3
4
0
Q
FSM0 16383
FSM1 255
Note: Q = current counter value
Figure 79: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced on, UP=1) for Counter Data = 3
RESETIN
KEEP
COUNTEND
CLK
8
9
10 11 12
253 254 255
3
4
5
3
4
5
4
5
6
7
3
Q
FSM0 16383
FSM1 255
Note: Q = current counter value
Figure 80: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced on, UP=1) for Counter Data = 3
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14 Digital Comparator/Pulse Width Modulator
The SLG46620-A has three 8-bit digital comparator (DCMP)/ pulse width modulator (PWM) logic macrocells. Each of these three
logic macrocells can be either a digital comparator (DCMP) or a pulse width modulator (PWM) independently of how the other
two logic macrocells are defined.
Both the DCMP and PWM logic can operate at up to a frequency of 10 MHz. The input power for the three logic macrocells is
controlled independently by register [1678] for DCMP0/PWM0, register [1698] for DCMP1/PWM1 and register [1718] for DCMP2/
PWM2.
PWM power-down control is configured by register [1677] which is also shared with the ADC and OSC.
14.1 DCMP INPUT MODES
All three DCMP logic macrocells have a positive (IN+) and a negative (IN-) input. The signal (through the IN+ input) takes the
value from a 4:1 MUX selection between the following signals:
8-bit signal from the ADC Parallel Output
8-bit signal from the SPI logic cell output (SPI[15:8] for DCMP0 and DCMP2 or SPI[7:0] for DCMP1)
8-bit signal from the FSM (FSM0[7:0] for DCMP0 or FSM1[7:0] for DCMP1 and DCMP2)
8-bit user defined signal value.
The signal (through the IN- input) takes the value from a 4:1 MUX selection between the following signals:
8-bit signal from the CNT (CNT9'Q [7:0] for DCMP1 or CNT8'Q [7:0] for DCMP0 and DCMP2)
8-bit signal from the SPI logic cell output (SPI[7:0] for DCMP0 and DCMP2 or SPI[15:8] for DCMP1)
8-bit signal from the FSM (FSM1' Q [7:0] for DCMP0 or FSM0'Q[7:0] for DCMP1 and DCMP2)
8-bit user defined signal value.
14.2 DCMP OUTPUT MODES
The two 8-bit parallel data inputs from IN+ and IN- are compared within the DCMP logic macrocells to produce the output (OUT+)
and an Equal signal (EQ).
There are two cases for the OUT+ signal controlled by register [1714], register [1694], register [1673].
If these registers = 0, then
if inp > inn, OUT+ = 1, EQ = 0
if inp < inn, OUT+ = 0, EQ = 0
if inp = inn, OUT+ = 0, EQ = 1
If these registers = 1, then
if inp > inn, OUT+ = 1, EQ = 0
if inp < inn, OUT+ = 0, EQ = 0
if inp = inn, OUT+ = 1, EQ = 1
Both the OUT+ and EQ signals are triggered by the rising or falling edge (controlled by register [1676], register [1697] and
register[1717]) of the CLK OSC signal (clock source is defined by registers [1629:1628]) and result of comparison can be read in
the next clock pulse, see Figure 81, where register [1714], register [1694], register [1673] are equal 0.
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CLK
IN+
78
254
200
178
250
248
249
95
255
240
254
(ADC Parallel data)
IN-
253
252
251
248
255
(CNT8'Q [7:0])
IN+ = IN-
IN+ > IN-
IN+ < IN-
EQ
EQ = 0
OUT = 1
EQ = 0
OUT = 0
EQ = 1
OUT = 0
OUT
Figure 81: DCMP Timing Diagram
14.3 PWM INPUT MODES
IN+ for the PWM is an 8-bit data string that can be selected from one of four sources;
8-bit signal from the ADC Parallel Output
8-bit signal from the SPI logic cell output (SPI[15:8] for DCMP0 and DCMP1 or SPI[7:0] for DCMP2)
8-bit signal from the FSM0[7:0]
8-bit user defined signal value
IN-’s 8-bit data string for all PWMs is sourced from an 8-bit signal from CNT/DLY1.
14.4 PWM OUTPUT MODES
The output (OUT+) duty cycle can be set to either count down to 0% or count up to 100% and each PWM is independently
controlled by the value of register [1673] (PWM0), register [1694] (PWM1), and register [1714] (PWM2). When both inputs are
equal the output signal (EQ) will go high. The outputs (OUT- and OUT+) are non-overlapping.
When registers [1673/1694/1714] = “0”
PWM output duty cycle ranges from 0% to 99.61% and is determined by: Output Duty Cycle = IN+/256
(IN+ = 0: output duty cycle = 0/256 = 0%; IN+ = 255: output duty cycle = 255/256 = 99.61%)
Output signals are triggered by the rising or falling edge of the CLK OSC signal (defined by bit registers [1676], [1697],
[1717]).
When registers [1673/1694/1714] = “1”
PWM output duty cycle ranges from 0.39% to 100% and is determined by Output Duty Cycle = (IN+ + 1)/256
8(IN+ = 0: output duty cycle = 1/256 = 0.39%; IN+ = 255: output duty cycle = 256/256 = 100%)
Output signals are triggered by the rising or falling edge of the CLK OSC signal (defined by bit registers [1676], [1697],
[1717]).
When IN+ = IN- then EQ = “1”
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14.5 DCMP0/PWM0 FUNCTIONAL DIAGRAM
register [1678]
Connection Matrix 1 Output [82]
register [1677]
PWM PD
Select
registers [1680:1674]
Connection Matrix 1
Output [84:83]
ADC[7:0]
00
8MSBs SPI
FSM0[7:0]
01
10
11
register 0 [1730:1723]
IN+
00
register 1 [1710:1703]
register 2 [1690:1683]
register 3 [1669:1662]
01
10
11
DCMP0/PWM0
To Connection Matrix 1 Input [43]
To Connection Matrix 1 Input [42]
CNT8_Q[7:0]
reg0
OUT+
00
01
10
11
IN-
8LSBs SPI
FSM1[7:0]
EQ/OUT-
CLK OSC
Output Range Select
0 = 0% to 99.61%
1 = 0.39% to 100%
registers [1682:1681]
register [1676]
register [1673]
Figure 82: DCMP0/PWM0 Functional Diagram
14.6 DCMP1/PWM1 FUNCTIONAL DIAGRAM
register [1698]
Connection Matrix 1 Output [82]
register [1677]
PWM PD
Select
registers [1700:1699]
ADC [7:0]
00
8LSBs SPI
Connection Matrix 1
Output [84:83]
01
10
11
IN+
FSM1[7:0]
reg1
DCMP1/PWM1
To Connection Matrix 1 Input [45]
To Connection Matrix 1 Input [44]
register 3 [1669:1662]
00
CNT9_Q[7:0]
OUT+
register 2 [1690:1683]
register 1 [1710:1703]
register 0 [1730:1723]
00
01
10
11
01
10
11
IN-
8LSBs SPI
FSM0[7:0]
EQ/OUT-
CLK OSC
Output Range Select
registers [1702:1701]
0 = 0% to 99.61%
1 = 0.39% to 100%
register [1694]
register [1697]
Figure 83: DCMP1/PWM1 Functional Diagram
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14.7 DCMP2/PWM2 FUNCTIONAL DIAGRAM
register [1718]
Connection Matrix 1 Output [82]
register [1677]
PWM PD
Select
registers [1720:1719]
ADC]7:0]
00
SPI [15:8]
01
10
11
IN+
FSM1[7:0]
reg3
DCMP2/PWM2
To Connection Matrix 1 Input [47]
To Connection Matrix 1 Input [46]
CNT8_Q[7:0]
OUT+
00
01
10
11
registers [1690:1683]
IN-
EQ/OUT-
8LSBs SPI
FSM0[7:0] (CNT2_Q[7:0])
CLK OSC
Output Range Select
0 = 0% to 99.61%
1 = 0.39% to 100%
registers [1722:1721]
register [1717]
register [1714]
Figure 84: DCMP2/PWM2 Functional Diagram
14.8 PWM DEAD BAND CONTROL
The dead band interval can be controlled with NVM bits from PWM0 registers [1722:1720], from PWM1 registers [1693:1691],
from PWM2 registers [1713:1711]. The typical dead band time starts at 8 ns and can go to 64 ns, increasing by 8 ns intervals.
For the Delay dead band control, the dead time control range is:
T
D = (PWM Register bits + 1) x 8ns
14.9 PWM DEAD BAND CONTROL TIMING DIAGRAM
PWM (out)
Reference
outp
outn
Dead time
Dead time
Figure 85: PWM Dead Band Control Timing Diagram
14.10 DCMP/PWM POWER-DOWN CONTROL
The power-down source for the DCMP/PWM logic cells is selected by registers [1521:1516]. The DCMP/PWM logic cells can
then be turned on or off individually with the appropriate register. The power-down control of each logic cell is managed by the
following register settings:
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When register [1678] = “0” DCMP0/PWM0 is powered down, when “1” logic cell is ON
When register [1698] = “0” DCMP1/PWM1 is powered down, when “1” logic cell is ON
When register [1718] = “0” DCMP2/PWM2 is powered down, when “1” logic cell is ON
14.11 DCMP/PWM CLOCK INVERT CONTROL
The three DCMP/PWM logic cells can invert the CLK OSC input signal during the compare or PWM function. Register [1676],
register [1697] and register [1717] is used to control the three logic cells clock inversion for PWM0, PWM1, and PWM2
respectively.
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15 Slave SPI - Serial to Parallel/Parallel to Serial Converter (SPI)
The Slave SPI data can be communicated between the SLG46620-A and the larger system design through either the serial to
parallel or parallel to serial interface. The SPI has two 8-bit registers (2 bytes) that are used for data transfer. The external clock
signal and the nCSB (Enable Control Signal) comes from the Connection Matrix OUT.
For serial to parallel operation (S2P), the serial data in (MOSI) comes from PIN 10 of the SLG46620-A. The S2P will produce a
16-bit parallel data output (S2P[15:0]) where the MSB [15:8] can be used by the PWM/DCMP0_IN+, PWM/DCMP1_IN-, PWM/
DCMP2_IN+ and FSM1 logic cells, while the LSB [7:0] can be used by the PWM/DCMP0_IN-, PWM/DCMP1_IN+, PWM/
DCMP2_IN- and FSM0 logic cells.
In parallel to serial mode (P2S) there is an additional configuration of the length of converted code - 8-bit and 16-bit. With 8-bit
configuration the parallel data from FSM0 or ADC can be converted to serial data. PIN 10 is used to output this 8-bit serial data
OUT (MISO) signal. With 16 bit configuration the parallel data from FSM0 and FSM1 can be converted into a serial code. 8 LSB
bits of FSM1 data will be sent to PAR_IN[7:0] and 8-bits of FSM0 will be sent to PAR_IN[15:8]. Same as in 8-bit mode 16 bit serial
data will be output to PIN 10.
15.1 SPI FUNCTIONAL DIAGRAM
FSM1
FSM CLK SYNC register [1634]
PWM/DCMP0 IN+
PWM/DCMP1 IN-
PWM/DCMP2 IN+
PWM CLK SYNC register [1633]
ADC CLK SYNC register [1641]
ADC Buffer Enable register [1656]
IO Mode register [1661]
PDO[15:8]
PDO [7:0]
SPI
SPI Mode registers [1659:1658]
16/8-bit Mode select register [1660]
Parallel Data in Source register[1657]
FSM0
PWM/DCMP0 IN-
PWM/DCMP1 IN+
PWM/DCMP2 IN-
Matrix 1 IN [51:44]
FSM0 and FSM1
0
PDI
ADC
1
Pin 10
SDI
Connection Matrix 0 Output [82]
Connection Matrix 0 Output [83]
CSB
SCLK
SDO
0X
10
11
Pin 10
SDO path select registers [2017:2016]
Figure 86: SPI Functional Diagram
15.2 CLOCK POLARITY AND PHASE
In addition to setting the clock frequency, it is possible to configure the clock polarity and phase with respect to the data. This is
configured by the CPOL and CPHA respectively.
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Figure 87 shows the SPI timing diagram when CPHA=0; in this mode data can only be transmitted from serial to parallel, not from
parallel to serial. Figure 88 shows the SPI timing diagram when CPHA=1; in this mode data can be transmitted both from serial
to parallel and from parallel to serial.
tCSW
CSB
tCSS
tCH tCL
tCP
tCSH
SCLK (CPOL=0)
tCSH
SCLK (CPOL=1)
tDIS tDIH
SDI
LSB
MSB
Bit[1]
LSB
MSB
Bit[1]
Figure 87: Timing Diagram showing Clock Polarity and Phase, CPHA=0
Table 59: CPHA = 0 Timing Characteristics
Description
Parameter
tCP
Min
500
250
250
250
250
500
100
50
Max
--
Units
ns
SCLK period
SCLK pulse width high
SCLK pulse width low
CSB fall to SCLK first edge setup
SCLK last edge to CSB rise hold
CSB pulse width high
SCLK to SDI hold
tCH
--
ns
tCL
--
ns
tCSS
tCSH
tCSW
tDIH
--
ns
--
ns
--
ns
--
ns
SCLK to SDI setup
tDIS
--
ns
SCLK rise/fall time
tCKR
--
20
ns
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tCSW
CSB
SCLK (CPOL=0)
tCSS
tCH tCL
tCP
tCSH
tCSH
LSB
SCLK (CPOL=1)
tDOD tDOS
tDOD
tDOE
tDOH
MSB
Bit[1]
LSB
tSIR
MSB
tSIF
Bit[1]
SDO
tSI
tCI
Interrupt
tDIS tDIH
SDI
LSB
MSB
Bit[1]
LSB
MSB
Bit[1]
Figure 88: Timing Diagram showing Clock Polarity and Phase, CPHA = 1
Table 60: CPHA = 1 Timing Characteristics
Description
Parameter
tCP
Min
500
250
250
250
250
100
100
--
Max
--
Units
SCLK period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width high
SCLK pulse width low
CSB fall to SCLK first edge setup
SCLK last edge to CSB rise hold
SCLK to SDO hold
tCH
--
tCL
--
tCSS
--
tCSH
tDOH
tDOS
tDOD
tDOD
tDOE
tCSW
tSIR
--
--
SCLK to SDO setup
--
SCLK to SDO delay
150 (Note 1)
150 (Note 1)
150 (Note 1)
--
CSB rise to SDO disable
CSB fall to SDO enable
CSB pulse width high
LSB' SCLK fall to Interrupt high
MSB' SCLK fall to Interrupt low
SCLK to Interrupt high
CSB rise to Interrupt low
SCLK to SDI hold
5
5
500
5
150 (Note 1)
150 (Note 1)
150 (Note 1)
150 (Note 1)
--
tCIF
5
tSI
5
tCI
5
tDIH
100
50
--
SCLK to SDI setup
tDIS
--
SCLK rise/fall time
tCKR/tCKF
tDOR/tDOF
20
SDO rise/fall time
--
20*
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Table 60: CPHA = 1 Timing Characteristics
Description
Parameter
Min
Max
Units
Interrupt rise/fall time
tIR/tIF
--
20*
ns
Note 1 The data is based on 50 pF loading on the output PIN, and the output drive strength is 2x option.
At CPOL=0 the base value of the clock is zero
For CPHA=0, data are captured on the clock's rising edge (LOW→HIGH transition) and data is propagated on a falling
edge (HIGH→LOW clock transition)
For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge
At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge
For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge
That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock
edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle
before the first clock cycle.
The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI
master and slave devices may well sample data at different points in that half cycle.
This adds more flexibility to the communication channel between the master and slave.
15.3 SPI CLOCK SYNCHRONIZATION
When the parallel data is going to be loaded into the buffer in SPI, the SPI will generate the "sync" signal, it will be gating the
ADC/PWM CLOCK or FSM CLOCK/256 to stop the running ADC, PWM, FSM or CNTs to avoid mis-catch data due to the
asynchronization of SCLK and the internal clocks, see Figure 79.
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Note: The internal clock and SPI clock must satisfy the: 2TCLK_INT<1/2TSCK
SYNC
CLK_INT
sync_pipe
The delay is within 2 CLK_INT period
CLK_synced
Half of the SCK period
LOAD (in the SPI)
When load to trigger the ADC data,
the data must be frozen
Figure 89: Timing Diagram showing SPI Clock synchronization
15.4 SPI DATA BUFFER FUNCTION
SPI data buffer can be used to have DCMP compare two different ADC timing data. The ADC buffer is shared with the DFFs that
are in the SPI macrocell. When the SPI is set to ADC buffer mode (register [1656]=1), the DFF 's data inputs of SPI's parallel
outputs are from ADC and the DFF's clock source comes from matrix0_output83 which can be programmed by user. The DFF's
output (SPI[7:0]) is the ADC data's buffered output which can be sent to DCMP/PWMs or FSM (CNT)s.
register [1656]
0
16
0,ADC[7:0]
SPI [15:0]
D
Q
Q
16
1
Ck
RB
register [1659]
SPI_SCLK
(matrix0_out83)
nRST_core
Figure 90: The SPI used as ADC data buffer diagram
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16 Pipe Delay
The SLG46620-A has two 16-stages DFF Pipe Delay (PD) Macrocells.
Each Pipe Delay has three input signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe delay cell is built
from 16 D Flip-Flop logic cells that provide two delay options which are user selectable. The DFF cells are tied in series where
the output (Q) of each delay cell goes to the next DFF cell. The two outputs (OUT0 and OUT1) provide user selectable options
for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input MUX that is
controlled by register bits. The 4-input MUX is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46620-A design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or any Oscillator within the SLG46620-A). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell.
registers [1617:1614]
register [1618]
0
OUT1
To Connection
Matrix 0 Input [21]
1
From Connection
RST
Matrix 0 Output [53]
From Connection
IN
16 Flip-Flops
Matrix 0 Output [52]
From Connection
CLK
Matrix 0 Output [51]
OUT0
To Connection
Matrix 0 Input [20]
registers [1613:1610]
Figure 91: Pipe Delay 0
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registers [1626:1623]
register [1627]
0
1
OUT1
To Connection
Matrix 1 Input [21]
From Connection
RST
Matrix 1 Output [53]
From Connection
IN
16 Flip-Flops
Matrix 1 Output [52]
From Connection
Matrix 1 Output [51]
CLK
OUT0
To Connection
Matrix 1 Input [20]
registers [1622:1619]
Figure 92: Pipe Delay 1
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17 Programmable Delay/Edge Detector
The SLG46620-A has two programmable time delay logic cells available that can generate a delay that is selectable from one of
four timings (time1) configured in the GreenPAK Designer. The programmable time delay cells can generate one of four different
delay patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. Three of these patterns
can be further modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection
during the delay period. Note that, delayed edge detection function is not available for both edge delay pattern. See the timing
diagrams below for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out
registers [1603:1602]
Delay Value Selection
registers [1601:1600]
Edge Mode Selection
To Connection
Matrix 0 Input [22]
Programmable
From Connection Matrix 0 Output [54]
IN
OUT
Delay 0
register [1604]
Delayed Edge Detector Output
Figure 93: Programmable Delay
registers [1608:1607]
Delay Value Selection
registers [1606:1605]
Edge Mode Selection
To Connection
Matrix 1 Input [22]
Programmable
From Connection Matrix 1 Output [54]
IN
OUT
Delay 1
register [1609]
Delayed Edge Detector Output
Figure 94: Programmable Delay
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17.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
time1
time1
IN
Rising Edge Detector
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time1 can be set by register value, see Table 10
Figure 95: Edge Detector Output
time2
time2
time1
time1
IN
Delayed Rising Edge Detector
Delayed Falling Edge Detector
Delayed Edge
Detector Output
Delayed Both Edge Detector
time1
Delayed Both Edge Delay
time1
time1 can be set by register value (150 ns, 300 ns, 450 ns, 600 ns)
time2 is a fixed value at ~200 ns
Figure 96: Delayed Edge Detector Output
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17.2 PROGRAMMABLE DELAY TIMING DIAGRAM - GLITCH FILTERING FOR EDGE DETECTOR OUTPUT
IN
Edge
Rising Edge Detector
Detector Output
Falling Edge Detector
Both Edge Detector
Both Edge Delay
Rising Edge Detector
Falling Edge Detector
Delayed Edge
Detector Output
Both Edge Detector
Both Edge Delay
Figure 97: Glitch Filtering for Edge Detector Output
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18 Voltage Reference
18.1 VOLTAGE REFERENCE OVERVIEW
The SLG46620-A has a Voltage Reference Macrocell to provide references to the six analog comparators. This macrocell can
supply a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally
supplied voltage references from pins 5, 7,10 and 14. The macrocell also has the option to output reference voltages on pins 18
and 19. See table below for the available selections for each analog comparator. Also see Figure 98 below, which shows the
reference output structure.
18.2 VREF SELECTION TABLE
Table 61: Vref Selection Table
registers
acmpxref_sel
[4:0]
11111
11110
ACMP0_Vref
DAC0_OUT
DAC1_OUT
ACMP1_Vref
DAC0_OUT
DAC1_OUT
ACMP2_Vref
DAC0_OUT
DAC1_OUT
ACMP3_Vref
DAC0_OUT
DAC1_OUT
ACMP4_Vref
DAC0_OUT
DAC1_OUT
ACMP5_Vref
DAC0_OUT
DAC1_OUT
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
11101
11100
11011
11010
mp0 / 2
mp0 / 2
mp2 / 2
mp2 / 2
mp2 / 2
mp5 / 2
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
mp1 / 2
mp1 / 2
mp1 / 2
mp1 / 2
mp1 / 2
mp1 / 2
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
mp0
mp0
mp2
mp2
mp2
mp5
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
Vref_ext_ac-
mp1
mp1
mp1
mp1
mp1
mp1
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
V
DD/4
VDD/4
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
VDD/4
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
VDD/4
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
VDD/4
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
VDD/4
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
VDD/3
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
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Table 61: Vref Selection Table
registers
acmpxref_sel
[4:0]
00001
00000
ACMP0_Vref
0.10
ACMP1_Vref
0.10
ACMP2_Vref
0.10
ACMP3_Vref
0.10
ACMP4_Vref
0.10
ACMP5_Vref
0.10
0.05
0.05
0.05
0.05
0.05
0.05
Table 62: Vref Range
VDD
Practical Vref Range Note
2.0 V - 3.6 V
1.7 V - 2.0V
50 mV ~ 1.2 V
50 mV ~ 1.1 V
Do not operate above 1.1 V
18.3 VREF BLOCK DIAGRAM
registers [896:892]
register [936]
External VDD
2.7 V - 3.6 V
ACMP0_Vref
ext_Vref_acmp5
(Pin5)
Pin19_aio_en
registers [1962:1961]=11
registers [901:897]
01
10
11
ext_Vref_acmp0
ext_Vref_acmp1
ACMP1_Vref
Vref Out_0 (Pin19)
OP
(Pin7)
registers [906:902]
ext_Vref_acmp0
ext_Vref_acmp1
ext_Vref_acmp2
ext_Vref_acmp3
ext_Vref_acmp4
ext_Vref_acmp5
registers [879:878]
ACMP2_Vref
Pin18_aio_en
registers [1955:1954]=11
01
10
11
registers [911:907]
Vref Out_1 (Pin18)
OP
(Pin10)
ACMP3_Vref
ext_Vref_acmp2
ext_Vref_acmp3
ext_Vref_acmp4
registers [916:912]
ACMP4_Vref
registers [877:876]
(Pin14)
VDD / 3
VDD / 4
DAC0
DAC1
registers [921:917]
Vref Out_0 is floating in case of registers[879:878]=00
Vref Out_1 is floating in case of registers[877:876]=00
ACMP5_Vref
Figure 98: Voltage Reference Block Diagram
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18.4 VREF OUT TYPICAL PERFORMANCE
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ꢂꢂꢁꢀ
ꢂꢂꢀꢀ
ꢂꢀꢁꢀ
ꢂꢀꢀꢀ
ꢉꢁꢀ
ꢉꢀꢀ
ꢈꢁꢀ
ꢈꢀꢀ
ꢇꢁꢀ
ꢇꢀꢀ
ꢆꢁꢀ
ꢆꢀꢀ
ꢁꢁꢀ
ꢁꢀꢀ
ꢅꢁꢀ
ꢅꢀꢀ
ꢄꢁꢀ
ꢄꢀꢀ
ꢃꢁꢀ
ꢃꢀꢀ
ꢂꢁꢀ
ꢂꢀꢀ
ꢁꢀ
Vref = 1200 mV
Vref = 800 mV
Vref = 600 mV
Vref = 300 mV
Vref = 100 mV
ꢀ
ꢀ8ꢀꢃ ꢀ8ꢀꢅ ꢀ8ꢀꢆ ꢀ8ꢀꢈ ꢀ8ꢂ ꢀ8ꢃ ꢀ8ꢅ ꢀ8ꢆ ꢀ8ꢈ
ꢂ
ꢃ
ꢅ
ꢆ
ꢈ
ꢂꢀ ꢃꢀ ꢅꢀ ꢆꢀ ꢈꢀ ꢂꢀꢀ ꢃꢀꢀ ꢅꢀꢀ ꢆꢀꢀ ꢈꢀꢀ ꢂꢀꢀꢀ ꢃꢀꢀꢀ
Load, uA
Figure 99: Typical Load Regulation, T = 25°C, VDD = 3.3 V
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19 Clocking
19.1 OSCILLATORS GENERAL DESCRIPTION
The SLG46620-A has three internal RC oscillators (25 kHz or 2 MHz, user selectable), as well as one Low-Frequency oscillator
(1.73 kHz) and one Ring oscillator (27 MHz).
There are two divider stages for the RC and Ring oscillators, one divider stage for the Low-Frequency oscillator, that gives the
user flexibility for introducing clock signals to connection matrix 0 and 1, as well as various other Macrocells. The pre-divider (first
stage) for RC Oscillator allows the selection of /1, /2, /4 or /8, for LF OSC - /1, /2, /4 or /16 and for Ring OSC - /1, /4, /8 or /16 to
divide down frequency from the fundamental. The second stage divider (does not apply for LF OSC) has an input of frequency
from the pre-divider, and outputs one of eight different frequencies on Connection Matrix Input lines [49] and [48]. The output of
LF OSC Pre-divider goes directly on Connection Matrix Input line [50]. Please see Figure 87, for more details on the SLG46620-
A clock scheme.
The Matrix Power-down function allows to switch on/off the oscillators using an external pin (register [1648] for 25 kHz / 2 MHz
OSC, register [1652] for LF OSC and register [1638] for Ring OSC):
Enable [1]. If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH
the oscillator will be turned off.
Disable [0]. Turns off the Matrix Power-down function.
The PWR CONTROL signal has the highest priority.
The user can select two OSC POWER MODEs (register [1649] for 25 kHz / 2 MHz OSC, register [1653] for LF OSC and register
[1640] for Ring OSC):
If FORCE POWER-ON [1] is selected, the OSC will run when the SLG46620-A is powered on.
If AUTO POWER-ON [0] is selected, the OSC will run only when any macrocell that uses OSC is powered on.
OSC can be turned on by:
Register control (force power-on)
Delay mode, when delay requires OSC
ADC
PWM/DCMP
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register [1642]
PWR DOWN
Matrix0_out84
en
registers [1644:1643]
registers [1647:1645]
1/2/4/3/8/12/24/64
1/2/4/3/8/12/24/64
cko
cko
divs
cki
Matrix IN0_49
register [1637]
RC OSC
(2 MHz,
25kHz)
en
DIV1/2/4/8
registers [1632:1630]
Matrix IN0_48
Matrix IN0_50
divs
cki
registers [2:0]
0
Cnt_end0 used as the wake/
shared with
wake/sleep
oscillator
sleep signal to matrix in
registers [1655:1654]
DIV4
DIV24
DIV64
1
2
3
4
5
6
7
LF OSC
(1.73 kHz)
CNT/ DLY
DIV1/2/4/16
cnt(x-1)_end
cnt_end
clk
Matrix OUT
CNT0/CNT1/CNT3/CNT5/CNT6/CNT7
Matrix0_72 for CNT0/CNT2/CNT9/
Matrix0_73 for CNT5/CNT6
Matrix1_73 for CNT7/CNT8/PWM/ADC
Matrix1_74 for CNT1/CNT3/CNT4
registers[3:0]
0
CNT/
DLY/
FSM/
DIV4
DIV12
DIV24
1
2
3
4
5
DIV64
PWM_ramp
cnt(x-1)_end
clk
6
7
8
DIV8
CLK_SPI_SCK
9
Matrix Out0_83
10
11
12
DIV256
CNT2/CNT4/CNT8/CNT9
register [1675] /
register [1696] /
register [1716]
Regulator
(1.8 V)
PWM/
1
0
DCMP/
CLK_RINGOSC
clk
Ring OSC
(27 MHz)
DIV1/4/8/16
0
PWM0/PWM1/PWM2/
1
2
3
registers [1636:1635]
DIV16
0
ADC
CLK_ADC
CLK
1
register [1639]
Figure 100: Oscillator Block Diagram
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19.2 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 101: Oscillator Startup Diagram
Note 1 OSC power mode: “Auto Power-On”.
Note 2 “OSC Enable” signal appears when any macrocell that uses OSC is powered on.
Note 3 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
Figure 102: LF Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, OSC = 1.73 kHz
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1300
1200
1100
1000
900
800
1.71
3
3.3
3.6
VDD (V)
Figure 103: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, RC OSC = 2 MHz
Figure 104: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, RC OSC = 25 kHz
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280
260
240
220
200
180
160
140
1.71
3
3.3
3.6
VDD (V)
Figure 105: Ring Oscillator Maximum Power-On Delay vs. VDD at T = 25°C, OSC = 27 MHz
19.3 OSCILLATORS ACCURACY
Note calculations based on HTOL drift data obtained through AEC-Q100 stress tests.
Figure 106: RC Oscillator Frequency vs. VDD, RC OSC = 25 kHz, T = 25 °C
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Figure 107: RC Oscillator Frequency vs. VDD, RC OSC = 25 kHz, T = -40 °C to 105 °C
Figure 108: Ring Oscillator Frequency vs. VDD, OSC = 27 MHz, T = 25 °C
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Figure 109: Ring Oscillator Frequency vs. VDD, OSC = 27 MHz, T = -40 °C to 105 °C
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20 Power-On Reset
The SLG46620-A has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IO pins.
20.1 GENERAL OPERATION
The SLG46620-A is guaranteed to be powered down and non-operational when the VDD voltage (voltage on PIN1) is less than
Power-Off Threshold (see in Section 3.4), but not less than -0.6 V. Another essential condition for the chip to be powered down
is that no voltage higher (Note) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a
voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG46620-A, the voltage applied on the VDD should be higher than the Power_ON threshold
(Note 1). The full operational VDD range for the SLG46620-A is 1.71V – 3.6V (1.8 V ±5% - 3.3 V±10%). This means that the VDD
voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises
to the Power_ON threshold. After the POR sequence has started, the SLG46620-A will have a typical period of time to go through
all the steps in the sequence (see Figure 96 and Figure 97), and will be ready and completely operational after the POR sequence
is complete.
Note 1: The Power_ON threshold is defined in Section 3.4.
Note 2: VDD ramp rising speed must be less than 0.6 V/µs after power-on. Violating this specification may cause chip to restart.
To power-down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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20.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 110.
VDD
t
POR_NVM
(reset for NVM)
t
t
t
t
t
t
t
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 110: POR sequence
As can be seen from Figure 110 after the VDD has start ramping up and crosses the Power_ON threshold, first, the on-chip NVM
memory is reset. Next the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC, DFFs,
Latches and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes
from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to
active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence).
20.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46620-A operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 111 describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high
impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also
output LOW. Only P DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.
Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal
switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.
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VDD
Guaranteed HIGH before POR_GPI
t
VDD_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Unpredictable
t
t
Input PIN_out
to matrix
Determined by External Signal
Determined by Input signals
LUT_out
to matrix
Determined by input signals
OUT = IN without Delay
t
t
t
t
t
t
t
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
Prog. Edge_Detector_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
Determined by initial state
DFF/Latch_out
to matrix
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Ext. GPO
Tri-state
Determined by input signals
Figure 111: Internal Macrocell States during POR sequence
20.4 INITIALIZATION
All internal macrocells by default have initial low level. Starting from indicated powerup time of 1.15 V - 1.6 V, macrocells in
SLG46620-A are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then
the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. Input pins, ACMP, Pull-up/down.
2. LUTs.
3. DFFs, Delays/Counters, Pipe Delay.
4. POR output to matrix.
5. Output pin corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin →
VDD and pin → GND on each pin. So if the input signal applied to pin is higher than VDD, then current will sink through the diode
to VDD. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following the voltage on the input
pin.There is no effect from input pin when input voltage is applied at the same time as VDD
.
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20.5 POWER-DOWN
VDD (V)
2 V
1.6 V
1.15 V
1 V Vref OUT Signal
1 V
Time
Not guaranteed output state
Figure 112: Power-Down
During powerdown, macrocells in SLG46620-A are powered off after VDD falling down below Power-Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state during this time.
20.6 EXTERNAL RESET
The SLG46620-A has an optional External Reset function on Pin2. It allows to reset the chip while powered on.
Pin2 must be configured as Digital Input registers [942:941] and function Reset must be enabled also, register [2020]: 0 - disabled,
1 - enabled. Unlike POR, External Reset affects only GPI, LUTs, DLY, RC OSC, DFFs, Latchs, Pipe Delay, Matrix and GPO. While
NVM remains its previous state, see Figure 113 to Figure 115.
Note: External Reset affects Pipe Delay only if its nRST is connected to POR.
Note that during External Reset the output pin's status will depend on the OE control circuits and current consumption is
determined by the design.
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External Reset
(
high active)
VDD
t
t
t
t
t
t
t
t
POR_NVM
(reset for NVM)
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 113: External Reset Sequence (High Active).
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External Reset
(
rising edge detect)
t
t
VDD
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
(reset for input enable)
t
POR_LUT
(reset for LUT output)
t
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
t
POR_OUT
(generate low to high
t
POR_GPO
(reset for output en-
t
Figure 114: External Reset Sequence (Rising Edge Detect).
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External Reset
(
falling edge detect)
t
t
VDD
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
(reset for input enable)
t
POR_LUT
(reset for LUT output)
t
POR_CORE
reset for DLY/RCO/DFF
/LATCH/Pipe DLY
t
POR_OUT
(generate low to high
t
POR_GPO
(reset for output en-
t
Figure 115: External Reset Sequence (Falling Edge Detect).
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21 Power Detector
The Power Detect (PWR DET) is used to monitor the state of the internal Charge Pump regulator. The macrocell only has one
output (OUT). The PWR DET output is HIGH when VDD < 2.7V and LOW when VDD > 2.7V. In order to use the macrocell
register[2010] must be set to 0.
22 Additional Logic Functions
The SLG46620-A has two additional logic functions that are connected directly to the Connection Matrix inputs and outputs. There
are two inverters which can switch the polarity of any Connection Matrix signal.
22.1 INV_0 GATE
INV_0 Gate
From Connection Matrix0 Output [55]
To Connection Matrix0 Input [23]
Figure 116: INV_0 Gate
22.2 INV_1 GATE
INV_1 Gate
From Connection Matrix1 Output [55]
To Connection Matrix1 Input [23]
Figure 117: INV_1 Gate
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23 Register Definitions
23.1 REGISTER MAP
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
5:0
Matrix 0 OUT: In0 of LUT2_0
Matrix 0 OUT: In1 of LUT2_0
Matrix 0 OUT: In0 of LUT2_1
Matrix 0 OUT: In1 of LUT2_1
Matrix 0 OUT: In0 of LUT2_2
Matrix 0 OUT: In1 of LUT2_2
Matrix 0 OUT: In0 of LUT2_3
Matrix 0 OUT: In1 of LUT2_3
Matrix 0 OUT: In0 of LUT3_0
Matrix 0 OUT: In1 of LUT3_0
Matrix 0 OUT: In2 of LUT3_0
Matrix 0 OUT: In0 of LUT3_1
Matrix 0 OUT: In1 of LUT3_1
Matrix 0 OUT: In2 of LUT3_1
Matrix 0 OUT: In0 of LUT3_2
Matrix 0 OUT: In1 of LUT3_2
Matrix 0 OUT: In2 of LUT3_2
Matrix 0 OUT: In0 of LUT3_3
Matrix 0 OUT: In1 of LUT3_3
Matrix 0 OUT: In2 of LUT3_3
Matrix 0 OUT: In0 of LUT3_4
Matrix 0 OUT: In1 of LUT3_4
Matrix 0 OUT: In2 of LUT3_4
Matrix 0 OUT: In0 of LUT3_5
Matrix 0 OUT: In1 of LUT3_5
Matrix 0 OUT: In2 of LUT3_5
Matrix 0 OUT: In0 of LUT3_6
Matrix 0 OUT: In1 of LUT3_6
Matrix 0 OUT: In2 of LUT3_6
Matrix 0 OUT: In0 of LUT3_7
Matrix 0 OUT: In1 of LUT3_7
Matrix 0 OUT: In2 of LUT3_7
Matrix 0 OUT: In0 of LUT4_0
Matrix 0 OUT: In1 of LUT4_0
Matrix 0 OUT: In2 of LUT4_0 or PGEN CLK
Matrix 0 OUT: In3 of LUT4_0 or PGEN nRST
Matrix 0 OUT: nSET or nRST of DFF0/Latch0
Matrix 0 OUT: Data of DFF0/Latch0
Matrix 0 OUT: Clock of DFF0/Latch0
Matrix 0 OUT: nSET or nRST of DFF1/Latch1
11:6
17:12
23:18
29:24
35:30
41:36
47:42
53:48
59:54
65:60
71:66
77:72
83:78
89:84
95:90
101:96
107:102
113:108
119:114
125:120
131:126
137:132
143:138
149:144
155:150
161:156
167:162
173:168
179:174
185:180
191:186
197:192
203:198
209:204
215:210
221:216
227:222
233:228
239:234
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
245:240
251:246
257:252
263:258
269:264
275:270
281:276
287:282
293:288
299:294
305:300
311:306
317:312
323:318
Matrix 0 OUT: Data of DFF1/Latch1
Matrix 0 OUT: Clock of DFF1/Latch1
Matrix 0 OUT: nSET or nRST of DFF2/Latch2
Matrix 0 OUT: Data of DFF2/Latch2
Matrix 0 OUT: Clock of DFF2/Latch2
Matrix 0 OUT: Data of DFF3/Latch3
Matrix 0 OUT: Clock of DFF3/Latch3
Matrix 0 OUT: Data of DFF4/Latch4
Matrix 0 OUT: Clock of DFF4/Latch4
Matrix 0 OUT: Data of DFF5/Latch5
Matrix 0 OUT: Clock of DFF5/Latch5
Matrix 0 OUT: Clock of Pipe Delay 0
Matrix 0 OUT: Input Data of Pipe Delay 0
Matrix 0 OUT: Reset of Pipe Delay 0
Matrix 0 OUT: Input of Edge Detector and Programma-
ble Delay 0
329:324
335:330
341:336
347:342
353:348
359:354
365:360
371:366
377:372
383:378
389:384
395:390
401:396
407:402
413:408
419:414
425:420
431:426
Matrix 0 OUT: Input of Inverter 0
Matrix 0 OUT: Digital Output of PIN 3
Matrix 0 OUT: OE of PIN 3
Matrix 0 OUT: Digital Output of PIN 4
Matrix 0 OUT: Digital Output of PIN 5
Matrix 0 OUT: OE of PIN 5
Matrix 0 OUT: Digital Output of PIN 6
Matrix 0 OUT: Digital Output of PIN 7
Matrix 0 OUT: OE of PIN 7
Matrix 0 OUT: Digital Output of PIN 8
Matrix 0 OUT: Digital Output of PIN 9
Matrix 0 OUT: OE of PIN 9
Matrix 0 OUT: Digital Output of PIN 10
Matrix 0 OUT: OE of PIN 10
Matrix 0 OUT: PDB (Power-down) for ACMP0
Matrix 0 OUT: PDB (Power-down) for ACMP4
Matrix 0 OUT: PDB (Power-down) for ACMP5
Matrix 0 OUT: CNT0/CNT2/CNT9/ External
Clock(CLK_Matrix0)
437:432
443:438
Matrix 0 OUT: CNT5/CNT6 External Clock(CLK_Ma-
trix1)
449:444
455:450
461:456
467:462
473:468
479:474
Matrix 0 OUT: Input of DLY/CNT0
Matrix 0 OUT: Input of DLY/CNT2
Matrix 0 OUT: Keep of DLY/CNT2
Matrix 0 OUT: Up of DLY/CNT2
Matrix 0 OUT: Input of DLY/CNT5
Matrix 0 OUT: Input of DLY/CNT6
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
485:480
491:486
497:492
503:498
509:504
515:510
521:516
527:522
533:528
539:534
545:540
551:546
557:552
563:558
569:564
575:570
Matrix 0 OUT: Input of DLY/CNT9
Matrix 0 OUT: ADC Power-down
Matrix 0 OUT: CSB of SPI
Matrix 0 OUT: SCLK of SPI
Matrix 0 OUT: Oscillator Power-down
Matrix 0 OUT: Cross Connection Output to Matrix 1 [0]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [1]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [2]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [3]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [4]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [5]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [6]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [7]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [8]
Matrix 0 OUT: Cross Connection Output to Matrix 1 [9]
Reserved
LUT Data
579:576
583:580
587:584
591:588
599:592
607:600
615:608
623:616
631:624
639:632
647:640
655:648
LUT2_0 Data
LUT2_1 Data
LUT2_2 Data
LUT2_3 Data
LUT3_0 Data
LUT3_1 Data
LUT3_2 Data
LUT3_3 Data
LUT3_4 Data
LUT3_5 Data
LUT3_6 Data
LUT3_7 Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
LUT4_0 and PGEN
671:656
675:672
LUT4_0 & PGEN Data
Data
Data
4-bit counter Data in PGEN
0: LUT4 Function
1: PGEN Function
676
PGEN Enable Signal
DFF/LATCH 0
0: DFF Function
1: LATCH Function
677
Mode Select
0: Q Output
1: nQ Output
678
679
680
Output Parity Control
nSET or nRST Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
DFF/LATCH 1
0: DFF Function
1: LATCH Function
681
682
683
684
Mode Select
0: Q Output
1: nQ Output
Output Parity Control
Set or Reset Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 2
0: DFF Function
1: LATCH Function
685
Mode Select
0: Q Output
1: nQ Output
686
687
688
Output Parity Control
Set or Reset Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 3
0: DFF Function
1: LATCH Function
689
Mode Select
0: Q Output
1: nQ Output
690
691
Output Parity Control
Initial State During POR
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 4
0: DFF Function
1: LATCH Function
692
Mode Select
0: Q Output
1: nQ Output
693
694
Output Parity Control
Initial State During POR
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 5
0: DFF Function
1: LATCH Function
695
Mode Select
0: Q Output
1: nQ Output
696
697
Output Parity Control
Initial State During POR
0: Initial State is 0
1: Initial State is 1
LUT Data
701:698
705:702
709:706
713:710
721:714
729:722
LUT2_4 Data
LUT2_5 Data
LUT2_6 Data
LUT2_7 Data
LUT3_8 Data
LUT3_9 Data
Data
Data
Data
Data
Data
Data
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
737:730
745:738
753:746
761:754
769:762
777:770
793:778
LUT3_10 Data
LUT3_11 Data
LUT3_12 Data
LUT3_13 Data
LUT3_14 Data
LUT3_15 Data
LUT4_1 Data
Data
Data
Data
Data
Data
Data
Data
DFF/LATCH 6
0: DFF Function
1: LATCH Function
794
Mode Select
0: Q Output
1: nQ Output
795
796
797
Output Parity Control
Set or Reset Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 7
0: DFF Function
1: LATCH Function
798
Mode Select
0: Q Output
1: nQ Output
799
800
801
Output Parity Control
Set or Reset Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 8
0: DFF Function
1: LATCH Function
802
Mode Select
0: Q Output
1: nQ Output
803
804
805
Output Parity Control
Set or Reset Selection
Initial State During POR
0: Reset State by Matrix
1: Set State by Matrix
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 9
0: DFF Function
1: LATCH Function
806
Mode Select
0: Q Output
1: nQ Output
807
808
Output Parity Control
Initial State During POR
0: Initial State is 0
1: Initial State is 1
DFF/LATCH 10
0: DFF Function
1: LATCH Function
809
Mode Select
0: Q Output
1: nQ Output
810
Output Parity Control
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0: Initial State is 0
1: Initial State is 1
811
Initial State During POR
DFF/LATCH 11
0: DFF Function
1: LATCH Function
812
Mode Select
0: Q Output
1: nQ Output
813
814
Output Parity Control
Initial State During POR
0: Initial State is 0
1: Initial State is 1
ADC and ACMP Control
0: Disable
1: Enable
815
816
817
ADC Native Input From Internal DAC0
0: Disable (PIN 16 can not Control)
1: Enable
Multichannel Input MUX Enable (State by PIN 16)
ADC Input Mode Control
0: Single-Ended Input
1: Differential Input
000: Reserved
001: 0.5x (For single-ended operation only)
010: 1x
011: 2x
820:818
ADC PGA Gain Selection
100: 4x (For single-ended and differential operation)
101: 8x (For single-ended and differential operation)
110: 16x (For differential operation only)
111: Reserved
PGA Power-On Signal
Note: in ADC Wake Sleep/dynamic On/Off Mode, it
should Set to 0
0: Power-Down
1: Power-On
821
0: Disable
1: Enable
822
830:823
831
ADC Pseudo-Differential Mode Enable
DAC1 8 Bit register Control
00: DAC1 Output is ADC Vref bottom Voltage
FF: DAC1's Output is ADC Vref top Voltage
0: Disable
1: Enable
ACMP 1 Input 100u Current Source Enable
0: Disable
1: Enable
832
ACMP 0 Input 100u Current Source Enable
Reserved
833
0: Power-down
834
835
DAC1 Power-On Signal
Reserved
1: Power-On When DAC0 Used Only, need set this
bit
00: 1 K
01: 5 K
10: 20 K
11: 50 K
837:836
839:838
ACMP Buffer Bandwidth Selection
ADC Speed Selection
00: Reserved
01: Reserved
10: 100 kHz
11: Reserved
Datasheet
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0: Power-down
840
DAC0 Power-On Signal
1: Power-On When DAC0 Used Only, need set this
bit
00: ADC Vref
01: Reserved10: 1/4 VDD
11: None
842:841
843
ADC Vref Source Select
DAC0 Input Selection
0: From Register
1: From DCMP1's Negative Input
00: DAC0 Output is 0
FF: DAC0 Output is 1 V
851:844
852
DAC0 8 Bit Register Control
Reserved
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
854:853
856:855
858:857
860:859
ACMP 0 Positive Input Gain Control
ACMP 0 Input Selection
00: PIN 6 Input
01: With Buffer
10: VDD
11: None
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
ACMP 1 Positive Input Gain Control
ACMP 1 Input Selection
00: PIN 12 Input
01: ADC PGA OUT
10: ACMP 0 Input (before Gain)
11: None
861
862
Reserved
Reserved
0: PIN 13 Input
1: ACMP 0 Input (before Gain)
863
ACMP 2 Input Selection
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
865:864
866
ACMP 2 Positive Input Gain Control
Reserved
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
868:867
ACMP 3 Positive Input Gain Control
00: PIN 15 Input
01: PIN 13 Input
10: ACMP 0 Input (before Gain)
11: None
870:869
872:871
ACMP 3 Input Selection
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
ACMP 4 Positive Input Gain Control
Datasheet
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: PIN 3 Input
01: PIN 15 Input
10: ACMP 0 Input (before Gain)
11: None
874:873
875
ACMP 4 Input Selection
Reserved
00: Buffer Power-down
01: ACMP 2' Input
10: ACMP 3's Input
11: DAC1's Output
877:876
Output Buffer1 Source Selection
00: Buffer Power-down
01: ACMP 0' Input
10: ACMP 1's Input
11: DAC0's Output
879:878
Output Buffer0 Source Selection
880
881
Reserved
Reserved
Reserved
0: Disable
1: Enable
882
883
884
885
886
ADC Wake Sleep Enable
DAC1 Input Selection
0: From DCMP1's Negative input
1: From Register
0: Disable
1: Enable
ADC Wake Sleep Enable
Force ADC Analog Circuit On
PGA Output Enable
0: Disable
1: Enable
0: Disable
1: Enable
BG, ACMP and Vref
891:887 Reserved
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
896:892
ACMP0 Vref Value Selection
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP0
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP0 / 2
11110: DAC1_OUT
11111: DAC0_OUT
Datasheet
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
901:897
906:902
911:907
ACMP1 Vref Value Selection
ACMP2 Vref Value Selection
ACMP3 Vref Value Selection
10100: 1.05 V
10110: 11.5 V
11000: VDD/3
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP0
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP0 / 2
11110: DAC1_OUT
11111: DAC0_OUT
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP2
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP2 / 2
11110: DAC1_OUT
11111: DAC0_OUT
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP2
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP2 / 2
11110: DAC1_OUT
11111: DAC0_OUT
Datasheet
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
916:912
ACMP4 Vref Value Selection
10100: 1.05 V
10110: 1.15 V
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11000: VDD
3
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP2
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP2 / 2
11110: DAC1_OUT
11111: DAC0_OUT
00000: 50 mV
00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
921:917
ACMP5 Vref Value Selection
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: Vref_Ext_ACMP1
11011: Vref_Ext_ACMP5
11100: Vref_Ext_ACMP1 / 2
11101: Vref_Ext_ACMP5 / 2
11110: DAC1_OUT
11111: DAC0_OUT
Reserved
922
923
Bangap OK for ADC, ACMP Output Delay Time Select, 0: 550 us
the start Time is porb_core go to High
ACMP5 Hysteresis Control
1: 100 us
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
925:924
927:926
929:928
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
ACMP4 Hysteresis Control
ACMP3 Hysteresis Control
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
Datasheet
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
931:930
933:932
ACMP2 Hysteresis Control
ACMP1 Hysteresis Control
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
935:934
936
ACMP0 Hysteresis Control
0: Turn Off
Bandgap Turn On by Register
1: Turn On (if chip is Power-down, the Bandgap will
Power-down even if it is set to 1)
937
938
939
Reserved
Reserved
Reserved
IO Pad
940
0: Disable
1: Enable
IO pre-Charge Enable Bit
PIN2 Input Mode Control
PIN 2
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Reserved
942:941
00: Floating
01: 10 K
10: 100 K
944:943
945
PIN2 Pull-Up/Down Resistor Selection
PIN2 Pull-Up Resistor Enable
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 3
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Analog IO
947:946
949:948
PIN 3 Input Mode Control
PIN 3 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
951:950
952
PIN 3 Pull-Up/Down Resistor Selection
PIN 3 Pull-Up Resistor Enable
0: Pull-Down
1: Pull-Up
Datasheet
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
PIN 4
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
955:953
PIN 4 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
957:956
PIN 4 Pull-Up/Down Resistor Selection
0: Pull-Down
1: Pull-Up
958
959
PIN 4 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 4 Output Driver Current double
PIN 5
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Analog IO
961:960
963:962
PIN 5 Input Mode Control
PIN 5 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
965:964
966
PIN 5 Pull-Up/Down Resistor Selection
PIN 5 Pull-Up Resistor Enable
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 6
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
969:967
PIN 6 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
971:970
PIN 6 Pull-Up/Down Resistor Selection
11: 1 M
0: Pull-Down
1: Pull-Up
972
973
PIN 6 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 6 Output Driver Current double
PIN 7
Datasheet
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SLG46620-A
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Analog IO
975:974
977:976
PIN 7 Input Mode Control
PIN 7 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
979:978
980
PIN 7 Pull-Up/Down Resistor Selection
PIN 7 Pull-Up Resistor Enable
0: Pull-Down
1: Pull-Up
PIN 8
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
983:981
PIN 8 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
985:984
PIN 8 Pull-Up/Down Resistor Selection
0: Pull-Down
1: Pull-Up
986
987
PIN 8 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 8 Output Driver Current double
PIN 9
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Analog IO
989:988
991:990
PIN 9 Input Mode Control
PIN 9 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
993:992
994
PIN 9 Pull-Up/Down Resistor Selection
PIN 9 Pull-Up Resistor Enable
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 10
00: Digital in without Schmitt trigger
01: Digital in with Schmitt trigger
10: Low Voltage Digital IN
11: Analog IO
996:995
PIN 10 Input Mode Control
Datasheet
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SLG46620-A
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Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
998:997
PIN 10 Output Mode Control
00: Floating
01: 10 K
10: 100 K
1000:999
1001
PIN 10 Pull-Up/Down Resistor Selection
PIN 10 Pull-Up Resistor Enable
11: 1 M
0: Pull-Down
1: Pull-Up
0: Disable
1: Enable
1002
PIN 10 4x Drive Enable
Reserved
1015:1003
1023:1016
Reserved
Die ID:
Power up Sequence Bits
Data
Hex: 5A
Matrix 1 Output Selection
Matrix 1 OUT:In0 of LUT2_4
1029:1024
1035:1030
1041:1036
1047:1042
1053:1048
1059:1054
1065:1060
1071:1066
1077:1072
1083:1078
1089:1084
1095:1090
1101:1096
1107:1102
1113:1108
1119:1114
1125:1120
1131:1126
1137:1132
1143:1138
1149:1144
1155:1150
1161:1156
1167:1162
1173:1168
1179:1174
1185:1180
1191:1186
Matrix 1 OUT:In1 of LUT2_4
Matrix 1 OUT:In0 of LUT2_5
Matrix 1 OUT:In1 of LUT2_5
Matrix 1 OUT:In0 of LUT2_6
Matrix 1 OUT:In1 of LUT2_6
Matrix 1 OUT:In0 of LUT2_7
Matrix 1 OUT:In1 of LUT2_7
Matrix 1 OUT:In0 of LUT3_8
Matrix 1 OUT:In1 of LUT3_8
Matrix 1 OUT:In2 of LUT3_8
Matrix 1 OUT:In0 of LUT3_9
Matrix 1 OUT:In1 of LUT3_9
Matrix 1 OUT:In2 of LUT3_9
Matrix 1 OUT:In0 of LUT3_10
Matrix 1 OUT:In1 of LUT3_10
Matrix 1 OUT:In2 of LUT3_10
Matrix 1 OUT:In0 of LUT3_11
Matrix 1 OUT:In1 of LUT3_11
Matrix 1 OUT:In2 of LUT3_11
Matrix 1 OUT:In0 of LUT3_12
Matrix 1 OUT:In1 of LUT3_12
Matrix 1 OUT:In2 of LUT3_12
Matrix 1 OUT:In0 of LUT3_13
Matrix 1 OUT:In1 of LUT3_13
Matrix 1 OUT:In2 of LUT3_13
Matrix 1 OUT:In0 of LUT3_14
Matrix 1 OUT:In1 of LUT3_14
Datasheet
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© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
1197:1192
1203:1198
1209:1204
1215:1210
1221:1216
1227:1222
1233:1228
1239:1234
1245:1240
1251:1246
1257:1252
1263:1258
1269:1264
1275:1270
1281:1276
1287:1282
1293:1288
1299:1294
1305:1300
1311:1306
1317:1312
1323:1318
1329:1324
1335:1330
1341:1336
1347:1342
Matrix 1 OUT:In2 of LUT3_14
Matrix 1 OUT:In0 of LUT3_15
Matrix 1 OUT:In1 of LUT3_15
Matrix 1 OUT:In2 of LUT3_15
Matrix 1 OUT:In0 of LUT4_1
Matrix 1 OUT:In1 of LUT4_1
Matrix 1 OUT:In2 of LUT4_1
Matrix 1 OUT:In3 of LUT4_1
Matrix 1 OUT: Set or nRST of DFF6/Latch6
Matrix 1 OUT: Data of DFF6/Latch6
Matrix 1 OUT: Clock of DFF6/Latch6
Matrix 1 OUT: Set or nRST of DFF7/Latch7
Matrix 1 OUT: Data of DFF7/Latch7
Matrix 1 OUT: Clock of DFF7/Latch7
Matrix 1 OUT: Set or nRST of DFF8/Latch8
Matrix 1 OUT: Data of DFF8/Latch8
Matrix 1 OUT: Clock of DFF8/Latch8
Matrix 1 OUT: Data of DFF9/Latch9
Matrix 1 OUT: Clock of DFF9/Latch9
Matrix 1 OUT: Data of DFF10/Latch10
Matrix 1 OUT: Clock of DFF10/Latch10
Matrix 1 OUT: Data of DFF11/Latch11
Matrix 1 OUT: Clock of DFF11/Latch11
Matrix 1 OUT: Clock of Pipe Delay 1
Matrix 1 OUT: Input Data of Pipe Delay 1
Matrix 1 OUT: Reset of Pipe Delay 1
Matrix 1 OUT: Input of Edge Detector and Programma-
ble Delay 1
1353:1348
1359:1354
1365:1360
1371:1366
1377:1372
1383:1378
1389:1384
1395:1390
1401:1396
1407:1402
1413:1408
1419:1414
1425:1420
1431:1426
1437:1432
Matrix 1 OUT: Input of Inverter 1
Matrix 1 OUT: Digital Output of PIN 12
Matrix 1 OUT: Digital Output of PIN 13
Matrix 1 OUT: OE of PIN 13
Matrix 1 OUT: Digital Output of PIN 14
Matrix 1 OUT: OE of PIN 14
Matrix 1 OUT: Digital Output of PIN 15
Matrix 1 OUT: Digital Output of PIN 16
Matrix 1 OUT: OE of PIN 16
Matrix 1 OUT: Digital Output of PIN 17
Matrix 1 OUT: Digital Output of PIN 18
Matrix 1 OUT: OE of PIN 18
Matrix 1 OUT: Digital Output of PIN 19
Matrix 1 OUT: OE of PIN 19
Datasheet
16-Mar-2020
Revision 3.3
163 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
1443:1438
1449:1444
1455:1450
1461:1456
Matrix 1 OUT: Digital Output of PIN 20
Matrix 1 OUT: PDB(Power-down) for ACMP1
Matrix 1 OUT: PDB(Power-down) for ACMP2
Matrix 1 OUT: PDB(Power-down) for ACMP3
Matrix 1 OUT:CNT7/CNT8/PWM/ADC External Clock
(CLK_Matrix2)
1467:1462
1473:1468
Matrix 1 OUT:CNT1/CNT3/CNT4 External Clock
(CLK_Matrix3)
1479:1474
1485:1480
1491:1486
1497:1492
1503:1498
1509:1504
1515:1510
1521:1516
Matrix 1 OUT: Input of DLY/CNT1
Matrix 1 OUT: Input of DLY/CNT3
Matrix 1 OUT: Input of DLY/CNT4
Matrix 1 OUT: Keep of DLY/CNT4
Matrix 1 OUT: Up of DLY/CNT4
Matrix 1 OUT: Input of DLY/CNT7
Matrix 1 OUT: Input of DLY/CNT8
Matrix 1 OUT: PWM Power-down
Matrix 1 OUT: PWM/DCMP0 Positive Input and PWM/
DCMP1 Negative Input Register Selection Bit 0
1527:1522
1533:1528
Matrix 1 OUT: PWM/DCMP0 Positive Input and PWM/
DCMP1 Negative Input Register Selection Bit 1
1539:1534
1545:1540
1551:1546
1557:1552
1563:1558
1569:1564
1575:1570
1581:1576
1587:1582
1593:1588
1599:1594
Matrix 1 OUT: Cross Connection Output to Matrix 0 [0]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [1]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [2]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [3]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [4]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [5]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [6]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [7]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [8]
Matrix 1 OUT: Cross Connection Output to Matrix 0 [9]
Reserved
Programmable Delay with Edge Detector 0
00: Rising Edge Detect
01: Falling Edge Detect
10: Both Edge Detect
11: Both Edge Delay
1601:1600
Mode Selection
00: 110 ns Delay
01: 220 ns Delay
10: 330 ns Delay
11: 440 ns Delay
1603:1602
1604
Delay Time Selection
Output Delay Control
0: Output no Delay
1: Output Delay
Datasheet
16-Mar-2020
Revision 3.3
164 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
Programmable Delay with Edge Detector 1
00: Rising Edge Detect
01: Falling Edge Detect
10: Both Edge Detect
11: Both Edge Delay
1606:1605
Mode Selection
00: 110 ns Delay
01: 220 ns Delay
10: 330 ns Delay
11: 440 ns Delay
1608:1607
1609
Delay Time Selection
Output Delay Control
0: Output No Delay
1: Output Delay
Pipe Delay 0
Register Bits From 0 to 15, Data Delay From 1 to 16
pipes
1613:1610
OUT0 Selection Bits
Register Bits From 0 to 15, Data Delay From 1 to 16
pipes
1617:1614
1618
OUT1 Selection Bits
0: non-inverted
1: inverted
OUT1 Output polarity Control
Pipe Delay 1
Register Bits From 0 to 15, Data Delay From 1 to 16
pipes
1622:1619
OUT0 Selection Bits
Register Bits From 0 to 15, Data Delay From 1 to 16
pipes
1626:1623
OUT1 Selection Bits
0: non-inverted
1: inverted
1627
OUT1 Output polarity Control
Oscillator
00: RING OSC
01: Matrix(Matrix1_OUT73)
10: RC OSC
11: SPI_SCLK(Matrix0_OUT83)
1629:1628
1632:1630
PWM and ADC Clock Source Select
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
Clock divide Ratio Control for ring OSC to Matrix
0: Disable
1: Enable
1633
1634
PWM Data synchronized with SPI Clock Enable
FSM Data synchronized with SPI Clock Enable
0: Disable
1: Enable
00: /1
01: /4
10: /8
11: /16
1636:1635
Clock divide Ratio Control for RING OSC
Ring OSC Clock to Matrix Input Enable
0: Disable
1: Enable
1637
1638
Matrix Power-down (Matrix0_OUT84) enable for ring 0: Disable
Oscillator 1: Enable
Datasheet
16-Mar-2020
Revision 3.3
165 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0: Non-Bypass
1: Bypass
1639
ADC Clock divide by 16 Bypass
Ring OSC Turn On by Register
Note: if chip is Powered Down, the Ring OSC will Power-
down even if this bit is set to 1
0: Turn Off
1: Turn On
1640
0: Disable
1: Enable
1641
1642
ADC Data synchronized with SPI Clock Enable
RC OSC Clock to Matrix Input Enable
0: Disable
1: Enable
00: /1
01: /2
10: /4
11: /8
1644:1643
Clock divide Ratio Control for RC OSC
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
1647:1645
Clock divide Ratio Control for RC OSC to Matrix
Matrix Power-down (Matrix0_OUT84) enable for RC
Oscillator
0: Disable
1: Enable
1648
1649
RC OSC Turn On by Register
Note: if chip is Powered Down, the Ring OSC will Power-
down even if this Bit is Set to 1
0: Turn Off
1: Turn On
0: 25 kHz
1: 2 MHz
1650
1651
1652
RC OSC frequency Select
bypass RC oscillator with external clock(matrix-
_OUT1_73)
0: RC OSC
1: external clock
matrix power-down (matrix0_OUT84) enable for LF os- 0: Disable
cillator
1: Enable
0: Turn Off
1653
Low Frequency OSC turn on by register
1: Turn On (if chip is Power-down, the LF OSC will
Power-down even if it is Set to 1)
00: /1
01: /2
10: /4
11: /16
1655:1654
Clock divide Ratio Control for LF OSC
SPI
1656
1657
SPI Used as ADC Buffer Enable (1 Clock Delayed)
SPI Parallel Input Data Source Selection
0: FSM0[7:0], FSM1[7:0]
1: ADC
1658
1659
SPI Clock phase (CPHA)
SPI Clock polarity (CPOL)
0: 16 bits
1: 8-bits (least significant 8 Bits)
1660
1661
byte Selection
0: Serial IN Parallel OUT
1: Parallel IN Serial OUT
SPI Input/Output Mode Selection
PWM0
Datasheet
16-Mar-2020
Revision 3.3
166 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
Register 3, 8 Bits NVM Data to PWM/DCMP or DAC
Input
1669:1662
1672:1670
Data
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
PWM0 Dead Band zone Control
0: PWM Output duty cycle Down to 0% and DCMP
OUT=1 if IN+ > IN-
1: PWM Output duty cycle up to 100% and DCMP
OUT=1 if IN+ >= IN-
1673
1674
PWM/DCMP0 Mode Selection
PWM/DCMP0 Function Selection
0: PWM
1: DCMP When in PWM Mode, OUTN0 is pwm1's
Negative output When in DCMP Mode, OUTN0 is
DCMP1's match Output
0: Clock From MUX State by registers [1629:1628]
1: Matrix1_73
1675
1676
PWM/DCMP0 Clock Source Selection
PWM/DCMP0 Clock Inversion
0: Disable
1: Enable
0: power-down is not synchronized with clock, and
output reset to 0 when PWM/DCMP is power-down,
power-down sync to clock and output state control in 1: power-down is synchronized with clock, when
1677
power-down mode
PD=0, the clock is enabled after 2 clock cycles, while
when PD=1, the clock is gated immediately. and the
output is kept at current state when PD=1.
0: Disable
1: Enable
1678
PWM/DCMP0 Turn On by Register
00: ADC
01: 8MSBs SPI
10: FSM0_Q[7:0]
1680:1679
PWM/DCMP0 Positive Input Source Selection
11: From MUX State by Matrix1_OUT[84:83]
00: CNT8_Q[7:0]
01: Register 0
10: 8LSBs SPI
11: FSM1_Q[7:0]
1682:1681
1690:1683
PWM/DCMP0 Negative Input Source Selection
Register 2, 8 Bits NVM Data to PWM/DCMP or DAC
Input
Data
PWM1
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
1693:1691
PWM1 Dead Band zone Control
PWM/DCMP1 Mode Selection
0: PWM Output duty cycle Down to 0% and DCMP
OUT=1 if IN+ > IN-
1: PWM Output duty cycle up to 100% and DCMP
OUT=1 if IN+ >= IN-
1694
Datasheet
16-Mar-2020
Revision 3.3
167 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0: PWM
1: DCMP When in PWM Mode, OUTN1 is pwm1's
Negative output When in DCMP Mode, OUTN0 is
DCMP1's match Output
1695
PWM/DCMP1 Function Selection
0: Clock From MUX State by registers [1629:1628]
1: Matrix1_73
1696
1697
1698
PWM/DCMP1 Clock Source Selection
PWM/DCMP1 Clock Inversion
0: Disable
1: Enable
0: Disable
1: Enable
PWM/DCMP1 Turn On by Register
00: ADC
01: 8LSBs SPI
10: FSM1[7: 0]
11: Register 1
1700:1699
PWM/DCMP1 Positive Input Source Selection
00: CNT11_Q[7:0]
PWM/DCMP1 Negative Input and DAC Input Source 01: From MUX State by Matrix1_OUT[84:83]
1702:1701
1710:1703
Selection
10: 8MSBs SPI
11: FSM0_Q[7:0]
Register 1, 8 Bits NVM Data to PWM/DCMP or DAC
Input
Data
PWM2
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
1713:1711
PWM2 Dead Band zone Control
0: PWM Output duty cycle Down to 0% and DCMP
OUT=1 if IN+ > IN-
1: PWM Output duty cycle up to 100% and DCMP
OUT=1 if IN+ >= IN-
1714
1715
PWM/DCMP2 Mode Selection
PWM/DCMP2 Function Selection
0: PWM
1: DCMP When in PWM Mode, OUTN2 is pwm2's
Negative output When in DCMP Mode, OUTN2 is
DCMP1's match Output
0: Clock From MUX State by registers [1629: 1628]
1: Matrix1_73
1716
1717
1718
PWM/DCMP2 Clock Source Selection
PWM/DCMP2 Clock Inversion
0: Disable
1: Enable
0: Disable
1: Enable
PWM/DCMP2 Turn On by Register
00: ADC
01: 8MSBs SPI
10: FSM1[7: 0]
11: Register 3
1720:1719
1722:1721
PWM/DCMP2 Positive Input Source Selection
00: CNT8_Q[7: 0]
PWM/DCMP2 Negative Input and DAC Input Source 01: Register 2
Selection
10: 8LSBs SPI
11: FSM0_Q[7: 0]
Datasheet
16-Mar-2020
Revision 3.3
168 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
Register 0, 8 Bits NVM Data to PWM/DCMP or DAC
Input
1730:1723
Data
DLY/CNT 0
1744:1731
1747:1745
CNT0 14bits Data From Register
Data
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LFOSC
DLY/CNT0 Clock Source Select
101: DLY_OUT9
110: RING OSC
111: Matrix0_OUT72
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1749:1748
DLY0 Edge Mode Select or CNT0 Reset Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
00: DLY
01: CNT
10: Edge Detect
11: Wake Sleep Ratio Control
1751:1750
1752
DLY/CNT0 Macrocell Function Select
Wake Sleep Output State When WS Oscillator is Power- 0: in Power-down Mode
down
1: in Normal Operation State
DLY/CNT 1
1766:1753
CNT1 14-bits Data from Register
Data
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LF OSC
1769:1767
DLY/CNT1 Clock Source Select
101: DLY_OUT0
110: RING OSC
111: Matrix1_OUT74
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1771:1770
1773:1772
DLY1 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
00: DLY
01: CNT
10: Edge Detect
DLY/CNT1 Macrocell Function Select
11: Reserved
Datasheet
16-Mar-2020
Revision 3.3
169 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
DLY/CNT 2/FSM0
1787:1774
1791:1788
CNT2 14-bits Data from Register
Data
0000: RC OSC
0001: RC OSC_DIV4
0010: RC OSC_DIV12
0011: RC OSC_DIV24
0100: RC OSC_DIV64
0101: DLY_OUT1
0110: Matrix0_OUT72
0111: Matrix0_OUT72 divide by 8
1000: RING OSC
DLY2/CNT2/FSM0 Clock Source Select
1001: Matrix0_OUT83(SPI_SCLK)
1010: LF OSC
1011: CLK of FSM_DIV256
1100: CLK PWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1793:1792
1795:1794
DLY2 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
00: DLY
01: CNT/FSM
10: Edge Detect
11: None
DLY/CNT2 Macrocell Function Select
00: 14 Bits NVM Data
01: 8-bits ADC Data
10: 0
1797:1796
1798
FSM0 Input Data Source Select
CNT2 Value Control
11: 8LSBs SPI Parallel Data
0: Reset (CNT value = 0)
1: Set (CNT value = FSM Data)
DLY/CNT 3
1812:1799
CNT3 14-bits Data from Register
Data
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LF OSC
1815:1813
DLY/CNT3 Clock Source Select
101: DLY_OUT2
110: RING OSC
111: Matrix1_OUT74
Datasheet
16-Mar-2020
Revision 3.3
170 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1817:1816
DLY3 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
00: DLY
01: CNT
10: Edge Detect
11: CNT (the Reset From Matrix not Control the Os-
cillator)
1819:1818
DLY/CNT3 Macrocell Function Select
CNT4 8-bits Data From Register
DLY/CNT 4/FSM1
1827:1820
Data
0000: RC OSC
0001: RC OSC_DIV4
0010: RC OSC_DIV12
0011: RC OSC_DIV24
0100: RC OSC_DIV64
0101: DLY_OUT3
0110: Matrix1_OUT74
0111: Matrix0_OUT72 divide by 8
1000: RING OSC
1831:1828
DLY4/CNT4/FSM1 Clock Source Select
1001: Matrix0_OUT83(SPI_SCLK)
1010: LF OSC
1011: CLK FSM_DIV256
1100: CLK PWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1833:1832
DLY4 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT/FSM
1834
DLY4/CNT4/FSM1 Macrocell Function Select
FSM1 Input Data Source Select
CNT4 Value Control
00: 8-bits NVM Data
01: 8-bits ADC Data
10: 8MSBs SPI Parallel Data
11: 0
1836:1835
0: Reset (CNT value = 0)
1: Set (CNT value = FSM Data)
1837
DLY/CNT 5
Datasheet
16-Mar-2020
Revision 3.3
171 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
1845:1838
CNT5 8-bits Data From Register
Data
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LF OSC
1848:1846
DLY/CNT5 Clock Source Select
101: DLY_OUT4
110: RING OSC
111: Matrix0_OUT73
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1850:1849
DLY5 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT
1851
DLY/CNT 6
DLY/CNT5 Macrocell Function Select
CNT6 8-bits Data from Register
1859:1852
Data
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LF OSC
1862:1860
DLY/CNT6 Clock Source Select
101: DLY_OUT5
110: RING OSC
111: Matrix0_OUT73
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1864:1863
DLY6 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT
1865
DLY/CNT6 Macrocell Function Select
CNT7 8-bits Data from Register
DLY/CNT 7
1873:1866
Data
Datasheet
16-Mar-2020
Revision 3.3
172 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
000: RC OSC
001: RC OSC_DIV4
010: RC OSC_DIV24
011: RC OSC_DIV64
100: LF OSC
1876:1874
DLY/CNT7 Clock Source Select
101: DLY_OUT6
110: RING OSC
111: Matrix1_OUT73
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1878:1877
DLY7 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT
1879
DLY/CNT 8
DLY/CNT7 Macrocell Function Select
CNT8 8-bits Data from Register
1887:1880
Data
0000: RC OSC
0001: RC OSC_DIV4
0010: RC OSC_DIV12
0011: RC OSC_DIV24
0100: RC OSC_DIV64
0101: DLY_OUT7
0110: Matrix1_OUT73
0111: Matrix0_OUT72 divide by 8
1000: RING OSC
1891:1888
DLY/CNT8 Clock Source Select
1001: Matrix0_OUT83(SPI_SCLK)
1010: LF OSC
1011: CLK FSM_DIV256
1100: CLK PWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1893:1892
DLY8 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT/PWM_RAMP
1894
DLY/CNT 9
1902:1895
DLY/CNT8 Macrocell Function Select
CNT9 8-bits Data from Register
Data
Datasheet
16-Mar-2020
Revision 3.3
173 of 186
© 2020 Dialog Semiconductor
CFR0011-120-00
SLG46620-A
Auto Grade GreenPAK
Programmable Mixed-signal Matrix
Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0000: RC OSC
0001: RC OSC_DIV4
0010: RC OSC_DIV12
0011: RC OSC_DIV24
0100: RC OSC_DIV64
0101: DLY_OUT8
0110: Matrix0_OUT72
0111: Matrix0_OUT72 divide by 8
1000: RING OSC
1906:1903
DLY/CNT9 Clock Source Select
1001: Matrix0_OUT83(SPI_SCLK)
1010: LF OSC
1011: CLK FSM_DIV256
1100: CLK PWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
1908:1907
DLY9 Edge Mode Select
If CNT Reset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
0: DLY
1: CNT/PWM_RAMP
1909
1910
DLY/CNT9 Macrocell Function Select
Reserved
PIN 12
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital in
011: Analog IO
1913:1911
PIN 12 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
1915:1914
PIN 12 Pull-Up/Down Resistor Selection
11: 1 M
0: Pull-Down
1: Pull-Up
1916
1917
1918
PIN 12 Pull-Up Resistor Enable
PIN 12 Output Driver Current double
PIN 12 4x Drive Enable
0: 1x drive
1: 2x drive
0: Disable
1: Enable
PIN 13
00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low Voltage Digital Input
11: Analog IO
1920:1919
PIN 13 Input Mode Control
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
1922:1921
PIN 13 Output Mode Control
00: Floating
01: 10 K
10: 100 K
1924:1923
1925
PIN 13 Pull-Up/Down Resistor Selection
PIN 13 Pull-Up Resistor Enable
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 14
00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low Voltage Digital Input
11: Analog IO
1927:1926
1929:1928
PIN 14 Input Mode Control
PIN 14 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
1931:1930
1932
PIN 14 Pull-Up/Down Resistor Selection
PIN 14 Pull-Up Resistor Enable
0: Pull-Down
1: Pull-Up
PIN 15
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
1935:1933
PIN 15 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10K
10: 100K
11: 1M
1937:1936
PIN 15 Pull-Up/Down Resistor Selection
0: Pull-Down
1: Pull-Up
1938
1939
PIN 15 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 15 Output Driver Current double
PIN 16
00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low Voltage Digital Input
11: Analog IO
1941:1940
1943:1942
PIN 16 Input Mode Control
PIN 16 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
00: Floating
01: 10K
10: 100K
11: 1M
1945:1944
PIN 16 Pull-Up/Down Resistor Selection
PIN 16 Pull-Up Resistor Enable
0: Pull-Down
1: Pull-Up
1946
PIN 17
000: Digital in without Schmitt trigger
001: Digital in with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
1949:1947
PIN 17 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
1951:1950
PIN 17 Pull-Up/Down Resistor Selection
0: Pull-Down
1: Pull-Up
1952
1953
PIN 17 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 17 Output Driver Current double
PIN 18
00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low Voltage Digital Input
11: Analog IO
1955:1954
1957:1956
PIN 18 Input Mode Control
PIN 18 Output Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
1959:1958
1960
PIN 18 Pull-Up/Down Resistor Selection
PIN 18 Pull-Up Resistor Enable
0: Pull-Down
1: Pull-Up
PIN 19
00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low Voltage Digital Input
11: Analog IO
1962:1961
1964:1963
1966:1965
PIN 19 Input Mode Control
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-DRAIN
11: 2x Open-DRAIN
PIN 10 Output Mode Control
00: Floating
01: 10 K
10: 100 K
PIN 19 Pull-Up/Down Resistor Selection
11: 1 M
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
0: Pull-Down
1: Pull-Up
1967
PIN 20
PIN 19 Pull-Up Resistor Enable
000: Digital IN without Schmitt trigger
001: Digital IN with Schmitt trigger
010: Low Voltage Digital IN
011: Analog IO
1970:1968
PIN 20 Mode Control
100: Push-Pull
101: NMOS Open-DRAIN
110: PMOS Open-DRAIN
111: Analog IO & NMOS Open-DRAIN
00: Floating
01: 10 K
10: 100 K
11: 1 M
1972:1971
PIN 20 Pull-Up/Down Resistor Selection
0: Pull-Down
1: Pull-Up
1973
1974
PIN 20 Pull-Up Resistor Enable
0: 1x drive
1: 2x drive
PIN 20 Output Driver Current double
1981:1975
1987:1982
1995:1988
2001:1996
2007:2002
Reserved
Reserved
Reserved
Reserved
Reserved
0: 1.8 V Use Regulator
1: Bypass VDD as 1.8 V Device Power
2008
2009
2010
Bypass VDD to 1.8 V Device Only When Power is 1.8 V
Input pad Enable to Core nRST Delay 500 us Enable
Power Auto Detector Function for Charge Pump
0: Delay 4 us
1: Delay 500 us
0: Enable
1: Disable
2012:2011
2014:2013
Reserved
Reserved
SPI top Control
SPI Parallel Output Selection for Matrix 1 (IN[44] →
IN[51])
0: Matrix 1 Input From DCMP
1: Matrix 1 Input From SPI Parallel Output [7: 0]
2015
0X: PIN 10 digital OUT From Matrix 0 (OUT67)
10: From SPI (SDO)
2017:2016
SPI SDIO Output Control
11: From ADC serial Output
PIN 2 Reset Control
0: PIN 2 Edge Active
1: PIN 2 High Active
2018
2019
Bypass the PIN 2
0: Rising Edge
1: Falling Edge
PIN2 Edge Detect Mode
0: Enable
1: Disable
2020
PIN2 Reset Enable
Reserved
2027:2021
Reserved
NVM
2029:2028
Reserved
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Table 63: Register Map
Register Bit
Signal Function
Address
Register Bit Definition
2030
Reserved
Data
2038:2031
Pattern ID
Note: assigned to track code revision
0: Protection Disable
1: Protection Enable
2039
Read Protection
Data
Hex: A5
2047:2040
Die ID: Power up Sequence Bits
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24 Package Top Marking Definitions
24.1 TSSOP-20
XXXXXXXX
$RR###NNNN
YYWW
Device Name
$: Subcon
RR: Revision
###: Programming Code
NNNN: Alphanumeric
Date Code
Pin 1
Identifier
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25 Package Information
25.1 PACKAGE OUTLINES FOR TSSOP 20L 173 MIL GREEN PACKAGE
JEDEC MO-220
IC Net Weight: TBD g
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25.2 TSSOP HANDLING
Be sure to handle TSSOP package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle TSSOP package with fingers as this can contaminate the package pins and interface with solder reflow.
25.3 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 25.74 mm3 (nominal) for
TSSOP-20. More information can be found at www.jedec.org.
26 Ordering Information
Part Number
Type
SLG46620-AG
SLG46620-AGTR
20-pin TSSOP
20-pin TSSOP Tape and Reel (4k units)
26.1 TAPE AND REEL SPECIFICATIONS
Max Units
per Reel per Box
Leader (min)
Trailer (min)
Nominal
Package Size
(mm)
Reel &
Hub Size
(mm)
Tape
Width Pitch
(mm)
Part
Package # of
Length
(mm)
Length
Type
Pins
Pockets
Pockets
(mm)
(mm)
TSSOP
20L 173
MILGreen
20
6.5 x 6.4
4,000
4,000
330/100
42
336
42
336
16
8
Package
26.2 CARRIER TAPE DRAWING AND DIMENSIONS
Pocket Pocket
Index
Hole
Pitch
Index Hole Index Hole
Pocket
Depth
Pocket Index Hole
Tape
Tape
BTM
BTM
to Tape
Edge
to Pocket
Center
Package
Type
Pitch
Diameter
Width Thickness
Length
Width
A0
B0
K0
P0
P1
D0
E
F
W
T
TSSOP 20L
173 MIL
Green
6.8
6.9
1.6
4
8
1.5
1.75
7.5
16
0.3
Package
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26.3 TSSOP- 20
Refer to EIA-481 specification
Note: 1.Orientation in carrier: Pin1 is at upper left corner (Quadrant 1).
27 Layout Guidelines
27.1 TSSOP-20
Unit: µm
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Glossary
A
ACMP
ADC
Analog Comparator
Analog-to-Digital Converter
B
BG
BW
Bandgap
Bandwidth
C
CH
Channel Selection
Clock
CLK
CNT
CSB
Counter
Chip Select
D
DAC
DCMP
DFF
DLY
Digital to Analog Converter
Digital Comparator
D Flip-Flop
Delay
E
ESD
Electrostatic discharge
Finite State Machine
F
FSM
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
H
HTOL
High Temperature Operating Life
I
IN
IO
Input
Input/Output
L
LSB
LUT
Least Significant Bit
Look-Up Table
M
MOSI, SDI
Master Output Slave Input
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MISO, SDO
MSB
Master Input Slave Output
Most Significant Bit
Multiplexer
MUX
N
nRST
NVM
Reset
Non-Volatile Memory
O
OD
Open Drain
OE
Output Enable
Oscillator
OSC
OTP
OUT
One-Time-Programmable
Output
P
PD
Power-Down
PGA
PGEN
POR
PWR
P DLY
PWM
Programmable Gain Amplifier
Pattern Generator
Power-On Reset
Power
Programmable Delay
Pulse-Width Modulator
R
RTI
RTO
Referred to input
Referred to output
S
SCLK
SMT
Serial Clock
With Schmitt Trigger
V
Vref
Voltage Reference
W
WOSMT
WS
Without Schmitt Trigger
Wake and Sleep Controller
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Revision History
Revision
Date
Description
Corrected Table Electrical Characteristics (VIH, VIL)
Added note for CNTs
Added Note 3 in Register OE 4x Drive Structure Diagram
Fixed typos
3.3
16-Mar-2020
Updated Digital Comparator/Pulse Width Modulator section
Updated Block Diagram
Fixed typos
3.2
3.1
7-Oct-2019
30-Sept-2019
Updated Electrostatic Discharge Ratings
Updated ACMP Input Voltage Offset
Added Vref OUT Specification Table
Updated Oscillator Frequency Limits
Updated PGA Typical Performance Section
Updated ACMP Maximum Power-On Delay Figures
Added IO Typical Performance Section
Updated Input Leakage Current
Updated PIN Block Diagrams
Updated PGA Offset and Gain error for all mode
Updated ADC Characteristics (including PGA)
Updated graph for ACMP Input Current Source
Updated Programmable Delay Expected Delays and Widths
Updated Typical Current Consumption Estimated for Each Macrocell table
Updated Delay Estimated for Each ACMP table
Updated Typical Delay Estimated for Each Macrocell
Updated Vref Output Error
3.0
27-Sept-2019
Updated ACMP Buffer Input Voltage Offset
Updated ACMP Gain Error
Updated ACMP Startup Time
Updated Table EC at T = -40 °C to +105 °C, VDD = 1.71 V to 3.6 V, Unless Otherwise Noted
Updated Table Oscillators Frequency Limits
Updated Figures OSC Power-on Delay
Added Figures Oscillators Frequency vs. VDD
Updated Table OSC Power-On
Corrected Programmable Delay / Edge Detector description and timing diagrams
Corrected Oscillator Block Diagram
Final version
Datasheet
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Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification
changes are communicated via Customer Product Notifications. Datasheet
changes are communicated via www.dialog-semiconductor.com.
4.<n>
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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