AT25SF161B-UUD-T_技术文档

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Key Features

 Serial Peripheral Interface (SPI) Compatible

 Support Protocol: Single, Dual, Quad I/O operation

 108 MHz Maximum Operating Frequency

 Two Supply Voltage Options Available:

 2.7 V - 3.6 V

 2.5 V - 3.6.V

 Execute-In-Place (XiP) support

 Continuous Read mode (with 8/16/32/64 bytes wrap)

 Serial Flash Discoverable Parameters (SFDP, JDES216B) support

 OTP Memory

 Three Protected Programmable Security Register Pages (Page size: 256 bytes)

 64-bit factory programmable UID register

 Hardware Write Protection (WP pin)

 Software Write protection (Programmable non-volatile control registers)

 Program and Erase Suspend and Resume

 Byte programming size: up to 256 bytes

 Erase Size and Duration

 Uniform 4-kbyte Block Erase (60 ms typical)

 Uniform 32-kbyte Block Erase (150 ms typical)

 Uniform 64-kbyte Block Erase (250 ms typical)

 Full Chip Erase (7 seconds typical)

 Low Power Dissipation

 Standby Current (30 µA maximum)

 Deep Power Down Current (10 µA maximum)

 Endurance: 100,000 Program and Erase Cycles

 Data Retention: 20 Years

 Industrial Temperature Range (-40 ^oC to 85 ^oC)

 Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

 8-lead SOIC (0.150” Narrow and 0.208” Wide)

 8-pad Ultra-Thin DFN (5 x 6 x 0.6 mm)

 8-ball WLCSP (3 x 2 x 3 grid array)

 Die Wafer Form

 Other Package Options (contact Dialog Semiconductor)

Datasheet

21-Apr-2021

Revision E

1

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Contents

Key Features............................................................................................................................................................................. 1

1 Product Overview ................................................................................................................................................................. 6

2 Pin Descriptions and Package Pinouts .............................................................................................................................. 7

3 Block Diagram ...................................................................................................................................................................... 9

4 Memory Array ..................................................................................................................................................................... 10

5 Device Operation ................................................................................................................................................................ 12

5.1 Dual Output Read (1-1-2) ........................................................................................................................................12

5.2 Dual I/O Read (1-2-2) ..............................................................................................................................................12

5.3 Quad Output Read (1-1-4) .......................................................................................................................................12

5.4 Quad I/O Read (1-4-4) .............................................................................................................................................12

6 Commands and Addressing .............................................................................................................................................. 13

7 Read Commands ................................................................................................................................................................ 15

7.1 Read Array (0Bh and 03h) .......................................................................................................................................15

7.2 Dual-Output Read Array (3Bh) .................................................................................................................................16

7.3 Dual-I/O Read Array (BBh) ......................................................................................................................................17

7.3.1 Dual-I/O Read Array (BBh) with Continuous Read Mode .......................................................................... 18

7.4 Quad Output Fast Read Array (6Bh) .......................................................................................................................19

7.5 Quad-I/O Read Array (EBh) .....................................................................................................................................20

7.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode ......................................................................... 21

7.5.2 Set Burst with Wrap (77h) .......................................................................................................................... 22

7.6 Quad-I/O Word Fast Read (E7h) .............................................................................................................................23

7.6.1 Quad I/O Word Fast Read with “Continuous Read Mode” ......................................................................... 23

7.6.2 Quad I/O Word Fast Read with 8-, 16-, 32-, 64-Byte Wrap Around in Standard SPI Mode ....................... 24

7.7 Read Serial Flash Discoverable Parameter (5Ah) ...................................................................................................24

8 Program and Erase Commands ........................................................................................................................................ 25

8.1 Byte/Page Program (02h) ........................................................................................................................................25

8.2 Quad Page Program (32h) .......................................................................................................................................26

8.3 Block Erase (20h, 52h, or D8h) ................................................................................................................................27

8.4 Chip Erase (60h or C7h) ..........................................................................................................................................27

8.5 Program/Erase Suspend (75h) ................................................................................................................................28

8.6 Program/Erase Resume (7Ah) .................................................................................................................................29

9 Protection Commands and Features ................................................................................................................................ 30

9.1 Write Enable (06h) ...................................................................................................................................................30

9.2 Write Disable (04h) ..................................................................................................................................................30

9.3 Non-Volatile Protection ............................................................................................................................................31

9.4 Protected States and the Write Protect Pin .............................................................................................................32

9.5 Enable Reset (66h) and Reset Device (99h) ...........................................................................................................33

10 Security Register Commands ......................................................................................................................................... 34

10.1 Read Unique ID Number (4Bh) ..............................................................................................................................34

10.2 Erase Security Registers (44h) ..............................................................................................................................34

10.3 Program Security Registers (42h) ..........................................................................................................................36

10.4 Read Security Registers (48h) ...............................................................................................................................37

11 Status Register Commands ............................................................................................................................................ 38

11.1 Read Status Register (05h, 35h, and 15h) ............................................................................................................38

11.1.1 SRP1, SRP0 Bits ..................................................................................................................................... 40

11.1.2 CMP, BP4, BP3, BP2, BP1, BP0 Bits ...................................................................................................... 41

11.1.3 WEL Bit .................................................................................................................................................... 41

11.1.4 RDY/BSY Bit ............................................................................................................................................ 41

11.1.5 LB3, LB2, LB1 Bits ................................................................................................................................... 41

11.1.6 E_SUS Bit ................................................................................................................................................ 42

11.1.7 P_SUS Bit ................................................................................................................................................ 42

11.1.8 QE Bit ....................................................................................................................................................... 42

Datasheet

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Revision E

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DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11.2 Write Status Register (01h, 31h, 11h) ....................................................................................................................43

11.3 Write Enable for Volatile Status Register (50h) ......................................................................................................44

12 Other Commands and Functions .................................................................................................................................... 45

12.1 Read Manufacturer and Device ID (9Fh) ...............................................................................................................45

12.2 Read ID (Legacy Command) (90h) ........................................................................................................................46

12.3 Dual I/O Read Manufacture ID/ Device ID (92h) ....................................................................................................47

12.4 Quad I/O Read Manufacture ID / Device ID (94h) .................................................................................................48

12.5 Deep Power-Down (B9h) .......................................................................................................................................49

12.6 Resume from Deep Power-Down (ABh) ................................................................................................................50

12.6.1 Resume from Deep Power-Down and Read Device ID (ABh) ................................................................. 51

12.7 Hold Function .........................................................................................................................................................51

13 Electrical Specifications .................................................................................................................................................. 52

13.1 Absolute Maximum Ratings* ..................................................................................................................................52

13.2 DC and AC Operating Range ................................................................................................................................52

13.3 DC Characteristics .................................................................................................................................................52

13.4 AC Characteristics - Maximum Clock Frequencies ................................................................................................53

13.5 AC Characteristics - All Other Parameters .............................................................................................................53

13.6 Program and Erase Characteristics .......................................................................................................................54

13.7 Power Up Conditions .............................................................................................................................................54

13.8 Input Test Waveforms and Measurement Levels ...................................................................................................54

13.9 Output Test Load ...................................................................................................................................................54

14 AC Waveforms .................................................................................................................................................................. 55

15 Ordering Information ....................................................................................................................................................... 57

16 Packaging Information ..................................................................................................................................................... 59

16.1 8S1 – 0.150” Narrow JEDEC SOIC .......................................................................................................................59

16.2 8S2 – 8-lead, 0.208” Wide EIAJ SOIC ...................................................................................................................60

16.3 8MA1 – UDFN ........................................................................................................................................................61

16.4 8-WLCSP — 8-ball 3 x 2 x 3 WLCSP ....................................................................................................................62

17 Revision History ............................................................................................................................................................... 63

Datasheet

21-Apr-2021

Revision E

3

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Figures

Figure 1: 8-SOIC (0.150” and 0.208”) — Top View....................................................................................................................8

Figure 2: 8-ball WLCSP (3 x 2 x 3) — Bottom View...................................................................................................................8

Figure 3: 8-UDFN — Top View ..................................................................................................................................................8

Figure 4: Block Diagram.............................................................................................................................................................9

Figure 5: SPI Mode 0 and 3 .....................................................................................................................................................12

Figure 6: Read Array - 03h Opcode .........................................................................................................................................15

Figure 7: Read Array - 0Bh Opcode.........................................................................................................................................15

Figure 8: Dual-Output Read Array............................................................................................................................................16

Figure 9: Dual I/O Read Array (Initial command or previous M5,M4 ¹ 1,0) ..............................................................................17

Figure 10: Dual-I/O Read Array (Previous command set M5, M4 = 1,0) .................................................................................18

Figure 11: Quad-Output Read Array ........................................................................................................................................19

Figure 12: Quad-I/O Read Array (Initial command or previous M5, M4 ¹ 1,0)..........................................................................20

Figure 13: Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5, M4 = 1,0).................................21

Figure 14: Set Burst with Wrap Timing (SPI Mode) .................................................................................................................22

Figure 15: Quad I/O Word Fast Read Timing (Initial Command Set M5, M4 ≠ 1,0) SPI Mode................................................23

Figure 16: Quad I/O Word Fast Read Timing (Previous Command Set M5, M4 = 1,0) SPI Mode ..........................................23

Figure 17: Read Serial Flash Discoverable Parameter Command Timing...............................................................................24

Figure 18: Byte Program..........................................................................................................................................................25

Figure 19: Page Program Timing.............................................................................................................................................26

Figure 20: Quad Page Program (32h) Timing..........................................................................................................................26

Figure 21: Block Erase.............................................................................................................................................................27

Figure 22: Enable Reset (66h) and Reset Device (99h) Command Timing (SPI Mode)..........................................................33

Figure 23: Read Unique ID Timing (SPI Mode)........................................................................................................................34

Figure 24: Erase Security Register Page.................................................................................................................................35

Figure 25: Program Security Registers....................................................................................................................................36

Figure 26: Read Security Registers .........................................................................................................................................37

Figure 27: Read Status Register 1...........................................................................................................................................38

Figure 28: Read Status Register 2...........................................................................................................................................39

Figure 29: Write Status Register ..............................................................................................................................................43

Figure 30: Write Enable for Volatile Status Register................................................................................................................44

Figure 31: Read Manufacturer and Device ID..........................................................................................................................46

Figure 32: Read ID (Legacy Command) ..................................................................................................................................46

Figure 33: Dual I/O Read Manufacture ID/ Device ID Timing ..................................................................................................47

Figure 34: Quad I/O Read Manufacture ID / Device ID Timing................................................................................................48

Figure 35: Deep Power-Down..................................................................................................................................................49

Figure 36: Resume from Deep Power-Down ...........................................................................................................................50

Figure 37: Resume from Deep Power-Down and Read Device ID Timing ..............................................................................51

Figure 38: Serial Input Timing..................................................................................................................................................55

Figure 39: Serial Output Timing ...............................................................................................................................................55

Figure 40: WP Timing for Write Status Register Command When BPL = 1 ............................................................................55

Figure 41: HOLD Timing – Serial Input ....................................................................................................................................56

Figure 42: HOLD Timing – Serial Output .................................................................................................................................56

Datasheet

21-Apr-2021

Revision E

4

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Tables

Table 1: Pin Descriptions ...........................................................................................................................................................7

Table 2: Device Memory Map — Block Erase Address Ranges..............................................................................................10

Table 3: Device Memory Map — Page Program Address Ranges..........................................................................................11

Table 4: AT25SF161B Command Table..................................................................................................................................13

Table 5: Set Burst with Wrap Command Functions ................................................................................................................22

Table 6: Memory Array with CMP = 0 ......................................................................................................................................31

Table 7: Memory Array Protection with CMP = 1.....................................................................................................................32

Table 8: Security Register Addresses for Erase Security Register Page Command...............................................................35

Table 9: Security Register Addresses for Program Security Registers Command ..................................................................36

Table 10: Security Register Addresses for Read Security Registers Command .....................................................................37

Table 11: Status Register 1 Bit Assignments...........................................................................................................................38

Table 12: Status Register 2 Bit Assignments...........................................................................................................................39

Table 13: Status Register 3 Bit Assignments...........................................................................................................................40

Table 14: Status Register Protection Table..............................................................................................................................40

Table 15: Write Status Register 1 ............................................................................................................................................43

Table 16: Write Status Register 2 ............................................................................................................................................43

Table 17: Write Status Register 3 ............................................................................................................................................43

Table 18: Manufacturer and Device ID Information..................................................................................................................45

Table 19: Manufacturer and Device ID Information..................................................................................................................45

Table 20: Manufacturer and Device ID Details.........................................................................................................................45

Table 21: Ordering Codes for 2.7 V to 3.6 V Devices ..............................................................................................................57

Table 22: Ordering Codes for 2.5 V to 3.6 V Devices ..............................................................................................................57

Table 23: Description of Package Types..................................................................................................................................58

Datasheet

21-Apr-2021

Revision E

5

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

1

Product Overview

The AT25SF161B is a serial interface Flash memory device designed for a wide variety of high-volume consumer-based appli-

cations in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase

architecture of the AT25SF161B also is ideal for data storage, eliminating the need for additional data storage devices.

The AT25SF161B erase block sizes are optimized to meet the needs of today's code and data storage applications. This means

memory space can be used much more efficiently. Because certain code modules and data storage segments must reside in their

own erase regions, the wasted and unused memory space that occurs with large-block-erase Flash memory devices can be

reduced greatly. This increased memory space allows additional code routines and data storage segments to be added, while

maintaining the same overall device density.

This device also contains three Security Register pages for unique device serialization, system-level Electronic Serial Number

(ESN) storage, locked key storage, etc. These pages can be locked individually.

Datasheet

21-Apr-2021

Revision E

6

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

2

Pin Descriptions and Package Pinouts

Table 1: Pin Descriptions

Assert

State

Symbol Name and Function

Type

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted,

the device is deselected and normally be placed in standby mode.

A high-to-low transition on the CS pin is required to start an operation; a low-to-high

transition is required to end an operation. When ending an internally self-timed operation,

such as a program or erase cycle, the device does not enter the standby mode until the

operation is complete.

CS

Low

Input

SERIAL CLOCK: This pin provides a clock to the device. Command, address, and input

data present on the SI pin is latched in on the rising edge of SCK, while output data on the

SO pin is clocked out on the falling edge of SCK.

SCK

-

Input

SERIAL INPUT: The SI pin is used for all data input, including command and address

sequences. Data on the SI pin is always latched in on the rising edge of SCK.

With the Dual-Output and Quad-Output Read commands, the SI pin becomes an output pin

SI (I/O₀) (I/O₀) in conjunction with other pins to allow two or four bits of data (on

I/O_3-0) to be clocked in on every falling edge of SCK.

Input/

Output

-

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

SERIAL OUTPUT: Data on the SO pin is clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO pin remains an output pin (I/O₀) in

conjunction with other pins to allow two bits of data (on I/O_1-0) to be clocked in on every

falling edge of SCK.

Input/

Output

SO (I/O₁)

The SO pin is in a high-impedance state whenever the device is deselected (CS is

deasserted).

WRITE PROTECT: The WP pin controls the hardware locking feature of the device.

With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/

O₂) and, along with other pins, allows four bits (on I/O_3-0) of data to be clocked in on every

rising edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an

WP (I/O₂) output pin (I/O₂) in conjunction with other pins to allow four bits of data (on I/O3_3-0) to be

clocked in on every falling edge of SCK.

Input/

Output

-

The WP pin is internally pulled-high and can be left floating if hardware-controlled

protection is not used; however, it is recommended that the WP pin also be externally

connected to V_CCwhenever possible.

HOLD: The HOLD pin temporarily pauses serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data

on the SI pin are ignored, and the SO pin is in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state, for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

affect on internally self-timed operations, such as a program or erase cycle. See “Hold

Function”, on page 51 for additional details on the Hold operation.

HOLD (I/O₃)

Input/

Output

-

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin (I/

O₃) and, along with other pins, allows four bits (on I/O_3-0) of data to be clocked in on every

rising edge of SCK. With the Quad-Output Read commands, the HOLD pin becomes an

output pin (I/O₃) in conjunction with other pins to allow four bits of data (on I/O3_3-0) to be

clocked in on every falling edge of SCK.

The HOLD pin is internally pulled-high and can be left floating if the Hold function is not

used. It is recommended, however, that the HOLD pin is externally connected to V_CC

whenever possible.

Datasheet

21-Apr-2021

Revision E

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DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Table 1: Pin Descriptions (Continued)

Assert

State

Symbol Name and Function

Type

Power

V_CC

DEVICE POWER SUPPLY: The V_CCpin supplies the source voltage to the device.

-

GROUND: The ground reference for the power supply. Connect GND to the system

ground.

GND

CS 1

SO (IO₁) 2

WP (IO₂) 3

GND 4

8 VCC

7 HOLD (IO₃)

6 SCK

CS

SO (IO₁)

WP (IO₂)

GND

1

2

3

4

8

7

6

5

VCC

HOLD (IO₃)

SCK

SI (IO₀)

5 SI (IO₀)

Figure 3: 8-UDFN — Top View

Figure 1: 8-SOIC (0.150” and 0.208”) — Top View

CS

A3

VCC

A1

GND

B2

SO

C3

HOLD

C1

SI

D2

SCK

E1

WP

E3

Figure 2: 8-ball WLCSP (3 x 2 x 3) — Bottom View

Datasheet

21-Apr-2021

Revision E

8

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

3

Block Diagram

Control and

Protection Logic

I/O Buffers

and Latches

CS

SRAM

Data Buffer

SCK

Interface

Control

And

SI (I/O )

0

Y-Decoder

Y-Gating

Logic

SO (I/O )

1

Flash

Memory

Array

X-Decoder

WP (I/O )

2

HOLD

(I/O )

3

Note: I/O

3-0

pin naming convention is used for Dual-I/O and Quad-I/O commands.

Figure 4: Block Diagram

Datasheet

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Revision E

9

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

4

Memory Array

To provide the greatest flexibility, the memory array of the AT25SF161B can be erased in four levels of granularity, including a

full-chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data

segments to reside in their own erase regions. Note that in the following figures, the (Bxxx) value in parentheses indicates the

block number.

Table 2: Device Memory Map — Block Erase Address Ranges

64 kbyte Block Erase (D8h) 32 kbyte Block Erase (52h) 4 kbyte Block Erase (20h)

Block Address Range

4 kbytes (B511)

4 kbytes (B510)

4 kbytes (B509)

1FF000h - 1FFFFFh

1FE000h - 1FEFFFh

1FD000h - 1FDFFFh

1FC000h - 1FCFFFh

1FB000h - 1FBFFFh

1FA000h - 1FAFFFh

1F9000h - 1F9FFFh

1F8000h - 1F8FFFh

1F7000h - 1F7FFFh

1F6000h - 1F6FFFh

1F5000h - 1F5FFFh

1F4000h - 1F4FFFh

1F3000h - 1F3FFFh

1F2000h - 1F2FFFh

1F1000h - 1F1FFFh

1F0000h - 1F0FFFh

4 kbytes (B508)

4 kbytes (B507)

4 kbytes (B506)

4 kbytes (B505)

4 kbytes (B504)

4 kbytes (B503)

4 kbytes (B502)

4 kbytes (B501)

4 kbytes (B500)

4 kbytes (B499)

4 kbytes (B498)

4 kbytes (B497)

4 kbytes (B496)

32 kbytes

(block 63)

64 kbytes

(block 31)

32 kbytes

(block 62)

64 kbytes (block 30)

to

64 kbytes (block 1)

32 kbytes (block 61)

to

32 kbytes (block 2)

4 kbytes (B495)

to

4 kbytes (B16)

1EF000h - 1EFFFFh

to

010000h - 010FFFh

4 kbytes (B15)

4 kbytes (B14)

4 kbytes (B13)

4 kbytes (B12)

4 kbytes (B11)

4 kbytes (B10)

4 kbytes (B9)

4 kbytes (B8)

4 kbytes (B7)

4 kbytes (B6)

4 kbytes (B5)

4 kbytes (B4)

4 kbytes (B3)

4 kbytes (B2)

4 kbytes (B1)

4 kbytes (B0)

00F000h - 00FFFFh

00E000h - 00EFFFh

00D000h - 00DFFFh

00C000h - 00CFFFh

00B000h - 00BFFFh

00A000h - 00AFFFh

009000h - 009FFFh

008000h - 008FFFh

007000h - 007FFFh

006000h - 006FFFh

005000h - 005FFFh

004000h - 004FFFh

003000h - 003FFFh

002000h - 002FFFh

001000h - 001FFFh

000000h - 000FFFh

32 kbytes

(block 1)

64 kbytes

(block 0

32 kbytes

(block 0)

Datasheet

21-Apr-2021

Revision E

10

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Table 3: Device Memory Map — Page Program Address Ranges

4 kbytes Blocks

4 kbytes (B511)

4 kbytes (B510)

4 kbytes (B509)

4 kbytes (B508)

4 kbytes (B507)

4 kbytes (B506)

4 kbytes (B505)

4 kbytes (B504)

4 kbytes (B503)

4 kbytes (B502)

4 kbytes (B501)

4 kbytes (B500)

4 kbytes (B499)

4 kbytes (B498)

4 kbytes (B497)

4 kbytes (B496)

256 Byte Page

256 Bytes

1 - 256 Byte Page Program

1FFF00h - 1FFFFFh

1FFE00h - 1FFEFFh

1FFD00h - 1FFDFFh

1FFC00h - 1FFCFFh

1FFB00h - 1FFBFFh

1FFA00h - 1FFAFFh

1FF900h - 1FF9FFh

1FF800h - 1FF8FFh

1FF700h - 1FF7FFh

1FF600h - 1F6FFFh

1FF500h - 1FF5FFh

1FF400h - 1FF4FFh

1FF300h - 1FF3FFh

1FF200h - 1FF2FFh

1FF100h - 1FF1FFh

1FF000h - 1FF0FFh

4 kbytes (B494)

to

4 kbytes (B16)

.

4 kbytes (B15)

4 kbytes (B14)

4 kbytes (B13)

4 kbytes (B12)

4 kbytes (B11)

4 kbytes (B10)

4 kbytes (B9)

4 kbytes (B8)

4 kbytes (B7)

4 kbytes (B6)

4 kbytes (B5)

4 kbytes (B4)

4 kbytes (B3)

4 kbytes (B2)

4 kbytes (B1)

4 kbytes (B0)

256 Bytes

000F00h - 000FFFh

000E00h - 000EFFh

000D00h - 000DFFh

000C00h - 000CFFh

000B00h - 000BFFh

000A00h - 000AFFh

000900h - 0009FFh

000800h - 0008FFh

000700h - 0007FFh

000600h - 0006FFh

000500h - 0005FFh

000400h - 0004FFh

000300h - 0003FFh

000200h - 0002FFh

000100h - 0001FFh

000000h - 0000FFh

Datasheet

21-Apr-2021

Revision E

11

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

5

Device Operation

The AT25SF161B is controlled by a set of commands sent from a host controller, SPI Master. The SPI Master communicates with

the AT25SF161B through the SPI bus, which consists of four pins: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and

Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3). The AT25SF161B supports the two most common

modes, SPI modes 0 and 3. For these modes, data is latched in on the rising edge of SCK and output on the falling edge of SCK.

CS

SCK

MSB

LSB

SI

MSB

LSB

SO

Figure 5: SPI Mode 0 and 3

5.1 DUAL OUTPUT READ (1-1-2)

The AT25SF161B supports Dual Output (1-1-2) transfers, which enhance overall throughput over the standard SPI mode. This

mode transfers the command and address on the SI pin, but the data are transferred on the SI and SO pins. This means that only

half the number of clocks are required to transfer the data.

5.2 DUAL I/O READ (1-2-2)

The AT25SF161B supports Dual I/O (1-2-2) transfers, which enhance throughput over the standard SPI mode. This mode trans-

fers the command on the SI pin, but the address and data are transferred on the SI and SO pins. This means that only half the

number of clocks are required to transfer the address and data.

5.3 QUAD OUTPUT READ (1-1-4)

The AT25SF161B supports Quad Output (1-1-4) transfers, which enhance overall throughput over the standard SPI mode. This

mode transfers the command and address on the SI pin, but the data is transferred on the SI, SO, WP, and HOLD pins. This

means that only a quarter the number of clocks are required to transfer the data. With the Quad-Output Read Array command,

the SI, WP, and HOLD pins become outputs along with the SO pin.

5.4 QUAD I/O READ (1-4-4)

The AT25SF161B supports Quad I/O (1-4-4) transfers, which enhance throughput over the standard SPI mode. This mode

transfers the command on the SI pin, but the address and data are transferred on the SI, SO, WP, and HOLD pins. This means

that only a quarter of the number of clocks are required to transfer the address and data. With the Quad I/O Read Array command,

the SI, WP, and HOLD and SO pins become inputs during the address transfer, and switch to outputs during the data transfer.

Datasheet

21-Apr-2021

Revision E

12

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

6

Commands and Addressing

A valid command or operation must be started by first asserting the CS pin. After the CS pin has been asserted, the host controller

must clock out a valid eight-bit opcode on the SPI bus. Following the opcode, command-dependent information, such as address

and data bytes, can be clocked out by the host controller. All opcode, address, and data bytes are transferred with the most-

significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25SF161B are ignored by the device, and no operation is started. The device continues to ignore

any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). If the CS pin

is deasserted before complete opcode, and address information is sent to the device, no operation is performed, and the device

returns to the idle state and waits for the next operation.

Addressing of the device requires three bytes of information to be sent, representing address bits A23-A0. Since the upper

address limit of the AT25SF161B memory array is 1FFFFFh, address bits A23-A21 are ignored by the device.

Table 4: AT25SF161B Command Table

Bus Transfer

Command

Opcode

Mode Bit Mode Bit Wait Cycle Dum-

Data

Bytes

Command Name

Type

Present

Clocks

my Clocks

(OP-AD-DA) ¹

System Commands

Enable Reset

66h

99h

B9h

ABh

1-0-0

N

0

Reset Device

Deep Power-down

Release Power-down

Read Commands

Normal Read Data

03h

0Bh

3Bh

BBh

6Bh

EBh

1-1-1

1-1-2

1-2-2

0-2-2

1-1-4

1-4-4

N

Y

N

Y

0

4

0

2

0

8

0

8

4

1+

Fast Read

Dual Output Fast read

Dual I/O Fast read

Dual I/O Fast read (Continuous Mode)

Quad Output Fast read

Quad I/O Fast read

Quad I/O Fast read (Continuous

Mode)

EBh

E7h

77h

0-4-4

1-4-4

0-4-4

1-0-4

Y

N

2

0

4

2

6

1+

Word Read Quad I/O

Word Read Quad I/O (Continuous

Mode)

1+

Set Burst With Wrap

Write Commands

Write Enable

1, D[6:4]

06h

50h

04h

1-0-0

N

0

Volatile SR Write Enable

Write Disable

Datasheet

21-Apr-2021

Revision E

13

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Table 4: AT25SF161B Command Table (Continued)

Bus Transfer

Type

Command

Opcode

Mode Bit Mode Bit Wait Cycle Dum-

Data

Bytes

Command Name

Present

Clocks

my Clocks

(OP-AD-DA) ¹

Program Commands

Page Program

02h

32h

1-1-1

1-1-4

N

0

1+

Quad Page Program

Erase Commands

Block Erase (4KB)

20h

52h

1-1-0

1-0-0

N

0

Block Erase (32KB)

Block Erase (64KB)

D8h

Chip Erase

C7h/60h

Suspend/Resume Commands

Program/Erase Suspend

75h

7Ah

1-0-0

N

0

Program/Erase Resume

Status Register Commands

Read Status Register 1

05h

35h

15h

01h

31h

11h

1-0-1

N

0

1

Read Status Register 2

Read Status Register 3

Write Status Register 1

Write Status Register 2

Write Status Register 3

Device Information Commands

Manufacturer/Device ID

90h

92h

94h

9Fh

1-1-1

1-2-2

1-4-4

1-0-1

N

0

4

0

2

3

Mfgr./Device ID Dual I/O

Mfgr./Device ID Quad I/O

Read JEDEC ID

Read Serial Flash Discoverable

Parameter

5Ah

1-1-1

N

0

8

1+

OTP Commands

Erase Security Registers

44h

42h

48h

4Bh

1-1-0

1-1-1

1-0-1

N

0

Program Security Registers

Read Security Registers

Read Unique ID Number

1+

8

32

1. OP = Opcode (command number), AD = Address. DA = Data. 0 indicates the corresponding transfer does not occur in that command. 1 indicates the transfer

does occur. For example, 1-0-0 indicates a command transfer occurs, but no address or data transfers occur.

^{Op: Opcode or Commands (8-bits): 0}→ No Opcode [continuous Read], 1 → 8 clocks for Opcode, 2 → 4 clocks for Opcode, 4 → 2 clocks for opcode.

^{AD: Address (24-bits) Only: 0}→ No address, Opcode only operation, 1 → 24 clocks for Address, 2 → 12 clocks for address, 4 → 6 clocks for address.

^{AD: Address (24-bits) + Mode (8-bits): 2}→ 12 clocks for address, 4 clocks for mode [BBh only], 4 → 6 clocks for address, 2 clocks for mode [EBh and E7h].

^{DA: Data(8-bits): 1}→ 8 clocks for Byte, 2 → 4 clocks for Byte, 4 → 2 clocks for Byte.

Datasheet

21-Apr-2021

Revision E

14

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7

Read Commands

7.1 READ ARRAY (0BH AND 03H)

The Read Array command can be used to sequentially read a continuous stream of data from the device by providing the clock

pin once the initial starting address is specified. The device incorporates an internal address counter that automatically increments

every clock cycle.

To perform the Read Array operation, the CS pin first must be asserted, and the appropriate opcode (0Bh or 03h) must be clocked

into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address

location of the first byte to read within the memory array. If the 0Bh opcode is used for the Read Array operation, an additional

dummy byte must be clocked into the device after the three address bytes.

After the three address bytes (and the dummy byte, if using opcode 0Bh) have been clocked in, additional clock cycles result in

data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (1FFFFFh) of the

memory array has been read, the device continues reading back at the beginning of the array (000000h). No delays are incurred

when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. The CS pin can be

deasserted at any time and does not require a full byte of data be read.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

MSB

0

1

A

MSB

A

DATA BYTE 1

High-Impedance

D

MSB

D

MSB

D

SO

Figure 6: Read Array - 03h Opcode

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

OPCODE

ADDRESS BITS A23-A0

DON'T CARE

0

MSB

0

1

0

1

A

MSB

A

X

MSB

DATA BYTE 1

High-Impedance

D

MSB

D

MSB

D

SO

Figure 7: Read Array - 0Bh Opcode

Datasheet

21-Apr-2021

Revision E

15

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.2 DUAL-OUTPUT READ ARRAY (3BH)

The Dual-Output Read Array command is similar to the standard Read Array command; it can be used to sequentially read a

continuous stream of data from the device by providing the clock pin once the initial starting address has been specified. Unlike

the standard Read Array command, the Dual-Output Read Array command allows two bits of data to be clocked out of the device

on every clock cycle, rather than just one.

To perform the Dual-Output Read Array operation, the CS pin must first be asserted; then, the opcode 3Bh must be clocked into

the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first

byte to read within the memory array. Following the three address bytes, a single dummy byte also must be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles output data on both the SO and

SI pins. The data is output with the MSB of a byte first, and the MSB is output on the SO pin. During the first clock cycle, bit seven

of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the next clock cycle,

bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues with each byte of

data being output after every four clock cycles. When the last byte (1FFFFFh) of the memory array has been read, the device

continues reading from the beginning of the array (000000h). There are no delays because of wrapping around from the end of

the array to the beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI (SIO)

SO

ꢃꢖꢐꢄꢖꢐ

ꢆꢌꢐꢌꢎꢂꢗꢐꢇꢋ ꢆꢌꢐꢌꢎꢂꢗꢐꢇꢑ

ꢃꢖꢐꢄꢖꢐ

ꢃꢄꢅꢃꢆꢇ

ꢌꢆꢆꢍꢇꢁꢁꢎꢂꢏꢐꢁꢎꢌꢑꢊꢒꢌꢓꢎ

ꢆꢃꢔꢕꢐꢎꢎꢅꢌꢍꢇ

D

4

D

2

D

4

D

2

D

4

0

1

0

1

A

X

6

0

6

0

6

ꢀꢁꢂ

ꢘꢏꢙꢘꢒꢏꢀꢄꢇꢆꢌꢔꢅꢇ

ꢆ

ꢈ

ꢆ

ꢉ

ꢆ

ꢊ

ꢆ

7

ꢆ

ꢉ

ꢆ

ꢊ

ꢆ

ꢈ

ꢆ

ꢉ

ꢋ

ꢀꢁꢂ

Figure 8: Dual-Output Read Array

Datasheet

21-Apr-2021

Revision E

16

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.3 DUAL-I/O READ ARRAY (BBH)

The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially read a

continuous stream of data from the device by providing the clock pin once the initial starting address with two bits of address on

each clock and two bits of data on every clock cycle.

To perform the Dual-I/O Read Array operation, the CS pin must first be asserted; then, the opcode BBh must be clocked into the

device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte

to read within the memory array. Following the three address bytes, a single mode byte also must be clocked into the device.

After the three address bytes and the mode byte have been clocked in, additional clock cycles output data on both the SO and

SI pins. The data is always output with the MSB of a byte first, and the MSB is always output on the SO pin. During the first clock

cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the

next clock cycle, bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues

with each byte of data output after every four clock cycles. When the last byte (1FFFFFh) of the memory array has been read,

the device continues reading from the beginning of the array (000000h). No delays are incurred when wrapping around from the

end of the array to the beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins

into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12

19 20 21 22 23 24 25 26 27

SCK

Address Bits

A23-A16

Address Bits

A15-A8 A7-A0

Opcode

M7-M0

M₂M₀

Byte 1

D₂D₀

Byte 2

1

0

1

0

1

A

22

A

20

A

18

A

16

A

14

A

0

M

6

M

4

D

6

D

4

D

6

I/O₀

(SI)

MSB

M₃M₁

D₃D₁

D

I/O₁

(SO)

A

23

A

21

A

19

A

17

A

15

A

1

M

7

M

5

D

7

D

5

7

MSB

Figure 9: Dual I/O Read Array (Initial command or previous M5,M4 ≠ 1,0)

Datasheet

21-Apr-2021

Revision E

17

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.3.1 Dual-I/O Read Array (BBh) with Continuous Read Mode

The Fast Read Dual I/O command can further reduce command overhead through setting the Continuous Read Mode bits (M7-

0) after the input Address bits (A23-0), as shown in Figure 10. The upper nibble of M7-4 controls the length of the next Fast Read

Dual I/O command through the inclusion, or exclusion, of the first byte command code. The lower nibble bits of M3-0 are don't

care (“x”). However, the I/O pins must be high-impedance prior to the falling edge of the first data out clock. If the “Continuous

Read Mode” bits M5-4 = (1,0), the next Fast Read Dual I/O command (after CS is raised and then lowered) does not require the

BBh command code. This reduces the command sequence by eight clocks and allows the Read address to be immediately

entered after CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after CS is

raised and then lowered) requires the first byte command code, thus returning to normal operation. A Continuous Read Mode

Reset command can also be used to reset M7-0 before issuing normal commands.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

SCK

Address Bits

A23-A16

Address Bits

A7-A0

M7-M0

Byte 1

Byte 2

A15-A8

A

M₂M₀

D₂D₀

A

22

A

20

A

18

A

16

A

14

A

0

M

6

M

4

D

6

D

4

D

6

I/O₀

(SI)

MSB

M₃M₁

D₃D₁

I/O₁

(SO)

A

23

A

21

A

19

A

17

A

15

A

1

7

M

5

7

D

5

7

MSB

Figure 10: Dual-I/O Read Array (Previous command set M5, M4 = 1,0)

Datasheet

21-Apr-2021

Revision E

18

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.4 QUAD OUTPUT FAST READ ARRAY (6BH)

The Quad-Output Read Array command is followed by a three-byte address (A23 - A0) and one dummy byte, each bit being

latched in during the rising edge of SCLK; then, the memory contents are shifted out four bits per clock cycle from I/O₃, I/O₂, I/

O₁, and I/O₀. The first byte addressed can be at any location. The address automatically increments to the next higher address

after each byte of data is shifted out.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Byte 1 Byte 2 Byte 3 Byte 4 Byte 5

SCK

OUT

Opcode

Address Bits A23-A0

Don't Care

0

ꢀꢁꢂ

1

0

1

0

1

A

ꢀꢁꢂ

A

X

ꢀꢁꢂ

X

D₄D₀D₄D₀D₄D₀D₄D₀D₄D₀

D₅D₁D₅D₁D₅D₁D₅D₁D₅D₁

D₆D₂D₆D₂D₆D₂D₆D₂D₆D₂

I/O₀

(SI)

High-Impedance

I/O₁

(SO)

I/O₂

(WP)

D₇D₃D₇D₃D₇D₃D₇D₃D₇D₃

I/O₃

(HOLD)

MSB

Figure 11: Quad-Output Read Array

Datasheet

21-Apr-2021

Revision E

19

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.5 QUAD-I/O READ ARRAY (EBH)

The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. It allows four bits of address to be

clocked into the device on every clock cycle, rather than just one.

To perform the Quad-I/O Read Array operation, the CS pin must first be asserted; then, the opcode EBh must be clocked into the

device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte

to read within the memory array. Following the three address bytes, a single mode byte must also be clocked into the device.

After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles output data on

the I/O_3-0pins. The data is output with the MSB of a byte first, and the MSB is output on the I/O₃pin. During the first clock cycle,

bit 7 of the first data byte is output on the I/O₃pin while bits 6, 5, and 4 of the same data byte are output on the I/O₂, I/O₁, and I/

O₀pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte are output on the I/O₃, I/O₂, I/O₁and I/

O₀pins, respectively. The sequence continues with each byte of data being output after every two clock cycles.

When the last byte (1FFFFFh) of the memory array has been read, the device continues reading from the beginning of the array

(000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the

CS pin terminates the read operation and puts the I/O₃, I/O₂, I/O₁, and I/O₀pins into a high-impedance state. The CS pin can be

deasserted at any time and does not require a full byte of data to be read. The Quad Enable bit (QE) of the Status Register must

be set to enable for the Quad-I/O Read Array command.

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Opcode

A23-A16 A15-A8

A7-A0

M7-M0

Dummy

Byte 1

Byte 2

D₀D₄

I/O0

D

4

D

0

1

0

1

0

1

A

20

A

16

A

12

A

8

A

4

A0 M4 M0

(SI)

MSB

D₁D₅

D₂D₆

D₃D₇

D

5

D

1

I/O₁

A

21

A

17

A

13

A

9

A

5

A1 M5 M1

(SO)

I/O₂

D

6

D2

A

22

A

18

A14

A

10

A

6

A2 M6 M2

(WP)

I/O₃

D

7

D3

A

23

A19

A

15

A

11

A

7

A3 M7 M3

(HOLD)

Figure 12: Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)

Datasheet

21-Apr-2021

Revision E

20

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode

The Read Quad I/O command can further reduce command overhead through setting the Continuous Read Mode bits (M7-0)

after the input Address bits (A23-0), as shown in Figure 12. The upper nibble (M7-4) of the Continuous Read Mode bits controls

the length of the next Fast Read Quad I/O command through the inclusion, or exclusion, of the first byte command code. The

lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins must be high-impedance prior to

the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 = (1,0), the next Quad-I/O Read Array command

(after CS is raised and then lowered) does not require the EBh command code, as shown in Figure 13. This reduces the command

sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the Continuous

Read Mode bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the first byte

command code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset M7-0

before issuing normal commands.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

A23-A16 A15-A8

A7-A0

M7-M0

Dummy

Byte 1

Byte 2

I/O0

D₀D₄

A20

A

16

A12

A

8

A

4

A

0

M

4

M

0

D

4

D

0

(SI)

D₁D₅

D₂D₆

D₃D₇

I/O₁

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

D

5

D

1

(SO)

I/O₂

A

22

A

18

A14

A

10

A

6

A

2

M

6

M

2

D

6

D2

(WP)

I/O₃

A23

A19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

D3

(HOLD)

Figure 13: Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5, M4 = 1,0)

Datasheet

21-Apr-2021

Revision E

21

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.5.2 Set Burst with Wrap (77h)

The Set Burst with Wrap command is used in conjunction with the Quad I/O Fast Read and Quad I/O Word Fast Read command

to access a fixed length (8-, 16-, 32-, or 64-byte) section within a 256-byte page in standard SPI mode (see Table 5 and Figure 14).

Table 5: Set Burst with Wrap Command Functions

W4 = 0

W4 = 1 (Default)

W6, W5

Wrap Around

Wrap Length

8 bytes

Wrap Around

Wrap Length

0

1

0

1

0

1

Yes

No

N/A

16 bytes

32 bytes

64 bytes

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

Opcode

Byte 3

Byte 1 Byte 2

Byte 4

High-Impedance

I/O

0

(SI)

1

0

1

X

W

4

X

MSB

High-Impedance

I/O

1

W5

(SO)

I/O

2

(WP)

W

6

I/O

3

(HOLD)

X

Figure 14: Set Burst with Wrap Timing (SPI Mode)

The Set Burst with Wrap command sequence is: CS goes low → Send Set Burst with Wrap command → Send 24 Dummy bits

→ Send 8 “Wrap bits” → CS goes high.

If W6-4 is set by a Set Burst with Wrap command, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” commands

use the W6-4 setting to access the 8-, 16-, 32-, or 64-byte section within any page. To exit the “Wrap Around” function and return

to normal read operation, issue another Set Burst with Wrap command to set W4=1. The default value of W4 at power-on is 1.

Datasheet

21-Apr-2021

Revision E

22

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.6 QUAD-I/O WORD FAST READ (E7H)

The Quad I/O Word Fast Read command is similar to the Quad Fast Read command, except that the lowest address bit (A0)

must equal 0 and have two dummy clock cycles. Figure 15 shows the command sequence; the first byte addressed can be at

any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad

Enable bit (QE) of the Status Register (S9) must be set to enable.

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Opcode

A23-A16 A15-A8

A7-A0

M7-M0 Dummy

Byte 3

Byte 1

Byte 2

D₄

0

D₀D₄

I/O

0

D

0

1

0

1

A

20

A

16

A

12

A

8

A

4

A

0

M

4

M

0

D

4

D

(SI)

MSB

D₅

D₆

D₇

D₁D₅

D₂D₆

D₃D₇

I/O₁

D

5

D

1

D

1

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

(SO)

I/O₂

D

2

A

22

A

18

A

14

A

10

A

6

A

2

M

6

M

2

D

6

D

2

(WP)

I/O₃

D

3

A23

A

19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

D

3

(HOLD)

Figure 15: Quad I/O Word Fast Read Timing (Initial Command Set M5, M4 ≠ 1,0) SPI Mode

7.6.1 Quad I/O Word Fast Read with “Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead by setting the “Continuous Read Mode” bits

(M7-0) after input of the Address bits (A23-0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), the next Quad I/O Fast Read

command (after CS is raised and then lowered) does not require the E7h command code. Figure 16 shows the command

sequence. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command requires the first E7h command

code, thus returning to normal operation. A “Continuous Read Mode” Reset command also can be used to reset (M5-4) before

issuing normal command.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

A23-A16 A15-A8

A7-A0

M7-M0 Dummy

Byte 3

Byte 1

Byte 2

D₄

0

I/O0

D₀D₄

D

0

A20

A

16

A

12

A

8

A

4

A

0

M

4

M

0

D

4

D

(SI)

D₅

D₆

D₇

D₁D₅

D₂D₆

D₃D₇

I/O₁

D

1

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

D

5

D

1

(SO)

I/O₂

D

2

A

22

A

18

A

14

A

10

A

6

A

2

M

6

M

2

D

6

D

2

(WP)

I/O₃

D

3

A23

A

19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

D

3

(HOLD)

Figure 16: Quad I/O Word Fast Read Timing (Previous Command Set M5, M4 = 1,0) SPI Mode

Datasheet

21-Apr-2021

Revision E

23

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.6.2 Quad I/O Word Fast Read with 8-, 16-, 32-, 64-Byte Wrap Around in Standard SPI Mode

The Quad I/O Fast Read command also can be used to access a specific portion within a page by issuing a Set Burst with Wrap

(77h) command prior to E7h. The Set Burst with Wrap (77h) command can enable or disable the Wrap Around feature for the

following E7h commands. When enabled, the data accessed can be limited to an 8-, 16-, 32-, or 64-byte section of a 256-byte

page. The output data starts at the initial address specified in the command when it reaches the ending boundary of the 8-, 16-,

32-, or 64-byte section. The output wraps around to the beginning boundary automatically until CS is pulled high to terminate the

command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards

within a fixed length (8-, 16-, 32-, or 64-bytes) of data without issuing multiple read commands.

The Set Burst with Wrap command allows three Wrap Bits (W6-4) to be set. W4 enables or disables the wrap around operation;

W5 specifies the length of the wrap around section within a page.

7.7 READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature

capabilities of serial Flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by

host system software to enable adjustments needed to accommodate divergent features from multiple vendors. SFDP is a JEDEC

Standard, JESD216D. For more detailed SFDP values, contact Dialog Semiconductor.

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Figure 17: Read Serial Flash Discoverable Parameter Command Timing

Datasheet

21-Apr-2021

Revision E

24

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

8

Program and Erase Commands

8.1 BYTE/PAGE PROGRAM (02H)

The Byte/Page Program command allows one to 256 bytes of data to be programmed into previously erased memory locations.

An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page

Program command can be started, the Write Enable command must have been issued to the device (see “Write Enable (06h)”,

on page 30) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device, followed by the three address

bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked

in, data can then be clocked into the device and is stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all 0), special

circumstances regarding which memory locations to be programmed apply. In this situation, any data that is sent to the device

that goes beyond the end of the page wraps around back to the beginning of the same page. For example, if the starting address

denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, the first two bytes of data are programmed at

addresses 0000FEh and 0000FFh, and the last byte of data is programmed at address 000000h. The remaining bytes in the page

(addresses 000001h through 0000FDh) are not programmed and remain in the erased state (FFh). Also, if more than 256 bytes

of data are sent to the device, only the last 256 bytes sent are latched into the internal buffer.

When the CS pin is deasserted, the device takes the data stored in the internal buffer and programs it into the appropriate memory

array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If fewer than

256 bytes of data were sent to the device, the remaining bytes within the page are not programmed and remain in the erased

state (FFh). The programming of the data bytes is internally self-timed and, if only programming a single byte, must take place in

a time of t_PPor t_BP

.

The three address bytes and at least one complete data byte must be clocked into the device before the CS pin is deasserted,

and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device aborts the operation

and no data is programmed into the memory array. Also, if the memory is in the protected state, the Byte/Page Program command

is not executed, and the device returns to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register

is reset to the logical “0” state if: the program cycle aborts due to an incomplete address being sent, an incomplete byte of data

is sent, the CS pin is deasserted on uneven byte boundaries, or the memory location to be programmed is protected.

While the device is programming, the Status Register can be read and indicates that the device is busy. For faster throughput, it

is recommended that the Status Register be polled, rather than waiting the t_BPor t_PPtime to determine if the data bytes have

finished programming. At some point before the program cycle completes, the WEL bit in the Status Register is reset to the logical

“0” state.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN

0

MSB

0

1

0

A

MSB

A

D

MSB

D

High-Impedance

SO

Figure 18: Byte Program

Datasheet

21-Apr-2021

Revision E

25

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

CS

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN BYTE 1

DATA IN BYTE n

0

MSB

0

1

0

A

D

MSB

D

MSB

D

MSB

High-Impedance

SO

Figure 19: Page Program Timing

8.2 QUAD PAGE PROGRAM (32H)

This command is for programming the memory using pins: IO0, IO1, IO2, and IO3. To use this command, the Quad enable (bit 9

in Status Register) must be set (QE=1). A Write Enable command must previously have been executed to set the Write Enable

Latch bit before sending the Page Program command. The Quad Page Program command is entered by driving CS low, followed

by the command code (32H), three address bytes, and at least one data byte on I/O pins.

Figure 20 shows the command sequence. If more than 256 bytes are sent to the device, previously latched data are discarded,

and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If fewer than 256 data bytes are

sent to device, they are correctly programmed at the requested addresses without affecting other bytes of the same page. CS

must be driven high after the eighth bit of the last data byte has been latched in; otherwise, the Quad Page Program command

is not executed.

As soon as CS is driven high, the self-timed Quad Page Program cycle (whose duration is t_PP) is initiated. While the Quad Page

Program cycle is in progress, the Status Register can be read to check the value of the Write in Progress (WIP) bit. The Write In

Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle; it is 0 when done. At some unspecified time before the

cycle is completed, the Write Enable Latch bit is reset. A Quad Page Program command applied to a page which is protected by

the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6 and Table 7) is not executed.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41

DATA DATA DATA DATA DATA

SCK

IN 1

IN 2

IN 3

IN 4

IN 5

COMMAND

Address Bits A23-A0

C

D₄D₀D₄D₀D₄D₀D₄D₀D₄D₀

D₅D₁D₅D₁D₅D₁D₅D₁D₅D₁

D₆D₂D₆D₂D₆D₂D₆D₂D₆D₂

C

A

I/O₀

(SI)

High-Impedance

I/O₁

(SO)

I/O₂

(WP)

D₇D₃D₇D₃D₇D₃D₇D₃D₇D₃

I/O₃

(HOLD)

MSB

Figure 20: Quad Page Program (32h) Timing

Datasheet

21-Apr-2021

Revision E

26

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

8.3 BLOCK ERASE (20H, 52H, OR D8H)

A block of 4-, 32-, or 64-kbyte can be erased (all bits set to the logical “1” state) in a single operation by using one of three different

opcodes for the Block Erase command. An opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte

erase, and D8h is used for a 64-kbyte erase. Before a Block Erase command can be started, the Write Enable command must

have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into

the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32- or 64-kbyte

block to be erased must be clocked in. Any additional data clocked into the device is ignored. When the CS pin is deasserted,

the device erases the appropriate block. The erasing of the block is internally self-timed and takes place in a time of t_BLKE

.

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device.

Therefore, for a 4-kbyte erase, address bits A11-A0 are ignored by the device, and their values can be either a logical “1” or “0”.

For a 32-kbyte erase, address bits A14-A0 are ignored by the device. For a 64-kbyte erase, address bits A15-A0 are ignored by

the device. Despite the lower-order address bits not being decoded by the device, the complete three address bytes must still be

clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of

eight bits); otherwise, the device aborts the operation, and no erase operation is performed.

If the memory is in the protected state, the Block Erase command is not executed, and the device returns to the idle state once

the CS pin has been deasserted.

The WEL bit in the Status Register is reset to the logical “0” state if: the erase cycle aborts due to an incomplete address being

sent, the CS pin is deasserted on uneven byte boundaries, or because a memory location within the region to be erased is

protected.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the device is busy. For

faster throughput, poll the Status Register to determine if the device has finished erasing. At some point, before the erase cycle

completes, the WEL bit in the Status Register is reset to the logical “0” state.

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High-Impedance

ꢁꢃ

Figure 21: Block Erase

8.4 CHIP ERASE (60H OR C7H)

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command

can be started, the Write Enable command must have been previously issued to the device; this sets the WEL bit of the Status

Register to a logical “1” state.

Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device functionality when using

the two opcodes; thus, they can be used interchangeably. To perform a Chip Erase, one of the two opcodes must be clocked into

the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data

clocked in after the opcode is ignored. When the CS pin is deasserted, the device erases the entire memory array. The erasing

of the device is internally self-timed and takes place in a time of t_CHPE

.

Datasheet

21-Apr-2021

Revision E

27

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on

an byte boundary (multiples of eight bits); otherwise, no erase is performed. Also, if the memory array is in the protected state,

the Chip Erase command is not executed, and the device returns to the idle state once the CS pin has been deasserted. The

WEL bit in the Status Register is reset to the logical “0” state if the CS pin is deasserted on uneven byte boundaries, or if the

memory is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the device is busy. For

faster throughput, it is recommended that the Status Register be polled to determine if the device has finished erasing. At some

point before the erase cycle completes, the WEL bit in the Status Register is reset to the logical “0” state.

8.5 PROGRAM/ERASE SUSPEND (75H)

The Program/Erase Suspend command allows an in-progress program or erase operation to be suspended so that other device

operations can be performed. For example, by suspending an erase operation to a particular block, the system can perform

functions such as a program or read to a different block.

Chip Erase cannot be suspended. The Program/Erase Suspend command is ignored if it is issued during a Chip Erase. Aprogram

operation can be performed while an erase operation is suspended, but the program operation cannot be suspended while an

erase operation is currently suspended.

Other device operations, such as a Read Status Register, can also be performed while a program or erase operation is suspended.

Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need to be issued

prior to the Program/Erase Suspend command being issued. Thus, the Program/Erase Suspend command operates inde-

pendently of the state of the WEL bit in the Status Register.

To perform a Program/Erase Suspend, the CS pin must first be asserted, and the 75h opcode must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the program or erase operation currently in progress is suspended. The Suspend (E_SUS or P_SUS) bits in the Write

Status Register are set to the logical “1” state to indicate that the program or erase operation has been suspended. Also, the RDY/

BSY bit in the Status Register indicates that the device is ready for another operation. The complete opcode must be clocked into

the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits);

otherwise, no suspend operation is performed.

If a read operation is attempted to a suspended area (page for programming or block for erasing), the device outputs undefined

data. Thus, when performing a Read Array operation to an unsuspended area, and the device's internal address counter incre-

ments and crosses into the suspended area, the device starts outputting undefined data until the internal address counter crosses

to an unsuspended area.

A program operation is not allowed to a block that has been erase suspended. If a program operation is attempted to an erase

suspended block, then the program operation aborts, and the WEL bit in the Status Register is reset to a logical “0” state. Likewise,

an erase operation is not allowed to a block that included the page that has been program suspended. If attempted, the erase

operation aborts, and the WEL bit in the Status Register is reset to a logical “0” state.

If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a Write Status

Register operation, the device ignores the opcode, and no operation is performed. The state of the WEL bit in the Status Register

is not affected.

Note: Repeated suspend/resume sequences might significantly impact progress of the erase or program operation. To ensure

timely completion of the erase or program operation, limit the number of suspend/resume sequences during the same erase or

program operation; alternatively, provide sufficient time (up to 60 ms) after a resume operation to allow the erase or program

operation to complete.

Datasheet

21-Apr-2021

Revision E

28

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

8.6 PROGRAM/ERASE RESUME (7AH)

The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue program-

ming a Flash page or erasing a Flash memory block where it left off. The Program/Erase Resume command is accepted by the

device only if the E_SUS or P_SUS bits in the Write Status Register is 1, and the RDY/BSY bit is 0. If the E_SUS or P_SUS bits

is 0, or the RDY/BSY bit is 1, the Program/Erase Resume command is ignored by the device. As with the Program/Erase Suspend

command, the Write Enable command does not need to be issued before to the Program/Erase Resume command is issued.

Thus, the Program/Erase Resume command operates independently of the state of the WEL bit in the Status Register.

To perform Program/Erase Resume, the CS pin must first be asserted, and opcode 7Ah must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the program or erase operation currently suspended resumes. The E_SUS or P_SUS bit in the Status Register is

reset back to the logical “0” state to indicate the program or erase operation is no longer suspended. Also, the RDY/BSY bit in

the Status Register indicates that the device is busy performing a program or erase operation. The complete opcode must be

clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of

eight bits); otherwise, no resume operation is performed.

During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command results in the

program operation resuming first. After the program operation has been completed, the Program/Erase Resume command must

be issued again for the erase operation to be resumed.

While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend command

are ignored. Thus, if a resumed program or erase operation needs to be subsequently suspended again, the system must either

wait before issuing the Program/Erase Suspend command, or it must check the status of the RDY/BSY bit or the E_SUS or P_SUS

bit in the Status Register to determine if the previously suspended program or erase operation has resumed.

Datasheet

21-Apr-2021

Revision E

29

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

9

Protection Commands and Features

9.1 WRITE ENABLE (06H)

The Write Enable command sets the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must

be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register Pages or Write Status

Register command can be executed. This makes the issuance of these commands a two step process, thus reducing the chances

of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of

one of these commands, the command is not executed.

To issue the Write Enable command, the CS pin must first be asserted, and the opcode of 06h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the WEL bit in the Status Register is set to a logical “1”. The complete opcode must be clocked into the device before

the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device

aborts the operation, and the WEL bit state does not change.

9.2 WRITE DISABLE (04H)

The Write Disable command resets the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state. With the WEL

bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register commands are not executed.

Other conditions can also cause the WELbit to be reset; for more details, see the WELbit section of the Status Register description

(Section 9.1).

To issue the Write Disable command, the CS pin must be asserted first, and the opcode of 04h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the WEL bit in the Status Register is reset to a logical “0”. The complete opcode must be clocked into the device

before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the

device aborts the operation, and the WEL bit state does not change.

Datasheet

21-Apr-2021

Revision E

30

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

9.3 NON-VOLATILE PROTECTION

The device can be software-protected against erroneous or malicious program or erase operations by using the Non-Volatile

Protection feature. This feature can be enabled or disabled by using the Write Status Register command to change the value of

the Protection (CMP, BP4, BP3, BP2, BP1, BP0) bits in the Status Register. Table 6 outlines the states of the Protection bits and

the associated protection area.

Table 6: Memory Array with CMP = 0

Protection Bits

Memory Content

BP4

X

0

BP3

X

0

BP2

0

BP1

BP0

0

Address Range

None

Portion

None

0

1

0

1

0

1

0

1

0

1

0

1

1F0000h - 1FFFFFh

1E0000h - 1FFFFFh

1C0000h - 1FFFFFh

180000h - 1FFFFFh

100000h - 10FFFFh

000000h - 00FFFFh

000000h - 01FFFFh

000000h - 03FFFFh

000000h - 07FFFFh

000000h - 0FFFFFh

000000h - 1FFFFFh

1FF000h - 1FFFFFh

1FE000h - 1FFFFFh

1FC000h - 1FFFFFh

1F8000h - 1FFFFFh

000000h - 000FFFh

000000h - 001FFFh

000000h - 003FFFh

000000h - 007FFFh

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

Lower 1/32

Lower 1/16

Lower 1/8

Lower 1/4

Lower 1/2

ALL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

X

0

1

X

1

0

Upper 1/512

Upper 1/256

Upper 1/128

Upper 1/64

Lower 1/512

Lower 1/256

Lower 1/128

Lower 1/64

1

0

1

0

1

0

1

X

1

0

1

0

1

0

1

X

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Revision E

31

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Table 7: Memory Array Protection with CMP = 1

Protection Bits

Memory Content

BP4

X

0

BP3

X

0

BP2

0

BP1

0

BP0

0

Address Range

000000h - 1FFFFFh

000000h - 1EFFFFh

000000h - 1DFFFFh

000000h - 1BFFFFh

000000h - 17FFFFh

000000h - 0FFFFFh

010000h - 1FFFFFh

020000h - 1FFFFFh

040000h - 1FFFFFh

080000h - 1FFFFFh

100000h - 1FFFFFh

NONE

Portion

All

0

1

Lower 31/32

Lower 15/16

Lower 7/8

0

1

0

1

0

1

0

Lower 3/4

0

1

0

1

Lower 1/2

0

1

0

1

Upper 31/32

Upper 15/16

Upper 7/8

0

1

0

1

0

1

0

1

0

1

0

Upper 3/4

0

1

0

1

Upper 1/2

X

1

X

0

1

X

1

NONE

0

000000h - 1FEFFFh

000000h - 1FDFFFh

000000h - 1FBFFFh

000000h - 1F7FFFh

001000h - 1FFFFFh

002000h - 1FFFFFh

004000h - 1FFFFFh

008000h - 1FFFFFh

Lower 511/512

Lower 255/256

Lower 127/128

Lower 63/64

Upper 511/512

Upper 255/256

Upper 127/128

Upper 63/64

1

0

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

X

As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be locked from

updates by using the WP pin (see “Protected States and the Write Protect Pin”, on page 32, for more details).

9.4 PROTECTED STATES AND THE WRITE PROTECT PIN

The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead,

it controls the hardware locking mechanism of the device.

If the WP pin is permanently connected to GND, then the protection bits cannot be changed.

Datasheet

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Revision E

32

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

9.5 ENABLE RESET (66H) AND RESET DEVICE (99H)

Because of the small package and the limitation on the number of pins, the AT25SF161B provides a software Reset command

instead of a dedicated RESET pin. Once the software Reset command is accepted, any on-going internal operations are termi-

nated, and the device returns to its default power-on state and loses all the current volatile settings, including the Volatile Status

Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0), and

Wrap Bit setting (W6-W4).

To avoid accidental reset, the Enable Reset and Reset Device commands must be issued in sequence. Any other commands

other than Reset (99h) after the Enable Reset (66h) command disables the Reset Enable state. A new sequence of Enable Reset

and Reset Device is needed to reset the device. Once the Reset command is accepted by the device, the device takes approxi-

mately 30 µs to reset. During this period, no command is accepted.

The Enable Reset and Reset Device command sequence are shown in Figure 22.

Data corruption can happen if there is an on-going or suspended internal Erase or Program operation when the Reset command

sequence is accepted by the device. Check the BUSY bit and the E_SUS and P_SUS bits in the Status Register before issuing

the Reset command sequence.

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

0

ꢋ

1

0

1

0

1

0

1

0

Figure 22: Enable Reset (66h) and Reset Device (99h) Command Timing (SPI Mode)

Datasheet

21-Apr-2021

Revision E

33

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

10 Security Register Commands

The device contains three extra Security Register pages that can be used for unique device serialization, system-level Electronic

Serial Number (ESN) storage, locked key storage, etc. The Security Registers are independent of the main Flash memory.

Each page of the Security Register can be erased and programmed independently. Each page can also be independently locked

to prevent further changes.

10.1 READ UNIQUE ID NUMBER (4BH)

The Read Unique ID Number command accesses a factory-set, read-only 64-bit number that is unique to each AT25SF161B

device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system.

The Read Unique ID command is initiated by driving the CS pin low and shifting the command code 4Bh, followed by four dummy

byte clock cycles. After this, the 64-bit ID is shifted out on the falling edge of SCLK, as shown in Figure 23.

CS

19

Mode

13 14 15

20 21 22

0

1

2

3

4

5

6

7

8

9

10 11

Dummy Byte

16 17 18

23

3

0

12

SCK

SI

Command

1

Dummy Byte

2

4

Bh

High-Impedance

SO

CS

_

26

23

25

27 28 29 30

33

40

103

102

24

34

36 37 38 39

100 101

Mode3

Mode0

31 32

35

41

SCK

Dummy Byte 3

Dummy Byte

4

SI

High-Impedance

_

SO

1

2

63 62

MSB

0

bit Unique

Serial Number

64-

Figure 23: Read Unique ID Timing (SPI Mode)

10.2 ERASE SECURITY REGISTERS (44H)

Before an erase Security Register Page command can be started, the Write Enable command must have been previously issued

to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform an Erase Security Register Page command, the CS pin must be asserted first, and the opcode 44h must be clocked

into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register Page to be erased

must be clocked in. When the CS pin is deasserted, the device erases the appropriate page. The erasing of the page is internally

self-timed and takes place in a time of t_PP

.

Since the Erase Security Register Page command erases a region of bytes, the lower-order address bits do not need to be

decoded by the device. Thus, address bits A7-A0 are ignored by the device. Despite the lower-order address bits not being

decoded by the device, the complete three address bytes must be clocked into the device before the CS pin is deasserted, and

the CS pin must be deasserted right after the last address bit (A0); otherwise, the device aborts the operation, and no erase

operation is performed.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the device is busy. For

faster throughput, it is recommended that the Status Register be polled (rather than waiting the t_PPtime to determine if the device

has finished erasing). At some point before the erase cycle completes, the RDY/BSY bit in the Status Register is reset to the

logical “0” state.

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Revision E

34

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

The WEL bit in the Status Register is reset to the logical “0” state if: the erase cycle aborts due to an incomplete address being

sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is

protected.

The Security Registers Lock Bits (LB3 - LB1) in the Status Register can be used to OTP protect the security registers. Once a

Lock Bit is set to 1, the corresponding Security Register is permanently locked. The Erase Security Register Page command is

ignored for Security Registers with their Lock Bit set.

Table 8: Security Register Addresses for Erase Security Register Page Command

Address

A23 - A16

00h

A15 - A12

A11 - A8

A7 - A0

Security Register 1

Security Register 2

Security Register 3

1h

2h

3h

0h

Don’t Care

00h

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

29 30 31

OPCODE

24-BIT ADDRESS

0

MSB

1

0

1

0

A

Figure 24: Erase Security Register Page

Datasheet

21-Apr-2021

Revision E

35

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

10.3 PROGRAM SECURITY REGISTERS (42H)

The Program Security Registers command uses the internal 256-byte buffer for processing. Thus, the contents of the buffer are

altered from their previous state when this command is issued.

The Security Registers can be programmed in a similar fashion to the ProgramArray operation up to the maximum clock frequency

specified by f_CLK. Before a Program Security Registers command can be started, the Write Enable command must have been

previously issued to the device (see “Write Enable (06h)”, on page 30) to set the Write Enable Latch (WEL) bit of the Status

Register to a logical “1” state. To program the Security Registers, the CS pin must first be asserted, and the opcode of 42h must

be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting

address location of the first byte to program within the Security Register.

CS

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN BYTE 1

DATA IN BYTE n

0

MSB

1

0

1

0

A

D

MSB

D

MSB

D

MSB

High-Impedance

SO

Figure 25: Program Security Registers

Table 9: Security Register Addresses for Program Security Registers Command

Address

A23 - A16

A15 - A12

A11 - A8

A7 - A0

Security Register 1

00h

1h

0h

Byte Address

Security Register 2

Security Register 3

00h

2h

3h

0h

Datasheet

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Revision E

36

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

10.4 READ SECURITY REGISTERS (48H)

The Security Register can be sequentially read in a similar fashion to the ReadArray operation up to the maximum clock frequency

specified by f_CLK. To read the Security Register, the CS pin must first be asserted and the opcode of 48h must be clocked into

the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address

location of the first byte to read within the Security Register. Following the three address bytes, one dummy byte must be clocked

into the device before data can be output.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles result in the Security Register

data being output on the SO pin. When the last byte (0003FFh) of the Security Register has been read, the device continues

reading back at the beginning of the register (000000h). No delays are incurred when wrapping around from the end of the register

to the beginning of the register.

Deasserting the CS pin terminates the read operation and puts the SO pin into a high-impedance state. The CS pin can be

deasserted at any time and does not require that a full byte of data be read.

Table 10: Security Register Addresses for Read Security Registers Command

Address

A23 - A16

A15 - A12

A11 - A8

A7 - A0

Security Register 1

00h

1h

0h

Byte Address

Security Register 2

Security Register 3

00h

2h

3h

0h

Byte Address

ꢅꢁ

ꢁꢅ1

ꢁꢏ

ꢓ

ꢋ

ꢑ

ꢊ

ꢛ

ꢉ

ꢚ

ꢈ

(

ꢜ

ꢋꢓ ꢋꢋ ꢋꢑ

ꢑꢜ ꢊꢓ ꢊꢋ ꢊꢑ ꢊꢊ ꢊꢛ ꢊꢉ ꢊꢚ

ꢃꢄꢅꢃꢆꢇ

ꢌꢆꢆꢍꢇꢁꢁꢎꢂꢏꢐꢁꢎꢌꢑꢊꢒꢌꢓ

ꢆꢃꢔꢕꢐꢎꢅꢌꢍꢇ

ꢓ

ꢋ

ꢓ

ꢋ

ꢓ

ꢌ

2

ꢀꢁꢂ

ꢆꢌꢐꢌꢎꢂꢗꢐꢇꢎꢋ

ꢘ&-.ꢒꢏ*ꢝ#"/0 #

ꢆ

ꢁꢃ

ꢀꢁꢂ

Figure 26: Read Security Registers

Datasheet

21-Apr-2021

Revision E

37

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11 Status Register Commands

11.1 READ STATUS REGISTER (05H, 35H, AND 15H)

The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions, such

as Block Protection. The Status Register can be read at any time, including during an internally self-timed program or erase

operation.

To read Status Register 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the

opcode has been clocked in, the device begins outputting Status Register 1 data on the SO pin during every subsequent clock

cycle. After the last bit (0) of Status Register 1 has been clocked out, the sequence repeats itself, starting again with bit 7, as long

as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated,

so each repeating sequence outputs new data. Deasserting the CS pin terminates the Read Status Register operation and puts

the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data

be read.

Table 11: Status Register 1 Bit Assignments

Bit¹

Mnemonic

Name

Type²

Description

Status Register Protection

bit 0

7

SRP0

R/W

See Table 14 on Status Register Protection.

6

5

4

3

2

BP4

BP3

BP2

BP1

BP0

Block Protection

R/W

Top or Bottom Protection

Block Protection bit 2

Block Protection bit 1

Block Protection bit 0

See Table 6 and Table 7 on Non-Volatile Protection.

0

1

0

1

Device is not Write Enabled (default).

Device is Write Enabled.

1

0

WEL

Write Enable Latch Status

Ready/Busy Status

R

Device is ready.

RDY/BSY

Device is busy with an internal operation.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable; R = Readable only.

&6

ꢃ

ꢂ

ꢀ

ꢁ

ꢇ

ꢆ

ꢄ

ꢅ

ꢉ

ꢈ

ꢂꢃ ꢂꢂ ꢂꢀ ꢂꢁ ꢂꢇ ꢂꢆ ꢂꢄ ꢂꢅ ꢂꢉ ꢂꢈ ꢀꢃ ꢀꢂ ꢀꢀ ꢀꢁ ꢀꢇ ꢀꢆ ꢀꢄ ꢀꢅ ꢀꢉ ꢀꢈ ꢁꢃ

6&.

6,

OPCODE

&

06%

&

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 1

HIGH-IMPEDANCE

'

06%

'

06%

'

06%

'

62

Figure 27: Read Status Register 1

To read Status Register 2, the CS pin must first be asserted, and the opcode of 35h must be clocked into the device. After the

opcode has been clocked in, the device begins outputting Status Register 2 data on the SO pin during every subsequent clock

Datasheet

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Revision E

38

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

cycle. After the last bit (0) of Status Register 2 has been clocked out, the sequence repeats, itself starting again with bit 7, as long

as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated,

so each repeating sequence outputs new data. Deasserting the CS pin terminates the Read Status Register operation and puts

the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data

be read.

Table 12: Status Register 2 Bit Assignments

Bit⁽¹⁾

Name

Type⁽²⁾

Description

0

1

Erase operation is not suspended (default).

7

E_SUS Erase Suspend Status

R

Erase operation is suspended.

Complement Block

Protection

6

5

CMP

R/W

0

See Table 6 and Table 7 on Block Protection.

0

1

0

1

0

1

0

1

0

1

Security Register page-3 is not locked (default).

Security Register page-3 cannot be erased/programmed.

Security Register page-2 is not locked (default).

Security Register page-2 cannot be erased/programmed.

Security Register page-1 is not locked (default).

Security Register page-1 cannot be erased/programmed.

Program operation is not suspended (default).

Program operation is suspended.

LB3

LB2

LB1

Lock Security Register 3

Lock Security Register 2

Lock Security Register 1

4

3

2

R/W

R

P_SUS Program Suspend Status

HOLD and WP function normally (default).

HOLD and WP are I/O pins.

1

0

QE

Quad Enable

R/W

Status Register Protect bit

1

SRP1

See Table 14 on Status Register Protection.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable. R = Readable only.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

SCK

SI

OPCODE

0

1

0

1

0

1

MSB

STATUS REGISTER

BYTE 2

STATUS REGISTER

BYTE 2

STATUS REGISTER

BYTE 2

High-Impedance

D

SO

MSB

Figure 28: Read Status Register 2

To read Status Register 3, the CS pin must first be asserted, and the opcode of 15h must be clocked into the device. After the

opcode has been clocked in, the device begins outputting Status Register 3 data on the SO pin during every subsequent clock

cycle. After the last bit (0) of Status Register 3 has been clocked out, the sequence repeats itself starting again with bit 7 as long

Datasheet

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Revision E

39

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated,

so each repeating sequence outputs new data. Deasserting the CS pin terminates the Read Status Register operation and puts

the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data

be read.

Table 13 shows the bit assignments for Status Register 3.

Table 13: Status Register 3 Bit Assignments

Bit⁽¹⁾

Mnemonic

Name

Reserved

Type⁽²⁾

Description

7

Res

R/W

0

11

0

Reserved bit.

Drive level. The DRV1 and DRV0 bits are used to determine

the output driver strength during read operations. A setting

of 2’b11 allows the drive strength to be set by hardware

based on the VCC level. Four drive settings are supported.

6:5

DRV[1:0]

Drive Strength

R/W

This field is encoded as follows:

11: Auto (7 pF based on VCC level)

10: 50% (15 pF)

01: 75% (22 pF)

00: 100% (30 pF)

4:0

Res

Reserved

R/W

Reserved bit.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable. R = Readable only.

11.1.1 SRP1, SRP0 Bits

The SRP1 and SRP0 bits determine if the Status Register can be modified. The state of the WP pin, along with the values of the

SRP1 and SRP0, determine if the device is software-protected, hardware-protected, or permanently protected, as shown in Table

14.

Table 14: Status Register Protection Table

SRP1

SRP0

WP

Status Register

Description

The Status Register can be written to after a Write Enable com-

mand, WEL = 1.(Factory Default)

0

X

Software Protected

0

1

0

1

Hardware Protected WP = 0, the Status Register is locked and cannot be written.

WP = 1, the Status Register is unlocked and can be written to after

Hardware Unprotected

a Write Enable command, WEL = 1.

Power Supply Lock- Status Register is protected and cannot be written to again until the

1

0

X

Down¹

next Power-Down, Power-Up cycle.

1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle changes SRP1, SRP0 to the (0, 0) state.

Datasheet

21-Apr-2021

Revision E

40

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11.1.2 CMP, BP4, BP3, BP2, BP1, BP0 Bits

The CMP, BP4, BP3, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and program operations

(see Table 6 and Table 7).

The CMP bit complements the effect of the other bits.

The BP4 bit selects between large and small block size protection.

The BP3 bit selects between top of the array or bottom of the array protection.

The BP2, BP1, and BP0 bits determine how much of the array is protected.

11.1.3 WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device

does not accept any Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write Status Register

commands. The WEL bit defaults to the logical “0” state after a device power-up or reset operation. Also, the WEL bit is reset to

the logical “0” state automatically under the following conditions:

•

Write Disable operation completes successfully.

Write Status Register operation completes successfully or aborts.

Program Security Register operation completes successfully or aborts.

Erase Security Register operation completes successfully or aborts.

Byte/Page Program operation completes successfully or aborts.

Block Erase operation completes successfully or aborts.

Chip Erase operation completes successfully or aborts.

If the WELbit is in the logical “1” state, it is not reset to a logical “0” if an operation aborts because of an incomplete or unrecognized

opcode being clocked into the device before the CS pin is deasserted. For the WEL bit to be reset when an operation aborts

prematurely, the entire opcode for a Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write

Status Register command must have been clocked into the device.

11.1.4 RDY/BSY Bit

The RDY/BSY bit determines whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/

BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the

device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”.

11.1.5 LB3, LB2, LB1 Bits

The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked.

The LB3 bit is in the logical “1” state if Security Register page-2 is locked and cannot be erased or programmed.

The LB2 bit is in the logical “1” state if Security Register page-1 is locked and cannot be erased or programmed.

The LB1 bit is in the logical “1” state if Security Register page-0 is locked and cannot be erased or programmed.

Datasheet

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Revision E

41

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11.1.6 E_SUS Bit

This bit is set and cleared by hardware and indicates the status of an erase operation. This bit is encoded as follows:

0: Erase operation is not suspended (default).

1: Erase operation is suspended.

Hardware clears this bit once the condition that caused the erase suspend operation has been removed. Hardware typically sets

this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a Program/Erase Resume (7Ah)

command is executed.

11.1.7 P_SUS Bit

This bit is set and cleared by hardware and indicates the status of an program operation. This bit is encoded as follows:

0: Program operation is not suspended (default).

1: Program operation is suspended.

Hardware clears this bit once the condition that caused the program suspend operation has been removed. Hardware typically

sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a Program/Erase Resume

(7Ah) command is executed.

11.1.8 QE Bit

The QE bit determines if the device is in the Quad Enabled mode. If the QE bit is in the logical “1” state, the HOLD and WP pins

functions as input/output pins similar to the SI and SO. If the QE bit is in the logical “0” state, the HOLD pin functions as an input

only and the WP pin functions as an input only.

Datasheet

21-Apr-2021

Revision E

42

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11.2 WRITE STATUS REGISTER (01H, 31H, 11H)

The Write Status Register command modifies the Block Protection, Security Register Lock-down, Quad Enable, and Status

Register Protection. Before the Write Status Register command can be issued, the Write Enable command must have been

previously issued to set the WEL bit in the Status Register to a logical “1”.

The CS pin must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register command

is not executed. As soon as the CS pin is driven high, the self-timed Write Status Register cycle is initiated.

While the Write Status Register cycle is in progress, the Status Register can be read to check the value of the Write in Progress

(WIP) bit. The WIP bit is 1 during the self-timed Write Status Register cycle, and 0 when it is completed. When the cycle is

completed, the Write Enable Latch is reset.

The Write Status Register command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, BP0) bits,

to define the size of the area that is to be treated as read-only. The Write Status Register command also allows the user to set or

reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP) pin.

The Status Register Protect (SRP1 and SRP0) bits and WP pin allow the device to be put in the hardware protected mode. The

Write Status Register command is not executed once the hardware protected mode is entered.

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCLK

SI

Status Register in

Command

01h or 31h or 11h

7

6

5

4

3

2

1

0

MSB

High-Impedance

SO

Figure 29: Write Status Register

Table 15: Write Status Register 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

RDY/BSY

Table 16: Write Status Register 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

E_SUS

CMP

LB3

LB2

LB1

P_SUS

QE

SRP1

Table 17: Write Status Register 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DRV1

DRV0

Reserved

Datasheet

21-Apr-2021

Revision E

43

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

11.3 WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H)

The non-volatile Status Register bits can be written to as volatile bits. During power up reset, the non-volatile Status Register bits

are copied to a volatile version of the Status Register that is used during device operation. This gives more flexibility to change

the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or

affecting the endurance of the Status Register non-volatile bits.

To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) command must be

issued prior to each Write Status Registers (01h) command. The Write Enable for Volatile Status Register command does not set

the Write Enable Latch bit. It is valid only for the next Write Status Registers command, to change the volatile Status Register bit

values.

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

MSB

1

0

1

0

High-Impedance

SO

Figure 30: Write Enable for Volatile Status Register

Datasheet

21-Apr-2021

Revision E

44

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12 Other Commands and Functions

The AT25SF161B supports three different commands to access device identification that indicates the manufacturer, device type,

and memory density. The returned data bytes provide information, as shown in Table 18.

Table 18: Manufacturer and Device ID Information

Dummy

Bytes

Manufacturer ID

(Byte #1)

Device ID

(Byte #2)

Device ID

(Byte #3)

Command

Opcode

Read Manufacturer and Device ID

Read ID (Legacy Command)

Read ID (Dual I/O)

9Fh

90h

92h

94h

0

3

1Fh

86h

01h

14h

Read ID (Quad I/O)

Resume from Deep Power-Down and

Read Device ID

ABh

3

14h

12.1 READ MANUFACTURER AND DEVICE ID (9FH)

Identification information can be read from the device to enable systems to electronically query and identify the device.

Since not all Flash devices are capable of operating at very high clock frequencies, design applications to read the identification

information from the devices at a reasonably low clock frequency to ensure all devices used in the application can be identified

properly. Once the identification process is complete, the application can increase the clock frequency to accommodate specific

Flash devices that are capable of operating at the higher clock frequencies.

To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device.

After the opcode has been clocked in, the device begins outputting the identification data on the SO pin during the subsequent

clock cycles. The first byte output is the Manufacturer ID, followed by two bytes of Device ID information. Deasserting the CS pin

terminates the Manufacturer and Device ID read operation and puts the SO pin into a high-impedance state. The CS pin can be

deasserted at any time and does not require that a full byte of data be read.

Table 19: Manufacturer and Device ID Information

Byte Number

Data Type

Value

1

Manufacturer ID

1Fh

2

3

Device ID (Part 1)

Device ID (Part 2)

86h

01h

Table 20: Manufacturer and Device ID Details

Hex

Value

Data Type

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Details

JEDEC Assigned Code

JEDEC Code: 0001 1111 (1Fh for

Dialog Semiconductor)

Manufacturer ID

1Fh

86h

01h

0

1

0

1

0

1

0

1

Family Code

Density Code

1

Family Code:100 (AT25SFxxx series)

Density Code: 00110 (16-Mbit)

Device ID (Part 1)

Device ID (Part 2)

0

Sub Code

0

Product Version Code

Sub Code: 000 (Standard series)

Product Version: 00001

0

Datasheet

21-Apr-2021

Revision E

45

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

CS

0

6

7

8

14 15 16

22 23 24

30 31 32

SCK

SI

OPCODE

9Fh

High-Impedance

1Fh

01h

SO

86h

MANUFACTURER ID

DEVICE ID

BYTE1

DEVICE ID

BYTE2

Note: Each transition

shown for SI and SO represents one byte (8 bits)

Figure 31: Read Manufacturer and Device ID

12.2 READ ID (LEGACY COMMAND) (90H)

Identification information can be read from the device to enable systems to electronically query and identify the device. The

JEDEC standard “Read Manufacturer and Device ID (9Fh)” method, described in Section 12.1, is preferred; however, the legacy

Read ID command is supported on the AT25SF161B to enable backwards compatibility to previous generation devices.

To read the identification information, the CS pin must first be asserted, and the opcode 90h must be clocked into the device,

followed by three dummy bytes. After the opcode has been clocked, in followed by three dummy bytes, the device begins

outputting the identification data on the SO pin during the subsequent clock cycles. The first byte output is the Manufacturer ID

of 1Fh, followed by a single byte of data representing a device code 14h. After the device code is output, the sequence of bytes

repeats.

Deasserting the CS pin terminates the Read ID operation and puts the SO pin into a high-impedance state. The CS pin can be

deasserted at any time and does not require that a full byte of data read.

CS

0

1

2

3

4

5

6

7

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

3 DUMMY BYTES

1

MSB

0

1

0

X

DEVICE ID

High-Impedance

D

SO

MSB

Figure 32: Read ID (Legacy Command)

Datasheet

21-Apr-2021

Revision E

46

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12.3 DUAL I/O READ MANUFACTURE ID/ DEVICE ID (92H)

The Dual I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID command

that provides both the JEDEC-assigned Manufacturer ID and the specific Device ID by Dual I/O.

The command is initiated by driving the CS pin low and shifting the command code 92h, followed by a 24-bit address (A23 - A0)

of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first.

CS

0

2

4

5

6

7

12

15

21

1

3

8

9

10 11

13 14

16 17 18 19 20

22 23

SCK

Command

92h

SI

4

2

0

6

4

2

3

0

1

6

0

6

2

0

4

5

6

(IO0)

High-Impedance

SO

(IO1)

7

5

7

5

7

3

1

7

5

3

1

3

A23-16

A15-8

A7-0

Dummy

CS

23 24 25 26

28 29 30 31 32

39

42 43 44 45 46 47

27

40 41

SCK

SI

High-Impedance

6

7

2

6

7

0

4

5

2

4

5

6

7

4

5

0

6

7

2

3

4

5

0

1

(IO0)

2

0

1

SO

( IO1)

1

3

1

MFR and Device ID

(repeat)

MFR ID (repeat)

Device ID (repeat)

MFR ID

Device ID

Figure 33: Dual I/O Read Manufacture ID/ Device ID Timing

Datasheet

21-Apr-2021

Revision E

47

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12.4 QUAD I/O READ MANUFACTURE ID / DEVICE ID (94H)

The Quad I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID command

that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.

The command is initiated by driving the CS pin low and shifting the command code 94h, followed by a 24-bit address (A23 - A0)

of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device ID is read out first.

CS

0

2

4

5

6

7

12

4

15

21

0

1

3

9

11

13

16

20

4

8

10

4

14

17 18 19

22 23

SCK

Command

94h

SI

0

4

0

(IO₀)

High-Impedance

SO

5

6

1

2

5

6

1

2

5

6

1

2

1

2

5

6

1

2

5

6

1

2

5

6

(IO₁)

WP

(IO₂)

High-Impedance

HOLD

(IO₃)

7

3

7

3

7

3

7

3

7

3

7

Device ID

dummy

MFR ID

A7-0

dummy

A23-16

A15-8

CS

23 24 25 26

28 29 30 31

27

SCK

SI

4

0

4

0

(IO₀)

SO

5

6

1

2

5

6

1

2

5

6

1

2

5

6

(IO₁)

2

WP

(IO₂)

7

3

7

3

7

3

7

HOLD

(IO₃)

MFR ID DID ID MFR ID DID ID

(repeat) (repeat)(repeat) (repeat)

Figure 34: Quad I/O Read Manufacture ID / Device ID Timing

Datasheet

21-Apr-2021

Revision E

48

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12.5 DEEP POWER-DOWN (B9H)

During normal operation, the device is placed in Standby Mode to consume less power as long as the CS pin remains deasserted

and no internal operation is in progress. The Deep Power-Down command lets the device be put into an even lower-power

consumption state, called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands, including the Read Status Register command, are ignored,

with the exception of the Resume from Deep Power-Down command. Since all commands are ignored, the mode can be used

as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode of B9h, and then deasserting the

CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is deasserted, the device enters

the Deep Power-Down mode.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device aborts the operation and returns to the Standby Mode once the CS pin is deasserted.

Also, the device defaults to the Standby Mode after a power-cycle.

The Deep Power-Down command is ignored if an internally self-timed operation, such as a program or erase cycle, is in progress.

The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the

device to enter the Deep Power-Down mode.

CS

t_EDPD

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

MSB

0

1

0

1

High-Impedance

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 35: Deep Power-Down

Datasheet

21-Apr-2021

Revision E

49

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12.6 RESUME FROM DEEP POWER-DOWN (ABH)

To exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must

be issued. The Resume from Deep Power-Down command is the only command that the device recognizes while in the Deep

Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must be asserted first, and the opcode of ABh must be clocked into the

device. Any additional data clocked into the device after the opcode is ignored. When the CS pin is deasserted, the device exits

the Deep Power-Down mode and returns to the Standby Mode. After the device has returned to the Standby Mode, normal

command operations, such as Read Array, can be resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an byte boundary

(multiples of eight bits), the device aborts the operation and returns to the Deep Power-Down mode.

CS

t_RDPD

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

MSB

0

1

0

1

0

1

High-Impedance

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 36: Resume from Deep Power-Down

Datasheet

21-Apr-2021

Revision E

50

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

12.6.1 Resume from Deep Power-Down and Read Device ID (ABh)

The Resume from Deep Power-Down command also can be used to read the Device ID.

When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be asserted and

opcode ABh must be clocked into the device, followed by three dummy bytes. The Device ID bits are then shifted out on the falling

edge of SCLK, with the MSB first, as shown in Figure 37. This command only outputs a single byte Device ID. The Device ID

value for the AT25SF161B is listed in Table 18 on page 45.

After the last bit (0) of the Device ID has been clocked out, the sequence repeats itself, starting again with bit 7, as long as the

CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted, it must remain high until new commands can

be received.

The same command can be used to read the device ID when not in power down mode. In that case, CS does not have to remain

high remain after it is deasserted.

CS

0

1

2

3

4

5

6

7

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

3 DUMMY BYTES

t_RDPO

ꢋ

ꢓ

ꢋ

ꢓ

ꢋ

ꢓ

ꢋ

X

ꢀꢁꢂ

DEVICE ID

High-Impedance

Active Current

D

MSB

D

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 37: Resume from Deep Power-Down and Read Device ID Timing

12.7 HOLD FUNCTION

The HOLD pin pauses the serial communication with the device without having to stop or reset the clock sequence. The Hold

mode, however, does not affect any internally self-timed operations, such as a program or erase cycle. Thus, if an erase cycle is

in progress, asserting the HOLD pin does not pause the operation, and the erase cycle continues until it is finished.

If the QE bit value in the Status Register has been set to logical “1”, the HOLD pin does not function as a control pin. The HOLD

pin functions as an output for Quad-Output Read and input/output for Quad-I/O Read.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by asserting the HOLD pin during

the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, the Hold mode is not started until the beginning of the

next SCK low pulse. The device remains in the Hold mode as long as the HOLD pin and CS pin are asserted.

While in the Hold mode, the SO pin is in a high-impedance state. Also, both the SI pin and the SCK pin are ignored.

The WP pin, however, can still be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the

HOLD pin is deasserted during the SCK high pulse, the Hold mode does not end until the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is asserted, any operation that have been started are aborted, and the device

resets the WEL bit in the Status Register to the logical “0” state.

Datasheet

21-Apr-2021

Revision E

51

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

13 Electrical Specifications

13.1 ABSOLUTE MAXIMUM RATINGS*

*Notice: Stresses beyond those listed here can cause

permanent damage to the device. This is a

stress rating only; functional operation of the

device at these or any other conditions beyond

those indicated in the operational sections of

this specification is not implied. Exposure to

absolute maximum rating conditions for

Temperature under Bias . . . . . . . . . . . -55 °C to +125 °C

Storage Temperature . . . . . . . . . . . . . -65 °C to +150 °C

All Input Voltages (including NC Pins)

with Respect to Ground . . . . . . . . . . . . . -0.5 V to +4.0 V

All Output Voltages

with Respect to Ground . . . . . . . . .-0.6 V to V_CC+ 0.5 V

extended periods can affect device reliability.

13.2 DC AND AC OPERATING RANGE

Parameter

Condition

Value

Operating Temperature (Case)

V_CCPower Supply

Industrial

-40 °C to 85 °C

2.5 V to 3.6 V

13.3 DC CHARACTERISTICS

2.5 V to 3.6 V

Symbol

Parameter

Condition

Units

Min

Typ¹

Max

CS, HOLD, WP = V_IH

All inputs at CMOS levels

I_DPD

I_SB

Deep Power-Down Current

Standby Current

1.5

10

µA

CS, HOLD, WP = V_IH

All inputs at CMOS levels

15

30

f = 20 MHz; I_OUT= 0

f = 50 MHz; I_OUT= 0

f = 85 MHz; I_OUT= 0

f = 50 MHz; I_OUT= 0

4.0

4.5

5.5

5

6

7

mA

Active Current, Read (03h, 0Bh)

Operation

I_CC1

I_CC2

I_CC3

Active Current,(3Bh, BBh

Read Operation (Dual)

f = 85 MHz and 104 MHz;

I_OUT= 0

7.5

10

mA

f = 50 MHz; I_OUT= 0

7

9

mA

Active Current,(6Bh, EBh

Read Operation (Quad)

f = 85 MHz and 104 MHz;

I_OUT= 0

10

13

Active Current,

Program Operation

I_CC4

CS = V_CC

20

14

mA

Active Current,

Erase Operation

I_CC5

I_LI

I_LO

Input Load Current

Output Leakage Current

Input Low Voltage

All inputs at CMOS levels

±2

µA

V

V_IL

0.5

V_CCx 0.2

V_CC+ 0.4

0.4

V_IH

V_OL

V_OH

Input High Voltage

Output Low Voltage

Output High Voltage

V_CCx 0.8

V

I_OL= 100 µA

I_OH= -100 µA

V

V_CC- 0.2

V

1. Measured at 3.0 V @ 25 °C.

Datasheet

21-Apr-2021

Revision E

52

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

13.4 AC CHARACTERISTICS - MAXIMUM CLOCK FREQUENCIES

2.5 V to 3.6 V

Typ

Symbol

Parameter

Units

Min

Max

Maximum Clock Frequency for all opcodes except for 03h, 0Bh,

3Bh, and 6Bh

f_CLK

108

MHz

f_CLK1

f_CLK2

Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh

Maximum Clock Frequency for 03h opcode

85

55

MHz

13.5 AC CHARACTERISTICS - ALL OTHER PARAMETERS

2.5 V to 3.6 V

Parameter

Units

Symbol

Min

Typ

Max

t_CLKH

Clock High Time

4

ns

V/ns

ns

µs

ns

µs

t_CLKL

t_CLKR

t_CLKF

t_CSH

t_CSLS

t_CSLH

t_CSHS

t_CSHH

t_DS

Clock Low Time

Clock Rise Time, Peak-to-Peak (Slew Rate)¹

Clock Fall Time, Peak-to-Peak (Slew Rate)¹

CS High Time

0.1

20

5

CS Low Setup Time (relative to Clock)

CS Low Hold Time (relative to Clock)

CS High Setup Time (relative to Clock)

CS High Hold Time (relative to Clock)

Data In Setup Time

5

2

t_DH

Data In Hold Time

Output Disable Time¹

2

t_DIS

6

7

t_V

Output Valid Time

t_OH

Output Hold Time

0

5

t_HLS

HOLD Low Setup Time (relative to Clock)

HOLD Low Hold Time (relative to Clock)

HOLD High Setup Time (relative to Clock)

HOLD High Hold Time (relative to Clock)

HOLD Low to Output High-Z¹

HOLD High to Output High-Z¹

CS High to Standby Mode Without Electronic Signature Read

CS High to Standby Mode With Electronic Signature Read

CS High to Next Instruction After Suspend

Write Protect Setup Time¹

t_HLH

t_HHS

t_HHH

t_HLQZ

t_HHQZ

t_RES1

t_RES2

t_SUS

t_WPS

t_WPH

t_EDPD

t_RDPD

t_RDPO

6

20

Write Protect Hold Time¹

100

CS High to Deep Power-Down

CS High to Standby Mode

20

Resume Deep Power-Down, CS High to ID

1. Not 100% tested. Value guaranteed by design and characterization.

Datasheet

21-Apr-2021

Revision E

53

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

13.6 PROGRAM AND ERASE CHARACTERISTICS

2.5 V to 3.6 V

Symbol

Parameter

Condition

Min

Typ¹

Max²

Units

t_PP

Page Program Time (256 Bytes)

First Byte Program Time

0.4

1.8

ms

t_BP1

t_BP2

30

2.5

50

12

µs

Second Byte Program Time

4 kbyte

32 kbyte

64 kbyte

220

450

700

11

t_BLKE

Block Erase Time

120

200

5.5

5

ms

3

t_CHPE

Chip Erase Time

s

t_WRSR

Write Status Register Time

30

ms

1. Measured at 3.0 V @ 25 °C.

2. Unless specified otherwise, maximum is worst-case after 100k cycles.

3. Max spec based on limited endurance cycle.

13.7 POWER UP CONDITIONS

Symbol

Parameter

Min

70

Max

Units

t_VCSL

Minimum V_CCto Chip Select Low Time

µs

13.8 INPUT TEST WAVEFORMS AND MEASUREMENT LEVELS

0.9V_CC

AC

DRIVING

LEVELS

V_CC/2

MEASUREMENT

LEVEL

0.1V_CC

13.9 OUTPUT TEST LOAD

Device

Under

Test

30pF

Datasheet

21-Apr-2021

Revision E

54

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

14 AC Waveforms

W_&6+

&6

W_&6++

W_&6/6

W_&6/+

W_&/.+

W_&/./

W_&6+6

6&.

W_'6

W_'+

06%

/6%

06%

6,

+,*+ꢊ,03('$1&(

62

Figure 38: Serial Input Timing

&6

6&.

6,

W_&/.+

W_&/./

W_',6

W₂₊

W₉

62

Figure 39: Serial Output Timing

CS

WP

SCK

SI

t_WPS

t_WPH

0

X

MSB

MSB OF

LSB OF

WRITE STATUS REGISTER

DATA BYTE

MSB OF

NEXT OPCODE

WRITE STATUS REGISTER

OPCODE

High-Impedance

SO

Figure 40: WP Timing for Write Status Register Command When BPL = 1

Datasheet

21-Apr-2021

Revision E

55

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

CS

SCK

t_HHH

t_HLS

t_HLH

t_HHS

HOLD

SI

High-Impedance

SO

Figure 41: HOLD Timing – Serial Input

CS

SCK

HOLD

SI

t_HHH

t_HLS

t_HLH

t_HHS

t_HLQZ

t_HHQX

SO

Figure 42: HOLD Timing – Serial Output

Datasheet

21-Apr-2021

Revision E

56

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

15 Ordering Information

AT 25SF 161 B - S H B - T

Shipping Carrier

T = Tape and Reel

B = Bulk (tube)

Designator

DWF = Die Wafer Form

Product Family

Operating Voltage

B = 2.7 V - 3.6 V

D = 2.5 V - 3.6 V

Device Density

Device Grade

161 = 16 Mbit

H = Green NiPdAu lead frame

o

(-40 C to 85 C)

U = Green, Matte Sn or Sn alloy

Generation

Package Options

SS = 8-lead, SOP 0.150” (8S1)

S = 8-lead, SOP 0.208” (8S2)

M = 8-pad 5 x 6 UDFN (8MA1)

U = 8-ball WLCSP

Table 21: Ordering Codes for 2.7 V to 3.6 V Devices

Ordering Code¹

Package

Operating Voltage

Max. Freq. (MHz) Operation Range

AT25SF161B-SSHB-B

8S1

AT25SF161B-SSHB-T

AT25SF161B-SHB-B

AT25SF161B-SHB-T

AT25SF161B-MHB-T

AT25SF161B-UUB-T

AT25SF161B-DWF²

8S2

Industrial

108 MHz

2.7 V to 3.6 V

(-40 °C to +85 °C)

8MA1

8WLCSP

1. The shipping carrier option code is not marked on the devices.

2. Contact Dialog Semiconductor for detailed information.

Table 22: Ordering Codes for 2.5 V to 3.6 V Devices

Ordering Code¹

Package

Operating Voltage

Max. Freq. (MHz) Operation Range

AT25SF161B-SSHD-B

8S1

AT25SF161B-SSHD-T

AT25SF161B-SHD-B

AT25SF161B-SHD-T

AT25SF161B-MHD-T

AT25SF161B-UUD-T

Industrial

108 MHz

8S2

2.5 V to 3.6 V

(-40 °C to +85 °C)

8MA1

8WLCSP

1. The shipping carrier option code is not marked on the devices.

Datasheet

21-Apr-2021

Revision E

57

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Table 23: Description of Package Types

Package Type

Description

8S1

8-lead, 0.150" Narrow, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra-thin Dual Flat No-lead (UDFN)

8-ball, 3 x 2 x 3 mm Ball Matrix, 0.35 mm Z-Height

8S2

8MA1

8WLCSP

Datasheet

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Revision E

58

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

16 Packaging Information

16.1 8S1 – 0.150” NARROW JEDEC SOIC

C

1

E

E1

L

N

Ø

TOP VIEW

END VIEW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.35

0.10

MAX

1.75

0.25

NOM

NOTE

SYMBOL

A1

A

–

A1

b

C

0.31

0.17

4.80

3.81

5.79

–

0.51

0.25

5.05

3.99

6.20

–

D

–

D

E1

E

–

SIDE VIEW

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

e

1.27 BSC

L

0.40

0°

–

1.27

8°

ꢀꢀꢀØꢀ

8S1, 8-lead (0.150” Narrow Body), Plastic Gull

Wing Small Outline Package (JEDEC SOIC)

5/19/10

TITLE

GPC

DRAWING NO.

REV.

8S1, 8-lead (0.150” Narrow Body), Plastic Gull

Wing Small Outline (JEDEC SOIC)

SWB

8S1

F

Datasheet

21-Apr-2021

Revision E

59

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

16.2 8S2 – 8-LEAD, 0.208” WIDE EIAJ SOIC

C

1

E

E1

L

N

T

TOP VIEW

END VIEW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.70

0.05

0.35

0.15

5.13

5.18

7.70

0.51

0°

MAX

2.16

0.25

0.48

0.35

5.35

5.40

8.26

0.85

8°

NOM

NOTE

SYMBOL

A1

A

A1

b

4

C

D

E1

E

D

2

L

SIDE VIEW

T

e

1.27 BSC

3

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. Determines the true geometric position.

4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/15/08

DRAWING NO.

REV.

GPC

TITLE

8S2, 8-lead, 0.208” Body, Plastic Small

Outline Package (EIAJ)

STN

8S2

F

Datasheet

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Revision E

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DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

16.3 8MA1 – UDFN

E

C

Pin 1 ID

SIDE VIEW

D

y

TOP VIEW

A1

A

K

E2

Option A

0.45

Pin #1

8

1

2

3

Pin #1 Notch

(0.20 R)

(Option B)

Chamfer

(C 0.35)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

NOTE

SYMBOL

7

A

0.45

0.55

0.60

e

D2

A1

b

0.00

0.35

0.02

0.40

0.152 REF

5.00

4.00

6.00

3.40

1.27

0.60

–

0.05

0.48

6

C

D

D2

E

4.90

3.80

5.90

3.20

5.10

4.20

6.10

3.60

5

4

b

BOTTOM VIEW

L

E2

e

L

0.50

0.00

0.20

0.75

0.08

–

y

K

–

4/15/08

GPC

YFG

DRAWING NO.

TITLE

REV.

8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally

Enhanced Plastic Ultra Thin Dual Flat No Lead

Package (UDFN)

8MA1

D

Datasheet

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Revision E

61

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

16.4 8-WLCSP — 8-BALL 3 X 2 X 3 WLCSP

TITLE

Ordering Part REV.

Number ID

Internal Package

Identifier

8-ball (3 x 2 x 3 Array)

Wafer-Level Chip Scale (WLCSP)

A

DEC

UD

Datasheet

21-Apr-2021

Revision E

62

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

17 Revision History

Revision

Date

Tasks

A

01/2020

Initial release of AT25SF161B data sheet.

Replaced characterization numbers in tables 13.3 through 13.7.

Changed status from Advanced to Preliminary.

B

C

03/2020

01-2021

Correction to BP0 value for range 100000h-1FFFFFh in Table 9-2.

Transferred to new Dialog Semiconductor format.

Added 2.5 V - 3.6 V supply voltage option on Features page, sections 13.2, 13.3,

13.4, 13.5, and 13.6.

Added support for 2.5 V - 3.6 V to section 15, including new part numbers.

D

E

03-2021

04-2021

Removed “Preliminary” from datasheet designation.

Finalized numbers in Tables 13.3 and 13.6.

Datasheet

21-Apr-2021

Revision E

63

DS-AT25SF161B-188

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

Disclaimer

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associated software) can reasonably be expected to result in personal injury, death or severe property or environmental damage. Dialog Semiconductor and its suppliers

accept no liability for inclusion and/or use of Dialog Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion

and/or use is at the customer's own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, express or implied, as

to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any

information source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the specification and the design of

the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive grade version of the device, Dialog Semiconductor

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Phone: +44 1793 757700

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Email:

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www.dialog-semiconductor.com

Datasheet

21-Apr-2021

Revision E

64

DS-AT25SF161B-188


型号：	AT25SF161B-UUD-T
厂家：	Dialog Semiconductor
描述：	16-Mbit SPI Serial Flash Memory with Dual I/O and Quad I/O Support
文件：	总64页 (文件大小：1228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT25SF161B-UUD-T [DIALOG]

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