AT25PE20-MHN-T [DIALOG]

2-Mbit DataFlash-L Page Erase Serial Flash Memory;
AT25PE20-MHN-T
型号: AT25PE20-MHN-T
厂家: Dialog Semiconductor    Dialog Semiconductor
描述:

2-Mbit DataFlash-L Page Erase Serial Flash Memory

文件: 总64页 (文件大小:1119K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Following the acquision of Adesto Technologies, Dialog Semiconductor offers memory products as part of its  
product porolio. The exis�ng content from datasheets, including part numbers and codes should be used. Terms of  
Purchase are provided on the Dialog website  
https://www.dialog-semiconductor.com/general-terms-and-conditions-purchase  
View our Dialog memory products porolio:  
www.dialog-semiconductor.com/products/memory  
Contacting Dialog Semiconductor  
United Kingdom (Headquarters)  
Dialog Semiconductor (UK) LTD  
Phone: +44 1793 757700  
North America  
Dialog Semiconductor Inc.  
Phone: +1 408 845 8500  
Hong Kong  
Dialog Semiconductor Hong Kong  
Phone: +852 2607 4271  
China (Shenzhen)  
Dialog Semiconductor China  
Phone: +86 755 2981 3669  
Germany  
Japan  
Korea  
China (Shanghai)  
Dialog Semiconductor GmbH  
Phone: +49 7021 805-0  
Dialog Semiconductor K. K.  
Phone: +81 3 5769 5100  
Dialog Semiconductor Korea  
Phone: +82 2 3469 8200  
Dialog Semiconductor China  
Phone: +86 21 5424 9058  
The Netherlands  
Taiwan  
#
Dialog Semiconductor B.V.  
Phone: +31 73 640 8822  
Dialog Semiconductor Taiwan  
Phone: +886 281 786 222  
Email:  
Web site:  
enquiry@diasemi.com  
www.dialog-semiconductor.com  
AT25PE20  
2-Mbit DataFlash-L  
Page Erase Serial Flash Memory  
DATASHEET  
Features  
ò
ò
Single 1.65V - 3.6V supply  
Serial Peripheral Interface (SPI) compatible  
ò
Supports SPI modes 0 and 3  
Supports RapidSoperation  
ò
ò
ò
Continuous read capability through entire array  
ò
ò
ò
Up to 85MHz  
Low-power read option up to 15MHz  
Clock-to-output time (tV) of 6ns maximum  
User configurable page size  
ò
256 bytes per page (default)  
ò
264 bytes per page (customer selectable option)  
ò
ò
One SRAM data buffer (256/264 bytes)  
Flexible programming options  
ò
ò
ò
ò
Byte/Page Program (1 to 256/264 bytes) directly into main memory  
Buffer Write  
Buffer to Main Memory Page Program  
Single Command Page Read-Modify-Write Option  
ò
ò
Flexible erase options  
ò
ò
ò
ò
Page Erase (256/264 bytes)  
Block Erase (2KB)  
Sector Erase (32KB)  
Chip Erase (2-Mbits)  
128-byte Security Register  
128 bytes factory programmed with a unique identifier  
ò
ò
ò
ò
Hardware and software controlled reset options  
JEDEC Standard Manufacturer and Device ID Read  
Low-power dissipation  
ò
ò
ò
ò
300nA Ultra-Deep Power-Down current (typical)  
5µA Deep Power-Down current (typical)  
25µA Standby current (typical)  
7mA Active Read current (typical)  
ò
ò
ò
ò
Endurance: 100,000 program/erase cycles per page minimum  
Data retention: 20 years  
Complies with full industrial temperature range  
Green (Pb/Halide-free/RoHS compliant) packaging options  
ò
8-lead SOIC (0.150ʺ wide and 0.208" wide)  
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)  
ò
DS-25PE20–139C–8/2018  
Description  
The Adesto® AT25PE20 is a 1.65V minimum, serial-interface sequential access Flash memory is ideally suited for a wide  
variety of digital voice, image, program code, and data storage applications. The AT25PE20 also supports the RapidS  
serial interface for applications requiring very high speed operation. Its 2,162,688 bits of memory are organized as 1,024  
pages of 256 bytes (default) or 264 bytes (customer option) each. In addition to the main memory, AT25PE20 also  
contains one SRAM buffer of 256/264 bytes. The Buffer can be used as additional system scratch memory, and E2PROM  
emulation  
(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.  
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the  
Adesto DataFlash-L® uses a serial interface to sequentially access its data. The simple sequential access dramatically  
reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,  
and reduces package size. The device is optimized for use in many commercial and industrial applications where  
high-density, low-pin count, low-voltage, and low-power are essential.  
To allow for simple in-system re-programmability, AT25PE20 does not require high input voltages for programming. The  
device operates from a single 1.65V to 3.6V power supply for the erase and program and read operations. The  
AT25PE20 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input  
(SI), Serial Output (SO), and the Serial Clock (SCK).  
All programming and erase cycles are self-timed.  
1.  
Pin Configurations and Pinouts  
Figure 1-1. Pinouts  
8-lead SOIC  
Top View  
8-pad UDFN  
Top View  
(through package)  
CS  
SO  
1
2
3
4
8
7
6
5
Vcc  
CS  
SO  
1
2
3
4
8
7
6
5
Vcc  
RESET  
SCK  
SI  
RESET  
SCK  
SI  
WP  
WP  
GND  
GND  
Note: 1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.  
This pad can be a “no connect” or connected to GND.  
AT25PE20  
DS-25PE20–139C–8/2018  
2
Table 1-1. Pin Configurations  
Asserted  
State  
Symbol  
Name and Function  
Type  
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the  
device will be deselected and normally be placed in the standby mode (not Deep Power-Down  
mode) and the output pin (SO) will be in a high-impedance state. When the device is  
deselected, data will not be accepted on the input pin (SI).  
CS  
Low  
Input  
A high-to-low transition on the CS pin is required to start an operation and a low-to-high  
transition is required to end an operation. When ending an internally self-timed operation such  
as a program or erase cycle, the device will not enter the standby mode until the completion of  
the operation.  
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of  
data to and from the device. Command, address, and input data present on the SI pin is  
always latched on the rising edge of SCK, while output data on the SO pin is always clocked  
out on the falling edge of SCK.  
SCK  
Input  
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input  
including command and address sequences. Data on the SI pin is always latched on the rising  
edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS  
is deasserted).  
SI  
Input  
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is  
always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state  
whenever the device is deselected (CS is deasserted).  
SO  
Output  
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector  
Protection Register will be protected against program and erase operations regardless of  
whether the Enable Sector Protection command has been issued or not. The WP pin functions  
independently of the software controlled protection method. After the WP pin goes low, the  
contents of the Sector Protection Register cannot be modified.  
WP  
If a program or erase command is issued to the device while the WP pin is asserted, the device  
will simply ignore the command and perform no operation. The device will return to the idle  
state once the CS pin has been deasserted.  
Low  
Input  
The WP pin is internally pulled-high and may be left floating if hardware controlled protection  
will not be used. However, it is recommended that the WP pin also be externally connected to  
VCC whenever possible.  
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset  
the internal state machine to an idle state. The device will remain in the reset condition as long  
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin  
is brought back to a high level.  
RESET  
Low  
Input  
The device incorporates an internal power-on reset circuit, so there are no restrictions on the  
RESET pin during power-on sequences. If this pin and feature is not utilized, then it is  
recommended that the RESET pin be driven high externally.  
Device Power Supply: The VCC pin is used to supply the source voltage to the device.  
Operations at invalid VCC voltages may produce spurious results and should not be attempted.  
VCC  
Power  
Ground: The ground reference for the power supply. GND should be connected to the system  
ground.  
GND  
Ground  
AT25PE20  
DS-25PE20–139C–8/2018  
3
2.  
Block Diagram  
Figure 2-1. Block Diagram  
WP  
Flash Memory Array  
Page (256/264 bytes)  
Buffer 1 (256/264 bytes)  
SCK  
CS  
I/O Interface  
RESET  
V
CC  
GND  
SI  
SO  
AT25PE20  
DS-25PE20–139C–8/2018  
4
3.  
Memory Array  
To provide optimal flexibility, the AT25PE20 memory array is divided into three levels of granularity comprising of sectors,  
blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the  
number of pages per sector and block. Program operations to the DataFlash-L can be done at the full page level or at the  
byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level.  
Figure 3-1. Memory Architecture Diagram  
Sector Architecture  
Block Architecture  
Page Architecture  
Block 0  
Block 1  
Block 2  
8 Pages  
Page 0  
Page 1  
Sector 0a  
Sector 0a = 8 pages  
2,048/2,112 bytes  
Sector 0b = 120 pages  
30,720/31,680 bytes  
Page 6  
Page 7  
Page 8  
Page 9  
Block 14  
Block 15  
Block 16  
Block 17  
Sector 1 = 128 pages  
32,768/33,792 bytes  
Page 14  
Page 15  
Page 16  
Page 17  
Page 18  
Block 30  
Block 31  
Block 112  
Block 113  
Sector 6 = 128 pages  
32,768/33,792 bytes  
Sector 7 = 128 pages  
32,768/33,792 bytes  
Block 126  
Block 127  
Page 1,022  
Page 1,023  
Block = 2,048/2,112 bytes  
Page = 256/264 bytes  
AT25PE20  
DS-25PE20–139C–8/2018  
5
4.  
Device Operation  
The device operation is controlled by instructions from the host processor. The list of instructions and their associated  
opcodes are contained in Table 15-1 on page 35 through Table 15-4 on page 36. A valid instruction starts with the falling  
edge of CS followed by the appropriate 8-bit opcode and the Buffer or main memory address location. While the CS pin  
is low, toggling the SCK pin controls the loading of the opcode and the Buffer or main memory address location through  
the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit (MSB) first.  
Three address bytes are used to address memory locations in either the main memory array or in the Buffer. The three  
address bytes will be comprised of a number of dummy bits and a number of actual device address bits, with the number  
of dummy bits varying depending on the operation being performed and the selected device page size. Buffer addressing  
for the optional DataFlash-L page size (264 bytes) is referenced in the datasheet using the terminology BFA8 - BFA0 to  
denote the nine address bits required to designate a byte address within the Buffer. The main memory addressing is  
referenced using the terminology PA9 - PA0 and BA8 - BA0, where PA9 - PA0 denotes the 10 address bits required to  
designate a page address, and BA8 - BA0 denotes the nine address bits required to designate a byte address within the  
page. Therefore, when using the optional DataFlash-L page size, a total of 22 address bits are used.  
For the default page size (256 bytes), the Buffer addressing is referenced in the datasheet using the conventional  
terminology BFA7 - BFA0 to denote the eight address bits required to designate a byte address within the Buffer. Main  
memory addressing is referenced using the terminology A17 - A0, where A17 - A8 denotes the 10 address bits required  
to designate a page address, and A7 - A0 denotes the eight address bits required to designate a byte address within a  
page. Therefore, when using the default page size, a total of 21 address bits are used.  
AT25PE20  
DS-25PE20–139C–8/2018  
6
5.  
Read Commands  
By specifying the appropriate opcode, data can be read from the main memory or from the data buffer. The DataFlash-L  
supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., "Detailed Bit-level Read Waveforms: RapidS  
Mode 0/Mode 3" on page 52 for diagrams detailing the clock cycle sequences for each mode.  
5.1  
Continuous Array Read (Legacy Command: E8h)  
By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized  
to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional  
addressing information or control signals need to be provided. The DataFlash-L incorporates an internal address counter  
that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed  
without the need for additional address sequences. To perform a Continuous Array Read using the optional DataFlash-L  
page size (264-bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which  
comprise the 19-bit page and byte address sequence) and four dummy bytes. The first 10 bits (PA9 - PA0) of the  
19-bit address sequence specify which page of the main memory array to read and the last nine bits (BA8 - BA0) of the  
19-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using  
the default page size (256 bytes), the opcode E8h must be clocked into the device followed by three address bytes  
(A17 - A0) and four dummy bytes. The dummy bytes that follow the address bytes are needed to initialize the read  
operation. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the  
SO (Serial Output) pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes and the reading of  
data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue  
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover  
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,  
the device will continue reading back at the beginning of the first page of memory. As with crossing over page  
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array  
Read bypasses the data buffer and leaves the contents of the Buffer unchanged.  
Note: This command is not recommended for new designs.  
5.2  
Continuous Array Read (High Frequency Mode: 0Bh Opcode)  
This command can be used to read the main memory array sequentially at the highest possible operating clock  
frequency up to the maximum specified by fCAR1. To perform a Continuous Array Read using the optional DataFlash-L  
page size (264 bytes), the CS pin must first be asserted, and then an opcode of 0Bh must be clocked into the device  
followed by three address bytes and one dummy byte. The first 10 bits (PA9 - PA0) of the 19-bit address sequence  
specify which page of the main memory array to read and the last nine bits (BA8 - BA0) of the 19-bit address sequence  
specify the starting byte address within the page. To perform a Continuous Array Read using the default page size  
(256 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A17 - A0) and one dummy  
byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of  
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue  
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover  
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,  
the device will continue reading back at the beginning of the first page of memory. As with crossing over page  
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array  
Read bypasses the data buffer and leaves the contents of the Buffer unchanged.  
AT25PE20  
DS-25PE20–139C–8/2018  
7
5.3  
Continuous Array Read (Low Frequency Mode: 03h Opcode)  
This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum  
specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for lower  
clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To perform a  
Continuous Array Read using the optional DataFlash-L page size (264 bytes), the CS pin must first be asserted, and then  
an opcode of 03h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and  
byte address sequence). The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the main  
memory array to read, and the last nine bits (BA8 - BA0) of the 19-bit address sequence specify the starting byte address  
within the page. To perform a Continuous Array Read using the default page size (256 bytes), the opcode 03h must be  
clocked into the device followed by three address bytes (A17 - A0). Following the address bytes, additional clock pulses  
on the SCK pin will result in data being output on the SO pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end  
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the  
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of  
one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will  
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will  
be incurred when wrapping around from the end of the array to the beginning of the array.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The Continuous Array  
Read bypasses the data buffer and leaves the contents of the Buffer unchanged.  
5.4  
Continuous Array Read (Low Power Mode: 01h Opcode)  
This command is ideal for applications that want to minimize power consumption and do not need to read the memory  
array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the main memory  
array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. The memory can  
be read at clock frequencies up to maximum specified by fCAR3. To perform a Continuous Array Read using the optional  
DataFlash-L page size (264 bytes), the CS pin must first be asserted, and then an opcode of 01h must be clocked into  
the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). The first 10  
bits  
(PA9 - PA0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits  
(BA8 - BA0) of the 19-bit address sequence specify the starting byte address within the page. To perform a Continuous  
Array Read using the default page size (256 bytes), the opcode 01h must be clocked into the device followed by three  
address bytes (A17 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being  
output on the SO pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end  
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the  
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of  
one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will  
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will  
be incurred when wrapping around from the end of the array to the beginning of the array.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Continuous Array Read is defined by the fCAR3 specification. The Continuous Array  
Read bypasses the data buffer and leaves the contents of the Buffer unchanged.  
AT25PE20  
DS-25PE20–139C–8/2018  
8
5.5  
Main Memory Page Read  
A Main Memory Page Read allows the user to read data directly from any one of the 1,024 pages in the main memory,  
bypassing the data buffer and leaving the contents of the Buffer unchanged. To start a Main Memory Page Read using  
the optional DataFlash-L page size (264 bytes), the CS pin must first be asserted then an opcode of D2h must be  
clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence)  
and four dummy bytes. The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the main  
memory array to read, and the last nine bits (BA8 - BA0) of the 19-bit address sequence specify the starting byte address  
within the page. To perform a Main Memory Page Read with the default page size (256 bytes), the opcode D2h must be  
clocked into the device followed by three address bytes (A17 - A0) and four dummy bytes. The first 10 bits (A17 - A8) of  
the  
18-bit address sequence specify which page of the main memory array to read, and the last eight bits (A7 - A0) of the  
18-bit address sequence specify the starting byte address within that page. The dummy bytes that follow the address  
bytes are sent to initialize the read operation. Following the dummy bytes, the additional pulses on SCK result in data  
being output on the SO (Serial Output) pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of  
data. Unlike the Continuous Array Read command, when the end of a page in main memory is reached, the device will  
continue reading back at the beginning of the same page rather than the beginning of the next page.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page  
Read bypasses the data buffer and leaves the contents of the Buffer unchanged.  
5.6  
Buffer Read  
The data buffer can be accessed independently from the main memory array, and utilizing the Buffer Read command  
allows data to be sequentially read directly from the Buffer. Two opcodes, D4h or D1h, can be used for the Buffer Read  
command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the  
Buffer. The D4h opcode can be used at any SCK frequency up to the maximum specified by fCAR while the D1h opcode  
can be used for lower frequency read operations up to the maximum specified by fCAR2  
.
To perform a Buffer Read using the optional DataFlash-L buffer size (264 bytes), the opcode must be clocked into the  
device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 -BFA0). To  
perform a Buffer Read using the default buffer size (256 bytes), the opcode must be clocked into the device followed by  
three address bytes comprised of 16 dummy bits and eight address bits (A7 - A0). Following the address bytes, one  
dummy byte must be clocked into the device to initialize the read operation if using opcode D4h. The CS must remain low  
during the loading of the opcode, the address bytes, the dummy byte (for opcode D4h only), and the reading of data.  
When the end of a buffer is reached, the device will continue reading back at the beginning of the Buffer. A  
low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).  
AT25PE20  
DS-25PE20–139C–8/2018  
9
6.  
Program and Erase Commands  
6.1  
Buffer Write  
Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into the data buffer.  
To load data into the Buffer using the optional DataFlash-L buffer size (264 bytes), an opcode of 84h must be clocked  
into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0).  
The nine buffer address bits specify the first byte in the Buffer to be written.  
To load data into the Buffer using the default buffer size (256 bytes), an opcode of 84h must be clocked into the device  
followed by 16 dummy bits and eight address bits (A7 - A0). The eight address bits specify the first byte in the Buffer to  
be written.  
After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If  
the end of the data buffer is reached, the device will wrap around back to the beginning of the Buffer. Data will continue  
to be loaded into the Buffer until a low-to-high transition is detected on the CS pin.  
6.2  
Buffer to Main Memory Page Program with Built-In Erase  
The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in the Buffer to be  
written into an erased or programmed page in the main memory array. It is not necessary to pre-erase the page in main  
memory to be written because this command will automatically erase the selected page prior to the program cycle.  
To perform a Buffer to Main Memory Page Program with Built-In Erase using the optional DataFlash-L page size  
(264 bytes), an opcode of 83h must be clocked into the device followed by three address bytes comprised of five dummy  
bits,10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine dummy bits.  
To perform a Buffer to Main Memory Page Program with Built-In Erase using the default page size (256 bytes), an  
opcode of 83h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page  
address bits (A17 - A8) that specify the page in the main memory to be written, and eight dummy bits.  
When a low-to-high transition occurs on the CS pin, the device will first erase the selected page in main memory  
(the erased state is a Logic 1) and then program the data stored in the Buffer into that same page in main memory. Both  
the erasing and the programming of the page are internally self-timed and should take place in a maximum time of tEP  
During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.  
.
The device also incorporates intelligent erase and program algorithms that can detect when a byte location fails to erase  
or program properly. If an erase or programming error arises, it will be indicated by the EPE bit in the Status Register.  
6.3  
Buffer to Main Memory Page Program without Built-In Erase  
The Buffer to Main Memory Page Program without Built-In Erase command allows data that is stored in the Buffer to be  
written into a pre-erased page in the main memory array. It is necessary that the page in main memory to be written be  
previously erased in order to avoid programming errors.  
To perform a Buffer to Main Memory Page Program without Built-In Erase using the optional DataFlash-L page size  
(264 bytes), an opcode of 88h must be clocked into the device followed by three address bytes comprised of five dummy  
bits,10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine dummy bits.  
To perform a Buffer to Main Memory Page Program using the default page size (256 bytes), an opcode 88h must be  
clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (A17 - A8)  
that specify the page in the main memory to be written, and eight dummy bits.  
When a low-to-high transition occurs on the CS pin, the device will program the data stored in the Buffer into the  
specified page in the main memory. The page in main memory that is being programmed must have been previously  
erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase). The programming of  
the page is internally self-timed and should take place in a maximum time of tP. During this time, the RDY/BUSY bit in the  
Status Register will indicate that the device is busy.  
AT25PE20  
DS-25PE20–139C–8/2018  
10  
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program  
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.  
6.4  
Main Memory Page Program through Buffer with Built-In Erase  
The Main Memory Page Program through Buffer with Built-In Erase command combines the Buffer Write and Buffer to  
Main Memory Page Program with Built-In Erase operations into a single operation to help simplify application firmware  
development. With the Main Memory Page Program through Buffer with Built-In Erase command, data is first clocked  
into the Buffer, the addressed page in memory is then automatically erased, and then the contents of the Buffer are  
programmed into the just-erased main memory page.  
To perform a Main Memory Page Program through Buffer using the optional DataFlash-L page size (264 bytes), an  
opcode of 82h must first be clocked into the device followed by three address bytes comprised of five dummy bits,  
10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine buffer address bits  
(BFA8 - BFA0) that select the first byte in the Buffer to be written.  
To perform a Main Memory Page Program through Buffer using the default page size (256 bytes), an opcode of 82h must  
first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits  
(A17 - A8) that specify the page in the main memory to be written, and eight address bits (A7 - A0) that selects the first  
byte in the Buffer to be written.  
After all address bytes have been clocked in, the device will take data from the input pin (SI) and store it in the Buffer. If  
the end of the Buffer is reached, the device will wrap around back to the beginning of the Buffer. When there is a  
low-to-high transition on the CS pin, the device will first erase the selected page in main memory (the erased state is a  
Logic 1) and then program the data stored in the Buffer into that main memory page. Both the erasing and the  
programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the  
RDY/BUSY bit in the Status Register will indicate that the device is busy.  
The device also incorporates intelligent erase and programming algorithms that can detect when a byte location fails to  
erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register.  
6.5  
Main Memory Byte/Page Program through Buffer without Built-In Erase  
The Main Memory Byte/Page Program through the Buffer without Built-In Erase combines both the Buffer Write and  
Buffer to Main Memory Program without Built-In Erase operations to allow any number of bytes (1 to 256/264 bytes) to be  
programmed directly into previously erased locations in the main memory array. With the Main Memory Byte/Page  
Program through Buffer without Built-In Erase command, data is first clocked into Buffer, and then only the bytes clocked  
into the Buffer are programmed into the pre-erased byte locations in main memory. Multiple bytes up to the page size can  
be entered with one command sequence.  
To perform a Main Memory Byte/Page Program through the Buffer using the optional DataFlash-L page size (264 bytes),  
an opcode of 02h must first be clocked into the device followed by three address bytes comprised of five dummy bits,  
10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine buffer address bits  
(BFA8 - BFA0) that select the first byte in the Buffer to be written. After all address bytes are clocked in, the device will  
take data from the input pin (SI) and store it in the Buffer. Any number of bytes (1 to 264) can be entered. If the end of the  
Buffer is reached, then the device will wrap around back to the beginning of the Buffer.  
To perform a Main Memory Byte/Page Program through the Buffer using the default page size (256 bytes), an opcode of  
02h must first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address  
bits (PA9 - PA0) that specify the page in the main memory to be written, and eight address bits (A7 - A0) that selects the  
first byte in the Buffer to be written. After all address bytes are clocked in, the device will take data from the input pin (SI)  
and store it in the Buffer. Any number of bytes (1 to 256) can be entered. If the end of the Buffer is reached, then the  
device will wrap around back to the beginning of the Buffer. When using the default page size, the page and buffer  
address bits correspond to an 18-bit logical address (A17-A0) in the main memory.  
After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program  
operation in which the device will program the data stored in the Buffer into the main memory array. Only the data bytes  
that were clocked into the device will be programmed into the main memory.  
AT25PE20  
DS-25PE20–139C–8/2018  
11  
Example: If only two data bytes were clocked into the device, then only two bytes will be programmed into main  
memory and the remaining bytes in the memory page will remain in their previous state.  
The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise the operation will be aborted and  
no data will be programmed. The programming of the data bytes is internally self-timed and should take place in a  
maximum time of tP (the program time will be a multiple of the tBP time depending on the number of bytes being  
programmed). During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.  
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program  
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.  
6.6  
Page Erase  
The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to  
Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer  
command to be utilized at a later time.  
To perform a Page Erase with the optional DataFlash-L page size (264 bytes), an opcode of 81h must be clocked into the  
device followed by three address bytes comprised of five dummy bits, 10 page address bits (PA9 - PA0) that specify the  
page in the main memory to be erased, and nine dummy bits.  
To perform a Page Erase with the default page size (256 bytes), an opcode of 81h must be clocked into the device  
followed by three address bytes comprised of six dummy bits, 10 page address bits (A17 - A8) that specify the page in  
the main memory to be erased, and eight dummy bits.  
When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a  
Logic 1). The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the  
RDY/BUSY bit in the Status Register will indicate that the device is busy.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If  
an erase error arises, it will be indicated by the EPE bit in the Status Register.  
6.7  
Block Erase  
The Block Erase command can be used to erase a block of eight pages at one time. This command is useful when  
needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate Page Erase  
commands.  
To perform a Block Erase with the optional DataFlash-L page size (264 bytes), an opcode of 50h must be clocked into  
the device followed by three address bytes comprised of five dummy bits, seven page address bits (PA9 - PA3), and  
12 dummy bits. The seven page address bits are used to specify which block of eight pages is to be erased.  
To perform a Block Erase with the default page size (256 bytes), an opcode of 50h must be clocked into the device  
followed by three address bytes comprised of six dummy bits, seven page address bits (A17 - A11), and 11 dummy bits.  
The seven page address bits are used to specify which block of eight pages is to be erased.  
When a low-to-high transition occurs on the CS pin, the device will erase the selected block of eight pages. The erase  
operation is internally self-timed and should take place in a maximum time of tBE. During this time, the RDY/BUSY bit in  
the Status Register will indicate that the device is busy.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If  
an erase error arises, it will be indicated by the EPE bit in the Status Register.  
AT25PE20  
DS-25PE20–139C–8/2018  
12  
Table 6-1. Block Erase Addressing  
PA9/A17 PA8/A16 PA7/A15 PA6/A14 PA5/A13 PA4/A12 PA3/A11 PA2/A10 PA1/A9  
PA0/A8  
Block  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
124  
125  
126  
127  
6.8  
Sector Erase  
The Sector Erase command can be used to individually erase any sector in the main memory.  
The main memory array is comprised of nine sectors, and only one sector can be erased at a time. To perform an erase  
of Sector 0a or Sector 0b with the optional DataFlash-L page size (264 bytes), an opcode of 7Ch must be clocked into the  
device followed by three address bytes comprised of five dummy bits, seven page address bits (PA9 - PA3), and  
12 dummy bits. To perform a Sector 1-7 erase, an opcode of 7Ch must be clocked into the device followed by three  
address bytes comprised of five dummy bits, three page address bits (PA9 - PA7), and 16 dummy bits.  
To perform a Sector 0a or Sector 0b erase with the default page size (256 bytes), an opcode of 7Ch must be clocked into  
the device followed by three address bytes comprised of six dummy bits, seven page address bits (A17 - A11), and  
11 dummy bits. To perform a Sector 1-7 erase, an opcode of 7Ch must be clocked into the device followed by six dummy  
bits, three page address bits (A17 - A15), and 15 dummy bits.  
The page address bits are used to specify any valid address location within the sector is to be erased. When a  
low-to-high transition occurs on the CS pin, the device will erase the selected sector. The erase operation is internally  
self-timed and should take place in a maximum time of tSE. During this time, the RDY/BUSY bit in the Status Register will  
indicate that the device is busy.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If  
an erase error arises, it will be indicated by the EPE bit in the Status Register.  
AT25PE20  
DS-25PE20–139C–8/2018  
13  
Table 6-2. Sector Erase Addressing  
PA9/A17 PA8/A16 PA7/A15 PA6/A14 PA5/A13 PA4/A12 PA3/A11 PA2/A10 PA1/A9  
PA0/A8  
Sector  
0
0
0
0
0
0
0
0
1
0
0
X
0
0
X
0
0
0
1
X
X
X
X
X
X
X
X
X
X
0a  
0b  
1
X
1
1
1
0
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
6
7
6.9  
Chip Erase  
The Chip Erase command allows the entire main memory array to be erased at one time.  
To execute the Chip Erase command, a 4-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked into the  
device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device and any data  
clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin  
must be deasserted to start the erase process. The erase operation is internally self-timed and should take place in a  
time of tCE. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.  
The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will  
remain unchanged. Only those sectors that are not protected or locked down will be erased.  
The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle  
completes.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If  
an erase error arises, it will be indicated by the EPE bit in the Status Register.  
Table 6-3. Chip Erase Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Chip Erase  
C7h  
94h  
80h  
9Ah  
Figure 6-1. Chip Erase  
CS  
C7h  
94h  
80h  
9Ah  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
14  
6.10 Read-Modify-Write  
A completely self-contained read-modify-write operation can be performed to reprogram any number of sequential bytes  
in a page in the main memory array without affecting the rest of the bytes in the same page. This command allows the  
device to easily emulate an EEPROM by providing a method to modify a single byte or more in the main memory in a  
single operation, without the need for pre-erasing the memory or the need for any external RAM buffers. The  
Read-Modify-Write command is essentially a combination of the Main Memory Page to Buffer Transfer, Buffer Write, and  
Buffer to Main Memory Page Program with Built-in Erase commands.  
To perform a Read-Modify-Write using the optional DataFlash-L page size (264 bytes), an opcode of 58h for Buffer 1  
must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits  
(PA9 - PA0) that specify the page in the main memory to be written and nine byte address bits (BA8-BA0) that designate  
the starting byte address within the page to reprogram.  
To perform a Read-Modify-Write using the default page size (256 bytes), an opcode of 58h for Buffer 1 must be clocked  
into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (A17 - A8) that  
specify the page in the main memory to be written and eight byte address bits (A7-A0) that designate the starting byte  
address within the page to reprogram.  
After the address bytes have been clocked in, any number of sequential data bytes from one to 256/264 bytes can be  
clocked into the device. If the end of the buffer is reached when clocking in the data, then the device will wrap around  
back to the beginning of the buffer. After all data bytes have been clocked into the device, a low-to-high transition on the  
CS pin will start the self-contained, internal read-modify-write operation. Only the data bytes that were clocked into the  
device will be reprogrammed in the main memory.  
Example: If only one data byte was clocked into the device, then only one byte in main memory will be reprogrammed  
and the remaining bytes in the main memory page will remain in their previous state.  
The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and  
no data will be programmed. The reprogramming of the data bytes is internally self-timed and should take place in a  
maximum time of tP. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.  
The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to  
erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register.  
Note: The Read-Modify-Write command uses the same opcodes as the Auto Page Rewrite command. If no data bytes  
are clocked into the device, then the device will perform an Auto Page Rewrite operation. See the Auto Page  
Rewrite command description on page 22 for more details.  
AT25PE20  
DS-25PE20–139C–8/2018  
15  
7.  
Sector Protection  
Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous  
program and erase cycles. The software controlled method relies on the use of software commands to enable and  
disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin. The  
selection of which sectors that are to be protected or unprotected against program and erase operations is specified in  
the nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled  
by either the software or the hardware controlled methods can be determined by checking the Status Register.  
7.1  
Software Sector Protection  
Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host  
processor. In such instances, the WP pin may be left floating (the WP pin is internally pulled high) and sector protection  
can be controlled using the Enable Sector Protection and Disable Sector Protection commands.  
If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the  
Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used.  
7.1.1 Enable Sector Protection  
Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by  
issuing the Enable Sector Protection command. To enable the sector protection, a 4-byte command sequence of  
3Dh, 2Ah, 7Fh, and A9h must be clocked into the device. After the last bit of the opcode sequence has been clocked in,  
the CS pin must be deasserted to enable the Sector Protection.  
Table 7-1. Enable Sector Protection Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Enable Sector Protection  
3Dh  
2Ah  
7Fh  
A9h  
Figure 7-1. Enable Sector Protection  
CS  
A9h  
3Dh  
2Ah  
7Fh  
SI  
Each transition represents eight bits  
7.1.2 Disable Sector Protection  
To disable the sector protection, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and 9Ah must be clocked into the  
device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to disable the  
sector protection.  
Table 7-2. Disable Sector Protection Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Disable Sector Protection  
3Dh  
2Ah  
7Fh  
9Ah  
Figure 7-2. Disable Sector Protection  
CS  
3Dh  
2Ah  
7Fh  
9Ah  
SI  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
16  
7.2  
Hardware Controlled Protection  
Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be  
protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The  
Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as the WP  
pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is  
permanently connected to GND, then the contents of the Sector Protection Register cannot be changed. If the WP pin is  
deasserted or permanently connected to VCC, then the contents of the Sector Protection Register can be modified.  
The WP pin will override the software controlled protection method but only for protecting the sectors.  
Example: If the sectors were not previously protected by the Enable Sector Protection command, then simply  
asserting the WP pin would enable the sector protection within the maximum specified tWPE time. When the  
WP pin is deasserted, however, the sector protection would no longer be enabled (after the maximum  
specified tWPD time) as long as the Enable Sector Protection command was not issued while the WP pin was  
asserted. If the Enable Sector Protection command was issued before or while the WP pin was asserted,  
then simply deasserting the WP pin would not disable the sector protection. In this case, the Disable Sector  
Protection command would need to be issued while the WP pin is deasserted to disable the sector  
protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted.  
A noise filter is incorporated to help protect against spurious noise that my inadvertently assert or deassert the WP pin.  
Figure 7-3 and Table 7-3 detail the sector protection status for various scenarios of the WP pin, the Enable Sector  
Protection command, and the Disable Sector Protection command.  
Figure 7-3. WP Pin and Protection Status  
1
2
3
WP  
Table 7-3. WP Pin and Protection Status  
Time  
Sector  
Protection  
Status  
Sector  
Protection  
Register  
Disable Sector  
Protection Command  
Period  
WP Pin  
Enable Sector Protection Command  
Command Not Issued Previously  
X
Disabled  
Disabled  
Enabled  
Enabled  
Enabled  
Disabled  
Enabled  
Read/Write  
Read/Write  
Read/Write  
Read  
1
2
3
High  
Issue Command  
Issue Command  
Low  
X
X
Command Issued During Period 1 or 2  
Not Issued Yet  
Issue Command  
Read/Write  
Read/Write  
Read/Write  
High  
Issue Command  
AT25PE20  
DS-25PE20–139C–8/2018  
17  
7.3  
Sector Protection Register  
The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the  
software or hardware controlled protection methods. The Sector Protection Register contains eight bytes of data, of  
which byte locations 0 through 7 contain values that specify whether Sectors 0 through 7 will be protected or  
unprotected. The Sector Protection Register is user modifiable and must be erased before it can be reprogrammed.  
Table 7-4 illustrates the format of the Sector Protection Register.  
Table 7-4. Sector Protection Register  
Sector Number  
Protected  
0 (0a, 0b)  
1 to 7  
FFh  
See Table 7-5  
Unprotected  
00h  
Note: 1. The default values for bytes 0 through 7 are 00h when shipped from Adesto.  
Table 7-5. Sector 0 (0a, 0b) Sector Protection Register Byte Value  
Bit 7:6  
Bit 5:4  
Bit 3:2  
Bit 1:0  
Sector 0a  
(Page 0-7)  
Sector 0b  
(Page 8-127)  
N/A  
XX  
XX  
XX  
XX  
N/A  
XX  
XX  
XX  
XX  
Data Value  
Sectors 0a and 0b Unprotected  
Protect Sector 0a  
00  
11  
00  
11  
00  
00  
11  
11  
0Xh  
CXh  
3Xh  
FXh  
Protect Sector 0b  
Protect Sectors 0a and 0b  
Note: 1. X = Don’t care  
7.3.1 Erase Sector Protection Register  
In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector  
Protection Register command.  
To erase the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and CFh must be clocked into  
the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the  
internally self-timed erase cycle. The erasing of the Sector Protection Register should take place in a maximum time of  
tPE. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is  
powered-down before the completion of the erase cycle, then the contents of the Sector Protection Register cannot be  
guaranteed.  
The Sector Protection Register can be erased with sector protection enabled or disabled. Since the erased state (FFh) of  
each byte in the Sector Protection Register is used to indicate that a sector is specified for protection, leaving the sector  
protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention  
of accidental programming or erasing of the device. If for some reason an erroneous program or erase command is sent  
to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed,  
then the erroneous program or erase command will not be processed because all sectors would be protected.  
Table 7-6. Erase Sector Protection Register Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Erase Sector Protection Register  
3Dh  
2Ah  
7Fh  
CFh  
AT25PE20  
DS-25PE20–139C–8/2018  
18  
Figure 7-4. Erase Sector Protection Register  
CS  
SI  
3Dh  
2Ah  
7Fh  
CFh  
Each transition represents eight bits  
7.3.2 Program Sector Protection Register  
Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection  
Register command.  
To program the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be clocked  
into the device followed by eight bytes of data corresponding to Sectors 0 through 7. After the last bit of the opcode  
sequence and data have been clocked in, the CS pin must be deasserted to initiate the internally self-timed program  
cycle. The programming of the Sector Protection Register should take place in a maximum time of tP. During this time,  
the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is powered-down before the  
completion of the erase cycle, then the contents of the Sector Protection Register cannot be guaranteed.  
If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of the  
sectors corresponding to the bytes not clocked in cannot be guaranteed.  
Example: If only the first two bytes are clocked in instead of the complete eight bytes, then the protection status of the  
last six sectors cannot be guaranteed. Furthermore, if more than eight bytes of data is clocked into the  
device, then the data will wrap back around to the beginning of the register. For instance, if nine bytes of  
data are clocked in, then the ninth byte will be stored at byte location 0 of the Sector Protection Register.  
The data bytes clocked into the Sector Protection Register need to be valid values (0Xh, 3Xh, CXh, and FXh for Sector  
0a or Sector 0b, and 00h or FFh for other sectors) in order for the protection to function correctly. If a non-valid value is  
clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to  
that byte location cannot be guaranteed.  
Example: If a value of 17h is clocked into byte location 2 of the Sector Protection Register, then the protection status  
of Sector 2 cannot be guaranteed.  
The Sector Protection Register can be reprogrammed while the sector protection is enabled or disabled. Being able to  
reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the  
sector protection to an individual sector rather than disabling sector protection completely.  
The Program Sector Protection Register command utilizes the internal buffer for processing. Therefore, the contents of  
the Buffer will be altered from its previous state when this command is issued.  
Table 7-7. Program Sector Protection Register Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Program Sector Protection Register  
3Dh  
2Ah  
7Fh  
FCh  
Figure 7-5. Program Sector Protection Register  
CS  
Data Byte  
n
Data Byte  
n + 1  
Data Byte  
n + 7  
3Dh  
2Ah  
7Fh  
FCh  
SI  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
19  
7.3.3 Read Sector Protection Register  
To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device. After  
the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin will result  
in the Sector Protection Register contents being output on the SO pin. The first byte (byte location 0) corresponds to  
Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte location 7) corresponds to  
Sector 7. Once the last byte of the Sector Protection Register has been clocked out, any additional clock pulses will result  
in undefined data being output on the SO pin. The CS pin must be deasserted to terminate the Read Sector Protection  
Register operation and put the output into a high-impedance state.  
Table 7-8. Read Sector Protection Register Command  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Read Sector Protection Register  
32h  
XXh  
XXh  
XXh  
Note: 1. XX = Dummy byte  
Figure 7-6. Read Sector Protection Register  
CS  
32h  
XX  
XX  
XX  
SI  
Data  
n
Data  
n + 1  
Data  
n + 7  
SO  
Each transition represents eight bits  
7.3.4 About the Sector Protection Register  
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully  
evaluate the number of times the Sector Protection Register will be modified during the course of the application’s life  
cycle. If the application requires that the Security Protection Register be modified more than the specified limit of 10,000  
cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled  
while the Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a  
combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to  
be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded.  
AT25PE20  
DS-25PE20–139C–8/2018  
20  
8.  
Security Features  
8.1  
Security Register  
The device contains a specialized Security Register that can be used for purposes such as unique device serialization or  
locked key storage. The register is comprised of a total of 128 bytes (byte locations 0 through 127). All 128 bytes of the  
Security Register are factory programmed by Adesto and will contain a unique value for each device. The factory  
programmed data is fixed and cannot be changed.  
Table 8-1. Security Register  
Security Register Byte Number  
0
· · ·  
127  
Data Type  
Factory Programmed by Adesto  
8.1.1 Reading the Security Register  
To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last  
dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last  
byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output  
on the SO pin.  
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance  
state.  
Figure 8-1. Read Security Register  
CS  
SI  
77h  
XX  
XX  
XX  
Data  
n
Data  
n + 1  
Data  
n + x  
SO  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
21  
9.  
Additional Commands  
9.1  
Main Memory Page to Buffer Transfer  
A page of data can be transferred from the main memory to the Buffer. To transfer a page of data using the optional  
DataFlash-L page size (264 bytes), an opcode of 53h must be clocked into the device followed by three address bytes  
comprised of five dummy bits, 10 page address bits (PA9 - PA0) which specify the page in main memory to be  
transferred, and nine dummy bits. To transfer a page of data using the default page size (256 bytes), an opcode of 53h  
must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits  
(A17 - A8) which specify the page in the main memory to be transferred, and eight dummy bits.  
The CS pin must be low while toggling the SCK pin to load the opcode and the three address bytes from the input  
pin (SI). The transfer of the page of data from the main memory to the Buffer will begin when the CS pin transitions from  
a low to a high state. During the page transfer time (tXFR), the RDY/BUSY bit in the Status Register can be read to  
determine whether or not the transfer has been completed.  
9.2  
Main Memory Page to Buffer Compare  
A page of data in main memory can be compared to the data in the Buffer as a method to ensure that data was  
successfully programmed after a Buffer to Main Memory Page Program command. To compare a page of data with the  
optional DataFlash-L page size (264 bytes), an opcode of 60h must be clocked into the device followed by three address  
bytes comprised of five dummy bits, 10 page address bits (PA9 - PA0) which specify the page in the main memory to be  
compared to the Buffer, and nine dummy bits. To compare a page of data with the default page size (256 bytes), an  
opcode of 60h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page  
address bits (A17 - A8) which specify the page in the main memory to be compared to the Buffer, and eight dummy bits.  
The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). On  
the low-to-high transition of the CS pin, the data bytes in the selected Main Memory Page will be compared with the data  
bytes in the Buffer. During the compare time (tCOMP), the RDY/BUSY bit in the Status Register will indicate that the part is  
busy. On completion of the compare operation, bit 6 of the Status Register will be updated with the result of the compare.  
9.3  
Auto Page Rewrite  
This command only needs to be used if the possibility exists that static (non-changing) data may be stored in a page or  
pages of a sector and the other pages of the same sector are erased and programmed a large number of times.  
Applications that modify data in a random fashion within a sector may fall into this category. To preserve data integrity of  
a sector, each page within a sector must be updated/rewritten at least once within every 50,000 cumulative page  
erase/program operations within that sector. The Auto Page Rewrite command provides a simple and efficient method to  
“refresh” a page in the main memory array in a single operation.  
The Auto Page Rewrite command is a combination of the Main Memory Page to Buffer Transfer and Buffer to Main  
Memory Page Program with Built-In Erase commands. With the Auto Page Rewrite command, a page of data is first  
transferred from the main memory to the Buffer and then the same data is programmed back into the same page of main  
memory, essentially “refreshing” the contents of that page. To start the Auto Page Rewrite operation with the optional  
DataFlash-L page size (264 bytes), a 1-byte opcode, 58h must be clocked into the device followed by three address  
bytes comprised of five dummy bits, 10 page address bits (PA9-PA0) that specify the page in main memory to be  
rewritten, and nine dummy bits.  
To initiate an Auto Page Rewrite with the a default page size (256 bytes), the opcode 58h must be clocked into the device  
followed by three address bytes consisting of six dummy bits, 10 page address bits (A17 - A8) that specify the page in the  
main memory that is to be rewritten, and eight dummy bits. When a low-to-high transition occurs on the CS pin, the part  
will first transfer data from the page in main memory to the Buffer and then program the data from the Buffer back into  
same page of main memory. The operation is internally self-timed and should take place in a maximum time of tEP  
During this time, the RDY/BUSY Status Register will indicate that the part is busy.  
.
AT25PE20  
DS-25PE20–139C–8/2018  
22  
If a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be  
a page or pages of static data, then the programming algorithm shown in Figure 26-1 on page 56 is recommended;  
otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the  
programming algorithm shown in Figure 26-2 on page 57 is recommended.  
Please contact Adesto for availability of devices that are specified to exceed the 50,000 cycle cumulative limit.  
Note: The Auto Page Rewrite command uses the same opcodes as the Read-Modify-Write command. If data bytes  
are clocked into the device, then the device will perform a Read-Modify-Write operation. See the Read-Modify-  
Write command description on page 15 for more details.  
9.4  
Status Register Read  
The 2-byte Status Register can be used to determine the device's ready/busy status, page size, a Main Memory Page to  
Buffer Compare operation result, the sector protection status, erase/program error status, and the device density. The  
Status Register can be read at any time, including during an internally self-timed program or erase operation.  
To read the Status Register, the CS pin must first be asserted and then the opcode D7h must be clocked into the device.  
After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every  
subsequent clock cycle. After the second byte of the Status Register has been clocked out, the sequence will repeat  
itself, starting again with the first byte of the Status Register, as long as the CS pin remains asserted and the clock pin is  
being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence may output new  
data. The RDY/BUSY status is available for both bytes of the Status Register and is updated for each byte.  
Deasserting the CS pin will terminate the Status Register Read operation and put the SO pin into a high-impedance  
state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.  
Table 9-1. Status Register Format – Byte 1  
Type(1)  
Bit Name  
Description  
0
1
0
1
Device is busy with an internal operation.  
7
6
RDY/BUSY Ready/Busy Status  
R
Device is ready.  
Main memory page data matches buffer data.  
Main memory page data does not match buffer data.  
COMP  
Compare Result  
R
R
R
5:2 DENSITY Density Code  
Sector Protection  
0101 2-Mbit  
0
1
Sector protection is disabled.  
1
PROTECT  
Status  
Sector protection is enabled.  
Device is configured for optional DataFlash-L page size (264  
bytes).  
0
1
Page Size  
Configuration  
0
PAGE SIZE  
R
Device is configured for default page size (256 bytes).  
Note: 1. R = Readable only  
AT25PE20  
DS-25PE20–139C–8/2018  
23  
Table 9-2. Status Register Format – Byte 2  
Bit Name  
Type(1)  
Description  
0
1
x
0
1
x
x
x
x
x
Device is busy with an internal operation.  
7
6
5
RDY/BUSY Ready/Busy Status  
R
R
R
Device is ready.  
RES  
EPE  
Reserved for Future Use  
Erase/Program Error  
Reserved for future use.  
Erase or program operation was successful.  
Erase or program error detected.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
4
3
2
1
0
RES  
RES  
RES  
RES  
RES  
Reserved for Future Use  
Reserved for Future Use  
Reserved for Future Use  
Reserved for Future Use  
Reserved for Future Use  
R
R
R
R
R
Note: 1. R = Readable only  
2. x = Don’t care. Can be “0” or “1”.  
9.4.1 RDY/BUSY Bit  
The RDY/BUSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress.  
To poll the RDY/BUSY bit to detect the completion of an internally timed operation, new Status Register data must be  
continually clocked out of the device until the state of the RDY/BUSY bit changes from a Logic 0 to a Logic 1 to indicate  
completion.  
9.4.2 COMP Bit  
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using the COMP bit. If the  
COMP bit is a Logic 1, then at least one bit of the data in the Main Memory Page does not match the data in the Buffer.  
9.4.3 DENSITY Bits  
The device density is indicated using the DENSITY bits. For the AT25PE20, the four bit binary value is 0101. The  
decimal value of these four binary bits does not actually equate to the device density; the four bits represent a  
combinational code relating to differing densities of DataFlash-L devices. The DENSITY bits are not the same as the  
density code indicated in the JEDEC Device ID information. The DENSITY bits are provided only for backward  
compatibility to older generation DataFlash-L devices.  
9.4.4 PROTECT Bit  
The PROTECT bit provides information to the user on whether or not the sector protection has been enabled or disabled,  
either by the software-controlled method or the hardware-controlled method.  
9.4.5 PAGE SIZE Bit  
The PAGE SIZE bit indicates whether the Buffer size and the page size of the main memory array is configured for the  
default page size (256 bytes) or the optional DataFlash-L page size (264 bytes).  
AT25PE20  
DS-25PE20–139C–8/2018  
24  
9.4.6 EPE Bit  
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte  
during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state.  
The EPE bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or  
program a protected region. The EPE bit is updated after every erase and program operation.  
AT25PE20  
DS-25PE20–139C–8/2018  
25  
10. Deep Power-Down  
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin  
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place  
the device into an even lower power consumption state called the Deep Power-Down mode.  
When the device is in the Deep Power-Down mode, all commands including the Status Register Read command will be  
ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the  
mode can be used as an extra protection mechanism against program and erase operations.  
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode B9h, and  
then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS  
pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD  
.
The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device will abort the operation  
and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode  
after a power cycle.  
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is  
in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been  
completed in order for the device to enter the Deep Power-Down mode.  
Figure 10-1. Deep Power-Down  
CS  
tEDPD  
0
1
2
3
4
5
6
7
SCK  
OPCODE  
1
0
1
1
1
0
0
1
SI  
MSB  
HIGH-IMPEDANCE  
Active Current  
SO  
I
CC  
Standby Mode Current  
Deep Power-Down Mode Current  
AT25PE20  
DS-25PE20–139C–8/2018  
26  
10.1 Resume from Deep Power-Down  
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down  
command must be issued. The Resume from Deep Power-Down command is the only command that the device will  
recognize while in the Deep Power-Down mode.  
To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be  
clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is  
deasserted, the device will exit the Deep Power-Down mode and return to the standby mode within the maximum time of  
t
RDPD. After the device has returned to the standby mode, normal command operations such as Continuous Array Read  
can be resumed.  
If the complete opcode is not clocked in before the CS pin is deasserted, then the device will abort the operation and  
return to the Deep Power-Down mode.  
Figure 10-2. Resume from Deep Power-Down  
CS  
tRDPD  
0
1
2
3
4
5
6
7
SCK  
SI  
Opcode  
1
0
1
0
1
0
1
1
MSB  
High-impedance  
Active Current  
SO  
I
CC  
Standby Mode Current  
Deep Power-Down Mode Current  
AT25PE20  
DS-25PE20–139C–8/2018  
27  
10.2 Ultra-Deep Power-Down  
The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep  
Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shut down in this  
mode to conserve power, the contents of the Buffer cannot be maintained. Therefore, any data stored in the Buffer will be  
lost once the device enters the Ultra-Deep Power-Down mode.  
When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and Resume  
from Deep Power-Down commands will be ignored. Since all commands will be ignored, the mode can be used as an  
extra protection mechanism against program and erase operations.  
Entering the Ultra-Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode 79h,  
and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the  
CS pin is deasserted, the device will enter the Ultra-Deep Power-Down mode within the maximum time of tEUDPD  
.
The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device will abort the operation  
and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode  
after a power cycle.  
The Ultra-Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase  
cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed operation  
has been completed in order for the device to enter the Ultra-Deep Power-Down mode.  
Figure 10-3. Ultra-Deep Power-Down  
CS  
tEUDPD  
0
1
2
3
4
5
6
7
SCK  
SI  
Opcode  
0
1
1
1
1
0
0
1
MSB  
High-impedance  
SO  
Active Current  
I
CC  
Standby Mode Current  
Ultra-Deep Power-Down Mode Current  
AT25PE20  
DS-25PE20–139C–8/2018  
28  
10.2.1 Exit Ultra-Deep Power-Down  
To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the  
minimum necessary tCSLU time, and then deasserting the CS pin again. To facilitate simple software development, a  
dummy byte opcode can also be entered while the CS pin is being pulsed; the dummy byte opcode is simply ignored by  
the device in this case. After the CS pin has been deasserted, the device will exit from the Ultra-Deep Power-Down mode  
and return to the standby mode within a maximum time of tXUDPD. If the CS pin is reasserted before the tXUDPD time has  
elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will be performed. The  
system must wait for the device to return to the standby mode before normal command operations such as Continuous  
Array Read can be resumed.  
Since the contents of the Buffer cannot be maintained while in the Ultra-Deep Power-Down mode, the Buffer will contain  
undefined data when the device returns to the standby mode.  
Figure 10-4. Exit Ultra-Deep Power-Down  
CS  
tCSLU  
tXUDPD  
High-impedance  
SO  
Active Current  
ICC  
Standby Mode Current  
Ultra-Deep Power-Down Mode Current  
AT25PE20  
DS-25PE20–139C–8/2018  
29  
11. Buffer and Page Size Configuration  
The memory array of DataFlash-L devices is actually larger than other Serial Flash devices in that extra user-accessible  
bytes are provided in each page of the memory array. For the AT25PE20, there are an extra eight bytes of memory in  
each page for a total of an extra 8KB (64-Kbits) of user-accessible memory.  
Some applications, however, may not want to take advantage of this extra memory and instead architect their software to  
operate on a binary, logical addressing scheme. To allow this, the DataFlash-L can be configured so that the Buffer and  
page sizes are 256 bytes instead of the optional 264 bytes. In addition, the configuration of the Buffer and page sizes is  
reversible and can be changed from 264 bytes to 256 bytes or from 256 bytes to 264 bytes. The configured setting is  
stored in an internal nonvolatile register so that the Buffer and page size configuration is not affected by power cycles.  
The nonvolatile register has a limit of 10,000 erase/program cycles; therefore, care should be taken to not switch  
between the size options more than 10,000 times.  
Devices are initially shipped from Adesto with the Buffer and page sizes set to 256 bytes. To configure the device for  
default page size (256 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A6h must be clocked into the device.  
After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-  
timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should  
take place in a time of tEP, during which time, the RDY/BUSY bit in the Status Register will indicate that the device is  
busy. The device does not need to be power cycled after the completion of the configuration process and register  
program cycle in order for the Buffer and page size to be configured to 256 bytes.  
To configure the device for optional DataFlash-L page size (264 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and  
A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be  
deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. The  
programming of the nonvolatile register should take place in a time of tEP, during which time, the RDY/BUSY bit in the  
Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of  
the configuration process and register program cycle in order for the Buffer and page size to be configured to 264 bytes.  
Table 11-1. Buffer and Page Size Configuration Commands  
Command  
Byte 1  
3Dh  
Byte 2  
2Ah  
Byte 3  
80h  
Byte 4  
A6h  
Default DataFlash-L page size (256 bytes)  
Optional DataFlash-L page size (264 bytes)  
3Dh  
2Ah  
80h  
A7h  
Figure 11-1. Buffer and Page Size Configuration  
CS  
Opcode  
Byte 4  
3Dh  
2Ah  
80h  
SI  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
30  
12. Manufacturer and Device ID Read  
Identification information can be read from the device to enable systems to electronically query and identify the device  
while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for  
“Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of  
information that can be read from the device includes the JEDEC-defined Manufacturer ID, the vendor-specific  
Device ID, and the vendor-specific Extended Device Information.  
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all Flash  
devices are capable of operating at very high clock frequencies, applications should be designed to read the  
identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the  
application can be identified properly. Once the identification process is complete, the application can then increase the  
clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies.  
To read the identification information, the CS pin must first be asserted, and then the opcode 9Fh must be clocked into  
the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin  
during the subsequent clock cycles. The first byte to be output will be the Manufacturer ID, followed by two bytes of the  
Device ID information. The fourth byte output will be the Extended Device Information (EDI) String Length, which will be  
01h, indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin will go into a  
high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As  
indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional.  
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a  
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.  
Table 12-1. Manufacturer and Device ID Information  
Byte No.  
Data Type  
Value  
1Fh  
23h  
1
2
3
4
5
Manufacturer ID  
Device ID (Byte 1)  
Device ID (Byte 2)  
00h  
Extended Device Information (EDI) String Length  
[Optional to Read] EDI Byte 1  
01h  
00h  
Table 12-2. Manufacturer and Device ID Details  
Hex  
Data Type  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details  
JEDEC Assigned Code  
Manufacturer ID  
1Fh  
23h  
00h  
JEDEC code: 0001 1111 (1Fh for Adesto)  
0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
Family Code  
Density Code  
0
Family code: 001 (AT45Dxxx Family)  
Density code: 00011 (2-Mbit)  
Device ID (Byte 1)  
Device ID (Byte 2)  
0
Sub Code  
0
Product Variant  
Sub code:  
000 (Standard Series)  
Product variant:00000  
0
0
0
AT25PE20  
DS-25PE20–139C–8/2018  
31  
Table 12-3. EDI Data  
Hex  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details  
Byte Number  
RFU  
0
Device Revision  
RFU:  
Reserved for Future Use  
5
00h  
Device revision:00000 (Initial Version)  
0
0
0
0
0
0
0
Figure 12-1. Read Manufacturer and Device ID  
CS  
0
6
7
8
14 15 16  
22 23 24  
30 31 32  
38 39 40  
47  
SCK  
SI  
Opcode  
9Fh  
High-impedance  
1Fh  
23h  
00h  
01h  
EDI  
00h  
EDI  
SO  
Manufacturer ID  
Device ID  
Byte 1  
Device ID  
Byte 2  
String Length  
Data Byte 1  
Note: Each transition  
shown for SI and SO represents one byte (eight bits)  
AT25PE20  
DS-25PE20–139C–8/2018  
32  
13. Software Reset  
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the  
hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The  
Software Reset command allows a program or erase operation in progress to be ended abruptly and returns the device  
to an idle state.  
To perform a Software Reset, the CS pin must be asserted and a 4-byte command sequence of F0h, 00h, 00h, and 00h  
must be clocked into the device. Any additional data clocked into the device after the last byte will be ignored. When the  
CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time tSWRST. Since  
the program or erase operation may not complete before the device is reset, the contents of the page being programmed  
or erased cannot be guaranteed to be valid.  
The Software Reset command has no effect on the states of the Sector Protection Register or the Buffer and page size  
configuration.  
The complete 4-byte opcode must be clocked into the device before the CS pin is deasserted; otherwise, no reset  
operation will be performed.  
Table 13-1. Software Reset  
Command  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Software Reset  
F0h  
00h  
00h  
00h  
Figure 13-1. Software Reset  
CS  
F0h  
00h  
00h  
00h  
SI  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
33  
14. Operation Mode Summary  
The commands described previously can be grouped into four different categories to better describe which commands  
can be executed at what times.  
Group A commands consist of:  
1. Main Memory Page Read  
2. Continuous Array Read (SPI)  
3. Read Sector Protection Register  
4. Read Security Register  
5. Buffer Read  
Group B commands consist of:  
1. Page Erase  
2. Block Erase  
3. Sector Erase  
4. Chip Erase  
5. Main Memory Page to the Buffer Transfer  
6. Main Memory Page to the Buffer Compare  
7.  
8.  
Buffer to Main Memory Page Program with Built-In Erase  
Buffer to Main Memory Page Program without Built-In Erase  
9. Main Memory Page Program through the Buffer with Built-In Erase  
10. Main Memory Byte/Page Program through Buffer without Built-In Erase  
11. Auto Page Rewrite  
12. Read-Modify-Write  
Group C commands consist of:  
1. Buffer Write  
2. Status Register Read  
3. Manufacturer and Device ID Read  
Group D commands consist of:  
1. Erase Sector Protection Register  
2. Program Sector Protection Register  
3. Buffer and Page Size Configuration  
If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D should not be  
started. However, during the internally self-timed portion of Group B commands, any command in Group C can be  
executed. The Group B commands using the Buffer should use Group C commands. Finally, during the internally  
self-timed portion of a Group D command, only the Status Register Read command should be executed.  
AT25PE20  
DS-25PE20–139C–8/2018  
34  
15. Command Tables  
Table 15-1. Read Commands  
Command  
Opcode  
D2h  
01h  
Main Memory Page Read  
Continuous Array Read (Low Power Mode)  
Continuous Array Read (Low Frequency)  
Continuous Array Read (High Frequency)  
Continuous Array Read (Legacy Command – Not Recommended for New Designs)  
Buffer Read (Low Frequency)  
03h  
0Bh  
E8h  
D1h  
D4h  
Buffer Read (High Frequency)  
Table 15-2. Program and Erase Commands  
Command  
Opcode  
Buffer Write  
84h  
Buffer to Main Memory Page Program with Built-In Erase  
Buffer to Main Memory Page Program without Built-In Erase  
Main Memory Page Program through Buffer with Built-In Erase  
Main Memory Byte/Page Program through Buffer without Built-In Erase  
Page Erase  
83h  
88h  
82h  
02h  
81h  
Block Erase  
50h  
Sector Erase  
7Ch  
C7h + 94h + 80h + 9Ah  
58h  
Chip Erase  
Read-Modify-Write through Buffer 1  
AT25PE20  
DS-25PE20–139C–8/2018  
35  
Table 15-3. Protection and Security Commands  
Command  
Opcode  
Enable Sector Protection  
3Dh + 2Ah + 7Fh + A9h  
3Dh + 2Ah + 7Fh + 9Ah  
3Dh + 2Ah + 7Fh + CFh  
3Dh + 2Ah + 7Fh + FCh  
32h  
Disable Sector Protection  
Erase Sector Protection Register  
Program Sector Protection Register  
Read Sector Protection Register  
Read Security Register  
77h  
Table 15-4. Additional Commands  
Command  
Opcode  
Main Memory Page to Buffer Transfer  
Main Memory Page to Buffer Compare  
Auto Page Rewrite  
53h  
60h  
58h  
Deep Power-Down  
B9h  
Resume from Deep Power-Down  
Ultra-Deep Power-Down  
ABh  
79h  
Status Register Read  
D7h  
Manufacturer and Device ID Read  
Configure Default 256 Byte Page Size  
Configure Optional 264 Byte DataFlash-L Page Size  
Software Reset  
9Fh  
3Dh + 2Ah + 80h + A6h  
3Dh + 2Ah + 80h + A7h  
F0h + 00h + 00h + 00h  
Table 15-5. Legacy Commands(1)  
Command  
Opcode  
Buffer Read  
54H  
52H  
68H  
57H  
Main Memory Page Read  
Continuous Array Read  
Status Register Read  
Note: 1. Legacy commands are not recommended for new designs.  
AT25PE20  
DS-25PE20–139C–8/2018  
36  
Table 15-6. Detailed Bit-level Addressing Sequence for Default Page Size (256 bytes)  
Page Size = 256-bytes Address Byte Address Byte  
Address Byte  
Additional  
Dummy  
Bytes  
Opcode  
Opcode  
01h  
02h  
03h  
0Bh  
1Bh  
32h  
50h  
53h  
58h (1)  
58h (2)  
60h  
77h  
79h  
7Ch  
81h  
82h  
83h  
84h  
88h  
9Fh  
B9h  
ABh  
D1h  
D2h  
D4h  
D7h  
E8h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
0
1
1
0
1
0
1
0
0
1
1
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
X
X
A
A
A
A
X
A
A
A
A
A
X
X
A
A
A
A
X
A
A
A
A
A
X
X
A
A
A
A
X
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
X
X
X
X
A
X
X
A
A
A
A
A
X
X
X
X
A
X
X
N/A  
N/A  
N/A  
1
X
A
A
X
A
A
X
A
A
2
X
X
X
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
4
X
A
X
X
A
X
X
A
X
X
A
A
X
A
X
X
X
X
N/A  
X
N/A  
X
N/A  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
X
A
X
A
A
A
X
A
X
A
A
A
X
A
X
A
A
A
X
A
X
A
A
A
X
A
X
A
A
A
X
A
X
A
A
A
X
A
X
X
A
X
A
X
X
X
A
X
A
X
X
X
A
X
A
X
X
X
A
X
A
X
X
X
A
X
A
X
X
X
A
X
A
X
X
X
A
X
A
X
X
A
X
X
A
A
X
A
X
X
X
A
X
A
X
N/A  
N/A  
N/A  
X
N/A  
N/A  
N/A  
X
N/A  
N/A  
N/A  
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
X
X
A
X
X
A
X
X
A
X
X
A
X
X
A
X
X
A
X
X
A
X
X
A
X
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X
A
A
X
X
A
1
N/A  
X
N/A  
A
N/A  
A
N/A  
4
X
X
X
X
X
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1. Shown to indicate when Auto Page Rewrite Operation is executed.  
2. Shown to indicate when Read Modify Write Operation is executed.  
Note:  
X = Dummy Bit  
AT25PE20  
DS-25PE20–139C–8/2018  
37  
Table 15-7. Detailed Bit-level Addressing Sequence for Optional Page Size (264 bytes)  
Page Size = 264-bytes Address Byte Address Byte  
Address Byte  
Additional  
Dummy  
Bytes  
Opcode  
Opcode  
01h  
02h  
03h  
0Bh  
1Bh  
32h  
50h  
53h  
58h(1)  
58h(2)  
60h  
77h  
79h  
7Ch  
81h  
82h  
83h  
84h  
88h  
9Fh  
B9h  
ABh  
D1h  
D2h  
D4h  
D7h  
E8h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
0
1
1
0
1
0
1
0
0
1
1
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
X
X
P
P
P
P
X
P
P
P
P
P
X
X
P
P
P
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
B
B
B
B
B
X
X
X
X
B
X
X
N/A  
N/A  
N/A  
1
X
P
B
X
P
B
X
P
B
2
X
X
X
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
4
X
X
X
X
P
X
X
P
X
X
P
B
X
P
X
X
X
X
N/A  
X
N/A  
X
N/A  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
X
P
X
P
P
P
X
P
X
P
P
P
X
P
X
P
P
P
X
P
X
P
P
P
X
P
X
P
P
P
X
P
X
P
P
P
X
P
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
X
B
X
B
X
X
P
X
X
P
B
X
P
X
X
X
B
X
P
X
N/A  
N/A  
N/A  
X
N/A  
N/A  
N/A  
X
N/A  
N/A  
N/A  
B
X
X
X
X
X
X
X
X
X
X
X
X
X
P
X
X
P
X
X
P
X
X
P
X
X
P
X
X
P
X
X
P
X
X
P
X
X
P
X
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
X
P
B
X
X
B
1
N/A  
X
N/A  
P
N/A  
B
N/A  
4
X
X
X
X
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
1. Shown to indicate when Auto Page Rewrite Operation is executed.  
2. Shown to indicate when Read Moodify Write Operation is executed.  
Note:  
P = Page Address Bit B = Byte/Buffer Address Bit X = Dummy Bit  
AT25PE20  
DS-25PE20–139C–8/2018  
38  
16. Power-On/Reset State  
When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) will be in a high  
impedance state, and a high-to-low transition on the CSB pin will be required to start a valid instruction. The SPI mode  
(Mode 3 or Mode 0) will be automatically selected on every falling edge of CSB by sampling the inactive clock state.  
16.1 Power-Up/Power-Down Voltage and Timing Requirements  
As the device initializes, there will be a transient current demand. The system needs to be capable of providing this  
current to ensure correct initialization. During power-up, the device must not be accessed for at least the minimum tVCSL  
time after the supply voltage reaches the minimum VCC level. While the device is being powered-up, the internal Power-  
On Reset (POR) circuitry keeps the device in a reset mode until the supply voltage rises above the maximum POR  
threshold value (VPOR). During this time, all operations are disabled and the device will not respond to any commands.  
After power-up, the device will be in the standby mode.  
If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be  
started until the supply voltage reaches the minimum VCC level and an internal device delay has elapsed. This delay will  
be a maximum time of tPUW  
.
Table 16-1. Voltage and Timing Requirements for Power-Up/Power-Down  
Symbol  
Parameter  
Min  
Max  
Units  
V
(1)  
VPWD  
VCC for device initialization  
1.0  
(1)  
tPWD  
Minimum duration for device initialization  
Minimum VCC to chip select low time for Read command  
VCC rise time  
300  
70  
µs  
tVCSL  
µs  
(1)  
tVR  
1
500000  
µs/V  
V
VPOR  
tPUW  
Power on reset voltage  
1.45  
1.6  
3
Power up delay time before Program or Erase is allowed  
ms  
1. Not 100% tested (value guaranteed by design and characterization).  
Figure 16-1. Power-Up Timing  
VCC  
VCC min  
VPOR max  
tPUW  
Full Operation Permitted  
Read Operation  
Permitted  
tVCSL  
VPWD max  
tPWD  
tVR  
Time  
AT25PE20  
DS-25PE20–139C–8/2018  
39  
17. System Considerations  
The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals  
must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted  
as multiple edges and will cause improper operation of the device. PCB traces must be kept to a minimum distance or  
appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to  
provide filtering against noise glitches.  
As system complexity continues to increase, voltage regulation is becoming more important. A key element of any  
voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash-L  
devices occurs during the programming and erasing operations. The supply voltage regulator needs to be able to supply  
this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system  
noise, current starvation during programming or erasing can lead to improper operation and possible data corruption.  
AT25PE20  
DS-25PE20–139C–8/2018  
40  
18. Electrical Specifications  
18.1 Absolute Maximum Ratings*  
*Notice: Stresses beyond those listed under “Absolute  
Maximum Ratings” may cause permanent  
damage to the device. This is a stress rating only  
and functional operation of the device at these or  
any other conditions beyond those indicated in  
the operational sections of this specification is not  
implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device  
reliability.Voltage extremes referenced in the  
“Absolute Maximum Ratings” are intended to  
accommodate short duration  
Temperature under Bias . . . . . . . -55°C to +125°C  
Storage Temperature. . . . . . . . . . -65°C to +150°C  
Absolute Maximum Vcc . . . . . . . . . . . . . . . . .3.96V  
All Output Voltages with Respect to Ground  
undershoot/overshoot conditions and does not  
imply or guarantee functional device operation at  
these levels for any extended period of time.  
. . . . . . . . -0.6V to 4.2V (Max VCC of 3.6V + 0.6V)  
All Input Voltages with Respect to Ground  
(excluding VCC pin, including NC pins)  
. . . . . . . . -0.6V to 4.2V (Max VCC of 3.6V + 0.6V)  
18.2 DC and AC Operating Range  
AT25PE20  
-40°C to 85°C  
1.65V to 3.6V  
Operating Temperature (Case)  
VCC Power Supply  
Industrial  
AT25PE20  
DS-25PE20–139C–8/2018  
41  
18.3 DC Characteristics  
1.65V to 3.6V  
Typ  
2.3V to 3.6V  
Typ  
Symbol Parameter  
Condition(3)  
Min  
Max  
Min  
Max  
Units  
Ultra-Deep Power-  
IUDPD  
CS= VCC. All other inputs at  
0V or VCC  
0.5  
6
2
0.4  
8
2
µA  
Down Current  
Deep Power-Down  
Current  
CS= VCC. All other inputs at  
0V or VCC  
IDPD  
12  
40  
12  
40  
µA  
µA  
CS= VCC. All other inputs at  
0V or VCC  
ISB  
Standby Current  
25  
25  
f = 1MHz; IOUT = 0mA  
(1)(2)  
(1)(2)  
ActiveCurrent, Low  
Power Read (01h)  
Operation  
6
9
6
9
mA  
ICC1  
f = 15MHz; IOUT = 0mA  
f = 50MHz; IOUT = 0mA  
7
10  
12  
7
10  
12  
mA  
mA  
10  
10  
Active Current,  
Read Operation  
ICC2  
f = 85MHz; IOUT = 0mA  
CS = VCC  
12  
15  
12  
12  
15  
12  
mA  
mA  
Active Current,  
Program Operation  
(1)(2)  
(1)(2)  
ICC3  
10  
8
10  
8
Active Current,  
Erase Operation  
ICC4  
ILI  
CS = VCC  
12  
1
12  
1
mA  
µA  
µA  
Input Load Current  
All inputs at CMOS levels  
All inputs at CMOS levels  
Output Leakage  
Current  
ILO  
1
1
VCC  
0.2  
x
VCC  
0.3  
x
VIL  
Input Low Voltage  
Input High Voltage  
V
VCC  
0.8  
x
VCC  
0.7  
x
-
VIH  
V
V
V
VOL  
VOH  
Output Low Voltage IOL = 100µA  
0.2  
0.4  
Output High  
IOH = -100µA  
Voltage  
VCC  
0.2V  
-
VCC  
0.2V  
Notes: 1. Typical values measured at 1.8V @ 25°C for the 1.65V to 3.6V range.  
2. Typical values measured at 3.0V @ 25°C for the 2.3V to 3.6V range.  
3. All inputs (SI, SCK, CS, WP, and RESET) are guaranteed by design to be 5V tolerant.  
18.4 AC Characteristics  
1.65V to 3.6V  
Typ  
2.3V to 3.6V  
Symbol  
fSCK  
Parameter  
Min  
Max  
70  
Min  
Typ  
Max  
70  
Units  
MHz  
MHz  
SCK Frequency  
fCAR1  
SCK Frequency for Continuous Read  
70  
85  
33  
SCK Frequency for Continuous Read  
(Low Frequency)  
fCAR2  
33  
MHz  
AT25PE20  
DS-25PE20–139C–8/2018  
42  
1.65V to 3.6V  
Typ  
2.3V to 3.6V  
Typ  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Units  
SCK Frequency for Continuous Read  
(Low Power Mode – 01h Opcode)  
fCAR3  
15  
15  
MHz  
tWH  
tWL  
SCK High Time  
4
4
4
4
ns  
ns  
SCK Low Time  
(1)  
tSCKR  
SCK Rise Time, Peak-to-peak  
SCK Fall Time, Peak-to-peak  
Minimum CS High Time  
CS Setup Time  
0.1  
0.1  
20  
6
0.1  
0.1  
20  
5
V/ns  
V/ns  
ns  
(1)  
tSCKF  
tCS  
tCSS  
tCSH  
tSU  
tH  
ns  
CS Hold Time  
5
5
ns  
Data In Setup Time  
2
2
ns  
Data In Hold Time  
1
1
ns  
tHO  
Output Hold Time  
0
0
ns  
(1)  
tDIS  
Output Disable Time  
Output Valid  
8
7
1
1
3
6
6
1
1
3
ns  
tV  
ns  
tWPE  
tWPD  
WP Low to Protection Enabled  
WP High to Protection Disabled  
CS High to Ultra-Deep Power-Down  
µs  
µs  
(1)  
tEUDPD  
µs  
Minimum CS Low Time to Exit Ultra-Deep  
Power-Down  
tCSLU  
20  
20  
ns  
tXUDPD  
Exit Ultra-Deep Power-Down Time  
CS High to Deep Power-Down  
Resume from Deep Power-Down Time  
Page to Buffer Transfer Time  
Page to Buffer Compare Time  
RESET Pulse Width  
240  
2
120  
2
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
(1)  
tEDPD  
tRDPD  
35  
35  
tXFR  
tCOMP  
tRST  
100  
100  
100  
100  
10  
10  
tREC  
RESET Recovery Time  
1
1
tSWRST  
Software Reset Time  
35  
35  
Note: 1. Values are based on device characterization, not 100% tested in production.  
AT25PE20  
DS-25PE20–139C–8/2018  
43  
18.5 Program and Erase Characteristics  
Symbol  
Parameter  
Typ  
Max  
35  
3
Typ  
Max  
25  
3
Units  
Page Erase and Programming Time (256/264  
bytes)  
tEP  
10  
10  
ms  
tP  
Page Programming Time  
Byte Programming Time  
Page Erase Time  
1.5  
8
1.5  
8
ms  
µs  
ms  
ms  
ms  
s
tBP  
tPE  
tBE  
tSE  
tCE  
6
25  
35  
550  
4
6
25  
35  
550  
4
Block Erase Time  
25  
350  
3
25  
350  
3
Sector Erase Time  
Chip Erase Time  
19. Input Test Waveforms and Measurement Levels  
0.9VCC  
AC  
AC  
Driving  
Levels  
VCC/2  
Measurement  
Level  
0.1VCC  
t , t < 2ns (10% to 90%)  
R
F
20. Output Test Load  
Device  
Under  
Test  
30pF  
AT25PE20  
DS-25PE20–139C–8/2018  
44  
21. Utilizing the RapidS Function  
To take advantage of the RapidS function’s ability to operate at higher clock frequencies, a full clock cycle must be used  
to transmit data back and forth across the serial bus. The DataFlash-L is designed to always clock its data out on the  
falling edge of the SCK signal and clock data in on the rising edge of SCK.  
For full clock cycle operation to be achieved, when the DataFlash-L is clocking data out on the falling edge of SCK, the  
host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock  
its data out on the rising edge of SCK in order to give the DataFlash-L a full clock cycle to latch the incoming data in on  
the next rising edge of SCK.  
Figure 21-1. RapidS Mode  
Slave CS  
1
8
1
8
1
2
3
4
5
6
7
2
3
4
5
6
7
SCK  
MOSI  
MISO  
B
E
A
C
D
MSB  
LSB  
BYTE-MOSI  
H
G
I
F
MSB  
LSB  
BYTE-SO  
MOSI = Master Out, Slave In  
MISO = Master In, Slave Out  
The Master is the host controller and the Slave is the DataFlash.  
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.  
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.  
A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK  
B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK  
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK  
D. Last bit of BYTE-MOSI is clocked out from the Master  
E. Last bit of BYTE-MOSI is clocked into the slave  
F. Slave clocks out first bit of BYTE-SO  
G. Master clocks in first bit of BYTE-SO  
H. Slave clocks out second bit of BYTE-SO  
I. Master clocks in last bit of BYTE-SO  
AT25PE20  
DS-25PE20–139C–8/2018  
45  
Figure 21-2. Command Sequence for Read/Write Operations for Page Size 256 bytes  
(Except Status Register Read, Manufacturer and Device ID Read)  
SI (Input)  
CMD  
8-bits  
8-bits  
8-bits  
X X X X X X X X X X X X X X X X X X X X X X X X  
LSB  
MSB  
6 Dummy  
Bits  
Page Address  
(A17 - A8)  
Byte/Buffer Address  
(A7 - A0/BFA7 - BFA0)  
Figure 21-3. Command Sequence for Read/Write Operations for Page Size 264 bytes  
(Except Status Register Read, Manufacturer and Device ID Read)  
SI (Input)  
MSB  
CMD  
8-bits  
8-bits  
8-bits  
X
X X X X X X X X X X X X X X X  
X X X X X X X X  
LSB  
5 Dummy  
Bits  
Page Address  
(PA9 - PA0)  
Byte/Buffer Address  
(BA8 - BA0/BFA8 - BFA0)  
AT25PE20  
DS-25PE20–139C–8/2018  
46  
22. AC Waveforms  
Four different timing waveforms are shown in Figure 22-1 through F1ig.6u5reV2to2-34..6WV aveform 12.s3hVotwos3t.h6eVSCK signal being  
low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a  
high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified  
as tWL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies only up to 70MHz.  
Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.  
Waveform 3 and 4 illustrate general timing diagrams for RapidS serial interface. These are similar to Waveform 1 and 2,  
except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the  
full frequency range (maximum frequency = 70MHz) of the RapidS serial case.  
Figure 22-1. Waveform 1 = SPI Mode 0 Compatible  
tCS  
CS  
tCSS  
tWH  
tWL  
tCSH  
SCK  
SO  
SI  
tV  
tHO  
tDIS  
High-impedance  
tSU  
High-impedance  
Valid Out  
tH  
Valid In  
Figure 22-2. Waveform 2 = SPI Mode 3 Compatible  
tCS  
CS  
tCSS  
tWL  
tWH  
tCSH  
SCK  
SO  
tV  
tHO  
tDIS  
High Z  
High-impedance  
Valid Out  
tH  
tSU  
Valid In  
SI  
AT25PE20  
DS-25PE20–139C–8/2018  
47  
Figure 22-3. Waveform 3 = RapidS Mode 0  
tCS  
CS  
tCSS  
tWH  
tWL  
tCSH  
SCK  
SO  
SI  
tV  
tHO  
tDIS  
High-impedance  
tSU  
High-impedance  
Valid Out  
tH  
Valid In  
Figure 22-4. Waveform 4 = RapidS Mode 3  
tCS  
CS  
tCSS  
tWL  
tWH  
tCSH  
SCK  
SO  
tV  
tHO  
tDIS  
High Z  
High-impedance  
Valid Out  
tH  
tSU  
Valid In  
SI  
AT25PE20  
DS-25PE20–139C–8/2018  
48  
23. Write Operations  
The following block diagram and waveforms illustrate the various write sequences available.  
Figure 23-1. Block Diagram  
Flash Memory Array  
Page (256/264 bytes)  
Buffer To  
Main Memory  
Page Program  
Buffer (256/264 bytes)  
Buffer  
Write  
I/O Interface  
SI  
Figure 23-2. Buffer Write  
Completes Writing into Selected Buffer  
CS  
Default Page Size  
16 Dummy Bits + BFA7-BFA0  
CMD  
X
X···X, BFA8  
BFA7-0  
n
n + 1  
Last Byte  
SI (Input)  
Figure 23-3. Buffer to Main Memory Page Program  
Starts Self-timed Erase/Program Operation  
CS  
Binary Page Size  
A17-A8 + 8 Dummy Bits  
CMD  
PA9-7  
PA6-0, X  
XXXX XXX  
SI (Input)  
n
= 1st byte read  
n+1 = 2nd byte read  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
49  
24. Read Operations  
The following block diagram and waveforms illustrate the various read sequences available.  
Figure 24-1. Block Diagram  
Flash Memory Array  
Page (256/264 bytes)  
Main Memory  
Page To  
Buffer  
Buffer (256/264 bytes)  
Buffer  
Read  
Main Memory  
Page Read  
I/O Interface  
SO  
Figure 24-2. Main Memory Page Read  
CS  
Address for Default Page Size  
A16  
A15-A8  
A7-A0  
CMD  
PA8-7  
PA6-0, BA8  
BA7-0  
X
X
SI (Input)  
4 Dummy Bytes  
SO (Output)  
n
n + 1  
AT25PE20  
DS-25PE20–139C–8/2018  
50  
Figure 24-3. Main Memory Page to Buffer Transfer  
Data From the selected Flash Page is read into the Buffer  
Starts Reading Page Data into Buffer  
CS  
Default Page Size  
A17-A8 + 8 Dummy Bits  
...  
X, PA9-7  
X
CMD  
PA6-0, X  
XXXX XXXX  
SI (Input)  
SO (Output)  
Figure 24-4. Buffer Read  
CS  
Address for Default Page Size  
16 Dummy Bits + BFA7-BFA0  
...  
CMD  
X
X
X, BFA8  
BFA7-0  
X
SI (Input)  
No Dummy Byte (opcode D1h)  
1 Dummy Byte (opcode D4h)  
SO (Output)  
n
n + 1  
Each transition represents eight bits  
AT25PE20  
DS-25PE20–139C–8/2018  
51  
25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3  
Figure 25-1. Continuous Array Read (Legacy Opcode E8h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34  
62 63 64 65 66 67 68 69 70 71 72  
SCK  
SI  
Opcode  
Address Bits  
32 Dummy Bits  
1
1
1
0
1
0
0
0
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
MSB  
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-2. Continuous Array Read (Opcode 0Bh)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48  
SCK  
SI  
Opcode  
Address Bits A17 - A0  
Dummy Bits  
X
0
0
0
0
1
0
1
1
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
X
MSB  
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-3. Continuous Array Read (Opcode 01h or 03h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40  
SCK  
SI  
Opcode  
Address Bits A17-A0  
0
0
0
0
0
0
1
1
A
A
A
A
A
A
A
A
A
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
AT25PE20  
DS-25PE20–139C–8/2018  
52  
Figure 25-4. Main Memory Page Read (Opcode D2h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34  
62 63 64 65 66 67 68 69 70 71 72  
SCK  
SI  
Opcode  
Address Bits  
32 Dummy Bits  
1
1
0
1
0
0
1
0
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
MSB  
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-5. Buffer Read (Opcode D4h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48  
SCK  
Address Bits  
Default Page Size = 16 Dummy Bits + BFA7-BFA0  
Optional DataFlash-Lite Page Size =  
15 Dummy Bits + BFA8-BFA0  
Dummy Bits  
Opcode  
1
1
0
1
0
1
0
0
X
X
X
X
X
X
A
A
A
X
X
X
X
X
X
X
X
SI  
MSB  
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-6. Buffer Read – Low Frequency (Opcode D1h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40  
SCK  
Address Bits  
Default Page Size = 16 Dummy Bits + BFA7-BFA0  
Optional DataFlash Page Size =  
15 Dummy Bits + BA8-BFA0  
Opcode  
1
1
0
1
0
0
0
1
X
X
X
X
X
X
A
A
A
SI  
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
AT25PE20  
DS-25PE20–139C–8/2018  
53  
Figure 25-7. Read Sector Protection Register (Opcode 32h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40  
SCK  
SI  
Opcode  
Dummy Bits  
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-8. Read Security Register (Opcode 77h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39 40  
SCK  
SI  
Opcode  
Dummy Bits  
0
1
1
1
0
1
1
1
X
X
X
X
X
X
X
X
X
MSB  
MSB  
Data Byte 1  
High-impedance  
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
Figure 25-9. Status Register Read (Opcode D7h)  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
SCK  
SI  
Opcode  
1
1
0
1
0
1
1
1
MSB  
Status Register Data  
Status Register Data  
High-impedance  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SO  
MSB  
MSB  
MSB  
AT25PE20  
DS-25PE20–139C–8/2018  
54  
Figure 25-10. Manufacturer and Device Read (Opcode 9Fh)  
CS  
0
6
7
8
14 15 16  
22 23 24  
30 31 32  
38 39 40  
47  
SCK  
SI  
Opcode  
9Fh  
High-impedance  
1Fh  
23h  
00h  
01h  
EDI  
00h  
EDI  
SO  
Manufacturer ID  
Device ID  
Byte 1  
Device ID  
Byte 2  
String Length  
Data Byte 1  
Note: Each transition  
shown for SI and SO represents one byte (eight bits)  
Figure 25-11.Reset Timing  
CS  
t
t
CSS  
REC  
SCK  
RESET  
t
RST  
High-impedance  
High-impedance  
SO (Output)  
SI (Input)  
Note: 1. The CS signal should be in the high state before the RESET signal is deasserted.  
AT25PE20  
DS-25PE20–139C–8/2018  
55  
26. Auto Page Rewrite Flowchart  
Figure 26-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially  
START  
Provide Address  
and Data  
Buffer Write  
(84h)  
Main Memory Page Program  
through Buffer  
(82h)  
Buffer To Main  
Memory Page Program  
(83h)  
END  
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the  
array page-by-page.  
2. A page can be written using either a Main Memory Page Program operation or a buffer write operation  
followed by a buffer to Main Memory Page Program operation.  
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially  
for each page within the entire array.  
AT25PE20  
DS-25PE20–139C–8/2018  
56  
Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array Randomly  
START  
Provide Address of  
Page to Modify  
Main Memory Page  
to Buffer Transfer  
(53h)  
If planning to modify multiple  
bytes currently stored within  
a page of the Flash array  
Buffer Write  
(84h)  
Main Memory Page Program  
through Buffer  
(82h)  
Buffer to Main  
Memory Page Program  
(83h)  
(2)  
Auto Page Rewrite  
(58h)  
Increment Page  
(2)  
Address Pointer  
END  
Notes: 1. To preserve data integrity, each page of an DataFlash-L sector must be updated/rewritten at least once  
within every 50,000 cumulative page erase and program operations.  
2. A page address pointer must be maintained to indicate which page is to be rewritten. The auto page rewrite  
command must use the address specified by the page address pointer  
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to  
wait until 50,000 cumulative page erase and program operations have accumulated before rewriting all  
pages of the sector.  
AT25PE20  
DS-25PE20–139C–8/2018  
57  
27. Ordering Information  
27.1 Ordering Detail  
A T 2 5 P E 2 0 - S S H N - B  
Designator  
Shipping Carrier Option  
B
T
Y
= Bulk (tubes)  
= Tape and reel  
= Trays  
Product Family  
25PE = DataFlash-L  
Operating Voltage  
N
= 1.65V minimum (1.65V to 3.6V)  
Device Density  
20 = 2-Mbit  
Device Grade  
H
= Green, NiPdAu lead finish,  
Industrial temperature range  
(–40°C to +85°C)  
Package Option  
SS = 8-lead, 0.150” narrow SOIC  
S
= 8-lead, 0.208” wide SOIC  
M
= 8-pad, 5 x 6 x 0.6mm UDFN  
27.2 Ordering Codes (Default 256 Byte DataFlash-L Page Size)  
Ordering Code  
Package  
Lead Finish  
Operating Voltage  
fSCK  
Device Grade  
AT25PE20-SSHN-B (1)  
AT25PE20-SSHN-T(1)  
AT25PE20-SHN-B(1)  
AT25PE20-SHN-T(1)  
AT25PE20-MHN-Y(1)  
AT25PE20-MHN-T(1)  
8S1  
Industrial  
NiPdAu  
1.65V to 3.6V  
70MHz  
8S2  
(-40°C to 85°C)  
8MA1  
Notes: 1. The shipping carrier suffix is not marked on the device.  
Package Type  
8S1  
8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)  
8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC)  
8S2  
8MA1  
8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)  
AT25PE20  
DS-25PE20–139C–8/2018  
58  
28. Packaging Information  
28.1 8S1 – 8-lead JEDEC SOIC  
C
1
E
E1  
L
N
Ø
TOP VIEW  
END VIEW  
e
b
COMMON DIMENSIONS  
(Unit of Measure = mm)  
A
MIN  
1.35  
0.10  
MAX  
1.75  
0.25  
NOM  
NOTE  
SYMBOL  
A1  
A
A1  
b
0.31  
0.17  
4.80  
3.81  
5.79  
0.51  
0.25  
5.05  
3.99  
6.20  
C
D
E1  
E
e
D
SIDE VIEW  
1.27 BSC  
L
0.40  
0°  
1.27  
8°  
Notes: This drawing is for general information only.  
Refer to JEDEC Drawing MS-012, Variation AA  
for proper dimensions, tolerances, datums, etc.  
Ø
6/22/11  
DRAWING NO. REV.  
TITLE  
GPC  
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing  
Small Outline (JEDEC SOIC)  
SWB  
8S1  
G
Package Drawing Contact:  
contact@adestotech.com  
AT25PE20  
DS-25PE20–139C–8/2018  
59  
28.2 8S2 – 8-lead EIAJ SOIC  
C
1
E
E1  
L
N
q
TOP VIEW  
END VIEW  
e
b
COMMON DIMENSIONS  
(Unit of Measure = mm)  
A
MIN  
1.70  
0.05  
0.35  
0.15  
5.13  
5.18  
7.70  
0.51  
0°  
MAX  
2.16  
0.25  
0.48  
0.35  
5.35  
5.40  
NOM  
NOTE  
SYMBOL  
A1  
A
A1  
b
4
4
C
D
E1  
E
D
2
8.10  
L
0.85  
8°  
SIDE VIEW  
q
e
1.27 BSC  
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.  
2. Mismatch of the upper and lower dies and resin burrs aren't included.  
3. Determines the true geometric position.  
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.  
4/15/08  
REV.  
GPC  
DRAWING NO.  
TITLE  
8S2, 8-lead, 0.208” Body, Plastic Small  
Outline Package (EIAJ)  
Package Drawing Contact:  
contact@adestotech.com  
STN  
8S2  
F
AT25PE20  
DS-25PE20–139C–8/2018  
60  
28.3 8MA1 – 8-pad UDFN  
E
C
Pin 1 ID  
SIDE VIEW  
D
y
TOP VIEW  
A1  
A
K
E2  
Option A  
0.45  
Pin #1  
Chamfer  
(C 0.35)  
8
1
2
3
Pin #1 Notch  
(0.20 R)  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
(Option B)  
MIN  
MAX  
NOM  
NOTE  
SYMBOL  
7
A
0.45  
0.55  
0.60  
e
D2  
A1  
b
0.00  
0.35  
0.02  
0.40  
0.152 REF  
5.00  
4.00  
6.00  
3.40  
1.27  
0.60  
0.05  
0.48  
6
C
D
D2  
E
4.90  
3.80  
5.90  
3.20  
5.10  
4.20  
6.10  
3.60  
5
4
b
BOTTOM VIEW  
L
E2  
e
L
0.50  
0.00  
0.20  
0.75  
0.08  
y
K
4/15/08  
GPC  
YFG  
DRAWING NO.  
TITLE  
REV.  
Package Drawing Contact: 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally  
Enhanced Plastic Ultra Thin Dual Flat No Lead  
Package (UDFN)  
8MA1  
D
contact@adestotech.com  
AT25PE20  
DS-25PE20–139C–8/2018  
61  
29. Revision History  
Doc. Rev.  
Date  
Comments  
DS-25PE20-139A  
DS-25PE20-139B  
07/2017  
03/2018  
Initial document release.  
Change document status from ADVANCED to PRELIMINARY.  
Change document status from PRELIMINARY to production.  
Updated Figure 7-1.  
DS-25PE20-139C  
08/2018  
Updated Figure 16-1.  
AT25PE20  
DS-25PE20–139C–8/2018  
62  
Corporate Office  
California | USA  
Adesto Headquarters  
3600 Peterson Way  
Santa Clara, CA 95054  
Phone: (+1) 408.400.0578  
Email: contact@adestotech.com  
© 2017 Adesto Technologies. All rights reserved. / Rev.: DS-25PE20–139C–8/2018  
Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective  
owners. Adesto products in this datasheet are covered by certain Adesto patents registered in the United States and potentially other countries. Please refer to  
http://www.adestotech.com/patents for details.  
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms  
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications  
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the  
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.  

相关型号:

AT25PE20-MHN-Y

2-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE20-SHN-B

2-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE20-SHN-T

2-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE20-SSHN-B

2-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE20-SSHN-T

2-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-MHN-T

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-MHN-Y

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-SHN-B

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-SHN-T

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-SSHN-B

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG

AT25PE40-SSHN-T

4-Mbit DataFlash-L Page Erase Serial Flash Memory
DIALOG