DI2CS [DCD]

I2C Bus Interface - Slave; I2C总线接口 - 从


型号：	DI2CS
厂家：	DIGITAL CORE DESIGN
描述：	I2C Bus Interface - Slave I2C总线接口 - 从
文件：	总4页 (文件大小：148K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DI2CS

I²C Bus Interface - Slave

ver 3.02

● Fully synthesizable

O V E R V I E W

I²C is a two-wire, bi-directional serial bus that

provides a simple and efficient method of

data transmission over a short distance be-

tween many devices. The DI2CS core pro-

vides an interface between a microprocessor

/microcontroller and an I²C bus. It can works

as a slave transmitter or slave receiver de-

pending on working mode determined by a

master device. The DI2CS core incorporates

all features required by the latest I²C specifi-

cation including clock synchronization, arbi-

tration and High-speed transmission mode.

The DI2CS supports all the transmission

speed modes.

● Static synchronous design with positive

edge clocking and synchronous reset

● No internal tri-states

● Scan test ready

A P P L I C A T I O N S

● Embedded microprocessor boards

● Consumer and professional audio/video

● Home and automotive radio

● Low-power applications

● Communication systems

● Cost-effective reliable automotive sys-

K E Y F E A T U R E S

tems

● Conforms to v.2.1 of the I²C specification

D E L I V E R A B L E S

Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation mac-

ros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

Technical documentation

◊ Installation notes

● Slave operation

♦

○

Slave transmitter

Slave receiver

● Supports 3 transmission speed modes

○

Standard (up to 100 kb/s)

Fast (up to 400 kb/s)

High Speed (up to 3,4 Mb/s)

● Allows operation from a wide range of

♦

input clock frequencies

● Simple interface allows easy connection

◊ HDL core specification

◊ Datasheet

to microprocessor/microcontroller devices

♦

Synthesis scripts

Example application

Technical support

● Interrupt generation

● User-defined data setup time

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

◊ IP Core implementation support

◊ 3 months maintenance

S Y M B O L

●

Delivery the IP Core updates, minor

and major versions changes

Delivery the documentation updates

Phone & email support

datai(7:0)

datao(7:0)

address(1:0)

●

irq

L I C E N S I N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

scli

sdai

sclo

sdao

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implemen-

tation.

rst

clk

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

P I N S D E S C R I P T I O N

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

TYPE

DESCRIPTION

clk

rst

input

Global clock

Global reset

address(1:0)

Processor address lines

Chip select

● Single Design license for

Processor write strobe

Processor read strobe

I²C bus clock line (input)

I²C bus data line (input)

Processor data bus (input)

○

VHDL, Verilog source code called HDL

Source

scli

○

Encrypted, or plain text EDIF called Netlist

sdai

● One Year license for

Encrypted Netlist only

● Unlimited Designs license for

datai(7:0)

datao(7:0)

sclo

○

output Processor data bus (output)

output I²C bus clock line (output)

output I²C bus data line (output)

output Processor interrupt line

sdao

irq

○

HDL Source

Netlist

● Upgrade from

○

HDL Source to Netlist

Single Design to Unlimited Designs

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

I M P L E M E N T A T I O N

Figure below show the typical DI2CS imple-

mentations in system with Standard/Fast and

High-speed devices.

B L O C K D I A G R A M

Figure below shows the DI2CS IP Core block

diagram.

Receive

datai(7:0)

Data

Input

Filter

sdai

datao(7:0)

Shift

V_DD

address(1:0)

Output

CPU

sdao

Interface

Send

Data

R_P

SDA

SCL

Own

address

detection

irq

Control

Logic

R_S

Status

sdai

sda

Synchronization

Logic

Input

Filter

scli

sdao

open drain

Master

device

Clock

Stretching

Output

rst

clk

sclo

DI2CS

scli

scl

CPU Interface – Performs the interface func-

tions between DI2CS internal blocks and mi-

croprocessor. Allows easy connection of the

core to a microprocessor/microcontroller sys-

tem.

sclo

open drain

P E R F O R M A N C E

Control Logic – Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route (all key features

have been included):

Shift Register – Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Speed

grade

-5

Device

Logic Cells

F_max

Control Register – Contains five control bits

used for performing all types of I²C Bus

transmissions.

MERCURY

STRATIX

CYCLONE

APEX II

APEX20KC

APEX20KE

APEX20K

ACEX1K

FLEX10KE

MAX 7000AE

MAX 3000A

170

250 MHz

260 MHz

220 MHz

270 MHz

150 MHz

120 MHz

90 MHz

107 MHz

96 MHz

-5

-6

-7

-1

Status Register – Contains seven status bits

that indicates state of the I²C Bus and the

DI2CS core.

Input Filter – Performs spike filtering.

Synchronization Logic – Performs DI2CS

core synchronization.

-5

104 MHz

Core performance in ALTERA® devices

Clock Stretching – Performs I²C SCL clock

stretching when DI2CS core is not ready for

next transmission.

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

The main features of each Digital Core Design I²C compliant cores have been summarized in table

below. It gives a briefly member characterization helping user to select the most suitable IP Core

for its application.

Design

DI2CM

DI2CS

DI2CSB

3.0

2.1

I²C cores summary table

C O N T A C T S

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

info@dcd.pl

e-mail:

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

http://www.dcd.pl/apartn.php

Please check

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

DI2CS [DCD]

相关型号：

DI2CSB

DI3-72AV1AA0EX

DI3-72AV1AA0XX

DI3-72AV1AB0EX

DI3-72AV1AB0XX

DI3-72AV1AC0EX

DI3-72AV1AC0XX

DI3-72AV1AD0EX

DI3-72AV1AD0XX

DI3-72AV5AA0EX

DI3-72AV5AA0XX

DI3-72AV5AB0EX