PDU17F-4MC5 [DATADELAY]
7-BIT PROGRAMMABLE DELAY LINE (SERIES PDU17F); 7位可编程延迟线(系列PDU17F )型号: | PDU17F-4MC5 |
厂家: | DATA DELAY DEVICES, INC. |
描述: | 7-BIT PROGRAMMABLE DELAY LINE (SERIES PDU17F) |
文件: | 总5页 (文件大小:41K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PDU17F
Ò
7-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU17F)
data
delay
3
devices, inc.
FEATURES
PACKAGES
N/C
OUT/
OUT
EN/
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
N/C
A0
2
·
·
·
·
·
·
·
·
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
3
A1
4
PDU17F-xx
DIP
PDU17F-xxC5
Gull-Wing
PDU17F-xxM
Military DIP
PDU17F-xxMC5
GND
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
GND
N/C
EN/
A2
5
VCC
N/C
A3
6
7
Input & outputs fully TTL interfaced & buffered
8
10 T2L fan-out capability
A4
9
10
11
12
13
14
15
16
17
18
19
20
A5
Fits standard 40-pin DIP socket
Auto-insertable
VCC
N/C
N/C
N/C
N/C
VCC
N/C
A6
Military Gull-Wing
N/C
IN
N/C
GND
N/C
N/C
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Delay Line Input
The PDU17F-series device is a 7-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A6-A0) according to the following formula:
OUT Non-inverted Output
OUT/ Inverted Output
A0-A6 Address Bits
EN/ Output Enable
VCC +5 Volts
TDA = TD0 + TINC * A
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
.5 ± .3
Total Delay
Change (ns)
63.5 ± 3.2
·
·
·
Programmed delay tolerance: 5% or 2ns,
whichever is greater
Inherent delay (TD0): 13ns typical (OUT)
12ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (TAIS): 10ns
Disable to output delay (TDISO): 6ns typ. (OUT)
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: ICCH = 68ma
PDU17F-.5
PDU17F-1
PDU17F-2
PDU17F-3
PDU17F-4
PDU17F-5
PDU17F-6
PDU17F-8
PDU17F-10
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.5
6 ± 1.5
8 ± 2.0
10 ± 2.0
127 ± 6.4
254 ± 12.7
381 ± 19.1
508 ± 25.4
635 ± 31.8
762 ± 38.1
1,016 ± 50.8
1,270 ± 63.5
·
·
·
·
NOTE: Any dash number between .5 and 10 not
shown is also available.
ICCL = 86ma
·
Minimum pulse width: 8% of total delay
Ó1997 Data Delay Devices
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU17F
APPLICATION NOTES
possibility of spurious signals persists until the
required TDISH has elapsed.
ADDRESS UPDATE
The PDU17F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISH = Ai * TINC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
A6-A0
EN/
A i-1
Ai
TAENS
TOAX
TAIS
TENIS
PWIN
TDISH
IN
TDA
PWOUT
TDISO
OUT
OUT/
TSKEW
Figure 1: Timing Diagram
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
PDU17F
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
SYMBOL
TDT
MIN
TYP
127
13.0
1.5
UNITS
TINC
ns
TD0
Output Skew
TSKEW
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
ns
ns
ns
ns
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
6.0
2.0
10.0
8.0
ns
See Text
See Text
16
Absolute
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
Input Period
Suggested
Recommended
Absolute
32
200
8
16
Input Pulse Width
Suggested
Recommended
100
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
UNITS NOTES
V
V
C
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
VOH
2.5
3.4
V
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage
VOL
0.35
0.5
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
-1.0
20.0
mA
mA
V
V
V
2.0
-60
0.8
-1.2
0.1
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
mA
IIH
IIL
IOS
20
-0.6
-150
25
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
mA
mA
mA
Unit
Load
Output Low Fan-out
12.5
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU17F
PACKAGE DIMENSIONS
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
.650
MAX.
.580
MAX.
.010
±.002
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
2.100 MAX.
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
.280
MAX.
.015 TYP.
.070 MAX.
.018 TYP.
.100 TYP.
DIP (PDU17F-xx, PDU17F-xxM)
.020 TYP.
.040 TYP.
.010±.002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
.882
±.005
.710 .590
MAX.
±.005
.007
±.005
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
.090
.100
.280
MAX.
.050
±.010
1.100
2.080±.020
Gull-Wing (PDU17F-xxC5, PDU17F-xxMC5)
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
PDU17F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Load:
Cload
1 FAST-TTL Gate
5pf ± 10%
:
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.5 x Total Delay
PERIN = 4.5 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
OUT
IN
TIME INTERVAL
COUNTER
DEVICE UNDER
TEST (DUT)
TRIG
TRIG
Test Setup
PERIN
PWIN
VIH
TRISE
TFALL
INPUT
SIGNAL
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
TDAR
TDAF
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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