DDU4C-5125A2 [DATADELAY]

5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C); 5抽头, HCMOS ,接口固定的延时线(系列DDU4C )
DDU4C-5125A2
型号: DDU4C-5125A2
厂家: DATA DELAY DEVICES, INC.    DATA DELAY DEVICES, INC.
描述:

5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
5抽头, HCMOS ,接口固定的延时线(系列DDU4C )

延迟线 逻辑集成电路 光电二极管
文件: 总4页 (文件大小:53K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DDU4C  
Ò
5-TAP, HCMOS-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU4C)  
data  
3
delay  
inc.  
devices,  
PACKAGES  
FEATURES  
1
2
3
4
5
6
7
14  
VDD  
N/C  
T1  
N/C  
T3  
N/C  
T5  
IN  
N/C  
N/C  
T2  
N/C  
T4  
IN  
VCC  
1
4
14  
12  
10  
8
·
·
·
·
·
·
Five equally spaced outputs  
Fits standard 8-pin DIP socket  
Low profile  
13  
12  
11  
10  
9
T1  
T2  
Auto-insertable  
T3  
8
GND  
T4  
6
7
Input & outputs fully CMOS interfaced & buffered  
10 T2L fan-out capability  
GND  
T5  
SMD  
DIP  
DDU4C-xxA2 Comm.  
DDU4C-xxB2 Comm.  
DDU4C-xxMC2 Military  
DDU4C-xx Comm.  
DDU4C-xxM Military  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU4C-series device is a 5-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an  
amount determined by the device dash number (See Table). The total  
delay of the line is measured from IN to T5. The nominal tap-to-tap delay  
increment is given by one-fifth of the total delay.  
IN  
T1-T5 Tap Outputs  
VDD +5 Volts  
Signal Input  
GND Ground  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
·
·
·
·
Minimum input pulse width: 20% of total delay  
Output rise time: 8ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 40ma typical  
ICCH = 10ma typical  
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
Part  
Number  
Total  
Delay (ns)  
50 ± 2.5  
60 ± 3.0  
Delay Per  
Tap (ns)  
DDU4C-5050  
DDU4C-5060  
DDU4C-5075  
DDU4C-5100  
DDU4C-5125  
DDU4C-5150  
DDU4C-5200  
DDU4C-5250  
DDU4C-5300  
DDU4C-5400  
DDU4C-5500  
10.0 ± 3.0  
12.0 ± 3.0  
15.0 ± 3.0  
20.0 ± 3.0  
25.0 ± 3.0  
30.0 ± 3.0  
40.0 ± 4.0  
50.0 ± 5.0  
60.0 ± 6.0  
80.0 ± 8.0  
100.0 ± 10.0  
75 ± 4.0  
100 ± 5.0  
125 ± 6.5  
150 ± 7.5  
200 ± 10.0  
250 ± 12.5  
300 ± 15.0  
400 ± 20.0  
500 ± 25.0  
·
·
NOTE: Any dash number between 5050 and 5500  
not shown is also available.  
20%  
20%  
20%  
20%  
20%  
VDD IN  
T1  
T2  
T3  
T4  
T5 GND  
DDU4C Functional diagram  
Ó1997 Data Delay Devices  
Doc #97034  
12/10/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
DDU4C  
APPLICATION NOTES  
Delay Devices if your application requires device  
testing at a specific input condition.  
HIGH FREQUENCY RESPONSE  
The DDU4C tolerances are guaranteed for input  
pulse widths and periods greater than those  
specified in the test conditions. Although the  
device will function properly for pulse widths as  
small as 20% of the total delay and periods as  
small as 40% of the total delay (for a symmetric  
input), the delays may deviate from their values at  
low frequency. However, for a given input  
POWER SUPPLY BYPASSING  
The DDU4C relies on a stable power supply to  
produce repeatable delays within the stated  
tolerances. A 0.1uf capacitor from VDD to GND,  
located as close as possible to the VDD pin, is  
recommended. A wide VDD trace and a clean  
ground plane should be used.  
condition, the deviation will be repeatable from  
pulse to pulse. Contact technical support at Data  
DEVICE SPECIFICATIONS  
TABLE 1: ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
DC Supply Voltage  
Input Pin Voltage  
Storage Temperature  
Lead Temperature  
SYMBOL  
VDD  
VIN  
TSTRG  
TLEAD  
MIN  
-0.3  
-0.3  
-55  
MAX  
7.0  
VDD+0.3  
150  
UNITS NOTES  
V
V
C
300  
C
10 sec  
TABLE 2: DC ELECTRICAL CHARACTERISTICS  
(0C to 70C, 4.75V to 5.25V)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
High Level Output Voltage  
VOH  
3.98  
4.4  
V
VDD = 5.0, IOH = MAX  
VIH = MIN, VIL = MAX  
VDD = 5.0, IOL = MAX  
VIH = MIN, VIL = MAX  
Low Level Output Voltage  
VOL  
0.15  
0.26  
V
High Level Output Current  
Low Level Output Current  
High Level Input Voltage  
Low Level Input Voltage  
Input Current  
IOH  
IOL  
VIH  
VIL  
IIH  
-4.0  
4.0  
mA  
mA  
V
V
mA  
3.15  
1.35  
0.10  
VDD = 5.0  
Doc #97034  
12/10/97  
DATA DELAY DEVICES, INC.  
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
2
DDU4C  
PACKAGE DIMENSIONS  
14  
12  
10  
8
7
Lead Material:  
Nickel-Iron alloy 42  
TIN PLATE  
14  
12  
10  
8
7
.410  
TYP.  
1
4
6
1
4
6
.280  
MAX.  
.780 MAX.  
.820 MAX.  
.290  
MAX.  
.320  
MAX.  
.020  
TYP.  
.015 TYP.  
.070 MAX.  
.130  
.010 .002  
±
.030  
±
.020 TYP.  
.018  
.100  
TYP.  
.018 TYP.  
.600 TYP.  
TYP.  
.300  
TYP.  
.350  
MAX.  
.600 .010  
±
DDU4C-xxM (Military DIP)  
DDU4C-xx (Commercial DIP)  
.020 TYP.  
14 13 12 11 10  
.040  
TYP.  
.010 TYP.  
.040  
TYP.  
.020 TYP.  
.050 TYP.  
9
6
8
7
14 13 12 11 10  
9
6
8
7
.320  
TYP.  
.270  
TYP.  
.430  
TYP.  
.270  
TYP.  
1
2
3
4
5
1
2
3
4
5
.090  
.100  
.300  
MAX.  
.050  
TYP.  
.110  
.100  
.350  
MAX.  
.110  
TYP.  
.600  
.600  
.790 MAX.  
.790 MAX.  
DDU4C-xxA2 (Commercial Gull-Wing)  
DDU4C-xxB2 (Commercial J-Lead)  
.020 TYP.  
.040  
.010 .002  
±
TYP.  
14 13 12 11 10  
9
8
.882  
.005  
.710 .590  
MAX.  
±
.005  
±
.007  
.005  
±
1
2
3
4
5
6
7
.090  
.100  
.320  
MAX.  
.050  
.010  
.600  
±
.780 .020  
±
DDU4C-xxMC2 (Military SMD)  
Doc #97034  
12/10/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
3
DDU4C  
DELAY LINE AUTOMATED TESTING  
TEST CONDITIONS  
INPUT:  
OUTPUT:  
Ambient Temperature: 25oC ± 3oC  
Supply Voltage (VDD): 5.0V ± 0.1V  
Load:  
Cload  
1 FAST-TTL Gate  
5pf ± 10%  
:
Input Pulse:  
High = 5.0V ± 0.1V  
Threshold: 2.5V (Rising & Falling)  
Low = 0.0V ± 0.1V  
Source Impedance:  
Rise/Fall Time:  
50W Max.  
5.0 ns Max. (measured  
between 0.5V and 4.5V )  
PWIN = 1.5 x Total Delay  
PERIN = 10 x Total Delay  
Pulse Width:  
Period:  
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.  
PRINTER  
COMPUTER  
SYSTEM  
REF  
PULSE  
GENERATOR  
OUT  
IN  
T1  
T2  
T3  
T4  
T5  
IN  
TIME INTERVAL  
COUNTER  
DEVICE UNDER  
TEST (DUT)  
TRIG  
TRIG  
Test Setup  
PERIN  
PWIN  
VIH  
TRISE  
TFALL  
INPUT  
SIGNAL  
4.5V  
2.5V  
0.5V  
4.5V  
2.5V  
0.5V  
VIL  
TRISE  
TFALL  
OUTPUT  
SIGNAL  
VOH  
2.5V  
2.5V  
VOL  
Timing Diagram For Testing  
Doc #97034  
12/10/97  
DATA DELAY DEVICES, INC.  
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
4

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