3D7503G [DATADELAY]
MONOLITHIC MANCHESTER ENCODER/DECODER; 单片曼彻斯特编码/解码器
| 型号： | 3D7503G |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC MANCHESTER ENCODER/DECODER |
| 文件： | 总5页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7503
Ò
MONOLITHIC MANCHESTER
ENCODER/DECODER
(SERIES 3D7503)
data
3
delay
devices, inc.
PACKAGES
FEATURES
CIN
CEN
RX
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
·
·
·
·
·
·
·
·
·
·
All-silicon, low-power CMOS technology
Encoder and decoder function independently
Encoder has buffered clock output
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range: ±15%
CBUF
LOOP
TXENB
DOUTB
TXB
COUT
DIN
RESB
GND
8
TX
3D7503-xxx
3D7503G-xxx Gull Wing (.300)
3D7503D-xxx SOIC (.150)
DIP (.300)
Lock-in time: 1 bit
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
Encoder:
The 3D7503 is a monolithic CMOS Manchester Encoder/Decoder combo
chip. The device uses bi-phase-level encoding to embed a clock signal
into a data stream for transmission across a communications link. In this
encoding mode, a logic one is represented by a high-to-low transition in
the center of the bit cell, while a logic zero is represented by a low-to-high
transition.
CIN
DIN
Clock Input
Data Input
RESB Reset
CEN
Clock buffer enable
TXENB Transmit enable
CBUF Buffered clock
TX,TXB Transmitted signal
The Manchester encoder combines the clock (CIN) and data (DIN) into a
single bi-phase-level signal (TX). An inverted version of this signal (TXB)
is also available. The data baud rate (in MBaud) is equal to the input
clock frequency (in MHz). A replica of the clock input is also available
(CBUF).
Decoder:
RX
Received Signal
COUT Recovered Clock
DOUTB Recovered Data
The encoder may be reset by setting the RESB input low; otherwise, it
should be left high. The TX and TXB signals may be disabled (high-Z) by
setting TXENB high. Similarly, CBUF may be disabled by setting CEN
low. Under most operating conditions, the encoder is never reset, TX and
TXB are always enabled, and CBUF is not used. With this in mind, the
3D7503 provides an internal pull-up resistor on RESB and internal pull-
Common:
LOOP Loop enable
VDD
GND
+5 Volts
Ground
down resistors on CEN and TXENB, so that most users can leave these inputs uncommitted.
The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and
data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The
operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may
vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the
information received.
Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the
received signal. Rather, the device requires at most one bit cell before the data presented at the output is
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise
turned off.
Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the
encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is
useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if
this feature is not needed.
Ó1998 Data Delay Devices
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7503
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7503-5
3D7503-10
3D7503-20
3D7503-25
3D7503-30
3D7503-40
3D7503-50
DECODER BAUD RATE (MBaud)
Nominal Minimum Maximum
5.00
4.25
5.75
11.50
23.00
28.75
34.50
46.00
57.50
10.00
20.00
25.00
30.00
40.00
50.00
8.50
17.00
21.25
25.50
34.00
42.50
NOTE: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost.
APPLICATION NOTES
ENCODER
The encoder presents at its outputs the true and
the complimented encoded data. The High-to-
Low time skew of the selected data output should
be budgeted by the user, as it relates to his
application, to satisfactorily estimate the
distortion of the transmitted data stream. Such
an estimate is very useful in determining the
functionality and margins of the data link, if a
Manchester decoder is used to decode the
received data.
The Manchester encoder subsystem samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the by-
phase level Manchester code.
The encoder employs the timing of the clock
rising and falling edges (duty cycle) to implement
the required coding scheme, as shown in Figure
1. To reduce the difference between the output
data high time and low time, it is essential that
the deviation of the input clock duty cycle from
50/50 be minimized.
RESET
(RESB)
(Left high for normal operation)
1/fC
1
0
1
1
0
0
1
0
CLOCK
(CIN)
tDS
tDH
DATA
(DIN)
T2H
T2L
TRANSMIT
(TXB)
T1H
T1L
TRANSMIT
(TX)
1
0
1
1
0
0
1
0
Figure 1: Timing Diagram (Encoder)
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7503
APPLICATION NOTES (CONT’D)
DECODER
to one over twice the baud rate. Otherwise,
the input is presented at the clock output
unchanged, shifted in time. Therefore, the clock
duty cycle is strongly dependent on the baud
rate, as this will affect the clock-high duration.
The Manchester decoder subsystem samples the
input at precise pre-selected intervals to retrieve
the data and to recover the clock from the
received data stream. Its architecture comprises
finely tuned delay elements and proprietary
circuitry which, in conjunction with other circuits,
implement the data decoding and clock recovery
function.
The clock output falling edge is not operated on
by the clock recovery circuitry. It, therefore,
preserves more accurately the clock frequency
information embedded in the transmitted data. It
can therefore be used, if desired, to retrieve
clock frequency information.
Typically, the encoded data transmitted from a
source arrives at the decoder corrupted. Such
corruption of the received data manifests itself
as jitter and/or pulse width distortion at the
decoder input. The instantaneous deviations
from nominal Baud Rate and/or Pulse Width
(high or low) adversely impact the data
extraction and clock recovery function if their
published limits are exceeded. See Table 4,
Allowed Baud Rate/Duty Cycle. The decoder,
being a self-timed device, is tolerant of
frequency modulation (jitter) present in the input
data stream, provided that the input data pulse
width variations remain within the allowable
ranges.
INPUT SIGNAL CHARACTERISTICS
The 3D7503 inputs are TTL compatible. The
user should assure him/herself that the 1.5
volt TTL threshold is used when referring to all
timing, especially to the input clock duty cycle
(encoder) and the received data (decoder).
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7503 Manchester encoder/decoder
utilizes novel and innovative compensation
circuitry to minimize timing variations induced by
fluctuations in power supply and/or temperature.
Nevertheless, optimum performance is achieved
by providing a stable power supply and a clean
ground plane, and by placing a bypass capacitor
(0.1uf typically) as close to the device as
possible.
The decoder presents at its outputs the decoded
data (inverted) and the recovered clock. The
decoded data is valid at the rising edge of the
clock.
The clock recovery function operates in two
modes dictated by the input data stream bit
sequence. When a data bit is succeeded by its
inverse, the clock recovery circuit is engaged
and forces the clock output low for a time equal
ENCODED
0
1
0
1
1
0
0
1
RECEIVED
(RX)
tC
tCL
tCWL
tCD
CLOCK
(CLK)
DATA
(DATB)
DECODED
1
0
1
1
0
0
1
Figure 2: Timing Diagram (Decoder)
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7503
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-10
MAX
7.0
VDD+0.3
10
150
300
UNITS NOTES
V
V
mA
C
25C
-55
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
40
UNITS
mA
V
V
mA
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
IIL
IOH
2.0
0.8
1.0
1.0
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
mA
mA
-4.0
4.0
Low Level Output Current
IOL
mA
ns
Output Rise & Fall Time
TR & TF
2
*IDD(Dynamic) = 2 * CLD * VDD * F
where: CLD = Average capacitance load/pin (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V, except as noted)
SYMBOL
fBN
PARAMETER
Input Baud Rate (Encoder)
Clock Frequency
MIN
TYP
MAX
50
50
UNITS
MBaud
MHz
ns
NOTES
fC
tDS
tDH
t1H - t1L
t2H - t2L
t1H - t2L
fBN
Data set-up to clock rising
Data hold from clock rising
TX High-Low time skew
TXB High-Low time skew
TX - TXB High/Low time skew
Nominal Input Baud Rate (Decoder)
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
3.5
0
-3.5
-2.0
-3.0
ns
ns
ns
ns
3.5
2.0
3.0
50
1
1
1
5
MBaud
fB
fB
-0.15 fBN
-0.05 fBN
0.15 fBN MBaud
0.05 fBN MBaud
25C, 5.00V
-40C to 85C
4.75V to 5.25V
-55C to 125C
4.75V to 5.25V
Allowed Input Baud Rate Deviation
fB
-0.03 fBN
42.5
0.03 fBN MBaud
Allowed Input Duty Cycle
Bit Cell Time
Input Data Edge to Clock Falling Edge
Clock Width Low
50.0
1000/fB
0.75 tc
500/fBN
4.0
57.5
%
ns
ns
ns
ns
tc
tCL
tCWL
tCD
±2ns or 5%
Clock Falling Edge to Data Transition
3.0
5.0
Notes: 1: Assumes a 50% duty cycle clock input
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
3D7503
AUTOMATED TESTING - MONOLITHIC PRODUCTS
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KW ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1/(2*BAUD)
PERIN = 1/BAUD
Source Impedance:
Rise/Fall Time:
Device
Under
Test
Digital
Scope
10KW
Pulse Width:
Period:
5pf
470W
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
WAVEFORM
GENERATOR
OUT
IN DEVICE UNDER OUT
TEST (DUT)
IN
DIGITAL SCOPE
TRIG
TRIG
Figure 3: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
SIGNAL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 4: Timing Diagram
Doc #98009
12/11/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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