3D7424-1 [DATADELAY]
MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE; 单芯片4通道4位可编程延迟线
| 型号： | 3D7424-1 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE |
| 文件： | 总6页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7424
MONOLITHIC QUAD 4-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7424)
FEATURES
PACKAGES
•
•
•
•
•
•
•
•
•
•
•
Four indep’t programmable lines on a single chip
I1
SC
I2
I3
I4
1
2
3
4
5
6
7
14
VDD
All-silicon CMOS technology
13
12
11
10
9
AL
Low quiescent current (5mA typical)
O1
SO
O2
O3
O4
Leading- and trailing-edge accuracy
I1
SC
I2
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
AL
Vapor phase, IR and wave solderable
O1
SO
O2
O3
O4
I3
Increment range: 0.75ns through 400ns
Delay tolerance: 3% or 2ns (see Table 1)
Line-to-line matching: 1% or 1ns typical
Temperature stability: ±1.5% typical (-40C to 85C)
Vdd stability: ±0.5% typical (4.75V to 5.25V)
Minimum input pulse width: 10% of total delay
SI
GND
I4
SI
8
GND
8
SOIC-14
DIP-14
3D7424D-xx
3D7424-xx
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7424 device is a small, versatile, quad 4-bit programmable
monolithic delay line. Delay values, programmed via the serial interface,
can be independently varied over 15 equal steps. The step size (in ns) is
determined by the device dash number. Each input is reproduced at the
corresponding output without inversion, shifted in time as per user
selection. For each line, the delay time is given by:
I1-I4
Signal Inputs
O1-O4 Signal Outputs
AL
SC
SI
Address Latch In
Serial Clock In
Serial Data In
SO
Serial Data Out
VDD 5.0V
TDn = T0 + An * TI
GND Ground
where T0 is the inherent delay, An is the delay address of the n-th line
and TI is the delay increment (dash number). The desired addresses are
shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The
serial interface can also be used to enable/disable each delay line. The 3D7424 operates at 5 volts and
has a typical T0 of 6ns. The 3D7424 is TTL/CMOS-compatible, capable of sourcing or sinking 4mA loads,
and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-
insertable DIP and a space saving surface mount 14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DELAYS & TOLERANCES (NS)
INPUT RESTRICTIONS
Part
Delay
Step
Inherent
Total
Relative
Max Frequency
Min Pulse Width
Number
Delay
Delay
Tolerance
Recom’d Absolute Recom’d
Absolute
3D7424-.75
3D7424-1
3D7424-1.5
3D7424-2
3D7424-4
3D7424-5
3D7424-10
3D7424-15
3D7424-20
3D7424-40
3D7424-50
3D7424-100
3D7424-200
3D7424-400
3% or 0.50ns
3% or 0.50ns
3% or 0.50ns
3% or 0.75ns
3% or 0.75ns
3% or 0.75ns
3% or 1.25ns
3% or 1.88ns
3% or 2.50ns
3% or 5.00ns
3% or 6.25ns
3% or 12.5ns
3% or 25.0ns
3% or 50.0ns
19 MHz
16 MHz
12 MHz
9.2 MHz
5.0 MHz
4.1 MHz
2.1 MHz
1.4 MHz
1.0 MHz
550 KHz
440 KHz
220 KHz
110 KHz
55 KHz
166 MHz
166 MHz
111 MHz
83 MHz
83 MHz
66 MHz
33 MHz
22 MHz
16 MHz
8.3 MHz
6.6 MHz
3.3 MHz
1.6 MHz
833 KHz
26 ns
32 ns
3.0 ns
.75 ± 0.19 6.0 ± 2.0 17.25 ± 2.0
3.0 ns
1.0 ± 0.25 6.0 ± 2.0
1.5 ± 0.38 6.0 ± 2.0
2.0 ± 0.50 6.0 ± 2.0
4.0 ± 1.00 6.0 ± 2.0
5.0 ± 1.25 6.0 ± 2.0
10 ± 2.50 6.0 ± 2.0
15 ± 3.75 6.0 ± 2.0
20 ± 5.00 6.0 ± 2.0
40 ± 10.0 6.0 ± 2.0
50 ± 10.0 6.0 ± 2.0
100 ± 12.5 6.0 ± 2.0
21.0 ± 2.0
28.5 ± 2.0
36.0 ± 2.0
66.0 ± 2.0
81.0 ± 2.5
156 ± 5.0
231 ± 7.5
306 ± 10
606 ± 20
756 ± 25
1506 ± 50
43 ns
4.5 ns
54 ns
99 ns
6.0 ns
6.0 ns
122 ns
234 ns
347 ns
459 ns
909 ns
1.2 us
2.3 us
4.5 us
9.0 us
7.5 ns
15.0 ns
22.5 ns
30.0 ns
60.0 ns
75.0 ns
150 ns
300 ns
600 ns
200 ± 20.0 6.0 ± 2.0 3006 ± 100
400 ± 40.0 6.0 ± 2.0 6006 ± 200
NOTE: Any increment between 0.75ns and 400ns not shown is also available as standard
See page 4 for details regarding input restrictions
2006 Data Delay Devices
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7424
APPLICATION NOTES
THEORY OF OPERATION
PROGRAMMED DELAY INTERFACE
The quad 4-bit programmable 3D7424 device
architecture is comprised of four independently
operating delay lines. Each delay line produces
at its output a replica of the signal present at its
input, shifted in time. A single delay line is
Figure 1 illustrates the main functional blocks of
the 3D7424 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in Table 2,
and the associated timing diagram is shown in
Figure 2. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
comprised of a number of delay cells connected
in series. Delay selection is achieved by routing
one output in each string of cells to its respective
output pin (O1-O4). The delay of each of the four
lines can be controlled independently, via the
serial interface, as described in the next section.
The change in delay from one address setting to
the next is called the increment, or LSB. It is
nominally equal to the device dash number. The
minimum delay, achieved by setting the address
of a line to zero, is called the inherent delay.
impedance state, while setting it high returns the
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
TABLE 2: BIT SEQUENCE
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
Bit
Delay
Function
Line
1
4
3
2
1
1
Output Enable
Output Enable
Output Enable
Output Enable
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
2
3
4
5
6
7
DELAY
I4
I3
I2
I1
AL
O4
O3
O2
O1
LINE
8
9
2
3
4
DELAY
LINE
10
11
12
13
14
15
16
17
18
19
20
DELAY
LINE
DELAY
LINE
ADDR4
ADDR3
ADDR2
ADDR1
ENABLES
20-BIT LATCH
20-BIT SHIFT REGISTER
SI
SO
SC
Figure 1: Functional block diagram
tLW
LATCH
(AL)
tCW tCW
tCSL
CLOCK
(SC)
tDSC
tDHC
SERIAL
INPUT
NEW
BIT 1
NEW
NEW
BIT 2
BIT 20
tPCQ
SERIAL
OUTPUT
(SO)
OLD
BIT 1
OLD
OLD
NEW
BIT 1
BIT 2
BIT 20
tLDV
tLDX
DELAY
TIMES
NEW
PREVIOUS VALUES
VALUES
Figure 2: Serial interface timing diagram
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7424
APPLICATION NOTES (CONT’D)
DELAY ACCURACY
DELAY STABILITY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the delay step at a given address
from its nominal value. For all dash numbers, the
DNL is within 1/4 LSB at every address (see
Table 1: Delay Step).
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D7424 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
With regard to stability, the delay of the 3D7424
at a given address, i, can be split into two
components: the inherent delay (T0) and the
relative delay (Ti – T0). These components exhibit
very different stability coefficients, both of which
must be considered in very critical applications.
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The thermal coefficient of the relative delay is
limited to ±250 PPM/C, which is equivalent to a
variation, over the -40C to 85C operating range,
of ±1.5% from the room-temperature delay
settings. This holds for dash numbers greater
than 1. For smaller dash numbers, the thermal
drift will be larger and will always be positive. The
thermal coefficient of the inherent delay is
nominally +15ps/C for all dash numbers.
The relative error is defined as follows:
erel = (Ti – T0) – i * Tinc
where i is the address, Ti is the measured delay
at the i’th address, T0 is the measured inherent
delay, and Tinc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For
most dash numbers, the relative error is less than
1/8 LSB at every address (see Table 1: Relative
Tolerance).
The power supply sensitivity of the relative delay
is ±0.5% over the 4.75V to 5.25V operating
range, with respect to the delay settings at the
nominal 5.0V power supply. This holds for all
dash numbers greater than 1. For smaller dash
numbers, the voltage sensitivity will be greater
and will always be negative. The sensitivity of the
inherent delay is nominally -1ps/mV for all dash
numbers.
The absolute error is defined as follows:
eabs = Ti – (Tinh + i * Tinc)
where Tinh is the nominal inherent delay. The
absolute error tolerance is given for addresses 0
and 15 (see Table 1: Inherent Delay, Total Delay,
respectively). At any intermediate address, the
tolerance can be found via linear interpolation of
the address 0 & address 15 tolerances.
The matching error is a measure of how well the
delay of the four lines track each other when they
are all programmed to the same address. The
lines are typically matched to within 1% or 1ns,
whichever is greater, for all addresses and all
dash numbers.
3D7424
3D7424
3D7424
SI
SO
SI
SC AL
SO
SI
SC AL
SO
SC AL
FROM
TO
WRITING
DEVICE
NEXT
DEVICE
Figure 3: Cascading Multiple Devices
DATA DELAY DEVICES, INC.
Doc #06019
6/5/2006
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7424
APPLICATION NOTES (CONT’D)
The minimum operating pulse width (high or low)
specification determines the smallest pulse width
of the delay line input signal for which the output
delay accuracy tabulated in Table 1 is
guaranteed.
INPUT SIGNAL CONSIDERATIONS
The frequency and/or pulse width (high or low) of
operation may adversely impact the specified
delay and increment accuracy of the particular
device. The reasons for the dependency of the
output delay accuracy on the input signal
characteristics are varied and complex.
Operation below the recommended minimum
pulse width will cause the delays to shift slighty
with respect to their values at long-pulse-width
operation. The magnitudes of these deviations
will increase as the absolute minimum pulse
width is approached. However, if the input pulse
width and frequency remain constant, the device
will exhibit the same delays from one period to
the next (ie, no appreciable jitter).
Therefore, a recommended and an absolute
maximum operating input frequency and a
recommended and an absolute minimum
operating pulse width have been specified.
OPERATING FREQUENCY
The absolute maximum operating frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
PROGRAMMED DELAY UPDATE
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output. Each 4-bit delay line in the 3D7424 is
represented by 15 serially connected delay
elements (individually addressed by the
The recommended maximum operating
frequency specification determines the highest
frequency of the delay line input signal for which
the output delay accuracy is guaranteed.
Operation above the recommended maximum
frequency will cause the delays to shift slighty
with respect to their values at low-frequency
operation. The magnitudes of these deviations
will increase as the absolute maximum frequency
is approached. However, if the input frequency
and pulse width remain constant, the device will
exhibit the same delays from one period to the
next (ie, no appreciable jitter).
programming data), each capable of storing data
for a time equal to the device increment (step
time). The delay line memory property, in
conjunction with the operational requirement of
“instantaneously” connecting the delay element
addressed by the programming data to the
output, may inject spurious information onto the
output data stream. In order to ensure that
spurious outputs do not occur, it is essential that
the input signal be idle (held high or low) for a
short duration prior to updating the programmed
delay. This duration is given by the maximum
programmable delay. Satisfying this requirement
allows the delay line to “clear” itself of spurious
edges. Once the new address is loaded, the
input signal can begin to switch.
OPERATING PULSE WIDTH
The absolute minimum operating pulse width
(high or low) specification, tabulated in Table 1,
determines the smallest pulse width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion.
Doc #06019
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
6/5/2006
3D7424
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-10
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
10
IIN
TSTRG
TLEAD
mA
C
25C
-55
150
300
C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
mA
V
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
5.0
7.0
VDD = 5.25V
2.0
0.8
0.1
0.1
-6.0
V
-0.1
-0.1
0.0
0.0
-8.0
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
µA
IIL
IOH
µA
mA
Low Level Output Current
IOL
6.0
7.5
2
mA
ns
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = 4 * CLD * VDD * F
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
NOTES
Latch Width
TLW
tDSC
10
10
1
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup to Clock
Data Hold from Clock
Clock Width (High or Low)
Clock Setup to Latch
Clock to Serial Output
Latch to Delay Valid
Latch to Delay Invalid
Input Pulse Width
Input Period
tDHC
tCW
15
20
tCSL
tPCQ
12
35
20
45
tLDV
1
1
tLDX
5
10
20
tWI
% of Total Delay See Table 1
% of Total Delay See Table 1
Period
tPLH, tPHL
Input to Output Delay
ns
See Text
NOTES: 1 - Refer to PROGRAMMED DELAY UPDATE section
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7424
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (VDD): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.3V ± 0.1V
Threshold: 1.65V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.7V )
PWIN = 1.25 x Total Delay
PERIN = 2.5 x Total Delay
Device
Digital
Scope
10KΩ
Under
Test
Pulse Width:
Period:
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
PULSE
OUT
IN
DIGITAL SCOPE/
DEVICE UNDER
TEST (DUT)
GENERATOR
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 4: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.7V
1.65V
0.6V
2.7V
1.65V
SIGNAL
VIL
0.6V
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.65V
1.65V
VOL
Figure 5: Timing Diagram
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
6
相关型号：
©2020 ICPDF网 联系我们和版权申明