3D7303K-100 [DATADELAY]

MONOLITHIC TRIPLE FIXED DELAY LINE; 单片三固定延迟线


型号：	3D7303K-100
厂家：	DATA DELAY DEVICES, INC.
描述：	MONOLITHIC TRIPLE FIXED DELAY LINE 单片三固定延迟线延迟线逻辑集成电路光电二极管
文件：	总4页 (文件大小：35K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

3D7303

MONOLITHIC TRIPLE

FIXED DELAY LINE

(SERIES 3D7303)

data

delay

devices, inc.

FEATURES

PACKAGES

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

VDD

N/C

VDD

N/C

GND

N/C

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range: 10 through 500ns

Delay tolerance: 2% or 1.0ns

Temperature stability: ±3% typical (0C-70C)

Vdd stability: ±1% typical (4.75V-5.25V)

Minimum input pulse width: 20% of total

delay

3D7303M DIP

3D7303H Gull-Wing

(300 Mil)

N/C

GND

N/C

3D7303 DIP

VDD

3D7303G Gull-Wing

3D7303K Unused pins

removed

GND

3D7303Z SOIC

(150 Mil)

(300 Mil)

14-pin DIP available as drop-in replacement for

hybrid delay lines

PIN DESCRIPTIONS

FUNCTIONAL DESCRIPTION

Delay Line 1 Input

Delay Line 2 Input

Delay Line 3 Input

Delay Line 1 Output

Delay Line 2 Output

Delay Line 3 Output

The 3D7303 Triple Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains three matched,

independent delay lines. Delay values can range from 10ns through

500ns. The input is reproduced at the output without inversion,

shifted in time as per the user-specified dash number. The 3D7303

is TTL- and CMOS-compatible, capable of driving ten 74LS-type

loads, and features both rising- and falling-edge accuracy.

VCC +5 Volts

GND Ground

N/C

No Connection

The all-CMOS 3D7303 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

DELAY

PER LINE

(ns)

INPUT RESTRICTIONS

Absolute Max Min Operating

DIP-8

3D7303M

3D7303H

-10

SOIC-8

DIP-14

3D7303K

Max Operating

Frequency

Absolute Min

Oper. P.W.

3D7303Z

3D7303

3D7303G

-10

Oper. Freq.

Pulse Width

-10

-15

-10

-15

-20

-25

-30

33.3 MHz

22.2 MHz

16.7 MHz

13.3 MHz

11.1 MHz

8.33 MHz

6.67 MHz

3.33 MHz

1.67 MHz

1.11 MHz

0.83 MHz

0.67 MHz

100.0 MHz

83.3 MHz

71.4 MHz

62.5 MHz

50.0 MHz

25.0 MHz

12.5 MHz

8.33 MHz

6.25 MHz

5.00 MHz

15.0 ns

22.5 ns

30.0 ns

37.5 ns

45.0 ns

60.0 ns

75.0 ns

150.0 ns

300.0 ns

450.0 ns

600.0 ns

750.0 ns

5.0 ns

10 ± 1.0

15 ± 1.0

20 ± 1.0

25 ± 1.0

30 ± 1.0

-15

-20

5.0 ns

-25

6.0 ns

-30

7.0 ns

-40

-50

8.0 ns

40 ± 1.0

50 ± 1.0

-50

10.0 ns

20.0 ns

40.0 ns

60.0 ns

80.0 ns

100.0 ns

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

100 ± 2.0

200 ± 4.0

300 ± 6.0

400 ± 8.0

500 ± 10.0

NOTE: Any delay between 10 and 500 ns not shown is also available.

Ó1996 Data Delay Devices

Doc #96001

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7303

APPLICATION NOTES

To guarantee the Table 1 delay accuracy for

OPERATIONAL DESCRIPTION

input frequencies higher than the Maximum

Operating Frequency, the 3D7303 must be

tested at the user operating frequency.

Therefore, to facilitate production and device

identification, the part number will include a

custom reference designator identifying the

intended frequency of operation. The

programmed delay accuracy of the device is

guaranteed, therefore, only at the user specified

input frequency. Small input frequency variation

about the selected frequency will only marginally

impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended

that the engineering staff at DATA DELAY

DEVICES be consulted.

The 3D7303 triple delay line architecture is

shown in Figure 1. The individual delay lines are

composed of a number of delay cells connected

in series. Each delay line produces at its output

a replica of the signal present at its input, shifted

in time. The delay lines are matched and share

the same compensation signals, which

minimizes line-to-line delay deviations over

temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low)

of operation may adversely impact the specified

delay accuracy of the particular device. The

reasons for the dependency of the output delay

accuracy on the input signal characteristics are

varied and complex. Therefore a Maximum and

an Absolute Maximum operating input

frequency and a Minimum and an Absolute

Minimum operating pulse width have been

specified.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse

Width (high or low) specification, tabulated in

Table 1, determines the smallest Pulse Width of

the delay line input signal that can be

reproduced, shifted in time at the device output,

with acceptable pulse width distortion.

OPERATING FREQUENCY

The Minimum Operating Pulse Width (high or

low) specification determines the smallest Pulse

Width of the delay line input signal for which the

output delay accuracy tabulated in Table 1 is

guaranteed.

The Absolute Maximum Operating Frequency

specification, tabulated in Table 1, determines

the highest frequency of the delay line input

signal that can be reproduced, shifted in time at

the device output, with acceptable duty cycle

distortion.

To guarantee the Table 1 delay accuracy for

input pulse width smaller than the Minimum

Operating Pulse Width, the 3D7303 must be

tested at the user operating pulse width.

Therefore, to facilitate production and device

identification, the part number will include a

The Maximum Operating Frequency

specification determines the highest frequency of

the delay line input signal for which the output

delay accuracy is guaranteed.

VDD

Delay

Line

Delay

Line

Delay

Line

Temp & VDD

Compensation

GND

Figure 1: 3D7303 Functional Diagram

Doc #96001

12/2/96

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

3D7303

APPLICATION NOTES (CONT’D)

circuitry to minimize the delay variations induced

by fluctuations in power supply and/or

temperature.

custom reference designator identifying the

intended frequency and duty cycle of operation.

The programmed delay accuracy of the device is

guaranteed, therefore, only for the user specified

input characteristics. Small input pulse width

variation about the selected pulse width will only

marginally impact the programmed delay

accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at

DATA DELAY DEVICES be consulted.

The thermal coefficient is reduced to 600

PPM/C, which is equivalent to a variation , over

the 0C-70C operating range, of ±3% from the

room-temperature delay settings and/or 1.0ns,

whichever is greater. The power supply

coefficient is reduced, over the 4.75V-5.25V

operating range, to ±1% of the delay settings at

the nominal 5.0VDC power supply and/or 2.0ns,

whichever is greater. It is essential that the

power supply pin be adequately bypassed

and filtered. In addition, the power bus

should be of as low an impedance

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The monolithic 3D7303 programmable delay line

utilizes novel and innovative compensation

construction as possible. Power planes are

preferred.

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Input Pin Current

Storage Temperature

Lead Temperature

SYMBOL

V_DD

V_IN

I_IN

T_STRG

T_LEAD

MIN

-0.3

-1.0

-55

MAX

7.0

V_DD+0.3

1.0

150

300

UNITS NOTES

25C

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Static Supply Current*

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

High Level Output Current

I_DD

V_IH

V_IL

I_IH

I_IL

I_OH

2.0

0.8

V_IH= V_DD

V_IL= 0V

V_DD= 4.75V

V_OH= 2.4V

V_DD= 4.75V

V_OL= 0.4V

C_LD= 5 pf

-4.0

4.0

Low Level Output Current

I_OL

Output Rise & Fall Time

T_R& T_F

*I_DD(Dynamic) = 3 * C_LD* V_DD* F

where: C_LD= Average capacitance load/line (pf)

F = Input frequency (GHz)

Input Capacitance = 10 pf typical

Output Load Capacitance (C_LD) = 25 pf max

Doc #96001

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7303

SILICON DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): 5.0V ± 0.1V

R_load

C_load

10KW ± 10%

5pf ± 10%

Input Pulse:

High = 3.0V ± 0.1V

Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance:

Rise/Fall Time:

50W Max.

3.0 ns Max. (measured

between 0.6V and 2.4V )

PW_IN= 1.25 x Total Delay

PER_IN= 2.5 x Total Delay

Device

Under

Test

Digital

Scope

10KW

Pulse Width:

Period:

5pf

470W

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

PRINTER

COMPUTER

SYSTEM

REF

PULSE

GENERATOR

OUT

IN1

IN2

IN3

OUT1

OUT2

OUT3

DIGITAL SCOPE/

TIME INTERVAL COUNTER

DEVICE UNDER

TEST (DUT)

TRIG

Figure 2: Test Setup

PER_IN

PW_IN

t_RISE

t_FALL

INPUT

SIGNAL

V_IH

2.4V

1.5V

0.6V

2.4V

1.5V

0.6V

V_IL

t_PLH

t_PHL

OUTPUT

SIGNAL

V_OH

1.5V

V_OL

Figure 3: Timing Diagram

Doc #96001

12/2/96

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

相关型号：