3D7205 [DATADELAY]
MONOLITHIC 5-TAP FIXED DELAY LINE; 整体式5抽头固定的延时线
| 型号： | 3D7205 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 文件： | 总4页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7205
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7205)
FEATURES
PACKAGES
IN
1
2
3
4
8
7
6
5
VDD
O1
•
•
•
All-silicon, low-power CMOS
technology
IN
O2
O4
VDD
O1
O3
IN
N/C
N/C
O2
N/C
O4
VDD
N/C
O1
N/C
O3
N/C
O5
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
O2
O4
O3
GND
O5
TTL/CMOS compatible
inputs and outputs
3D7205Z
SOIC
GND
O5
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
(150 Mil)
3D7205M DIP
3D7205H Gull-Wing
•
•
•
•
•
•
•
•
•
IN
N/C
N/C
O2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
N/C
N/C
O1
GND
8
Leading- and trailing-edge accuracy
Delay range: 8 through 500ns
Delay tolerance: 5% or 2ns
3D7205 DIP
3D7205G Gull-Wing
3D7205K Unused pins
removed
N/C
O4
N/C
O3
N/C
GND
N/C
O5
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±2% typical (4.75V-5.25V)
3D7205S SOL
(300 Mil)
Minimum input pulse width: 20% of total delay
14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines
For mechanical dimensions, click here.
For package marking details, click here.
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Delay Line Input
The 3D7205 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 8.0ns through 100ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7205 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
O1
O2
O3
O4
O5
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
VDD +5 Volts
GND Ground
N/C No Connection
The all-CMOS 3D7205 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-
insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
TOLERANCES
INPUT RESTRICTIONS
DIP-8
SOIC-8
DIP-14
3D7205
3D7205
G
SOIC-16
3D7205S
TOTAL
TAP-TAP
DELAY
(ns)
Max
Absolute
Max
Min
Absolute
Min
3D7205M
3D7205H
3D7205Z
DELAY (ns)
Operating
Frequency
Operating
Pulse Width
Oper. Freq.
Oper. P.W.
3D7205K
-8
-10
-15
-20
-25
-30
-50
-75
-100
-8
-10
-15
-20
-25
-30
-50
-75
-100
-8
-10
-15
-20
-25
-30
-50
-75
-100
-8
-10
-15
-20
-25
-30
-50
-75
-100
9.52 MHz
6.67 MHz
4.44 MHz
3.33 MHz
2.66 MHz
2.22 MHz
1.33 MHz
0.89 MHz
0.67 MHz
71.4 MHz
50.0 MHz
33.3 MHz
25.0 MHz
20.0 MHz
16.7 MHz
10.0 MHz
6.67 MHz
5.00 MHz
52.5 ns
75.0 ns
113 ns
150 ns
188 ns
225 ns
375 ns
563 ns
750 ns
7.0 ns
10.0 ns
15.0 ns
20.0 ns
25.0 ns
30.0 ns
50.0 ns
75.0 ns
100.0 ns
40.0 ± 2.0
50.0 ± 2.5
75.0 ± 3.8
100 ± 5.0
125 ± 6.3
150 ± 7.5
250 ± 12.5
375 ± 18.8
8.0 ± 1.5
10.0 ± 2.0
15.0 ± 2.3
20.0 ± 2.5
25.0 ± 2.5
30.0 ± 3.0
50.0 ± 5.0
75.0 ± 7.5
500 ± 25.0 100 ± 10.0
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7205
APPLICATION NOTES
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7205 must be
tested at the user operating frequency.
OPERATIONAL DESCRIPTION
The 3D7205 five-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
OPERATING FREQUENCY
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7205 must be
tested at the user operating pulse width.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
Therefore, to facilitate production and device
identification, the part number will include a
IN
O1
O2
O3
O4
O5
20%
20%
20%
20%
20%
Temp & VDD
Compensation
VDD
GND
Figure 1: 3D7205 Functional Diagram
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7205
APPLICATION NOTES (CONT’D)
utilizes novel and innovative compensation
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 600
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of ±3% from the
room-temperature delay settings. The power
supply coefficient is reduced, over the 4.75V-
5.25V operating range, to ±2% of the delay
settings at the nominal 5.0VDC power supply. It
is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7205 programmable delay line
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
1.0
IIN
TSTRG
TLEAD
mA
C
25C
150
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
mA
V
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
15
2.0
0.8
1
V
VIH = VDD
VIL = 0V
µA
IIL
IOH
-250
4.0
µA
-4.0
mA
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
Low Level Output Current
IOL
mA
ns
V
OL = 0.4V
Output Rise & Fall Time
TR & TF
2
CLD = 5 pf
*IDD(Dynamic) = 5 * CLD * VDD * F
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/tap (pf)
F = Input frequency (GHz)
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7205
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.25 x Total Delay
PERIN = 2.5 x Total Delay
Device
Digital
Scope
10KΩ
Under
Test
Pulse Width:
Period:
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
OUT1
PULSE
OUT
OUT2
OUT3
OUT4
OUT5
IN
DIGITAL SCOPE/
DEVICE UNDER
TEST (DUT)
GENERATOR
TIME INTERVAL COUNTER
TRIG
IN
TRIG
Figure 2: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4V
1.5V
2.4V
1.5V
0.6V
SIGNAL
VIL
0.6V
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
相关型号：
3D7205-20
Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14
DATADELAY
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