DS4000CW/WBGA [DALLAS]
Oscillator,;
| 型号： | DS4000CW/WBGA |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Oscillator, 振荡器 石英晶振 温度补偿晶振 |
| 文件： | 总16页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS4000
Digitally Controlled TCXO
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS4000 digitally controlled temperature-compen-
sated crystal oscillator (DC-TCXO) features a digital
temperature sensor, one fixed-frequency temperature-
Cꢀ Aging ≤1.0ppm (First Year)
Cꢀ Frequency Stability ±1.0ppm from -40°C to +85°C
Cꢀ Frequency Versus Supply Stability of ±1.0ppm per
Volt
compensated
square-wave
output
(F1),
one
programmable temperature-compensated square-
wave output (F2), and digital communication for
frequency tuning (SDA, SCL).
Base Frequency is Digitally Tunable by ±10ppm
One Fixed-Frequency Output and One
(n + 1) or 2(n + 1) Division of the Base
Frequency Output
Cꢀ Temperature Measurements from -40CL to +85LC
with 10-Bit/+0.25°C Resolution and ±3°C
Accuracy
APPLICATIONS
Reference Oscillators in PLL Circuits
Global Positioning Systems
SATCOM
Cꢀ 2-Wire Serial Interface
Telecom
PIN CONFIGURATION
Wireless Base Stations
TOP VIEW
A
B
C
D
ORDERING INFORMATION
SCL
SDA
6
5
4
3
2
1
F2
PART
DS4000
DS4000N
TEMP RANGE
PIN-PACKAGE
24 BGA
24 BGA
VCC
F1
0°C to +70°C
-40°C to +85°C
A0
GNDOSC
N.C.
VOSC
GND
GND
Selector Guide appears end of data sheet.
GND
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 16
REV: 072403
DS4000 Digitally Controlled TCXO
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Storage Temperature Range
Operating Voltage Range
Operating Temperature Range
Commercial
-0.3V to +6.0V
-55°C to +85°C
V
CC = 5V ±5%
0°C to +70°C
-40°C to +85°C
Industrial
Soldering Temperature
See IPC/JEDEC J-STD-020A (2x max)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 5V ±5%, over the operating temperature range.)
PARAMETER
Supply Voltage
SYMBOL
VCC
CONDITIONS
(Notes 1, 2)
MIN
4.75
4.75
2.2
TYP
5.0
MAX
5.25
UNITS
V
V
V
V
Oscillator Supply Voltage
Input Logic High
VOSC
VIH
(Notes 1, 2)
(Note 1)
5.0
5.25
VCC + 0.3
+0.8
Input Logic Low
VIL
(Note 1)
-0.3
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5%, over the operating temperature range.)
PARAMETER
Active Supply Current
Active Oscillator Supply Current
Output Logic High 2.4V
Output Logic Low 0.4V
Input Leakage
SYMBOL
ICC
CONDITIONS
(Notes 3, 4)
MIN
TYP
1.5
MAX
2
UNITS
mA
mA
mA
mA
ꢀA
IOSC
IOH
(Notes 3, 4)
(Note 1)
3.5
5.5
-1
IOL
(Note 1)
4
1
ILI
I/O Leakage
ILO
1
ꢀA
Temperature Conversion Time
tCONVT
(Note 3)
250
300
ms
Note 1: All voltages are referenced to ground.
Note 2: For ±10% operating range, contact factory.
Note 3: Typical values are at +25LC and nominal supplies.
Note 4: These parameters are measured with the outputs disabled.
2 of 16
DS4000 Digitally Controlled TCXO
AC ELECTRICAL CHARACTERISTICS: TCXO
(VCC = 5V ±5%, over the operating temperature range.)
PARAMETER
Output Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
F1
F2
CMOS (Note 5)
10
20
MHz
Frequency Stability vs.
Temperature
-1.0
+1.0
ppm
ꢁF/TA
Frequency Stability vs. Voltage
(Note 6)
±1.0
±1.0
ppm/V
ꢁF/V
Frequency Stability vs. Aging
ppm/Yr
ꢁF/Yr
F1, F2 Rise and Fall Time, 10% to
90%
tR, tF
4
ns
Max Output Capacitive Load
Duty Cycle
CL
10
60
pF
%
tW / t
40
50
10Hz
-85
100Hz
1kHz
-115
-129
-134
-139
Phase Noise f1 Output (Note 7)
dBc/Hz
ꢂ
N
10kHz
100kHz
Note 5: F1 is the base frequency as defined by the package markings. F2 is a programmable frequency output. The output frequency of F2 is
derived from the base frequency, F1, by programming the F2 frequency select register and duty cycle (DC) bit in the TCXO control
register. The minimum output frequency is F1 / (28 + 1) with DC = 0 and f1 / [2 x (28 + 1)] with DC = 1.
Note 6: First year typical.
Note 7: 16.384MHz, 5V, +25°C with one of the two outputs enabled.
3 of 16
DS4000 Digitally Controlled TCXO
AC ELECTRICAL CHARACTERISTICS—2-WIRE SERIAL INTERFACE
(VCC = 4.75 to 5.25V, TA = -40LC to +85LC)
PARAMETER
SYMBOL
CONDITION
Fast mode
MIN
0
TYP
MAX
400
UNITS
SCL Clock Frequency
fSCL
kHz
Standard mode
Fast mode
0
100
1.3
Bus Free Time Between
a STOP and START
Condition
tBUF
ꢀs
Standard mode
4.7
Fast mode (Note 7)
Standard mode (Note 7)
Fast mode
0.6
4.0
1.3
Hold Time (Repeated)
START Condition
tHD:STA
ꢀs
ꢀs
Low Period of SCL
Clock
tLOW
Standard mode
4.7
Fast mode
0.6
4.0
0.6
High Period of SCL
Clock
tHIGH
ꢀs
Standard mode
Fast mode
Setup Time for a
Repeated START
Condition
tSU:STA
tHD:DAT
tSU:DAT
ꢀs
ꢀs
ns
Standard mode
4.7
Fast mode (Note 8)
0
0
0.9
0.9
Data Hold Time
Data Setup Time
Standard mode (Note 8)
Fast mode (Note 9)
100
250
Standard mode (Note 9)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 10)
Standard mode (Note 10)
Fast mode
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
300
1000
300
Rise Time of Both SDA
and SCL
ns
ns
ꢀs
tR
Fall Time of Both SDA
and SCL
tF
1000
Setup Time for STOP
Condition
tSU:STO
Standard mode
4.0
Capacitive Load for
Each Bus Line
(Note 10)
400
pF
pF
CB
CI
Input Capacitance
5
Note 7: After this period, the first clock pulse is generated.
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard mode system, but the requirement t
>250ns must then be met. This is automatically
SU:DAT
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released.
Note 10: CB: Total capacitance of one bus line in pF.
4 of 16
DS4000 Digitally Controlled TCXO
Figure 1. Timing Diagram
PIN DESCRIPTION
PIN
1A, 1B, 1C,
1D, 2C, 2D
NAME
GND
N.C.
GNDOSC
VOSC
A0
FUNCTION
Ground. DC power is provided to the device on these pins.
No Connection. (Do not connect to ground.)
2A, 2B
3A, 3B
3C, 3D
4A, 4B
4C, 4D
5A, 5B
5C, 5D
6A, 6B
6C, 6D
Oscillator Ground. DC power is provided to the oscillator on these pins.
Oscillator Power Supply. DC power is provided to the oscillator on these pins.
2-Wire Slave Address Input. This pin is used to configure the slave address.
DC-TCXO Frequency Output
F1
2-Wire Serial-Data Input/Output. SDA is the input/output pin for the 2-wire serial
interface. The SDA pin is open drain and requires an external pullup resistor.
SDA
VCC
Power Supply. DC power is provided to the device on these pins.
2-Wire Serial-Clock Input. SCL is used to synchronize data movement on the serial
interface. The SCL pin is open drain and requires an external pullup resistor.
SCL
F2
DC-TCXO Frequency Output
5 of 16
DS4000 Digitally Controlled TCXO
DETAILED DESCRIPTION
The DS4000 digitally controlled temperature-compensated crystal oscillator (DC-TCXO) features a digital
temperature sensor, one fixed-frequency temperature-compensated square-wave output (F1), one programmable
temperature-compensated square-wave output (F2), and digital communication for frequency tuning (SDA, SCL).
Figure 2. Block Diagram
VOSC
VCC
TEMPERATURE-
F2
F1
COMPENSATED
CRYSTAL
OSCILLATOR
SDA
SCL
A0
2-WIRE
SERIAL
INTERFACE
DIGITAL
TEMPERATURE
SENSOR
DS4000
OSC
GND
GND
6 of 16
DS4000 Digitally Controlled TCXO
TEMPERATURE-COMPENSATED CRYSTAL OSCILLATOR
The DS4000 can either function as a standalone TCXO or as a digitally controlled TCXO. When used as a
standalone TCXO, the only requirements needed to function properly are power, ground, and an output. However,
the 2-wire interface must be used to tune (push and pull) the crystal.
The DS4000 is capable of supplying two different outputs, F1 and F2.
1) F1 is the base frequency of the crystal unit inside of the device. The output type is a CMOS square wave.
2) F2 is a programmable frequency output. The frequency select register can program this output to an integer
division of the base (F1) frequency. The duty cycle (DC) bit determines if the output is an n + 1 or a 2(n + 1)
division of F1.
F2 FREQUENCY SELECT REGISTER (FSR) (5Dh)
Bit
7
D7
0
6
D6
0
5
D5
0
4
D4
0
3
D3
0
2
D2
0
1
D1
0
0
D0
0
Name
Default
F2 = F1 / (FSR value + 1); with DC = 0
F2 = F1 / [2 x (FSR value + 1)]; with DC = 1
TCXO CONTROL REGISTER (60h)
Bit
7
X
0
6
X
0
5
X
0
4
X
0
3
F2OE
0
2
F1OE
0
1
FT
0
0
DC
0
Name
Default
DC, Duty Cycle Bit: If 50% duty cycle is desired, then this bit must be set to logic 1. The default condition at
power-up is logic 0.
FT: This bit must be programmed by the user to 0.
F1OE, F1 Output Enable Bit: This bit allows the user to disable/enable the F1 output.
F2OE, F2 Output Enable Bit: This bit allows the user to disable/enable the F2 output.
7 of 16
DS4000 Digitally Controlled TCXO
DIGITAL TUNING THE BASE CRYSTAL FREQUENCY
When using the 2-wire interface for tuning the base frequency, the frequency tuning register is used. The frequency
tuning register contains two’s complement data. The data is used to add or subtract an offset from the crystal
loading register. When the tuning register is programmed with a value, the next temperature-update cycle sums the
programmed value with the factory-compensated value. This allows the user/system to digitally control the base
frequency by a microcontroller using the 2-wire protocol.
FREQUENCY TUNING REGISTER (66h)
Bit
7
SIGN
0
6
FO6
0
5
FO5
0
4
FO4
0
3
FO3
0
2
FO2
0
1
FO1
0
0
FO0
0
Name
Default
FOS[6:0], Frequency Offset: These bits are used to tune the base crystal frequency. Each bit represents
approximately 0.08ppm and, therefore, for a value of 07FH, pushes or pulls the base frequency by approximately
10.16ppm.
SIGN, Sign Bit: This bit is used to determine whether to add or subtract the frequency offset from the crystal
loading.
Table 1. Frequency Tuning Relationship
CALCULATED
DIGITAL DATA
(Binary)
DIGITAL DATA
(hex)
FREQUENCY OFFSET
(ppm)
-10.16
-8.00
-5.28
-1.84
-0.08
0.0
0111 1111
0110 0100
0100 0010
0001 0111
0000 0001
0000 0000
1111 1111
1110 1000
1011 0011
1001 1100
1000 0000
7Fh
64h
42h
17h
01h
00h
FFh
E8h
B3h
9Ch
80h
+0.08
+1.84
+5.28
+8.00
+10.16
8 of 16
DS4000 Digitally Controlled TCXO
DIGITAL TEMPERATURE SENSOR
The digital temperature sensor provides 10-bit temperature readings that indicate the temperature of the device.
Temperature readings are communicated from the DS4000 over a 2-wire serial interface. No additional
components are required. The DS4000 has an external address bit that allows a user to choose the slave address
from two possible values.
The factory-calibrated temperature sensor requires no external components. Upon power-up, the DS4000 starts
performing temperature conversions with a resolution of 10 bits (+0.25°C resolution). Following an 8-bit command
protocol, temperature data can be read over the 2-wire interface. The host can periodically read the value in the
temperature register, which contains the last completed conversion. As conversions are performed in the
background, reading the temperature register does not affect the conversion in progress.
READING TEMPERATURE
The DS4000 measures temperature through the use of an on-chip temperature-measurement technique with an
operation range from 0°C to +70°C (commercial) or -40°C to +85°C (industrial). The device performs continuous
conversions with the most recent result being stored in the temperature register. The digital temperature is
retrieved from the temperature register using the READ TEMPERATURE command, as described in detail in the
following paragraphs.
Table 2 shows the exact relationship of output data to measured temperature. The data is transmitted serially over
the 2-wire serial interface, MSB first. The MSB of the temperature register contains the “sign” (S) bit, denoting
whether the temperature is positive or negative. For Fahrenheit usage, a lookup table or conversion routine must
be used.
TEMPERATURE/DATA RELATIONSHIP (UNIT = LC)
MSB (64h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
S
26
25
24
23
22
21
20
LSB
(65h)
BIT 7
BIT 6
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
2-1
2-2
Table 2. Temperature/Data Relationship
TEMPERATURE
DIGITAL OUTPUT
DIGITALOUTPUT
(hex)
(°C)
(Binary)
+85
+75
+0.5
0
0101 0101 0000 0000
0100 1011 0000 0000
0000 0000 1000 0000
0000 0000 0000 0000
1111 1111 1000 0000
1110 1100 0000 0000
1101 1000 0000 0000
5500h
4B00h
0080h
0000h
FF80h
EC00h
D800h
-0.5
-20
-40
Note: Internal power dissipation raises the temperature above the ambient. The delta between ambient and the die temperature depends on
power consumption, PC board layout, and airflow.
9 of 16
DS4000 Digitally Controlled TCXO
READ TEMPERATURE COMMAND
This command reads the last temperature conversion result from the temperature register in the format described
in the Reading Temperature section. If an application can accept temperature resolutions of +1.0°C, then the
master can read the first data byte and follow with a NACK and STOP. For higher resolution, both bytes must be
read.
Table 3. Command Set
2-WIRE BUS DATA
INSTRUCTION
FUNCTION
PROTOCOL
AFTER ISSUING
PROTOCOL
Frequency Select
Register (Note 1)
Read or write 1 data
byte
Defines F2 output frequency
5Dh
60h
64h
66h
TCXO Control
Enables/disables F1 and F2;
sets duty cycle of F2
Read or write 1 data
Register (Note 1)
byte
Read Temperature
Reads 10-bit temperature register
Read 1 or 2 data bytes
(Note 2)
Frequency Tuning
Register (Note 2)
Digitally adds/subtracts an offset
from oscillator
Read or write 1 data
byte
Note 1: The slave does not increment the internal address pointer between instructions. The address pointer must be reinitialized after each
access.
Note 2. If the user only desires 8-bit thermometer readings, the master can read one data byte, and follow with a NACK and STOP. If higher
resolution is required, both bytes must be read.
10 of 16
DS4000 Digitally Controlled TCXO
2-WIRE SERIAL INTERFACE
The DS4000 supports a bidirectional 2-wire serial bus and data transmission protocol. The bus must be controlled
by a master device, which generates the serial clock (SCL), controls the bus access, and generates the START
and STOP conditions. The DS4000 operates as a slave on the 2-wire bus. The DS4000 works in a regular mode
(100kHz clock rate) and a fast mode (400kHz clock rate), which are defined within the bus specifications.
Connections to the bus are made by the open-drain I/O signals SDA and SCL.
The following bus protocol has been defined (Figure 3):
Cꢀ Data transfer can be initiated only when the bus is not busy.
Cꢀ During data transfer, the data signal must remain stable whenever the clock signal is HIGH. Changes in the
data signal while the clock signal is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock signals remain HIGH.
Start Data Transfer: A change in the state of the data signal, from HIGH to LOW, while the clock line is HIGH,
defines the START condition.
Stop Data Transfer: A change in the state of the data signal, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data Valid: The state of the data signal represents valid data when, after a START condition, the data signal is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is required to generate an acknowledge after reception of
each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the serial data (SDA) signal during the acknowledge clock pulse in
such a way that the SDA signal is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end-of-data to the slave by not
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must
leave the data signal HIGH to enable the master to generate the STOP condition.
11 of 16
DS4000 Digitally Controlled TCXO
Figure 3. Data Transfer On 2-Wire Serial Bus
SDA
MSB
SLAVE
ADDRESS
R/W BIT
8
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
SCL
1
2
3-5
6
7
9
1
2
3-7
8
9
ACK
ACK
REPEATED IF
START
MORE BYTES ARE
TRANSFERRED
STOP CONDITION
OR REPEATED
CONDITION
START CONDITION
DATA TRANSFER
Figures 4 and 5 detail how data transfer is accomplished on the 2-wire bus.
Depending on the R/W bit in the transmission protocols as shown, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the
slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At
the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial
clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer,
the bus is not released.
12 of 16
DS4000 Digitally Controlled TCXO
SLAVE ADDRESS
The slave address is the first byte received following the START condition generated by the master device. The
address byte consists of a 7-bit slave address and the R/W direction bit. The DS4000 slave address is set to
100010A0, where A0 is externally hardwired to a HIGH or LOW state. This allows design flexibility to set the slave’s
address to one of two possible address locations. The last bit following the slave address is the direction bit (R/W)
and defines the operation to be performed by the master, transmit data (R/W = 0), or receive data (R/W = 1).
Following the START condition, the DS4000 monitors the SDA bus by checking the slave address being
transmitted. Upon receiving the proper slave address and R/W bit, the slave device outputs an acknowledge signal
on the SDA line regardless of the operation mode.
The DS4000 can operate in the following two modes:
1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received,
an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a
serial transfer. Address recognition is performed by the hardware after reception of the slave address and
direction bit (Figure 4).
2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in
this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by
the DS4000 while the serial clock is input on SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (Figure 5).
Figure 4. Data Write—Slave Receiver Mode
<SLAVE ADDRESS>
<DATA ADDRESS>
<DATA (n)>
R/W
S
100010A0
0
A
XXXXXXXX
A
XXXXXXXX
A
A
P
S = START
A = ACKNOWLEDGE
P = STOP
Figure 5. Data Read—Slave Transmitter Mode
<SLAVE ADDRESS>
R/W
<DATA (n)>
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
S
100010A0
1
A
XXXXXXXX
A
XXXXXXXX
XXXXXXXX
A
XXXXXXXX
A
P
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
13 of 16
DS4000 Digitally Controlled TCXO
SELECTOR GUIDE
FREQUENCY
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK
DESIGNATOR (MHz)
DS4000A0/WBGA
DS4000A0N/WBGA
DS4000CW/WBGA
DS4000CWN/WBGA
DS4000D0/WBGA
DS4000D0N/WBGA
DS4000EC/WBGA
DS4000ECN/WBGA
DS4000G0/WBGA
DS4000G0N/WBGA
DS4000GF/WBGA
DS4000GFN/WBGA
DS4000GW/WBGA
DS4000GWN/WBGA
DS4000KI/WBGA
DS4000KIN/WBGA
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
24 BGA
DS4000A0
10.00000
10.00000
12.80000
12.80000
13.00000
13.00000
14.31818
14.31818
16.00000
16.00000
16.38400
16.38400
16.80000
16.80000
19.44000
19.44000
DS4000A0
###XX N
DS4000CW
DS4000CW
###XX N
DS4000D0
DS4000D0
###XX N
DS4000EC
DS4000EC
###XX N
DS4000G0
DS4000G0
###XX N
DS4000GF
DS4000GF
###XX N
DS4000GW
DS4000GW
###XX N
DS4000KI
DS4000KI
###XX N
14 of 16
DS4000 Digitally Controlled TCXO
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
NOTE: THE BGA IS SOLDER-MASKED DEFINED.
15 of 16
DS4000 Digitally Controlled TCXO
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
1.27
PAD: 0.85mm
1.27
SOLDERMASK: 0.60mm
8.89
DIMENSIONS IN MILLIMETERS
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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