DS3153_技术文档

DEMO KIT AVAILABLE

DS3151/DS3152/DS3153/DS3154

Single/Dual/Triple/Quad

DS3/E3/STS-1 LIUs

www.maxim-ic.com

GENERAL DESCRIPTION

FEATURES

The DS3151 (single), DS3152 (dual), DS3153

(triple), and DS3154 (quad) line interface units (LIUs)

perform the functions necessary for interfacing at the

physical layer to DS3, E3, or STS-1 lines. Each LIU

has independent receive and transmit paths and a

built-in jitter attenuator.

Cꢀ Single, Dual, Triple, or Quad Integrated

Transmitter, Receiver, and Jitter Attenuators for

DS3, E3, and STS-1

Cꢀ Each Port Independently Configurable

Cꢀ Perform Receive Clock/Data Recovery and

Transmit Waveshaping

Cꢀ Hardware or CPU Bus Configuration Options

Cꢀ Jitter Attenuators can be Placed in Either the

Receive or Transmit Paths

APPLICATIONS

SONET/SDH and PDH Multiplexers

Digital Cross-Connects

Access Concentrators

ATM and Frame Relay Equipment

Routers

Cꢀ Interface to 75ꢀ Coaxial Cable at Lengths Up to

380m (DS3), 440m (E3), or 360m (STS-1)

Cꢀ Use 1:2 Transformers on Tx and Rx

Cꢀ Require Minimal External Components

Cꢀ Local and Remote Loopbacks

PBXs

Cꢀ Low-Power 3.3V Operation (5V Tolerant I/O)

Cꢀ Industrial Temperature Range:

-40°C to +85LC

DSLAMs

CSUs/DSUs

Cꢀ Small Package: 144-Pin, 13mm x 13mm

Thermally Enhanced CSBGA

FUNCTIONAL DIAGRAM

Cꢀ IEEE 1149.1 JTAG Support

EACH LIU

Features continued on page 5.

LINE IN

RECEIVE

CLOCK

ORDERING INFORMATION

RXP

RXN

CLK

DS3, E3,

OR STS-1

DATA

Dallas

PART

LIUs

TEMP RANGE

PIN-PACKAGE

AND DATA

DS3151

DS3151N

DS3152

DS3152N

DS3153

DS3153N

DS3154

DS3154N

1

2

3

4

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

144 TE-CSBGA

Semiconductor

DS315x

CONTROL

STATUS

LINE OUT

DS3, E3,

OR STS-1

TRANSMIT

CLOCK

TXP

TXN

CLK

DATA

AND DATA

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

TABLE OF CONTENTS

1.

2.

3.

4.

5.

6.

7.

8.

9.

DETAILED DESCRIPTION.................................................................................................5

APPLICATIONS .................................................................................................................7

HARDWARE MODE AND CPU BUS MODE......................................................................8

PIN DESCRIPTIONS ........................................................................................................10

REGISTER DESCRIPTIONS............................................................................................15

RECEIVER........................................................................................................................22

TRANSMITTER ................................................................................................................25

DIAGNOSTICS .................................................................................................................28

JITTER ATTENUATOR....................................................................................................29

10. RESET LOGIC..................................................................................................................30

11. TRANSFORMERS............................................................................................................31

12. JTAG TEST ACCESS PORT AND BOUNDARY SCAN..................................................32

13. ELECTRICAL CHARACTERISTICS ................................................................................37

14. PIN ASSIGNMENTS.........................................................................................................46

15. PACKAGE INFORMATION..............................................................................................59

16. THERMAL INFORMATION ..............................................................................................60

17. REVISION HISTORY........................................................................................................60

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

LIST OF FIGURES

Figure 1-1. External Connections ............................................................................................................ 7

Figure 2-1. 4-Port Unchannelized DS3/E3 Card ...................................................................................... 7

Figure 3-1. Hardware Mode Block Diagram............................................................................................. 8

Figure 3-2. CPU Bus Mode Block Diagram.............................................................................................. 9

Figure 5-1. Status Register Logic .......................................................................................................... 16

Figure 6-1. Receiver Jitter Tolerance..................................................................................................... 24

Figure 7-1. E3 Waveform Template....................................................................................................... 27

Figure 7-2. DS3 AIS Structure............................................................................................................... 28

Figure 8-1. PRBS Output with Normal RCLK Operation ........................................................................ 29

Figure 8-2. PRBS Output with Inverted RCLK Operation....................................................................... 29

Figure 9-1. Jitter Attenuation/Jitter Transfer........................................................................................... 30

Figure 12-1. JTAG Block Diagram......................................................................................................... 32

Figure 12-2. JTAG TAP Controller State Machine ................................................................................. 33

Figure 13-1. Transmitter Framer Interface Timing Diagram ................................................................... 38

Figure 13-2. Receiver Framer Interface Timing Diagram....................................................................... 39

Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)...................................................................... 41

Figure 13-4. CPU Bus AC Timing Diagram (Multiplexed)....................................................................... 43

Figure 13-5. JTAG Timing Diagram....................................................................................................... 45

Figure 14-1. DS3151 Hardware Mode Pin Assignment.......................................................................... 51

Figure 14-2. DS3151 CPU Bus Mode Pin Assignment .......................................................................... 52

Figure 14-3. DS3152 Hardware Mode Pin Assignment.......................................................................... 53

Figure 14-4. DS3152 CPU Bus Mode Pin Assignment .......................................................................... 54

Figure 14-5. DS3153 Hardware Mode Pin Assignment.......................................................................... 55

Figure 14-6. DS3153 CPU Bus Mode Pin Assignment .......................................................................... 56

Figure 14-7. DS3154 Hardware Mode Pin Assignment.......................................................................... 57

Figure 14-8. DS3154 CPU Bus Mode Pin Assignment .......................................................................... 58

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

LIST OF TABLES

Table 1-A. Applicable Telecommunications Standards............................................................................ 6

Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes................................................................. 10

Table 4-B. Transmitter Pin Descriptions ................................................................................................ 11

Table 4-C. Receiver Pin Descriptions.................................................................................................... 12

Table 4-D. Global Pin Descriptions........................................................................................................ 13

Table 4-E. JTAG and Test Pin Descriptions .......................................................................................... 14

Table 4-F. Transmitter Data Select Options........................................................................................... 14

Table 4-G. Receiver PRBS Pattern Select Options................................................................................ 14

Table 5-A. Register Map........................................................................................................................ 15

Table 7-A. DS3 Waveform Template..................................................................................................... 26

Table 7-B. DS3 Waveform Test Parameters and Limits......................................................................... 26

Table 7-C. STS-1 Waveform Template.................................................................................................. 26

Table 7-D. STS-1 Waveform Test Parameters and Limits ..................................................................... 27

Table 7-E. E3 Waveform Test Parameters and Limits ........................................................................... 27

Table 11-A. Transformer Characteristics ............................................................................................... 31

Table 11-B. Recommended Transformers............................................................................................. 31

Table 12-A. JTAG Instruction Codes ..................................................................................................... 35

Table 12-B. JTAG ID Code.................................................................................................................... 35

Table 13-A. Recommended DC Operating Conditions........................................................................... 37

Table 13-B. DC Characteristics ............................................................................................................. 37

Table 13-C. Framer Interface Timing..................................................................................................... 38

Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes.................................................... 39

Table 13-E. Receiver Input Characteristics—E3 Mode.......................................................................... 39

Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes ............................................. 40

Table 13-G. Transmitter Output Characteristics—E3 Mode................................................................... 40

Table 13-H. CPU Bus Timing ................................................................................................................ 40

Table 13-I. JTAG Interface Timing......................................................................................................... 45

Table 14-A. Pin Assignments Sorted by Signal Name ........................................................................... 46

Table 14-B. Pin Assignments Sorted by Pin Number............................................................................. 48

Table 16-A. Thermal Properties, Natural Convection............................................................................. 60

Table 16-B. Theta-JA (ꢀ ) vs. Airflow.................................................................................................... 60

JA

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

FEATURES (continued)

Receiver

Cꢀ AGC/equalizer block handles from 0 to 15dB of cable loss

Cꢀ Loss-of-lock (LOL) PLL status indication

Cꢀ Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp

Cꢀ Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)

Cꢀ Optional B3ZS/HDB3 decoder

Cꢀ Line-code violation output pin and counter

Cꢀ Binary or bipolar framer interface

Cꢀ On-board 2¹⁵- 1 and 2²³- 1 PRBS detector

Cꢀ Clock inversion for glueless interfacing

Cꢀ Tri-state clock and data outputs support protection switching applications

Cꢀ Per-channel power-down control

Transmitter

Cꢀ Binary or bipolar framer interface

Cꢀ Gapped clock capable up to 51.84MHz

Cꢀ Wide 50 M20% transmit clock duty cycle

Cꢀ Clock inversion for glueless interfacing

Cꢀ Optional B3ZS/HDB3 encoder

Cꢀ On-board 2¹⁵- 1 and 2²³- 1 PRBS generator

Cꢀ Complete DS3 AIS generator (ANSI T1.107)

Cꢀ Unframed all-ones generator (E3 AIS)

Cꢀ Line build-out (LBO) control

Cꢀ Tri-state line driver outputs support protection switching applications

Cꢀ Per-channel power-down control

Cꢀ Output driver monitor

1. DETAILED DESCRIPTION

The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) LIUs perform the functions necessary

for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit

paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or HDB3-coded

alternate mark inversion (AMI) signal and monitors for loss of the incoming signal. The receiver optionally performs

B3ZS/HDB3 decoding and outputs the recovered data in either binary or bipolar format. The transmitter accepts

data in either binary or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standard pulse-shape

waveforms onto 75ꢀ coaxial cable. The jitter attenuator can be mapped into the receiver data path, mapped into

the transmitter data path, or be disabled. The DS315x LIUs conform to the telecommunications standards listed in

Table 1-A. Figure 1-1 shows the external components required for proper operation.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 1-A. Applicable Telecommunications Standards

SPECIFICATION

SPECIFICATION TITLE

ANSI

T1.102-1993

T1.107-1995

T1.231-1997

T1.404-1994

Digital Hierarchy—Electrical Interfaces

Digital Hierarchy—Formats Specification

Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring

Network-to-Customer Installation—DS3 Metallic Interface Specification

ITU-T

G.703

G.751

Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991

Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the

Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993

Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance

Criteria, November 1994

G.775

G.823

G.824

O.151

The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps

Hierarchy, 1993

The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps

Hierarchy, 1993

Error Performance Measuring Equipment Operating at the Primary Rate and Above,

October 1992

ETSI

Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,

D34S, D140U, and D140S); Network Interface Presentation, 1996

Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);

Connection Characteristics, 1996

ETS 300 686

ETS 300 687

ETS EN 300 689

TBR 24

Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal

equipment interface, July 2001

Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;

Attachment Requirements for Terminal Equipment Interface, 1997

TELCORDIA

GR-253-CORE

GR-499-CORE

SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995

Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1,

December 1998

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 1-1. External Connections

TRANSMIT

EACH LIU

TXP

V_DD

0.1ꢀF

0.01ꢀF

1ꢀF

3.3V

POWER

PLANE

330ꢁ

V_DD

(1%)

0.05ꢀF

(OPTIONAL)

TXN

0.1ꢀF

0.01ꢀF

1ꢀF

1:2ct

Dallas

Semiconductor

RECEIVE

DS315x

V_SS

RXP

GROUND

PLANE

330ꢁ

V_SS

(1%)

0.05ꢀF

(OPTIONAL)

RXN

2. APPLICATIONS

Figure 2-1. 4-Port Unchannelized DS3/E3 Card

DS3154

QUAD

DS3144

QUAD

DS3/E3/STS-1

LIU

DS3/E3

FRAMER

Shorthand Notations. The notation “DS315x” throughout this data sheet refers to either the DS3151, DS3152,

DS3153, or DS3154. This data sheet is the specification for all four parts. The LIUs on the DS315x are identical.

For brevity, this document uses the pin name and register name shorthand “NAMEn,” where “n” stands in place of

the LIU port number. For example, on the DS3154 quad LIU, TCLKn is shorthand notation for pins TCLK1, TCLK2,

TCLK3, and TCLK4 on LIU ports 1, 2, 3, and 4, respectively. This document also uses generic pin and register

names such as TCLK (without a number suffix) when describing LIU operation. When working with a specific LIU

on the DS315x devices, generic names like TCLK should be converted to actual pin names, such as TCLK1.

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3. HARDWARE MODE AND CPU BUS MODE

The DS315x can operate in either hardware mode or CPU bus mode. In hardware mode, pulling configuration input

pins high or low does all configuration, and all status information is reported on status output pins. Internal registers

are not accessible in hardware mode. The device is configured for hardware mode when the HW pin is wired high

(HW = 1).

In CPU bus mode, most of the configuration and status pins used in hardware mode are reassigned to be address,

data, and control lines that provide a glueless interface to an 8-bit microprocessor bus. Through the CPU bus, an

external processor can access a set of internal registers. Setting configuration register bits high or low can do

configuration, and status information can be read from status register bits. Events indicated by status register bits

can also activate the interrupt output pin (INT), if configured to do so by a set of interrupt-enable bits. A few

configuration and status pins are active in hardware mode and CPU bus mode to support specialized applications,

such as protection switching. The device is configured for CPU bus mode when the HW pin is wired low (HW = 0).

With the exception of the HW pin, configuration and status pins available in hardware mode have corresponding

register bits in the CPU bus mode. The hardware mode pins and the CPU bus mode register bits have identical

names and functions, with the exception that all register bits are active high. For example, LOS is indicated by the

receiver on the RLOS pin (active low) in hardware mode and the RLOS register bit (active high) in CPU bus mode.

The few configuration input pins that are active in CPU bus mode also have corresponding register bits. In these

cases, the actual configuration is the logical OR of pin assertion and register bit assertion. For example, the

transmitter output driver is tri-stated if the TTS pin is asserted (i.e., low) or the TTS register bit is asserted (high).

Figure 3-1 and Figure 3-2 show block diagrams of the DS315x in hardware mode and in CPU bus mode. Table 4-A

lists the pins that are active in each mode.

Figure 3-1. Hardware Mode Block Diagram

RMONn T3MCLK E3MCLK STMCLK

RJAn

RLOSn

RBIN

V_DD

V_SS

Power

Supply

Digital LOS

Detector

PRBS

Clock Mux

Detector

PRBSn

B3ZS/HDB3

Decoder

RTSn

Automatic

Gain

RXPn

RPOSn/RDATn

RNEGn/RLCVn

RCLKn

Control

+

Output

Drivers,

Clock

Clock &

Data

Adaptive

Equalizer

Recovery

RXNn

Invert

RCINV

Remote

ALOS

Loopback

squelch

Digital

Analog

Local

HIZ

RST

Local

Loopback

Global

HW

Configuration

E3Mn

STSn

TDMn

Driver

Monitor

TPOSn/TDATn

TNEGn

TXPn

TXNn

TCLKn

Clock

Invert

B3ZS/

HDB3

TCINV

Encoder

AIS, 100100…,

PRBS Pattern

Generation

Loopback Control

Dallas

Semiconductor

DS315x

TTSn LLBn RLBn

TLBOn

TJAn

TBIN

TDSAn,

TDSBn

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 3-2. CPU Bus Mode Block Diagram

RLOSn

T3MCLK E3MCLK STMCLK

Clock Mux

V_DD

V_SS

Digital LOS

Detector

PRBS

Power

Supply

Dallas

Semiconductor

DS315x

Detector

PRBSn

B3ZS/HDB3

Decoder

RTSn

Automatic

Gain

RXPn

RXNn

RPOSn/RDATn

RNEGn/RLCVn

RCLKn

Control

Clock &

Output

Drivers,

Clock

+

Data

Adaptive

Recovery

Equalizer

Invert

Remote

ALOS

Loopback

HIZ

squelch

RST

Digital

Analog

Local

Loopback

HW

Local

CPU Bus

MOT

ALE

Loopback

Interface

and

CS

Global

WR/R/W

RD/DS

A[5:0]

D[7:0]

INT

Configuration

TDMn

Driver

Monitor

TPOSn/TDATn

TNEGn

TCLKn

TXPn

TXNn

Clock

Invert

B3ZS/

HDB3

Encoder

AIS, 100100…,

PRBS Pattern

Generation

Loopback Control

TTSn

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

4. PIN DESCRIPTIONS

Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes

HARDWARE

MODE

CPU BUS

MODE

NAME

TYPE

FUNCTION

TRANSMITTER

TCLKn

TPOSn/TDATn

TNEGn

I

Transmitter Clock

Active

Transmitter Positive AMI/Transmitter Data

Transmitter Negative AMI

Transmitter Analog Outputs

Transmitter Tri-State Enable

Transmitter Driver Monitor Output

Transmitter Data Select

I

TXPn, TXNn

TTSn

O

I

O

I

TDMn

TDSAn, TDSBn

TLBOn

I

Transmitter Line Build-Out Enable

Transmitter Jitter Attenuator Enable

RECEIVER

TJAn

I

RXPn, RXNn

RCLKn

I

O

I

Receiver Analog Inputs

Active

Receiver Clock

RPOSn/RDATn

RNEGn/RLCVn

RTSn

Receiver Positive AMI/Receiver Data

Receiver Negative AMI/Line-Code Violation

Receiver Tri-State Enable

Receiver LOS Output

Receiver Monitor Enable

Receiver Jitter Attenuator Enable

GLOBAL

O

I

RLOSn

RMONn

RJAn

I

High-Z Enable

Reset Enable

Active

HIZ

RST

HW

I

Hardwired Mode Enable

T3MCLK

E3MCLK

STMCLK

PRBSn

LLBn, RLBn

E3Mn, STSn

RBIN

I

T3 Master Clock (44.736MHz ±20ppm)

E3 Master Clock (34.368MHz ±20ppm)

STS-1 Master Clock (51.840MHz ±20ppm)

PRBS Detector Output

I

O

I

Local Loopback, Remote Loopback Select

E3 Mode Enable, STS-1 Mode Enable

Receiver Binary Interface Enable

Transmitter Binary Interface Enable

Receiver Clock Invert

I

TBIN

I

RCINV

TCINV

MOT

I

Transmitter Clock Invert

I

Motorola CPU Bus Enable

Address Latch Enable

Active

ALE

CS

I

Chip Select

Write Enable / Read/Write Select

Read Enable/Data Strobe

Address Bus

WR / R/W

RD/DS

A[5:0]

I

D[7:0]

INT

I/O

O

Data Bus

Interrupt Output

Note: In CPU bus mode, status/control pins are replaced by register bits. See Register Map in Section 5. For pin names of the form PINn,

n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 4-B. Transmitter Pin Descriptions

NAME

I/O

FUNCTION

Transmitter Clock. A DS3 (44.736MHz M20ppm), E3 (34.368MHz M20ppm), or STS-1 (51.840MHz

M20ppm) clock should be applied at this signal. Data to be transmitted is clocked into the device at

TPOS/TDAT and TNEG either on the rising edge of TCLK (TCINV = 0) or the falling edge of TCLK

(TCINV = 1). See Section 7 for additional details.

TCLKn

I

Transmitter Positive AMI/Transmitter Data. When the transmitter is configured to have a bipolar

interface (TBIN = 0), a positive pulse is transmitted on the line when TPOS is high. When the

transmitter is configured to have a binary interface (TBIN = 1), the data on TDAT is transmitted after

B3ZS or HDB3 encoding. TPOS/TDAT is sampled either on the rising edge of TCLK (TCINV = 0) or

on the falling edge of TCLK (TCINV = 1).

TPOSn/

TDATn

I

Transmitter Negative AMI. When the transmitter is configured to have a bipolar interface (TBIN = 0), a

negative pulse is transmitted on the line when TNEG is high. When the transmitter is configured to

have a binary interface (TBIN = 1), TNEG is ignored and should be wired either high or low. TNEG is

sampled either on the rising edge of TCLK (TCINV = 0) or on the falling edge of TCLK (TCINV = 1).

Transmitter Analog Outputs. These differential AMI outputs are coupled to the outbound 75ꢀ coaxial

cable through a 2:1 step-down transformer (Figure 1-1). These outputs can be tri-stated using the TTS

pin or the TTS or TPS configuration bits.

TNEGn

I

TXPn,

TXNn

O3

Transmitter Tri-State Enable (Active Low). TTS tri-states the transmitter outputs (TXP and TXN). This

feature supports applications requiring LIU redundancy. Transmitter outputs from multiple LIUs can be

wire-ORed together, eliminating external switches. The transmitter continues to operate internally

when TTS is active.

TTSn

I

0 = tri-state the transmitter output driver

1 = enable the transmitter output driver

Transmitter Driver Monitor (Active Low, Open Drain). TDM reports the status of the transmit driver

monitor. When the transmit driver monitor detects a faulty transmitter, TDM is driven low. TDM

O

I

TDMn

requires an external pullup to V_DD

.

TDSAn,

TDSBn

Transmitter Data Select. These inputs select the source of the transmit data. See Table 4-F for details.

Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and

STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low.

0 = cable length O 225ft

TLBOn

I

1 = cable length < 225ft

Transmitter Jitter Attenuator Enable

0 = remove jitter attenuator from the transmitter path

1 = insert jitter attenuator into the transmitter path

(Note that TJA = 1 takes precedence over RJA = 1.)

TJAn

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 4-C. Receiver Pin Descriptions

NAME

I/O

FUNCTION

RXPn,

Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75ꢀ coaxial cable

I

RXNn

through a 1:2 step-up transformer (Figure 1-1).

Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the

RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of

RCLK (RCINV = 1). During a loss of signal (RLOS = 0), the RCLK output signal is derived from the

LIU’s master clock.

RCLKn

O3

Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface

(RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is

configured to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT

is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).

Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar

interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is

configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See

Section 6 for further details on code violations. RNEG/RLCV is updated either on the falling edge of

RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).

RPOSn/

RDATn

RNEGn/

RLCVn

O3

I

Receiver Tri-State Enable (Active Low). RTS tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK

receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs

from multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes.

The receiver continues to operate internally when RTS is low.

RTSn

0 = tri-state the receiver outputs

1 = enable the receiver outputs

Receiver Loss of Signal (Active Low, Open Drain). RLOS is asserted upon detection of 175 M75

consecutive zeros in the receive data stream. RLOS is deasserted when there are no excessive

zero occurrences over a span of 175 M75 clock periods. An excessive zero occurrence is defined as

three or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3

mode. See Section 6 for additional details.

RLOSn

O

Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is

enabled to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This

feature should be enabled when the device is being used to monitor signals that have been

resistively attenuated by a monitor jack.

RMONn

RJAn

I

0 = disable the monitor preamp

1 = enable the monitor preamp

Receiver Jitter Attenuator Enable

0 = remove jitter attenuator from the receiver path

1 = insert jitter attenuator into the receiver path

(Note that TJA = 1 takes precedence over RJA = 1.)

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 4-D. Global Pin Descriptions

NAME

I/O

FUNCTION

High-Z Enable Input (Active Low, Open Drain)

HIZ

I_PU

0 = tri-state all output pins (Note that the JTRST pin must be low.)

1 = normal operation

Reset Input (Active Low, Open Drain, Internal 10kꢀ Pullup to V_DD). When this global asynchronous

reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced

RST

I_PU

to their default values. The device is held in reset as long as RST is low. RST should be held low for

at least two master clock cycles.

Hardwired Mode Select

0 = CPU bus mode

HW

I

1 = hardwired mode

See Section 3 for details.

T3 Master Clock. A transmission-quality DS3 (44.736MHz M20ppm, low jitter) clock should be applied

at this pin. Wiring T3MCLK high forces LIUs in DS3 mode to use TCLK for receiver clock and data

recovery.

T3MCLK

E3MCLK

I

E3 Master Clock. A transmission-quality E3 (34.368MHz M20ppm, low jitter) clock should be applied

at this pin. Wiring E3MCLK high forces LIUs in E3 mode to use TCLK for receiver clock and data

recovery.

STS-1 Master Clock. A transmission-quality STS-1 (51.840MHz M20ppm, low jitter) clock should be

applied at this pin. Wiring STMCLK high forces LIUs in STS-1 mode to use TCLK for receiver clock

and data recovery.

STMCLK

PRBSn

I

PRBS Detector Output. This signal reports the status of the PRBS detector. See Section 8 for further

details.

O

Local Loopback Select, Remote Loopback Select

{LLB, RLB} =

00 = no loopback

LLBn,

RLBn

I

01 = remote loopback

10 = analog local loopback

11 = digital local loopback

E3 Mode Enable

0 = DS3 operation

E3Mn

STSn

1 = E3 or STS-1 operation

STS-1 Mode Enable

When E3M = 1,

0 = E3 operation

1 = STS-1 operation

When E3M = 0, STS selects the DS3 AIS pattern.

Receiver Binary Framer-Interface Enable

0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is

disabled.

RBIN

TBIN

I

1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code

violations. The B3ZS/HDB3 encoder is enabled.

Transmitter Binary Framer-Interface Enable

0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is

disabled.

1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired

low.) The B3ZS/HDB3 encoder is enabled.

Receiver Clock Invert

RCINV

TCINV

MOT

I

0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.

1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.

Transmitter Clock Invert

0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.

1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.

Motorola Bus Mode Enable

0 = Intel bus mode

1 = Motorola bus mode

Address Latch Enable. This signal controls a latch on the A[5:0] inputs. In nonmultiplexed bus

applications, ALE should be wired high to make the latch transparent. In multiplexed bus

applications, A[5:0] should be wired to D[5:0]. The falling edge of ALE latches the address.

ALE

I

CS

Chip Select (Active Low). CS must be asserted in order to read or write internal registers.

Write Enable (Active Low) or Read/Write Select. In Intel bus mode (MOT = 0), WR is asserted to

WR / R/W

write internal registers. In Motorola bus mode (MOT = 1), R/W determines the type of bus

13 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

NAME

I/O

FUNCTION

transaction, with R/W = 1 indicating a read and R/W = 0 indicating a write.

Read Enable (Active Low) or Data Strobe (Active Low). In Intel bus mode (MOT = 0), RD is asserted

to read internal registers. In Motorola bus mode (MOT = 1), the rising edge of DS writes data to

internal registers.

I

RD/DS

Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not

present on the DS3152. A5 and A4 are not present on the DS3151.

Data Bus. These bidirectional lines are inputs during writes to internal registers. They are outputs

during reads from internal registers.

A[5:0]

D[7:0]

I

I/O

Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more

unmasked, active interrupt sources within the device. INT remains low until the interrupt is serviced or

masked.

INT

O

V_DD

V_SS

P

Positive Supply. 3.3V M5%. All V_DDsignals should be wired together.

Ground Reference. All V_SSsignals should be wired together.

Table 4-E. JTAG and Test Pin Descriptions

NAME

I/O

FUNCTION

JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of

JTDO on the falling edge. If boundary scan is not used, JTCLK should be pulled high.

JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10kꢀ Pullup). Test instructions and data are

clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left

unconnected or pulled high.

JTCLK

I

JTDI

I_PU

JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on

the falling edge of JTCLK.

JTDO

O

JTAG IEEE 1149.1 Test Reset (Internal 10kꢀ Pullup). This pin is used to asynchronously reset the

test access port (TAP) controller. If boundary scan is not used, JTRST can be held low or high.

JTAG IEEE 1149.1 Test Mode Select (Internal 10kꢀ Pullup). This pin is sampled on the rising edge

of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary scan

is not used, JTMS should be left unconnected or pulled high.

I_PU

JTRST

JTMS

I_PU

Factory Test Pin. Leave unconnected or wire high for normal operation.

TEST

Note 1: Pin type I = input pin. Pin type O = output pin. Pin type P = power-supply pin.

Note 2: Pin type O3 is an output that can be tri-stated.

Note 3: Pin type I_PUis an input with an internal 10kꢀ pullup.

Note 4: For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.

Note 5: Section 14 shows hardware mode and CPU bus mode pin assignments.

Table 4-F. Transmitter Data Select Options

TDSA

TDSB

E3M

X

0

STS

X

0

Tx MODE

Any

TRANSMIT DATA SELECTED

0

1

0

1

0

1

Normal data as input at TPOS and TNEG

DS3

Unframed all ones

1

0

E3

1

STS-1

DS3

0

1

DS3 AIS per ANSI T1.107 (Figure 7-2)

Unframed 100100… pattern

X

1

X

0

Any

E3

2²³- 1 PRBS pattern per ITU O.151

0

X

1

DS3

2¹⁵- 1 PRBS pattern per ITU O.151

1

STS-1

Note 1: This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by holding TDSA = 0 and changing TDSB

from 0 to 1. The type of DS3 AIS signal is selected by the STS bit with E3M = 0.

Note 2: If E3M and/or STS are changed when {TDSA,TDSB} U 00, TDSA and TDSB must both be cleared to 0. After they are cleared, TDSA

and TDSB can be configured to transmit a pattern in the new operating mode.

Table 4-G. Receiver PRBS Pattern Select Options

E3M

STS

Rx MODE

RECEIVER PRBS PATTERN SELECTED

1

0

1

0

X

1

E3

2²³- 1 PRBS pattern per ITU O.151

DS3

2¹⁵- 1 PRBS pattern per ITU O.151

STS-1

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

5. REGISTER DESCRIPTIONS

When the DS315x is configured in CPU bus mode (HW = 0), the registers shown in Table 5-A are accessible

through the CPU bus interface. All registers for the LIU ports are forced to their default values during an internal

power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all registers for that LIU to

their default values. All register bits marked “—” must be written 0 and ignored when read. The TEST registers

must be left at their reset value of 00h for normal operation.

On the DS3153, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.

Reads from LIU 4 address space return all zeros. On the DS3152, address line A5 is not present, limiting the

address space to the LIU 1 and 2 registers. On the DS3151, address lines A5 and A4 are not present, limiting the

address space to the LIU 1 registers.

Table 5-A. Register Map

ADDRESS

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

LIU 1

00h

01h

GCR1

TCR1

RCR1

SR1

E3M

—

STS

TBIN

RBIN

—

LLB

RLB

TJA

RJA

PRBS

PRBSL

PRBSIE

RCV[4]

RCV[12]

—

TDSA

TPD

TDSB

TTS

—

RST

—

TCINV

RCINV

TDM

TLBO

RMON

RLOL

RLOLL

RLOLIE

RCV[1]

RCV[9]

—

02h

ITU

RPD

RTS

RCVUD

RLOS

RLOSL

RLOSIE

RCV[0]

RCV[8]

—

03h

—

04h

SRL1

—

TDML

TDMIE

RCV[5]

RCV[13]

—

PBERL

PBERIE

RCV[3]

RCV[11]

—

RCVL

RCVIE

RCV[2]

RCV[10]

—

05h

SRIE1

RCVL1

RCVH1

TEST

—

06h

RCV[7]

RCV[15]

—

RCV[6]

RCV[14]

—

07h

08h–0Fh

LIU 2

LLB

TCINV

RCINV

TDM

TDML

TDMIE

RCV[5]

RCV[13]

—

10h

11h

GCR2

TCR2

RCR2

SR2

E3M

—

STS

TBIN

RBIN

—

RCV[6]

RCV[14]

—

RLB

TJA

RJA

PRBS

PRBSL

PRBSIE

RCV[4]

RCV[12]

—

TDSA

TPD

TDSB

TTS

--

RST

--

TLBO

RMON

RLOL

RLOLL

RLOLIE

RCV[1]

RCV[9]

—

12h

ITU

RPD

RTS

RCVUD

RLOS

RLOSL

RLOSIE

RCV[0]

RCV[8]

—

13h

—

14h

SRL2

—

PBERL

PBERIE

RCV[3]

RCV[11]

—

RCVL

RCVIE

RCV[2]

RCV[10]

—

15h

SRIE2

RCVL2

RCVH2

TEST

—

16h

RCV[7]

RCV[15]

—

17h

18h–1Fh

LIU 3

LLB

TCINV

RCINV

TDM

TDML

TDMIE

RCV[5]

RCV[13]

—

20h

21h

GCR3

TCR3

RCR3

SR3

E3M

—

STS

TBIN

RBIN

—

RCV[6]

RCV[14]

—

RLB

TJA

RJA

PRBS

PRBSL

PRBSIE

RCV[4]

RCV[12]

—

TDSA

TPD

TDSB

TTS

—

RST

—

TLBO

RMON

RLOL

RLOLL

RLOLIE

RCV[1]

RCV[9]

—

22h

ITU

RPD

RTS

RCVUD

RLOS

RLOSL

RLOSIE

RCV[0]

RCV[8]

—

23h

—

24h

SRL3

—

PBERL

PBERIE

RCV[3]

RCV[11]

—

RCVL

RCVIE

RCV[2]

RCV[10]

—

25h

SRIE3

RCVL3

RCVH3

TEST

—

26h

RCV[7]

RCV[15]

—

27h

28h–2Fh

LIU 4

LLB

TCINV

RCINV

TDM

TDML

TDMIE

RCV[5]

RCV[13]

—

30h

31h

GCR4

TCR4

RCR4

SR4

E3M

—

STS

TBIN

RBIN

—

RCV[6]

RCV[14]

—

RLB

TJA

RJA

PRBS

PRBSL

PRBSIE

RCV[4]

RCV[12]

—

TDSA

TPD

TDSB

TTS

—

RST

—

TLBO

RMON

RLOL

RLOLL

RLOLIE

RCV[1]

RCV[9]

—

32h

ITU

RPD

RTS

RCVUD

RLOS

RLOSL

RLOSIE

RCV[0]

RCV[8]

—

33h

—

34h

SRL4

—

PBERL

PBERIE

RCV[3]

RCV[11]

—

RCVL

RCVIE

RCV[2]

RCV[10]

—

35h

SRIE4

RCVL4

RCVH4

TEST

—

36h

RCV[7]

RCV[15]

—

37h

38h–3Fh

Note 1: Underlined bits are read-only; all other bits are read-write.

Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4).

Note 3: The bit names are the same for each LIU register set.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Status Register Description

The status registers have two types of status bits. Real-time status bits—located in the SRn registers—indicate the

state of a signal at the time it was read. Latched status bits—located in the SRLn registers—are set when a signal

changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1

value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits—

located in the SRIEn registers—control whether or not the INT pin is driven low when latched register bits are set.

Figure 5-1. Status Register Logic

REAL-TIME STATUS

EVENT

SR

LATCHED STATUS

LATCHED STATUS REGISTER

SET ON EVENT DETECT CLEAR

ON WRITE LOGIC 1

SRL

WR

INT

INT ENABLE

REGISTER

WR

OTHER INT

SOURCE

Register Name:

GCRn

Register Description:

Register Address:

Global Configuration Register

00h, 10h, 20h, 30h

Bit

7

E3M

0

6

STS

0

5

LLB

0

4

RLB

0

3

TDSA

0

2

TDSB

0

1

0

Name

Default

—

RST

0

Bit 7: E3 Mode Enable (E3M)

0 = DS3 operation

1 = E3 or STS-1 operation

Bit 6: STS-1 Mode Enable (STS)

When E3M = 1,

0 = E3 operation

1 = STS-1 operation

When E3M = 0, STS selects the DS3 AIS pattern (Table 4-F).

Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB)

00 = no loopback

01 = remote loopback

10 = analog local loopback

11 = digital local loopback

Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See Table 4-F for details.

Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU

(except the RST bit) are forced to their default values. RST is cleared to 0 at power-up and when the RST pin is

activated.

0 = normal operation

1 = reset LIU

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Register Name:

TCRn

Register Description:

Register Address:

Transmitter Configuration Register

01h, 11h, 21h, 31h

Bit

7

—

0

6

TBIN

0

5

TCINV

0

4

TJA

0

3

TPD

0

2

TTS

1

TLBO

0

Name

Default

—

Bit 6: Transmitter Binary Interface Enable (TBIN)

0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is

disabled.

1 = Transmitter framer interface is binary on the TDAT pin. The B3ZS/HDB3 encoder is enabled.

Bit 5: Transmitter Clock Invert (TCINV)

0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.

1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.

Bit 4: Transmitter Jitter Attenuator Enable (TJA)

0 = Remove jitter attenuator from the transmitter path.

1 = Insert jitter attenuator into the transmitter path.

Bit 3: Transmitter Power-Down Enable (TPD)

0 = enable the transmitter

1 = power-down the transmitter (output driver tri-stated)

Bit 2: Transmitter Tri-State Enable (TTS). This bit is set to 1 on reset, which tri-states the transmitter TXP and

TXN pins. The transmitter circuitry is left powered up in this mode. The TTS input pin is inverted and logically ORed

with this bit.

0 = enable the transmitter output driver

1 = tri-state the transmitter output driver

Bit 1: Transmitter Line Build-Out (TLBO). TLBO indicates cable length for waveform shaping in DS3 and STS-1

modes. TLBO is ignored in E3 mode.

0 = cable length O 225ft

1 = cable length < 225ft

17 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Register Name:

RCRn

Register Description:

Register Address:

Receiver Configuration Register

02h, 12h, 22h, 32h

Bit

7

ITU

0

6

RBIN

0

5

RCINV

0

4

RJA

0

3

RPD

0

2

RTS

1

RMON

0

RCVUD

0

Name

Default

Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations

on the RLCV pin and counted in the RCV register. It also controls whether or not excessive zero (EXZ) events are

flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth

consecutive zero (E3 mode) in a sequence of zeros.

0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and

counted. EXZ events are also flagged and counted.

1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3

mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not

flagged and counted in any mode.

Bit 6: Receiver Binary Interface Enable (RBIN)

0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is

disabled.

1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.

The B3ZS/HDB3 encoder is enabled.

Bit 5: Receiver Clock Invert (RCINV)

0 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.

1 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.

Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TJA = 1 takes precedence over RJA = 1.)

0 = remove jitter attenuator from the receiver path

1 = insert jitter attenuator into the receiver path

Bit 3: Receiver Power-Down Enable (RPD)

0 = enable the receiver

1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)

Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,

RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The RTS pin is inverted and logically

ORed with this bit.

0 = enable the receiver outputs

1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)

Bit 1: Receiver Monitor Preamp Enable (RMON)

0 = disable the monitor preamp

1 = enable the monitor preamp

Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the

RCVLn and RCVHn registers are loaded with the current code-violation count, and the internal code-violation

counter is cleared.

0J1 = Update RCV registers and clear internal code-violation counter

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Register Name:

SRn

Register Description:

Register Address:

Status Register

03h, 13h, 23h, 33h

Bit

7

6

5

TDM

0

4

PRBS

0

3

2

1

RLOL

1

0

RLOS

1

Name

Default

—

Bit 5: Transmitter Driver Monitor (TDM). This read-only status bit indicates the current state of the transmit driver

monitor.

0 = the transmitter is operating normally

1 = the transmitter has a fault condition

Bit 4: PRBS Detector Output (PRBS). This read-only status bit indicates the current state of the receiver’s PRBS

detector. See Table 4-G for the expected PRBS pattern.

0 = in sync with expected pattern

1 = out of sync, expected pattern not detected

Bit 1: Receiver Loss of Lock (RLOL). This read-only status bit indicates the current state of the receiver clock

recovery PLL.

0 = the receiver PLL is locked onto the incoming signal

1 = the receiver PLL is not locked onto the incoming signal

Bit 0: Receiver Loss of Signal (RLOS). This read-only status bit indicates the current state of the receiver loss-of-

signal detector.

0 = signal present

1 = loss of signal

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Register Name:

SRLn

Register Description:

Register Address:

Status Register Latched

04h, 14h, 24h, 34h

Bit

7

6

5

TDML

0

4

PRBSL

0

3

PBERL

0

2

RCVL

0

1

RLOLL

0

RLOSL

0

Name

Default

—

Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit

changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set

again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE

interrupt-enable bit is set to one. The interrupt is cleared when TDML is cleared or TDMIE is set to zero.

Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit

changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not

set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the

PRBSIE interrupt-enable bit is set to one. The interrupt is cleared when PRBSL is cleared or PRBSIE is set to zero.

Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is

in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not

set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the

PBERIE interrupt-enable bit is set to one. The interrupt is cleared when PBERL is cleared or PBERIE is set to zero.

Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is set to one when the RCV status bit

goes high. RCVL is cleared when the host processor writes a one to it and is not set again until RCV goes high

again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable bit is set to one.

The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.

Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status

bit changes state (low to high or high to low). RLOLL is cleared when the host processor writes a one to it and is

not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware interrupt to occur if the

RLOLIE interrupt-enable bit is set to one. The interrupt is cleared when RLOLL is cleared or RLOLIE is set to zero.

Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit

changes state (low to high or high to low). RLOSL is cleared when the host processor writes a one to it and is not

set again until RLOS changes state again. When RLOSL is set, it can cause a hardware interrupt to occur if the

RLOSIE interrupt-enable bit is set to one. The interrupt is cleared when RLOSL is cleared or RLOSIE is set to zero.

20 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Register Name:

SRIEn

Register Description:

Register Address:

Status Register Interrupt Enable

05h, 15h, 25h, 35h

Bit

7

6

5

TDMIE

0

4

PRBSIE

0

3

PBERIE

0

2

RCVIE

0

1

RLOLIE

0

RLOSIE

0

Name

Default

—

Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE)

0 = mask TDML interrupt

1 = enable TDML interrupt

Bit 4: PRBS Detector Interrupt Enable (PRBSIE)

0 = mask PRBSL interrupt

1 = enable PRBSL interrupt

Bit 3: PRBS Detector Bit-Error Interrupt Enable (PBERIE)

0 = mask PBERL interrupt

1 = enable PBERL interrupt

Bit 2: Receiver Line-Code Violation Interrupt Enable (RCVIE)

0 = mask RCVL interrupt

1 = enable RCVL interrupt

Bit 1: Receiver Loss-of-Clock Lock Interrupt Enable (RLOLIE)

0 = mask RLOLL interrupt

1 = enable RLOLL interrupt

Bit 0: Receiver Loss-of-Signal Interrupt Enable (RLOSIE)

0 = mask RLOSL interrupt

1 = enable RLOSL interrupt

Register Name:

RCVLn

Register Description:

Register Address:

Receiver Code-Violation Count Register (Low Byte)

06h, 16h, 26h, 36h

Bit

7

RCV[7]

0

6

RCV[6]

0

5

RCV[5]

0

4

RCV[4]

0

3

RCV[3]

0

2

RCV[2]

0

1

RCV[1]

0

RCV[0]

0

Name

Default

Register Name:

RCVHn

Register Description:

Register Address:

Receiver Code-Violation Count Register (High Byte)

07h, 17h, 27h, 37h

Bit

7

RCV[15]

0

6

RCV[14]

0

5

RCV[13]

0

4

RCV[12]

0

3

RCV[11]

0

2

RCV[10]

0

1

RCV[9]

0

RCV[8]

0

Name

Default

Bits 15 to 0: Receiver Code-Violation Counter Register (RCV[15:0]). The RCV registers form a 16-bit register

for reading the line-code violation counter value. The registers are updated with the line-code violation counter

value when the RCVUD control bit is toggled low to high. After the RCV registers are updated, the line-code

violation counter is cleared. The counter operates in two modes, depending on the setting of the ITU bit in the RCR

register. See the RCR register description for details about the ITU control bit.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

6. RECEIVER

Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the

receiver interfaces to the incoming coaxial cable (75ꢀ) through a 1:2 step-up transformer. Figure 1-1 shows the

arrangement of the transformer and other recommended interface components. Table 11-A specifies the required

characteristics of the transformer. The receiver expects the incoming signal to be in B3ZS- or HDB3-coded AMI

format.

Optional Preamp. The receiver can be used in monitoring applications, which typically have series resistors with a

resistive loss of approximately 20dB. When the RMON input pin is high, the receiver compensates for this resistive

loss by applying approximately 14dB of flat gain to the incoming signal before sending the signal to the

AGC/equalizer block where additional flat gain is applied as needed.

Automatic Gain Control (AGC) and Adaptive Equalizer. The AGC circuitry applies flat (frequency independent)

gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission

power. Since the incoming signal also experiences frequency-dependent losses as it passes through the coaxial

cable, the adaptive equalizer circuitry applies frequency-dependent gain to offset line losses and restore the signal.

The AGC/equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to

380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent).

The AGC and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and

pulse shape to the clock and data recovery block. The AGC/equalizer block automatically handles direct (0 meters)

monitoring of the transmitter output signal.

Clock and Data Recovery (CDR). The CDR block takes the amplified, equalized signal from the AGC/equalizer

block and produces separate clock, positive data, and negative data signals. The CDR requires a master clock. If

the signal on the appropriate MCLK pin is toggling, the LIU selects the MCLK signal as its master clock. If the

appropriate MCLK pin is wired high, the LIU uses the signal on the TCLK pin as the master clock. The appropriate

MCLK is selected based on the settings of the E3M and STS mode pins or register bits.

The receiver locks onto the incoming signal using a clock recovery PLL. The status of the PLL lock is indicated in

the RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and MCLK

frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state of the

RLOL status bit can cause an interrupt on the INT pin if enabled to do so by the RLOLIE interrupt-enable bit. Note

that if MCLK is not present, or MCLK is high and TCLK is not present, RLOL is not set.

Loss-of-Signal (LOS) Detector. The receiver contains analog and digital LOS detectors. The analog LOS detector

resides in the AGC/equalizer block. If the incoming signal level is less than a signal level approximately 24dB below

nominal, analog LOS (ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs

the AGC/equalizer mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital

LOS (DLOS), which is indicated by the RLOS pin and the RLOS status bit. ALOS clears when the incoming signal

level is greater than or equal to a signal level approximately 18dB below nominal.

The digital LOS detector declares DLOS when it detects 175 M75 consecutive zeros in the recovered data stream.

When DLOS occurs, the receiver asserts the RLOS pin (hardware mode) or the RLOS status bit (CPU bus mode).

DLOS is cleared when there are no EXZ occurrences over a span of 175 M75 clock periods. An EXZ occurrence is

defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in

the E3 mode. The RLOS pin goes inactive (high) when the DLOS condition is cleared. In CPU bus mode, a change

of the RLOS status bit can cause an interrupt on the INT pin if enabled to do so by the RLOSIE interrupt-enable bit.

The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which

asserts RLOS when it counts 175 M75 consecutive zeros coming out of the CDR block and clears RLOS when it

counts 175 M75 consecutive pulse intervals without excessive zero occurrences.

The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the

DLOS detector, as follows:

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

For E3 RLOS Assertion:

1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal

level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block.

(24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.)

2) The DLOS detector counts 175 M75 consecutive zeros coming out of the CDR block and asserts RLOS. (175

M75 meets the 10 ? N ? 255 pulse-interval duration requirement of G.775.)

For E3 RLOS Clear:

1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a

signal level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in

the “tolerance range” of G.775, where LOS may or may not be declared.)

2) The DLOS detector counts 175 M75 consecutive pulse intervals without EXZ occurrences and deasserts

RLOS. (175 M75 meets the 10 ? N ? 255 pulse-interval duration requirement of G.775.)

The DLOS detector supports the requirements of ANSI T1.231 for STS-1 LOS defects. At STS-1 rates, the time

required for the DLOS detector to count 175 M75 consecutive zeros falls in the range of 2.3? T? 100ꢁs required by

ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 175 M75

consecutive pulse intervals with no excessive zeros is less than the 125ꢁs–250ꢁs period required by ANSI T1.231

for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software.

During LOS, the RCLK output pin is derived from the LIU’s master clock. The ALOS detector has a longer time

constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector activates first

(asserting the RLOS pin or bit), followed by the ALOS detector. When a signal is restored, the DLOS detector does

not get a valid signal that it can qualify for no EXZ occurrences until the ALOS detector has seen the signal rise

above a signal level approximately 18dB below nominal.

Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in either binary or

bipolar format. To select the bipolar interface format, pull the RBIN pin low (hardware mode) or clear the RBIN

configuration bit (CPU bus mode). In bipolar format, the B3ZS/HDB3 decoder is disabled and the recovered data is

buffered and output on the RPOS and RNEG outputs. Received positive-polarity pulses are indicated by RPOS =

1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format, the receiver simply passes

on the received data and does not check it for BPV or EXZ occurrences.

To select the binary interface format, pull the RBIN pin high (hardware mode) or set the RBIN configuration bit

(CPU bus mode). In binary format, the B3ZS/HBD3 decoder is enabled, and the recovered data is decoded and

output as a binary value on the RDAT pin. Code violations are flagged on the RLCV pin. In the discussion that

follows, a valid pulse that conforms to the AMI rule is denoted as B. A BPV pulse that violates the AMI rule is

denoted as V.

In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where the data

on RDAT causes ones of the following code violations:

CꢀHardware mode or ITU bit set to 0

–

A BPV immediately preceded by a valid pulse (B, V).

A BPV with the same polarity as the last BPV.

The third zero in an EXZ occurrence.

CꢀITU bit set to 1

–

A BPV immediately preceded by a valid pulse (B, V).

A BPV with the same polarity as the last BPV.

In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT

causes one of the following code violations:

CꢀHardware mode or ITU bit set to 0

–

A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).

A BPV with the same polarity as the last BPV.

The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

CꢀITU bit set to 1

A BPV with the same polarity as the last BPV.

–

When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last

BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.

To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.

Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on

these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit

(CPU bus mode).

The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundant-

LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed

together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,

assert the RTS pin or the RTS configuration bit.

Receive Line-Code Violation Counter. The line-code violation counter is always enabled regardless of the

settings of the RBIN pin or the RBIN configuration bit. The receiver has an internal 16-bit saturating counter and a

16-bit latch, which the CPU can read as registers RCVH and RCVL. The value of the internal counter is latched into

the RCVH/RCVL register and cleared when the receive code-violation counter update bit, RCVUD, is changed from

a zero to a one. The RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV

increment pulse and an update pulse in the same clock period, the counter is preset to a one rather than cleared

so that the LCV is not missed. The counter is incremented when the RLCV pin flags a code violation as described

in the Framer Interface Format and the B3ZS/HDB3 Decoder section. The counter saturates at 65,535 (0FFFFh)

and does not roll over.

Receiver Power-Down. To minimize power consumption when the receiver is not being used, assert the RPD

configuration bit (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV

pins are tri-stated. In addition, the RXP and RXN pins become high impedance.

Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable

telecommunication standards in Table 1-A. See Figure 6-1.

Figure 6-1. Receiver Jitter Tolerance

15

STS-1 GR253

DS3 GR-499 Cat II

DS3 GR-499 Cat I

10

5

10

DS315x JITTER TOLERANCE

1.5

E3 G.823

1.0

0.1

0.3

0.15

0.1

30

300

669

2.3k

22.3k

60k

300k 800k

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

7. TRANSMITTER

Transmit Clock. The clock applied at the TCLK input clocks in data on the TPOS/TDAT and TNEG pins. If the jitter

attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock and must be

transmission quality (i.e., M20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the

transmit path, the signal on TCLK can be jittery and/or periodically gapped (not exceeding 8UI), but must still have

an average frequency within M20ppm of the nominal line rate. When enabled in the transmit path, the jitter

attenuator generates the transmit line clock from the signal applied on the appropriate MCLK pin. The signal on the

MCLK pin must, therefore, be a transmission-quality clock (M20ppm frequency accuracy and low jitter).

The polarity of TCLK can be inverted to support glueless interfacing to a variety of neighboring components.

Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample data on the

falling edge of TCLK, pull the TCINV pin high (hardware mode) or set the TCINV configuration bit (CPU bus mode).

Framer Interface Format and the B3ZS/HDB3 Encoder. Data to be transmitted can be input in either binary or

bipolar format. To select the binary interface format, pull the TBIN pin high (hardware mode) or set the TBIN

configuration bit (CPU bus mode). In binary format, the B3ZS/HBD3 encoder is enabled, and the data to be

transmitted is sampled on the TDAT pin. The TNEG pin is ignored in binary interface mode and should be wired

low. In DS3 and STS-1 modes, the B3ZS/HDB3 encoder operates in the B3ZS mode. In E3 mode the encoder

operates in HDB3 mode.

To select the bipolar interface format, pull the TBIN pin low (hardware mode) or clear the TBIN configuration bit

(CPU bus mode). In bipolar format, the B3ZS/HDB3 encoder is disabled and the data to be transmitted is sampled

on the TPOS and TNEG pins. Positive-polarity pulses are indicated by TPOS = 1, while negative-polarity pulses

are indicated by TNEG = 1.

Pattern Generation. The transmitter can generate several patterns internally, including unframed all ones (E3

AIS), 100100…, and DS3 AIS. See Figure 7-2 for the structure of the DS3 AIS signal. The TDSA and TDSB input

pins (hardware mode) or the TDSA and TDSB control bits (CPU bus mode) are used to select these patterns.

Table 4-F indicates the possible selections.

Waveshaping, Line Build-Out, Line Driver. The waveshaping block converts the transmit clock, positive data,

and negative data signals into a single AMI signal with the waveshape required for interfacing to DS3/E3/STS-1

lines. Table 7-A through Table 7-E and Figure 7-1 show the waveform template specifications and test parameters.

Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length

from 0 to 450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater,

the TLBO pin (hardware mode) or the TLBO configuration bit (CPU bus mode) should be low. When TLBO is low,

output pulses are driven onto the coaxial cable without any preattenuation. For cable lengths less than 225ft, TLBO

should be high to enable the LBO circuitry. When TLBO is high, pulses are preattenuated by the LBO circuitry

before being driven onto the coaxial cable. The LBO circuitry provides attenuation that mimics the attenuation of

225ft of coaxial cable.

The transmitter line driver can be disabled and the TXP and TXN outputs tri-stated by asserting the TTS input or

the TTS configuration bit. Powering down the transmitter through the TPD configuration bit (CPU bus mode) also

tri-states the TXP and TXN outputs.

Interfacing to the Line. The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75ꢀ) through a

2:1 step-down transformer connected to the TXP and TXN pins. Figure 1-1 shows the arrangement of the

transformer and other recommended interface components. Table 11-A specifies the required characteristics of the

transformer.

Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the TDM output

(hardware mode or CPU bus mode) or sets the TDM status bit and optionally activates the INT output (CPU bus

mode). When the transmitter is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to

be faulty when the transmitter outputs see a load of less than ~25ꢀ.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Transmitter Power-Down. To minimize power consumption when the transmitter is not being used, assert the

TPD configuration bit (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put

in a high-impedance state and the transmit amplifiers are powered down.

Transmitter Jitter Generation (Intrinsic). The transmitter meets the jitter generation requirements of all

applicable standards, with or without the jitter attenuator enabled.

Transmitter Jitter Transfer. Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter

through unchanged. With the jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer

requirements of all applicable telecommunication standards in Table 1-A. See Figure 9-1.

Table 7-A. DS3 Waveform Template

TIME (IN UNIT INTERVALS)

NORMALIZED AMPLITUDE EQUATION

UPPER CURVE

0.03

-0.85 ? T ? -0.68

-0.68 ? T ? +0.36

0.36 ? T ? 1.4

0.5 {1 + sin[(ꢁ / 2)(1 + T / 0.34)]} + 0.03

0.08 + 0.407e^{-1.84(T - 0.36)}

LOWER CURVE

-0.03

0.5 {1 + sin[(ꢁ / 2)(1 + T / 0.18)]} - 0.03

-0.03

-0.85 ? T ? -0.36

-0.36 ? T ? +0.36

0.36 ? T ? 1.4

Governing Specifications: ANSI T1.102 and Bellcore GR-499.

Table 7-B. DS3 Waveform Test Parameters and Limits

PARAMETER

SPECIFICATION

Rate

44.736Mbps (M20ppm)

Line Code

B3ZS

Transmission Medium

Test Measurement Point

Test Termination

Coaxial cable (AT&T 734A or equivalent)

At the end of 0 to 450ft of coaxial cable

75ꢀ (M1%) resistive

Pulse Amplitude

Between 0.36V and 0.85V

An isolated pulse (preceded by two zeros and

followed by one or more zeros) falls within the

curves listed in Table 7-A.

Pulse Shape

Unframed All-Ones Power Level at

22.368MHz

Between -1.8dBm and +5.7dBm

Unframed All-Ones Power Level at

44.736MHz

At least 20dB less than the power measured at

22.368MHz

Ratio of positive and negative pulses must be

between 0.90 and 1.10.

Pulse Imbalance of Isolated Pulses

Table 7-C. STS-1 Waveform Template

TIME (IN UNIT INTERVALS)

NORMALIZED AMPLITUDE EQUATIONS

UPPER CURVE

0.03

-0.85 ? T ? -0.68

-0.68 ? T ? +0.26

0.26 ? T ? 1.4

0.5 {1 + sin[(ꢁ / 2)(1 + T / 0.34)]} + 0.03

0.1 + 0.61e^{-2.4(T - 0.26)}

LOWER CURVE

-0.03

0.5 {1 + sin[(ꢁ / 2)(1 + T / 0.18)]} - 0.03

-0.03

-0.85 ? T ? -0.36

-0.36 ? T ? +0.36

0.36 ? T ? 1.4

Governing Specifications: Bellcore GR-253 and Bellcore GR-499 and ANSI T1.102.

26 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 7-D. STS-1 Waveform Test Parameters and Limits

PARAMETER

SPECIFICATION

Rate

51.840Mbps (M20ppm)

Line Code

B3ZS

Transmission Medium

Test Measurement Point

Test Termination

Coaxial cable (AT&T 734A or equivalent)

At the end of 0 to 450ft of coaxial cable

75ꢀ (M1%) resistive

Pulse Amplitude

0.800V nominal (not covered in specs)

An isolated pulse (preceded by two zeros and followed by one

or more zeros) falls within the curved listed in Table 7-C.

Between -1.8dBm and +5.7dBm

Pulse Shape

Unframed All-Ones Power Level at 25.92MHz

Unframed All-Ones Power Level at 51.84MHz

At least 20dB less than the power measured at 25.92MHz.

Table 7-E. E3 Waveform Test Parameters and Limits

PARAMETER

SPECIFICATION

Rate

34.368Mbps (M20ppm)

Line Code

HDB3

Transmission Medium

Test Measurement Point

Test Termination

Pulse Amplitude

Coaxial cable (AT&T 734A or equivalent)

At the transmitter

75ꢀ (M1%) resistive

1.0V (nominal)

An isolated pulse (preceded by two zeros and followed by one

or more zeros) falls within the template shown in Figure 7-1.

Pulse Shape

Ratio of the Amplitudes of Positive and Negative

Pulses at the Center of the Pulse Interval

Ratio of the Widths of Positive and Negative

Pulses at the Nominal Half Amplitude

0.95 to 1.05

Figure 7-1. E3 Waveform Template

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

17

8.65

G.703

E3

TEMPLATE

12.1

24.5

29.1

-0.1

-0.2

TIME (ns)

27 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 7-2. DS3 AIS Structure

M1 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

X1

(1)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M2 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

X2

(1)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M3 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

P1

(0)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M4 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

P2

(0)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M5 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

M1

(0)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M6 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

M2

(1)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

M7 Subframe

84

Info C1 Info F2

Bits (1) Bits

84

C2 Info

(0) Bits

84

M3

(0)

Info F1

Info

F3

Info C3 Info F4

Info

(0) Bits (0) Bits

(0) Bits

(0) Bits (1) Bits

Note 1: X1 is transmitted first.

Note 2: The 84 info bits contain the repetitive sequence 1010…, where the first 1 in the sequence immediately follows each X, P, F, C, or M bit.

8. DIAGNOSTICS

PRBS Generator and Detector. Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector

circuitry for physical layer testing. The device generates and detects unframed 2¹⁵- 1 (DS3 or STS-1) or 2²³- 1

PRBS, according to the ITU O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high

(hardware mode) or set configuration bits TDSA and TDSB (CPU bus mode). As Table 4-F shows, the PRBS

generator automatically generates 2¹⁵- 1 for DS3 and STS-1 modes and 2²³- 1 for E3 mode.

The PRBS detector, which is always enabled (Table 4-G), reports its status through the PRBS output pin (hardware

and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out

of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS

pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See Figure 8-1 and Figure

8-2 for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization and

set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit can cause an

interrupt on the INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an

interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detector also declares sync in the presence of

an incoming all-ones pattern.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Loopbacks. Each LIU has three internal loopbacks. See Figure 3-1 and Figure 3-2. The LLB and RLB pins

(hardware mode) or LLB and RLB control bits (CPU bus mode) enable these loopbacks. When LLB = RLB = 0,

loopbacks are disabled. Setting RLB = 1 with LLB = 0 enables remote loopback, which loops recovered clock and

data back through the LIU transmitter. During remote loopback, recovered clock and data are output on RCLK,

RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and TNEG pins are ignored. Setting LLB = 1 with RLB = 0

enables analog local loopback, which loops the outgoing transmit signal back to the receiver’s analog front end.

Setting LLB = RLB = 1 enables digital local loopback, which loops digital transmit clock and data back to the

receiver’s digital circuitry, including the LOS detector, the B3ZS/HDB3 decoder, and the PRBS detector. When

either of the local loopbacks is enabled, the transmit signal is output normally on TXP/TXN, but the received signal

on RXP/RXN is ignored.

Figure 8-1. PRBS Output with Normal RCLK Operation

RCINV = 0

RCLK

PRBS

PRBS DETECTOR IS IN SYNC; THE

PRBS PIN PULSES HIGH FOR EACH BIT

ERROR DETECTED

PRBS DETECTOR

IS NOT IN SYNC

Figure 8-2. PRBS Output with Inverted RCLK Operation

RCINV = 1

RCLK

PRBS

PRBS DETECTOR

IS NOT IN SYNC

PRBS DETECTOR IS IN SYNC; THE

PRBS PIN PULSES HIGH FOR EACH BIT

ERROR DETECTED

9. JITTER ATTENUATOR

Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can

be disabled. The TJA and RJA pins (hardware mode) or the TJA and RJA control bits (CPU bus mode) specify how

the jitter attenuator is used. Setting TJA = RJA = 0 disables the jitter attenuator. To use the jitter attenuator in the

receive path, set RJA = 1 (with TJA = 0). To use it in the transmit path, set TJA = 1. Figure 9-1 shows the minimum

jitter attenuation for the device when the jitter attenuator is enabled. Figure 9-1 also shows the receive jitter transfer

when the jitter attenuator is disabled.

The jitter attenuator consists of a narrowband PLL to retime the selected clock, a 16 x 2-bit FIFO to buffer the

associated data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very

large jitter amplitudes.

The jitter attenuator requires a transmission-quality master clock (i.e., M20ppm frequency accuracy and low jitter).

When enabled in the receive path, the JA can obtain its master clock from the appropriate MCLK pin or the TCLK

pin. If the signal on the MCLK pin is toggling, the JA uses the signal on the MCLK pin as its master clock. If the

MCLK pin is high, the JA uses the signal on the TCLK pin as its master clock. When enabled in the transmit path,

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

the JA must take its master clock from the MCLK pin. The clock and data recovery block also uses the selected

master clock.

The JA has a loop bandwidth of master_clock / 2,058,874 (see corner frequencies in Figure 9-1). The JA

attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower

frequencies to pass through relatively unaffected.

Figure 9-1. Jitter Attenuation/Jitter Transfer

21.7Hz (DS3)

16.7Hz (E3)

27Hz

40Hz

25.2Hz (STS-1)

1k

>150k

40k 59.6k

0

DS3 [GR-499 (1995)]

CATEGORY I

DS3 [GR-253 (1999)]

CATEGORY I

DS315x TYPICAL RECEIVER

JITTER TRANSFER WITH JITTER

ATTENUATOR DISABLED

STS-1 [GR-253

(1999)]

CATEGORY II

-10

-20

E3 [TBR24 (1997)]

DS315x

DS3/E3/STS-1

MINIMUM

DS3 [GR-499 (1999)]

CATEGORY II

JITTER

ATTENUATION

WITH JITTER

ATTENUATOR

ENABLED

-30

10k

10

100

1k

100k

1M

FREQUENCY (Hz)

10. RESET LOGIC

There are four sources for reset: an internal power-on reset (POR) circuit, the reset pin RST, the JTAG reset pin

JTRST, and the RST bit in each LIU’s global configuration register (GCR). The chip is divided into three zones for

reset: the digital logic, the analog circuits, and the JTAG logic. The digital logic includes the status and control

registers, the B3ZS/HDB3 encoder and decoder, the PRBS generator and detector, and the LOS detect logic. The

analog circuits include clock and data recovery, jitter attenuator, and transmit waveform generation. The JTAG

logic consists of the common boundary scan controller and the boundary scan cells at each pin.

The POR circuit resets the digital logic, analog circuits, and JTAG logic zones. The RST pin resets the digital logic

and the analog circuits but not the JTAG logic. The JTRST pin resets only the JTAG logic. Each LIU’s RST register

bit resets the digital logic for that LIU, including resetting the LIU’s registers to the default state (except for the RST

bit).

The POR signal and RST pin require an active master clock source for the LIU to properly reset.

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11. TRANSFORMERS

Table 11-A. Transformer Characteristics

PARAMETER

VALUE

Turns Ratio

1:2ct M2%

0.250MHz to 500MHz (typ)

19ꢂH (min)

Bandwidth 75ꢀ

Primary Inductance

Leakage Inductance

Interwinding Capacitance

Isolation Voltage

0.150ꢂH (max)

10pF (max)

1500V_RMS(min)

Table 11-B. Recommended Transformers

NO. OF

PIN-PACKAGE/

SCHEMATIC

MANUFACTURER

PART

TEMP RANGE

TRANSFORMERS

6 SMT

LS-1/C

6 Thru-Hole

LC-1/C

32 SMT

YB/1

1

PE-65968

PE-65969

0°C to +70°C

Pulse Engineering

1

8

1

T3049

6 SMT

TG07-0206NS

TD07-0206NE

SMD/B

6 DIP

Halo Electronics

DIP/B

Note: Table subject to change. Industrial temperature range and other multiples (dual, quad) are also available. Contact the manufacturers for

details at www.pulseeng.com and www.haloelectronics.com.

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12. JTAG TEST ACCESS PORT AND BOUNDARY SCAN

12.1 JTAG Description

The DS315x LIUs support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional

public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 12-1 features a block diagram. The LIUs

contain the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and

Boundary Scan Architecture:

Test Access Port (TAP)

TAP Controller

Bypass Register

Boundary Scan Register

Device Identification Register

Instruction Register

The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins

can be found in Section 4. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-

1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

Figure 12-1. JTAG Block Diagram

BOUNDARY

SCAN

REGISTER

IDENTIFICATION

REGISTER

BYPASS

REGISTER

INSTRUCTION

REGISTER

SELECT

TEST ACCESS PORT

TRI-STATE

CONTROLLER

10k

JTDI

JTMS

JTCLK

JTDO

JTRST

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12.2 JTAG TAP Controller State Machine Description

This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state

machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in Figure

12-2 are described in the following pages.

Figure 12-2. JTAG TAP Controller State Machine

Test-Logic-Reset

1

0

1

Select

1

Run-Test/Idle

DR-Scan

IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

0

1

0

1

Exit1- DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction

register contains the IDCODE instruction. All system logic on the device operates normally.

Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test

registers remain idle.

Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the

controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-

IR-SCAN state.

Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register

remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or

to the Exit1-DR state if JTMS is high.

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Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts

data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current

instruction is not placed in the serial path, it maintains its previous state.

Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,

which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR

state.

Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current

instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on

JTCLK with JTMS high puts the controller in the Exit2-DR state.

Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state

and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR

state.

Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of

the test registers into the data output latches. This prevents changes at the parallel output because of changes in

the shift register. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS

high, the controller enters the Select-DR-Scan state.

Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this

state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan

sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the

Test-Logic-Reset state.

Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This

value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the

Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.

Shift-IR. In this state, the instruction register’s shift register is connected between JTDI and JTDO and shifts data

one stage for every rising edge of JTCLK toward the serial output. The parallel register and the test registers

remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state.

A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state, while moving data one stage

through the instruction shift register.

Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the

rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.

Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts

the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge

on JTCLK.

Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops

back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.

Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling

edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A

rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller

enters the Select-DR-Scan state.

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12.3 JTAG Instruction Register and Instructions

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the

TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in

the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A

rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-

IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction

parallel output. Table 12-A shows the instructions supported by the DS315x and their respective operational binary

codes.

Table 12-A. JTAG Instruction Codes

INSTRUCTIONS

SAMPLE/PRELOAD

BYPASS

SELECTED REGISTER

Boundary Scan

Bypass

INSTRUCTION CODES

010

111

000

011

100

001

EXTEST

Boundary Scan

Bypass

CLAMP

HIGHZ

Bypass

IDCODE

Device Identification

SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This

instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register

without interfering with the device’s normal operation by using the Capture-DR state. SAMPLE/PRELOAD also

allows the DS315x to shift data into the boundary scan register through JTDI using the Shift-DR state.

EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in

the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs

of the digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The

Capture-DR samples all digital inputs into the boundary scan register.

BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO

through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s

normal operation.

IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test

register is selected. The device identification code is loaded into the identification register on the rising edge of

JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially

through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel

output.

HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI

and JTDO.

CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass

register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.

Table 12-B. JTAG ID Code

PART

REVISION

DEVICE CODE

MANUFACTURER CODE

REQUIRED

DS3154

DS3153

DS3152

DS3151

Consult factory

0000000000110011

0000000000110010

0000000000110000

0000000000100000

00010100001

1

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12.4 JTAG Test Registers

IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An

optional test register, the identification register, has been included in the device design. It is used with the IDCODE

instruction and the Test-Logic-Reset state of the TAP controller.

Bypass Register. This single 1-bit shift register, used with the BYPASS, CLAMP, and HIGHZ instructions,

provides a short path between JTDI and JTDO.

Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells

and digital I/O cells. DS315x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm.

Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.

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13. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Lead with Respect to V_SS(except V_DD)

Supply Voltage Range (V_DD) with Respect to V_SS

Ambient Operating Temperature Range

Junction Operating Temperature Range

Storage Temperature Range

-0.3V to +5.5V

-0.3V to +3.63V

-40°C to +85°C

-40°C to +125°C

-55°C to +125°C

Soldering Temperature

See IPC/JEDEC J-STD-020A Specification

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is

not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. Ambient operating temperature range

when device is mounted on a four-layer JEDEC test board with no airflow.

Note: The typical values listed in Tables 13-A through 13-I are not production tested.

Table 13-A. Recommended DC Operating Conditions

(T_A= -40°C to +85°C)

PARAMETER

SYMBOL

V_IH

CONDITIONS

MIN

2.0

TYP

MAX

5.5

UNITS

Logic 1

Logic 0

V

V_IL

-0.3

+0.8

3.465

Supply Voltage

V_DD

3.135

3.3

Table 13-B. DC Characteristics

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DS3151

DS3152

DS3153

DS3154

DS3151

DS3152

DS3153

DS3154

100

200

300

400

80

150

225

300

Supply Current (Note 1)

I_DD

mA

Supply Current, Transmitters Tri-Stated

I_DDTTS

mA

(All TTSn Low) (Note 2)

Power-Down Current (All TPD, RPD

Control Bits High)

I_DDPD

DS315x (Note 2)

55

7

70

mA

pF

Lead Capacitance

C_IO

I_IL

Input Leakage

(Note 3)

-50

-10

2.4

0

+10

V_DD

0.4

ꢁA

V

Output Leakage (when High-Z)

Output Voltage (I_O= -4.0mA)

Output Voltage (I_O= +4.0mA)

I_LO

V_OH

V_OL

V

Note 1: TCLKn = STMCLK = 51.84MHz; TXPn/TXNn driving all ones into 75ꢀ resistive loads; analog loopback enabled; all other inputs at V_DD

or grounded; all other outputs open.

Note 2: TCLKn = STMCLK = 51.84MHz; other inputs at V_DDor grounded; digital outputs left open circuited.

Note 3: 0V < V_IN< V_DD

.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 13-C. Framer Interface Timing

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.) (Figure 13-1 and Figure 13-2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

22.4

29.1

19.3

50

MAX

UNITS

(Note 4)

(Note 5)

(Note 6)

RCLK/TCLK Clock Period

t1

ns

RCLK Duty Cycle

TCLK Duty Cycle

MCLK Duty Cycle

t2/t1, t3/t1

(Notes 7, 8)

45

30

55

70

%

(Note 8)

TPOS/TDAT, TNEG to TCLK Setup

Time

t4

t5

t6

(Notes 8, 9)

2

ns

TPOS/TDAT, TNEG Hold Time

(Notes 8, 9)

RCLK to RPOS/RDAT, RNEG/RLCV,

and PRBS Value Change

(Notes 7, 8, 10)

6

5

RCLK Rise and Fall Time

TCLK Rise and Fall Time

t7

t8

(Notes 8, 11)

(Notes 8, 12)

5

ns

Note 4: DS3 mode.

Note 5: E3 mode.

Note 6: STS-1 mode.

Note 7: Outputs loaded with 25pF, measured at 50% threshold.

Note 8: Not tested during production test.

Note 9: When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG are

sampled on the falling edge of TCLK.

Note 10: When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and

RNEG/RLCV are updated on the rising edge of RCLK.

Note 11: Outputs loaded with 25pF, measured between V_OL(max) and V_OH(min).

Note 12: Measured between V_IL(max) and V_IH(min).

Figure 13-1. Transmitter Framer Interface Timing Diagram

t1

t2

t3

TCLK (NORMAL)

TCLK (INVERTED)

t8

t4

t5

TPOS/TDAT,

TNEG

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 13-2. Receiver Framer Interface Timing Diagram

t1

t2

t3

RCLK (NORMAL)

RCLK (INVERTED)

t6

t7

RPOS/RDAT,

RNEG/RLCV

Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.)

PARAMETER

MIN

TYP

1200

10

MAX

UNITS

Receive Sensitivity (Length of Cable)

900

ft

Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14)

Input Pulse Amplitude, RMON = 0 (Notes 14, 15)

Input Pulse Amplitude, RMON = 1 (Note 14, 15)

Analog LOS Declare, RMON = 0 (Note 16)

Analog LOS Clear, RMON = 0 (Note 16)

1000

200

-24

mVpk

dB

-17

-29

dB

Analog LOS Declare, RMON = 1 (Note 16)

Analog LOS Clear, RMON = 1 (Note 16)

-38

dB

Intrinsic Jitter Generation (Note 14)

0.03

UI_P-P

Table 13-E. Receiver Input Characteristics—E3 Mode

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.)

PARAMETER

MIN

TYP

1200

12

MAX

UNITS

Receive Sensitivity (Length of Cable)

900

ft

Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14)

Input Pulse Amplitude, RMON = 0 (Notes 14, 15)

Input Pulse Amplitude, RMON = 1 (Notes 14, 15)

Analog LOS Declare, RMON = 0 (Note 16)

Analog LOS Clear, RMON = 0 (Note 16)

Analog LOS Declare, RMON = 1 (Note 16)

Analog LOS Clear, RMON = 1 (Note 16)

Intrinsic Jitter Generation (Note 14)

1300

260

-24

mVpk

dB

-17

-29

dB

-38

dB

0.03

UI_P-P

Note 13: An interfering signal (2¹⁵- 1 PRBS for DS3/STS-1, 2²³- 1 PRBS for E3, B3ZS/HDB3 encoded, compliant waveshape, nominal bit rate)

is added to the wanted signal. The combined signal is passed through 0 to 900ft of coaxial cable and presented to the DS3154

receiver. This spec indicates the lowest signal-to-noise ratio that results in a bit error ratio <10^-9.

Note 14: Not tested during production test.

Note 15: Measured on the line side (i.e., the BNC connector side) of the 1:2 receive transformer (Figure 1-1). During measurement, incoming

data traffic is unframed 2¹⁵- 1 PRBS for DS3/STS-1 and unframed 2²³- 1 PRBS for E3.

Note 16: With respect to nominal 800mVpk signal for DS3/STS-1 and nominal 1000mVpk signal for E3.

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.)

PARAMETER

MIN

700

520

700

520

0.9

TYP

800

700

800

700

MAX

900

800

1100

850

1.1

UNITS

mVpk

DS3 Output Pulse Amplitude, TLBO = 0 (Note 17)

DS3 Output Pulse Amplitude, TLBO = 1 (Note 17)

STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17)

STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17)

Ratio of Positive and Negative Pulse-Peak Amplitudes

DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth

-1.8

+5.7

dBm

DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at

-20

dB

22.368MHz, 3kHz Bandwidth

Intrinsic Jitter Generation (Note 18)

0.02

0.05

UI_P-P

Table 13-G. Transmitter Output Characteristics—E3 Mode

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.)

PARAMETER

MIN

TYP

MAX

UNITS

mVpk

ns

Output Pulse Amplitude (Note 17)

900

1000 1100

14.55

Pulse Width

Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses)

Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude)

Intrinsic Jitter Generation (Note 18)

0.95

1.05

0.02

0.05

UI_P-P

Note 17: Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer (Figure 1-1).

Note 18: Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during

production test.

Table 13-H. CPU Bus Timing

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.) (Figure 13-3 and Figure 13-4)

PARAMETER

SYMBOL

MIN

0

TYP

MAX

UNITS

ns

t1

t2

t3

t4

Setup Time for A[5:0] Valid to CS Active (Notes 19, 20)

Setup Time for CS Active to RD, WR, or DS Active

Delay Time from RD or DS Active to D[7:0] Valid

Hold Time from RD or WR or DS Inactive to CS Inactive

Delay from CS or RD or DS Inactive to D[7:0] Invalid or Tri-State

(Note 21)

0

ns

65

20

ns

0

2

t5

ns

t6

t7

65

10

2

ns

Wait Time from WR or DS Active to Latch D[7:0]

D[7:0] Setup Time to WR or DS Inactive

D[7:0] Hold Time from WR or DS Inactive

A[5:0] Hold Time from WR or RD or DS Inactive

RD, WR, or DS Inactive Time

t8

t9

5

t10

t11

t12

t13

75

10

30

Muxed Address Valid to ALE Falling (Note 22)

Muxed Address Hold Time (Note 22)

ALE Pulse Width (Note 22)

Setup Time for ALE High or Muxed Address Valid to CS Active

t14

0

ns

(Note 22)

Note 19: D[7:0] loaded with 50pF when tested as outputs.

Note 20: If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the

largest TCLK gap.

Note 21: Not tested during production test.

Note 22: In nonmultiplexed bus applications (Figure 13-3), ALE should be wired high. In multiplexed bus applications (Figure 13-4), A[5:0]

should be wired to D[5:0] and the falling edge of ALE latches the address.

40 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)

INTEL READ CYCLE

t9

ADDRESS VALID

A[5:0]

D[7:0]

WR

DATA VALID

t5

t1

CS

RD

t2

t3

t4

t10

INTEL WRITE CYCLE

t9

ADDRESS VALID

A[5:0]

D[7:0]

t7

t8

RD

t1

CS

t2

t6

t4

t10

WR

41 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)(continued)

MOTOROLA READ CYCLE

t9

A[5:0]

D[7:0]

ADDRESS VALID

DATA VALID

t5

R/W

t1

CS

DS

t2

t3

t4

t10

MOTOROLA WRITE CYCLE

t9

ADDRESS VALID

A[5:0]

D[7:0]

t7

t8

R/W

t1

CS

DS

t2

t6

t4

t10

42 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 13-4. CPU Bus Timing Diagram (Multiplexed)

INTEL READ CYCLE

t13

t12

ALE

t11

ADDRESS

VALID

A[5:0]

D[7:0]

t14

DATA VALID

t5

WR

CS

RD

t2

t3

t4

t10

NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.

INTEL WRITE CYCLE

t13

t12

ALE

A[5:0]

D[7:0]

t11

ADDRESS

VALID

t14

t7

t8

RD

CS

t6

t4

t2

t10

WR

NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.

43 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 13-4. CPU Bus Timing Diagram (Multiplexed) (continued)

MOTOROLA READ CYCLE

t13

t12

ALE

t11

ADDRESS

A[5:0]

VALID

t14

D[7:0]

DATA VALID

t14

t5

R/W

CS

DS

t2

t3

t4

t10

NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.

MOTOROLA WRITE CYCLE

t13

ALE

t12

t11

ADDRESS

VALID

A[5:0]

t14

D[7:0]

t7

t8

R/W

CS

DS

t6

t2

t4

t10

NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.

44 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 13-I. JTAG Interface Timing

(V_DD= 3.3V M5%, T_A= -40°C to +85°C.) (Figure 13-5)

PARAMETER

JTCLK Clock Period

SYMBOL

MIN

TYP

1000

500

MAX

UNITS

ns

t1

t2/t3

t4

JTCLK Clock High/Low Time (Note 23)

JTCLK to JTDI, JTMS Setup Time

JTCLK to JTDI, JTMS Hold Time

JTCLK to JTDO Delay

50

2

ns

t5

ns

t6

50

ns

JTCLK to JTDO High-Z Delay (Note 24)

JTRST Width Low Time

t7

2

ns

t8

100

ns

Note 23: Clock can be stopped high or low.

Note 24: Not tested during production test.

Figure 13-5. JTAG Timing Diagram

t1

t2

t3

JTCLK

t4

t5

JTDI, JTMS, JTRST

t6

t7

JTDO

t8

JTRST

45 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

14. PIN ASSIGNMENTS

Table 14-A lists pin assignments sorted by signal name. Table 14-B lists pin assignments sorted by pin number.

DS3154 has all four LIUs. DS3153 has only LIUs 1, 2, and 3. DS3152 has only LIUs 1 and 2. DS3151 has only LIU

1. Figure 14-1 through Figure 14-8 show pinouts for the four devices in both hardware and CPU bus modes.

Table 14-A. Pin Assignments Sorted by Signal Name

HARDWARE

CPU BUS

NAME

MODE

LIU 1

LIU 2

LIU 3

LIU 4

A[0]

A[1]

A[2]

A[3]

A[4]

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

K6

L6

K7

L7

K8

L8

C7

B7

E3

F2

F3

G2

G3

H2

H3

J3

A[5]

ALE

CS

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

E3MCLK

E3Mn

HIZ

E12

F3

G10

C7

K6

J8

E9

C5

E4

H4

J4

HW

INT

JTCLK

JTDI

JTDO

JTMS

JTRST

LLBn

MOT

PRBSn

RBIN

RCINV

RCLKn

RD

D5

D4

B5

B1

L8

E11

A11

H2

M2

C6

L12

D9

J9

C1

K12

A10

M3

B6

RJAn

RLBn

RLOSn

B4

C5

A1

L9

K8

M12

D11

E10

A12

J2

H3

M1

46 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 14-A. Pin Assignments Sorted by Signal Name (continued)

HARDWARE

CPU

NAME

MODE

LIU 1

C3

C2

LIU 2

K10

K11

LIU 3

C10

B10

LIU 4

K3

L3

RNEGn

RPOSn

RST

Y

N

Y

N

Y

N

Y

N

Y

N

Y

H1

B2

A2

A3

L11

M11

M10

B11

B12

C12

L2

L1

K1

RTSn

RXNn

RXPn

STMCLK

STSn

T3MCLK

TBIN

TCINV

TCLKn

TDMn

TDSAn

TDSBn

TEST

M8

F2

G11

B7

L6

A5

D8

H9

E1

D3

G2

G3

H12

J10

F11

F10

A8

C9

B6

C6

M5

K4

L7

K7

J5

TJAn

C4

E3

D2

D1

E2

G1

F1

K9

D10

C8

B9

A9

B8

A6

A7

J3

K5

L4

M4

L5

TLBOn

TNEGn

TPOSn

TTSn

H10

J11

J12

H11

F12

G12

TXNn

TXPn

V_DD

M7

M6

D6, E5, E6, F4, F5, F6, G7, G8, G9, H7, H8, J7

D7, E7, E8, F7, F8, F9, G4, G5, G6, H5, H6, J6

B5

V_SS

WR

47 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Table 14-B. Pin Assignments Sorted by Pin Number

DS3154

DS3153

DS3152

DS3151

HARDWARE CPU BUS HARDWARE

CPU BUS HARDWARE CPU BUS HARDWARE CPU BUS

MODE

RLOS1

RXN1

RXP1

RMON1

T3MCLK

TXN3

TXP3

MODE

RLOS1

RXN1

RXP1

N.C.

MODE

RLOS1

RXN1

RXP1

RMON1

T3MCLK

TXN3

TXP3

MODE

RLOS1

RXN1

RXP1

N.C.

MODE

RLOS1

RXN1

RXP1

RMON1

T3MCLK

N.C.

MODE

RLOS1

RXN1

RXP1

N.C.

MODE

RLOS1

RXN1

RXP1

RMON1

T3MCLK

N.C.

MODE

RLOS1

RXN1

RXP1

N.C.

A1

A2

A3

A4

A5

T3MCLK

TXN3

TXP3

TCLK3

TPOS3

RCLK3

PRBS3

RLOS3

PRBS1

RTS1

N.C.

T3MCLK

TXN3

TXP3

TCLK3

TPOS3

RCLK3

PRBS3

RLOS3

PRBS1

RTS1

N.C.

T3MCLK

N.C.

T3MCLK

N.C.

A6

A7

N.C.

A8

TCLK3

TPOS3

RCLK3

PRBS3

RLOS3

PRBS1

RTS1

TCLK3

TPOS3

RCLK3

PRBS3

RLOS3

PRBS1

RTS1

N.C.

A9

N.C.

A10

A11

A12

B1

N.C.

PRBS1

RTS1

N.C.

PRBS1

RTS1

N.C.

PRBS1

RTS1

N.C.

PRBS1

RTS1

N.C.

B2

B3

N.C.

B4

RJA1

N.C.

RJA1

N.C.

RJA1

LLB1

N.C.

WR

RD

CS

RJA1

LLB1

N.C.

WR

RD

CS

B5

LLB1

WR

RD

CS

WR

B6

TDSA3

STS3

TTS3

TDSA3

STS3

TTS3

RD

CS

B7

N.C.

B8

N.C.

TTS3

TNEG3

RPOS3

RTS3

RXN3

RCLK1

RPOS1

RNEG1

N.C.

TTS3

TNEG3

RPOS3

RTS3

RXN3

RCLK1

RPOS1

RNEG1

N.C.

B9

TNEG3

RPOS3

RTS3

RXN3

RCLK1

RPOS1

RNEG1

TJA1

TNEG3

RPOS3

RTS3

RXN3

RCLK1

RPOS1

RNEG1

TJA1

N.C.

B10

B11

B12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

E1

N.C.

RCLK1

RPOS1

RNEG1

TJA1

RLB1

N.C.

RCLK1

RPOS1

RNEG1

N.C.

RCLK1

RPOS1

RNEG1

TJA1

RLB1

N.C.

RCLK1

RPOS1

RNEG1

N.C.

RLB1

TDSB3

E3M3

TLBO3

TDM3

RNEG3

N.C.

RLB1

TDSB3

E3M3

TLBO3

TDM3

RNEG3

N.C.

INT

MOT

ALE

N.C.

ALE

N.C.

ALE

N.C.

TDM3

RNEG3

N.C.

TDM3

RNEG3

N.C.

RXP3

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

RXP3

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

RXP3

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

RXP3

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

N.C.

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

TPOS1

TNEG1

TDM1

JTRST

JTMS

V_DD

V_SS

TBIN

N.C.

TBIN

N.C.

TBIN

RBIN

N.C.

TBIN

RBIN

N.C.

RBIN

N.C.

RBIN

N.C.

TJA3

N.C.

TJA3

N.C.

RJA3

N.C.

RJA3

N.C.

RMON3

TCLK1

TTS1

N.C.

RMON3

TCLK1

TTS1

N.C.

TCLK1

TTS1

D0

TCLK1

TTS1

D0

TCLK1

TTS1

TLBO1

JTCLK

V_DD

TCLK1

TTS1

D0

TCLK1

TTS1

TLBO1

JTCLK

V_DD

TCLK1

TTS1

D0

E2

E3

TLBO1

JTCLK

V_DD

TLBO1

JTCLK

V_DD

E4

JTCLK

V_DD

JTCLK

V_DD

JTCLK

V_DD

JTCLK

V_DD

E5

E6

V_DD

E7

V_SS

E8

V_SS

48 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

DS3153 DS3152 DS3151

DS3154

HARDWARE CPU BUS HARDWARE

CPU BUS HARDWARE CPU BUS HARDWARE CPU BUS

MODE

HW

MODE

HW

MODE

HW

MODE

HW

MODE

HW

MODE

HW

MODE

HW

MODE

HW

E9

E10

E11

E12

F1

RLB3

LLB3

E3MCLK

TXP1

STS1

E3M1

V_DD

N.C.

E3MCLK

TXP1

D1

RLB3

LLB3

E3MCLK

TXP1

STS1

E3M1

V_DD

N.C.

E3MCLK

TXP1

D1

N.C.

E3MCLK

TXP1

D1

N.C.

E3MCLK

TXP1

STS1

E3M1

V_DD

N.C.

E3MCLK

TXP1

D1

N.C.

E3MCLK

TXP1

STS1

E3M1

V_DD

F2

F3

D2

F4

V_DD

F5

V_DD

F6

V_DD

F7

V_SS

F8

V_SS

F9

V_SS

F10

F11

F12

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

J1

TDSB2

TDSA2

TXN2

TXN1

TDSA1

TDSB1

V_SS

N.C.

TXN2

TxN1

D3

TDSB2

TDSA2

TXN2

TXN1

TDSA1

TDSB1

V_SS

N.C.

TXN2

TXN1

D3

TDSB2

TDSA2

TXN2

TXN1

TDSA1

TDSB1

V_SS

N.C.

TXN2

TXN1

D3

N.C.

TXN1

TDSA1

TDSB1

V_SS

N.C.

TXN1

D3

D4

V_SS

V_DD

E3M2

STS2

TXP2

RST

N.C.

TXP2

RST

D5

E3M2

STS2

TXP2

RST

N.C.

TXP2

RST

D5

E3M2

STS2

TXP2

RST

N.C.

TXP2

RST

D5

N.C.

RST

N.C.

RST

D5

LLB4

RLB4

JTDI

N.C.

JTDI

V_SS

D6

N.C.

D6

N.C.

D6

JTDI

V_SS

JTDI

V_SS

JTDI

V_SS

JTDI

V_SS

JTDI

V_SS

JTDI

V_SS

V_DD

TCINV

TLBO2

TTS2

TCLK2

RMON4

RJA4

TJA4

JTDO

TEST

V_SS

N.C.

TTS2

TCLK2

N.C.

D7

TCINV

TLBO2

TTS2

TCLK2

N.C.

TTS2

TCLK2

N.C.

D7

TCINV

TLBO2

TTS2

TCLK2

N.C.

TTS2

TCLK2

N.C.

D7

TCINV

N.C.

JTDO

TEST

V_SS

N.C.

D7

J2

N.C.

J3

N.C.

J4

JTDO

TEST

V_SS

JTDO

TEST

V_SS

JTDO

TEST

V_SS

JTDO

TEST

V_SS

JTDO

TEST

V_SS

JTDO

TEST

V_SS

J5

J6

J7

V_DD

HIZ

V_DD

HIZ

N.C

V_DD

HIZ

V_DD

HIZ

N.C

V_DD

HIZ

V_DD

HIZ

N.C

V_DD

HIZ

V_DD

HIZ

J8

J9

RCINV

TDM2

TNEG2

TPOS2

RXP4

N.C.

RCINV

TDM2

TNEG2

TPOS2

N.C.

RCINV

TDM2

TNEG2

TPOS2

N.C.

RCINV

N.C.

N.C

N.C.

A0

J10

J11

J12

K1

TDM2

TNEG2

TPOS2

RXP4

N.C.

RNEG4

TDM4

N.C.

A0

TDM2

TNEG2

TPOS2

N.C.

A0

TDM2

TNEG2

TPOS2

N.C.

A0

K2

N.C.

K3

RNEG4

TDM4

TLBO4

E3M4

N.C.

K4

N.C.

K5

N.C.

K6

N.C.

49 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

DS3153 DS3152 DS3151

DS3154

HARDWARE CPU BUS HARDWARE

CPU BUS HARDWARE CPU BUS HARDWARE CPU BUS

MODE

TDSB4

RLB2

MODE

A2

MODE

N.C.

MODE

A2

MODE

N.C.

MODE

A2

MODE

N.C.

STMCLK

N.C.

MODE

A2

K7

K8

A4

RLB2

TJA2

RNEG2

RPOS2

RCLK2

N.C.

A4

RLB2

TJA2

RNEG2

RPOS2

RCLK2

N.C.

A4

N.C.

A1

K9

TJA2

N.C.

K10

K11

K12

L1

RNEG2

RPOS2

RCLK2

RXN4

RNEG2

RPOS2

RCLK2

RXN4

RTS4

RPOS4

TNEG4

TTS4

RNEG2

RPOS2

RCLK2

N.C.

RNEG2

RPOS2

RCLK2

N.C.

L2

N.C.

RTS4

L3

RPOS4

TNEG4

TTS4

N.C.

L4

N.C.

L5

N.C.

L6

STS4

A1

N.C.

A1

N.C.

A1

L7

TDSA4

LLB2

A3

N.C.

A3

N.C.

A3

L8

A5

LLB2

RJA2

N.C.

A5

LLB2

RJA2

N.C.

STMCLK

N.C.

L9

RJA2

N.C.

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

N.C.

RTS2

PRBS2

RLOS4

PRBS4

RCLK4

TPOS4

TCLK4

TXP4

TXN4

STMCLK

N.C.

RTS2

PRBS2

N.C.

RTS2

PRBS2

N.C.

RTS2

PRBS2

N.C.

RTS2

PRBS2

N.C.

PRBS2

RLOS4

PRBS4

RCLK4

TPOS4

TCLK4

TXP4

N.C.

TXN4

N.C.

STMCLK

RMON2

RXP2

STMCLK

RMON2

RXP2

RXN2

RLOS2

STMCLK

N.C.

STMCLK

RMON2

RXP2

RXN2

RLOS2

STMCLK

N.C.

RXP2

RXN2

RLOS2

RXP2

RXN2

RLOS2

RXP2

RXN2

RLOS2

RXN2

RLOS2

50 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-1. DS3151 Hardware Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

RMON1 T3MCLK

N.C.

B6

N.C.

B7

N.C.

B8

N.C.

B9

N.C.

B10

N.C.

B11

N.C.

B12

RLOS1

B1

B4

B5

PRBS1

C1

N.C.

C3

RJA1

C4

LLB1

C5

N.C.

C6

N.C.

C7

N.C.

C8

N.C.

C9

N.C.

C10

N.C.

C11

N.C.

C12

RTS1

C2

RCLK1 RPOS1 RNEG1

TJA1

D4

RLB1

D5

N.C.

D6

N.C.

D7

N.C.

D8

N.C.

D9

N.C.

D10

N.C.

D11

N.C.

D12

D1

D2

D3

V_DD

E6

TPOS1 TNEG1

JTMS

E5

V_SS

E7

TBIN

E8

RBIN

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

TLBO1

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

STS1

G2

E3M1

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

N.C.

G10

N.C.

G11

N.C.

G12

TXN1

H1

TDSA1

H2

TDSB1

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

N.C.

H10

N.C.

H11

N.C.

H12

N.C.

J2

N.C.

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

TCINV

J9

N.C.

J10

N.C.

J11

N.C.

J12

RST

J1

N.C.

K1

N.C.

K2

N.C.

K3

JTDO

K4

V_SS

K6

V_DD

K7

RCINV

K9

N.C.

K10

N.C.

K11

N.C.

K12

TEST

K5

HIZ

K8

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

N.C.

L6

N.C.

L7

N.C.

L8

N.C.

L9

N.C.

L10

N.C.

L11

N.C.

L12

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

N.C.

M6

N.C.

M7

N.C.

M8

N.C.

M9

N.C.

M10

N.C.

M11

N.C.

M12

N.C.

STMCLK

N.C.

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

51 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-2. DS3151 CPU Bus Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

N.C.

B4

T3MCLK

B5

N.C.

B6

N.C.

B7

N.C.

B8

N.C.

B9

N.C.

B10

N.C.

B11

N.C.

B12

RLOS1

B1

PRBS1

C1

N.C.

C3

N.C.

C4

N.C.

C8

N.C.

C9

N.C.

C10

N.C.

C11

N.C.

C12

RTS1

C2

WR

C5

RD

C6

CS

C7

RCLK1 RPOS1 RNEG1

N.C.

D4

MOT

D6

ALE

D7

N.C.

D8

N.C.

D9

N.C.

D10

N.C.

D11

N.C.

D12

INT

D5

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

N.C.

E8

N.C.

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

D0

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

D1

G2

D2

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

N.C.

G10

N.C.

G11

N.C.

G12

TXN1

H1

D3

H2

D4

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

N.C.

H10

N.C.

H11

N.C.

H12

D5

J2

D6

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

N.C.

J9

N.C.

J10

N.C.

J11

N.C.

J12

RST

J1

N.C.

K1

N.C.

K2

D7

K3

JTDO

K4

V_SS

K6

V_DD

K7

N.C.

K9

N.C.

K10

N.C.

K11

N.C.

K12

TEST

K5

HIZ

K8

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

A0

L6

A2

L7

N.C.

L8

N.C.

L9

N.C.

L10

N.C.

L11

N.C.

L12

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

A1

A3

N.C.

M8

N.C.

M9

N.C.

M10

N.C.

M11

N.C.

M12

M6

M7

N.C.

STMCLK

N.C.

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

52 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-3. DS3152 Hardware Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

RMON1 T3MCLK

N.C.

B6

N.C.

B7

N.C.

B8

N.C.

B9

N.C.

B10

N.C.

B11

N.C.

B12

RLOS1

B1

B4

B5

PRBS1

C1

N.C.

C3

RJA1

C4

LLB1

C5

N.C.

C6

N.C.

C7

N.C.

C8

N.C.

C9

N.C.

C10

N.C.

C11

N.C.

C12

RTS1

C2

RCLK1 RPOS1 RNEG1

TJA1

D4

RLB1

D5

N.C.

D6

N.C.

D7

N.C.

D8

N.C.

D9

N.C.

D10

N.C.

D11

N.C.

D12

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

TBIN

E8

RBIN

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

TLBO1

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

STS1

G2

E3M1

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

TDSB2

G10

TDSA2

G11

TXN2

G12

TXN1

H1

TDSA1

H2

TDSB1

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

E3M2

H10

STS2

H11

TXP2

H12

N.C.

J2

N.C.

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

TCINV

J9

TLBO2

J10

TCLK2

J12

RST

J1

TTS2

J11

N.C.

K1

N.C.

K2

N.C.

K3

JTDO

K4

V_SS

K6

V_DD

K7

RCINV

K9

TNEG2 TPOS2

K11 K12

TEST

K5

HIZ

K8

TDM2

K10

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

N.C.

L6

N.C.

L7

RLB2

L8

TJA2

L9

RNEG2 RPOS2 RCLK2

L10

L11

L12

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

N.C.

M6

N.C.

M7

LLB2

M8

RJA2

M9

N.C.

M10

PRBS2

M12

RTS2

M11

N.C.

STMCLK RMON2

RXP2

RXN2

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

53 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-4. DS3152 CPU Bus Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

N.C.

B4

T3MCLK

B5

N.C.

B6

N.C.

B7

N.C.

B8

N.C.

B9

N.C.

B10

N.C.

B11

N.C.

B12

RLOS1

B1

PRBS1

C1

N.C.

C3

N.C.

C4

N.C.

C8

N.C.

C9

N.C.

C10

N.C.

C11

N.C.

C12

RTS1

C2

WR

C5

RD

C6

CS

C7

RCLK1

D1

RPOS1 RNEG1

N.C.

D4

MOT

D6

ALE

D7

N.C.

D8

N.C.

D9

N.C.

D10

N.C.

D11

N.C.

D12

INT

D5

D2

D3

TPOS1

E1

TNEG1

E2

JTMS

E5

V_DD

E6

V_SS

E7

N.C.

E8

N.C.

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

TCLK1

F1

D0

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

D1

G2

D2

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

N.C.

G10

N.C.

G11

TXN2

G12

TXN1

H1

D3

H2

D4

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

N.C.

H10

N.C.

H11

TXP2

H12

D5

J2

D6

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

N.C.

J9

N.C.

J10

TCLK2

J12

RST

J1

TTS2

J11

N.C.

K1

N.C.

K2

D7

K3

JTDO

K4

V_SS

K6

V_DD

K7

N.C.

K9

TNEG2

K11

TPOS2

K12

TEST

K5

HIZ

K8

TDM2

K10

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

A0

L6

A2

L7

A4

L8

N.C.

L9

RNEG2 RPOS2

RCLK2

L12

L10

L11

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

A1

M6

A3

M7

N.C.

M8

N.C.

M9

N.C.

M10

PRBS2

M12

RTS2

M11

N.C.

STMCLK

N.C.

RXP2

RXN2

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

54 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-5. DS3153 Hardware Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

RMON1 T3MCLK

TXN3

B6

TXP3

B7

TCLK3

B8

TPOS3

B9

RCLK3

B10

PRBS3

B11

RLOS1

B1

RLOS3

B12

B4

B5

PRBS1

C1

N.C.

C3

RJA1

C4

LLB1

C5

TDSA3

C6

STS3

C7

TNEG3 RPOS3

RXN3

C12

RTS1

C2

TTS3

C8

RTS3

C11

C9

C10

RCLK1 RPOS1 RNEG1

TJA1

D4

RLB1

D5

TDSB3

D6

E3M3

D7

TLBO3

D8

RNEG3

D10

N.C.

D11

RXP3

D12

TDM3

D9

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

TBIN

E8

RBIN

E9

TJA3

E10

RJA3

E11

RMON3

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

TLBO1

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

RLB3

F10

LLB3

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

STS1

G2

E3M1

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

TDSB2

G10

TDSA2

G11

TXN2

G12

TXN1

H1

TDSA1

H2

TDSB1

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

E3M2

H10

STS2

H11

TXP2

H12

N.C.

J2

N.C.

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

TCINV

J9

TLBO2

J10

TCLK2

J12

RST

J1

TTS2

J11

N.C.

K1

N.C.

K2

N.C.

K3

JTDO

K4

V_SS

K6

V_DD

K7

RCINV

K9

TNEG2 TPOS2

K11 K12

TEST

K5

HIZ

K8

TDM2

K10

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

N.C.

L6

N.C.

L7

RLB2

L8

TJA2

L9

RNEG2 RPOS2 RCLK2

L10

L11

L12

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

N.C.

M6

N.C.

M7

LLB2

M8

RJA2

M9

N.C.

M10

PRBS2

M12

RTS2

M11

N.C.

STMCLK RMON2

RXP2

RXN2

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

55 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-6. DS3153 CPU Bus Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

N.C.

B4

T3MCLK

B5

TXN3

B6

TXP3

B7

TCLK3

B8

TPOS3

B9

RCLK3

B10

PRBS3

B11

RLOS1

B1

RLOS3

B12

PRBS1

C1

N.C.

C3

N.C.

C4

TNEG3 RPOS3

RXN3

C12

RTS1

C2

WR

C5

RD

C6

CS

C7

TTS3

C8

RTS3

C11

C9

C10

RCLK1 RPOS1 RNEG1

N.C.

D4

MOT

D6

ALE

D7

N.C.

D8

RNEG3

D10

N.C.

D11

RXP3

D12

INT

D5

TDM3

D9

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

N.C.

E8

N.C.

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

D0

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

D1

G2

D2

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

N.C.

G10

N.C.

G11

TXN2

G12

TXN1

H1

D3

H2

D4

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

N.C.

H10

N.C.

H11

TXP2

H12

D5

J2

D6

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

N.C.

J9

N.C.

J10

TCLK2

J12

RST

J1

TTS2

J11

N.C.

K1

N.C.

K2

D7

K3

JTDO

K4

V_SS

K6

V_DD

K7

N.C.

K9

TNEG2 TPOS2

K11 K12

TEST

K5

HIZ

K8

TDM2

K10

N.C.

L1

N.C.

L2

N.C.

L3

N.C.

L4

N.C.

L5

A0

L6

A2

L7

A4

L8

N.C.

L9

RNEG2 RPOS2 RCLK2

L10

L11

L12

N.C.

M1

N.C.

M2

N.C.

M3

N.C.

M4

N.C.

M5

A1

M6

A3

M7

A5

M8

N.C.

M9

N.C.

M10

PRBS2

M12

RTS2

M11

N.C.

STMCLK

N.C.

RXP2

RXN2

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

56 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-7. DS3154 Hardware Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

RMON1 T3MCLK

TXN3

B6

TXP3

B7

TCLK3

B8

TPOS3

B9

RCLK3

B10

PRBS3

B11

RLOS1

B1

RLOS3

B12

B4

B5

PRBS1

C1

N.C.

C3

RJA1

C4

LLB1

C5

TDSA3

C6

STS3

C7

TNEG3 RPOS3

RXN3

C12

RTS1

C2

TTS3

C8

RTS3

C11

C9

C10

RCLK1 RPOS1 RNEG1

TJA1

D4

RLB1

D5

TDSB3

D6

E3M3

D7

TLBO3

D8

RNEG3

D10

N.C.

D11

RXP3

D12

TDM3

D9

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

TBIN

E8

RBIN

E9

TJA3

E10

RJA3

E11

RMON3

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

TLBO1

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

RLB3

F10

LLB3

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

STS1

G2

E3M1

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

TDSB2

G10

TDSA2

G11

TXN2

G12

TXN1

H1

TDSA1

H2

TDSB1

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

E3M2

H10

STS2

H11

TXP2

H12

LLB4

J2

RLB4

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

TCINV

J9

TLBO2

J10

TCLK2

J12

RST

J1

TTS2

J11

RMON4

K1

RJA4

K2

TJA4

K3

JTDO

K4

V_SS

K6

V_DD

K7

RCINV

K9

TNEG2 TPOS2

K11 K12

TEST

K5

HIZ

K8

TDM2

K10

RXP4

L1

N.C.

L2

RNEG4

L3

TLBO4

L5

E3M4

L6

TDSB4

L7

RLB2

L8

TJA2

L9

RNEG2 RPOS2 RCLK2

TDM4

L4

L10

L11

L12

RXN4

M1

RPOS4 TNEG4

STS4

M6

TDSA4

M7

LLB2

M8

RJA2

M9

N.C.

M10

PRBS2

M12

RTS4

M2

TTS4

M5

RTS2

M11

M3

M4

PRBS4

RCLK4

TPOS4

TCLK4

TXP4

TXN4 STMCLK RMON2

RXP2

RXN2

RLOS4

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

57 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Figure 14-8. DS3154 CPU Bus Mode Pin Assignment

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

RXN1

B2

RXP1

B3

N.C.

B4

T3MCLK

B5

TXN3

B6

TXP3

B7

TCLK3

B8

TPOS3

B9

RCLK3

B10

PRBS3

B11

RLOS1

B1

RLOS3

B12

PRBS1

C1

N.C.

C3

N.C.

C4

TNEG3 RPOS3

RXN3

C12

RTS1

C2

WR

C5

RD

C6

CS

C7

TTS3

C8

RTS3

C11

C9

C10

RCLK1 RPOS1 RNEG1

N.C.

D4

MOT

D6

ALE

D7

N.C.

D8

RNEG3

D10

N.C.

D11

RXP3

D12

INT

D5

TDM3

D9

D1

D2

D3

TPOS1 TNEG1

JTMS

E5

V_DD

E6

V_SS

E7

N.C.

E8

N.C.

E9

N.C.

E10

N.C.

E11

N.C.

E12

TDM1

E3

JTRST

E4

E1

E2

TCLK1

F1

D0

F3

JTCLK

F4

V_DD

F5

V_DD

F6

V_SS

F7

V_SS

F8

HW

F9

N.C.

F10

N.C.

F11

E3MCLK

F12

TTS1

F2

TXP1

G1

D1

G2

D2

G3

V_DD

G4

V_DD

G5

V_DD

G6

V_SS

G7

V_SS

G8

V_SS

G9

N.C.

G10

N.C.

G11

TXN2

G12

TXN1

H1

D3

H2

D4

H3

V_SS

H4

V_SS

H5

V_SS

H6

V_DD

H7

V_DD

H8

V_DD

H9

N.C.

H10

N.C.

H11

TXP2

H12

D5

J2

D6

J3

JTDI

J4

V_SS

J5

V_SS

J6

V_DD

J7

V_DD

J8

N.C.

J9

N.C.

J10

TCLK2

J12

RST

J1

TTS2

J11

N.C.

K1

N.C.

K2

D7

K3

JTDO

K4

V_SS

K6

V_DD

K7

N.C.

K9

TNEG2 TPOS2

K11 K12

TEST

K5

HIZ

K8

TDM2

K10

RXP4

L1

N.C.

L2

RNEG4

L3

N.C.

L5

A0

L6

A2

L7

A4

L8

N.C.

L9

RNEG2 RPOS2 RCLK2

TDM4

L4

L10

L11

L12

RXN4

M1

RPOS4 TNEG4

A1

M6

A3

M7

A5

M8

N.C.

M9

N.C.

M10

PRBS2

M12

RTS4

M2

TTS4

M5

RTS2

M11

M3

M4

PRBS4

RCLK4

TPOS4

TCLK4

TXP4

TXN4 STMCLK

N.C.

RXP2

RXN2

RLOS4

RLOS2

High-Speed Analog

High-Speed Digital

Low-Speed Digital

V_DD

V_SS

58 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

15. PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to

www.maxim-ic.com/DallasPackInfo.)

Note: All dimensions in millimeters.

A1 BALL PAD CORNER

13.00

12 11 10

9

8

7

6

5

4

3

2

1

A

B

1.00

C

D

E

F

G

H

13.00

J

K

(1.00)

L

M

(1.00)

1.00

BOTTOM VIEW

59 of 60

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

16. THERMAL INFORMATION

Table 16-A. Thermal Properties, Natural Convection

PARAMETER

MIN

TYP

MAX

+85

+125

UNITS

LC

Ambient Temperature (Note 1)

-40

Junction Temperature

LC

22.4

9.2

1.6

Theta-JA (ꢂ ), Still Air (Note 2)

LC/W

JA

Psi-JB

Psi-JT

Note 1: The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power.

Note 2: Theta-JA (ꢁ ) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board

with no airfl^Jo^Aw and dissipating maximum power.

Table 16-B. Theta-JA (ꢀ ) vs. Airflow

JA

FORCED AIR (m/s)

THETA-JA (ꢀ )

JA

0

1

22.4LC/W

19.0LC/W

17.2LC/W

2.5

17. REVISION HISTORY

REVISION

DESCRIPTION

012103

DS3154 new product release

DS3151/DS3152/DS3153 new product releases.

Electrical Characteristics section, Notes 1 and 2: Changed 44.73MHz to 51.84MHz; added indication that

specs are lower for rev A2; “all ones driven into RXPn/RXNn (1.0V square wave)” changed to “analog

loopback enabled” to match production test methodology.

040403

Table 13-B, Input leakage, I_IL: -10ꢂA min changed to -50ꢂA min.

Table 13-B: Replaced TBD values for I_DD, I_DDTS, and I_DDPD(DS3151/DS3152/DS3153); changed I_DDPD

spec from 38 typ and 50 max to 45 typ and 70 max.

Table 14-A and Table 14-B: Changed pins RBIN, RCINV, TBIN, and TCINV to “N.C.” to reflect they are

not available in CPU bus mode.

Figure 1-1: Labeled capacitors connected to transformer center taps as “(optional)”.

Section 6, Optional Pre-Amp Paragraph: Clarified that the pre-amp contributes +14dB of flat gain.

Table 11-A: Changed leakage inductance to 0.150ꢂH max.

Table 11-B: Reformatted table and added row for Pulse Engineering’s T3049 octal transformer.

Table 13-H: Reworded Note 20.

072303

120303

GCR Register Definition (page 16): Clarified that RST bit holds the digital logic of the LIU in reset rather

than the whole LIU.

Table 13-B: Changed DS3151 I_DDfrom 130mA (max) to 100mA (max). Changed DS3151 I_DDTTSfrom

105mA (max) to 80mA (max). Removed sentences in Notes 1 and 2 that labeled I_DDand I_DDTTSspecs for

rev A1 devices.

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

60 of 60


型号：	DS3153
厂家：	DALLAS SEMICONDUCTOR
描述：	Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 单/双/三/四路，DS3 / E3 / STS - 1 LIU的电信集成电路电信电路
文件：	总60页 (文件大小：770K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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