DS1667 [DALLAS]
Digital Resistor with OP AMP; 数字电阻与运算放大器
| 型号： | DS1667 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Digital Resistor with OP AMP |
| 文件： | 总10页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1667
Digital Resistor with OP AMP
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Two digitally controlled 256-position
potentiometers
NINV0
INV0
VB
1
2
20
19
18
17
16
15
14
13
12
11
VCC
OUT0
SOUT
W0
ꢀ Serial port provides means for setting and
reading both potentiometers
3
W1
4
ꢀ Resistors can be connected in series to
provide additional resolution
H1
5
H0
L1
6
L0
RST
CLK
OUT1
GND
7
COUT
DQ
ꢀ Default wiper position on power up is 50%
ꢀ Resistive elements are temperature-
compensated to +20% end to end
ꢀ Two high-gain, wide bandwidth operational
amplifiers
8
9
INVI
NINVI
10
20-Pin DIP (300-mil) and 20-Pin SOIC
See Mech. Drawings Section
ꢀ Low power CMOS design
ꢀ Applications include analog-to-digital and
digital-to-analog converters, variable
oscillators, and variable gain amplifiers
ꢀ 20-pin DIP package or optional 20-pin SOIC
surface mount package
ꢀ Operating temperature range
- Commercial: 0°C to 70°C
ꢀ Resistance values:
PIN DESCRIPTION
VCC
- +5-Volt Supply
GND
L0, L1
H0, H1
W0, W1
VB
- Ground
- Low End of Resistor
- High End of Resistor
- Wiper End of Resistor
- Substrate Bias and OP
AMP Negative Supply
- Wiper for Stacked
Configuration
SOUT
RESOLUTION -3 dB POINT
DS1667-10: 10k 39 ohms
DS1667-50: 50k 195 ohms
DS1667-100: 100k 390 ohms 100 kHz
1.1 MHz
200 kHz
RST
DQ
CLK
COUT
- Serial Port Reset Input
- Serial Port Input/Output
- Serial Port Clock Input
- Cascade Serial Port
Output
NINV0, NINVI
- Noninverting OP AMP
Input
INV0, INVI
OUT0, OUT1
- Inverting OP AMP Input
- OP AMP Outputs
DESCRIPTION
The DS1667 is a dual-solid state potentiometer that is adjustable by digitally selected resistive elements.
Each potentiometer is composed of 256 resistive elements. Between each resistive section of each
potentiometer are tap points accessible to the wiper. The position of the wiper on the resistive array is set
by an 8-bit register that controls which tap point is connected to the wiper output. Each 8-bit register can
be read or written by sending or receiving data bits over a 3-wire serial port. In addition, the resistors can
be stacked such that a single potentiometer of 512 sections results. When two separate potentiometers are
used, the resolution of the DS1667 is equal to the resistance value divided by 256. When the
potentiometers are stacked end to end, the resistance value is doubled while the resolution remains the
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032000
DS1667
same. The DS1667 also contains two high gain wide bandwidth operational amplifiers. Each amplifier
has both the inverting and non-inverting inputs and the output available for user configuration. The
operational amplifiers can be paired with the resistive elements to perform such functions as analog to
digital conversion, digital to analog conversion, variable gain amplifiers, and variable oscillators.
OPERATION - DIGITAL RESISTOR SECTION
The DS1667 contains two potentiometers, each of which has its wiper set by a value contained in an 8-bit
register (see Figure 1). Each potentiometer consists of 256 resistors of equal value with tap points
between each resistor and at the low end.
In addition, the potentiometer can be stacked by connecting them in series such that the high end of
potentiometer 0 is connected to the low end of potentiometer 1. When stacking potentiometers, the stack
select bit is used to select which potentiometer wiper will appear at the stack multiplexer output (SOUT).
A zero written to the stack multiplexer will connect wiper 0 to the SOUT pin. This wiper will determine
which of the 256 bottom taps of the stacked potentiometer is selected. When a 1 is written to the stack
multiplexer, wiper 1 is selected and one of the upper 256 taps of the stacked potentiometer is presented at
the SOUT pin.
BLOCK DIAGRAM Figure 1
Information is written to and read from the wiper 0 and wiper 1 registers and the stack select bit via the
17-bit I/O shift register. The I/O shift register is serially loaded by a 3-wire serial port consisting of RST ,
DQ, and CLK. It is updated by transferring all 17 bits (Figure 2). Data can be entered into the 17-bit shift
register only when the RST input is at a high level. While at a high level, the RST function allows serial
entry of data via the D/Q pin. The potentiometers always maintain their previous value until RST is
taken to a low level, which terminates data transfer. While RST input is low, the DQ and CLK inputs are
ignored.
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DS1667
Valid data is entered into the I/O shift register while RST is high on the low-to-high transition of the
CLK input. Data input on the DQ pin can be changed while the clock input is high or low, but only data
meeting the setup requirements will enter the shift register. Data is always entered starting with the value
of the stack select bit. The next 8 bits to be entered are those specifying the wiper 1 setting. The MSB of
these 8 bits is sent first. The next 8 bits to be entered are those specifying the wiper 0 setting, sent MSB
first. The 17th bit to be entered, therefore, will be the least significant bit of the wiper 0 setting. If fewer
than 17 bits are entered, the value of the potentiometer settings will result from the number of bits that
were entered plus the remaining bits of the old value shifted over by the number of bits sent. If more than
17 bits are sent, only the last 17 bits are left in the shift register. Therefore, sending other than 17 bits can
produce indeterminate potentiometer settings.
As bits are entered into the shift register, the previous value is shifted out bit by bit on the cascade serial
port pin (COUT). By connecting the COUT pin to the DQ pin of a second DS1667, multiple devices can
be daisy chained together as shown in Figure 3.
When connecting multiple devices, the total number of bits sent is always 17 times the number of
DS1667s in the daisy chain. In applications where it is desirable to read the settings of potentiometers, the
COUT pin of the last device connected in a daisy chain must be connected back to the DQ input of the
first device through a resistor with a value of 1k to 10k. This resistor provides isolation between COUT
and DQ when writing to the device (see Figure 3).
When reading data, the DQ line is left floating by the reading device. When RST is held low, bit 17 is
always present on the COUT pin, which is fed back to the input DQ pin through the resistor (see Figure
4). This data bit can now be read by the reading device. The RST pin is then transitioned high to initiate a
data transfer. When the CLK input transitions low to high, bit 17 is loaded into the first position of the
I/O shift register and bit 16 becomes present on COUT and DQ. After 17 bits (or 17 times the number of
devices for a daisy chain), the data has shifted completely around and back to its original position. When
RST is transitioned back low to end data transfer, the value (the same as before the read occurred) is
loaded into the wiper 0 and wiper 1 registers and the stack select bit.
When power is applied to the DS1667, the device always has the wiper settings at half position and the
stack select bit is at 0.
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DS1667
WRITING DATA Figure 2
CASCADING MULTIPLE DEVICES Figure 3
READING DATA Figure 4
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DS1667
DS1667 LINEARITY MEASUREMENTS
An important specification for the DS1667 is linearity, that is, for a given digital input, how close the
analog output is to that which is expected.
The test circuit used to measure the linearity of the DS1667 is shown in Figure 5. Note that to get an
accurate output voltage it is necessary to assure that the output current is 0, in order to negate the effects
of wiper impedance RW, which is typically 400 ohms. For any given setting N for the pot, the expected
voltage output at SOUT is:
VO = -5 + [10 X (N/256)] (in volts)
Absolute linearity is a comparison of the actual measured output voltage versus the expected value given
by the equation above and is given in terms of an LSB, which is the change in expected output when the
digital input is incremented by 1. In this case the LSB is 10/256 or 0.03906 volts. The equation for the
absolute linearity of the DS1667 is:
VO (actual) - VO (expected)
= AL (in LSBs)
LSB
The specification for absolute linearity of the DS1667 is + 1 LSB typical.
Relative linearity is a comparison of the difference of actual output voltages of two successive taps and
the difference of the expected output voltages of two successive taps. The expected difference of output
voltages is 1 LSB or 0.03906V for the measurement system of Figure 5. Relative linearity is expressed in
terms of an LSB and is given by the equation:
∆VO (actual)- LSB
= RL
LSB
The specification for relative linearity of the DS1667 is ± 0.5 LSB typical.
Figure 6 is a plot of absolute linearity (AL) and relative linearity (RL) versus wiper setting for a typical
DS1667 at 25°C.
DESCRIPTION AND OPERATION - OP AMP SECTION
The DS1667 contains two operational amplifiers which are ideal for operation from a single 5V supply
and ground or from +5V supplies (see Figure 1). An internal resistor divider defines the internal reference
of the op amp to be halfway between the power supplies, i.e.:
VDD + VB
2
For optimal performance, choose analog ground to be this value. The operational amplifiers feature rail to
rail output swing in addition to an input common mode range that includes the positive rail. Performance
features include broad band noise immunity as well as voltage gain into realistic loads specified at both
600 ohms and 2k ohms. High voltage gain is produced with low input offset voltage and low offset
voltage drift. Current consumption is less than 1.9 mA per amplifier and the device is virtually immune to
latchup.
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DS1667
LINEARITY MEASUREMENT CONFIGURATION Figure 5
DS1667 ABSOLUTE AND RELATIVE LINEARITY Figure 6
Absolute and Relative Linearity
(Normalized to 1 LSB)
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DS1667
TIMING DIAGRAM: RESISTOR SECTION Figure 7
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DS1667
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground (VB = GND)
Voltage on Resistor Pins when VB = -5.5V
Voltage on VB
-0.5V to +7.0V
-5.5V to +7.0V
-5.5V to GND
Operating Temperature
0°C to 70°C
Storage Temperature
Soldering Temperature
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
RESISTOR SECTION
(0°C to 70°C)
PARAMETER
SYMBOL
VCC
VIH
VIL
VB
L, H, W
MIN
+4.5
2.0
-0.5
-5.5
TYP
5.0
MAX
5.5
VCC+0.5
+0.8
GND
VCC+0.5
UNITS NOTES
Positive Supply Voltage
Input Logic 1
Input Logic 0
Negative Supply Voltage
Resistor Inputs
V
V
V
V
V
1
1
1
1
2
VB - 0.5
DC ELECTRICAL CHARACTERISTICS
RESISTOR SECTION
(0°C to 70°C; VCC = 5.0V ± 10%, VB = -5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
5
UNITS NOTES
Positive Supply Current
Negative Supply Current
Input Leakage
Wiper Resistance
Wiper Current
ICC
IB
IU
RW
IW
ILO
IOH
IOL
TOLR
N
3
3
mA
mA
µA
ohms
mA
µA
mA
mA
%
5
-1
+1
1000
1
400
Output Leakage
-1
-1.0
+1
Logic 1 Output @ 2.4 Volts
Logic 0 Output @ 0.4 Volts
End-to-End Resistor Tolerance
Noise (ref: 1V)
4
+20
-20
9
-120
dB
Hz
LSB
LSB
ppm
°C
Absolute Linearity
Relative Linearity
Resistor Temperature
Coefficient
AL
RL
TCR
1.0
0.5
750
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(TA = 25°C)
SYMBOL
CIN
MIN
TYP
MAX
UNITS NOTES
5
7
pF
pF
COUT
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DS1667
AC ELECTRICAL CHARACTERISTICS
RESISTOR SECTION
(0°C to 70°C, VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
CLK Frequency
Width of CLK Pulse
Data Setup Time
fCLK
tW
tSU
tH
10
MHz
ns
ns
50
30
10
Data Hold Time
ns
Propagation Delay Time Low
to High Level Clock to Output
RST High to Clock Input High
RST Low from
tPLH
50
ns
3
tHHT
tHLT
50
50
ns
ns
Clock Input High
OPERATIONAL AMPLIFIER SECTION DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 10%, VB = -5.0V ± 10%)
PARAMETER
SYMBOL
VOS
MIN
TYP
5
10
MAX
UNITS NOTES
Input Offset Voltage
Input Offset Voltage Drift
Common Mode Rejection
Positive Power
Supply Rejection
Negative Power
Supply Rejection
Input Common
Mode Voltage Range
Large Signal Voltage Gain
Large Signal Voltage Gain
Output Swing
10
mV
uV/°C
dB
VOSD
CMR
62
+PSR
-PSR
CCCM
62
62
dB
dB
V
VB+1.5V
VCC
106
96
4.7
dB
dB
V
RL=2kΩ
RL=600kΩ
RL=2kΩ
to GND
VB = -5V
RL=600kΩ
to GND
VB = -5V
VO = 0V
VO = +5V
VSWGH
VSWGL
VSWGH
VSWGL
4.6
4.5
-4.7
4.6
-4.6
-4.5
V
V
V
Output Swing
Output Swing
-4.6
Output Swing
Output Current
Output Current
VO,SOURCE
VO,SINK
13
13
58
63
mA
mA
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DS1667
OPERATIONAL AMPLIFIER SECTION
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
VSL
MIN
0.7
TYP
2
MAX
UNITS NOTES
Slew Rate
V/µs
MHz
deg
dB
6
5
5
5
Gain Bandwidth Product
Phase Margin
GBP
PM
2.5
75
Gain Margin
GM
20
Amp-to-Amp Isolation
AAI
130
dB
Input Referred Voltage Noise
IRVF
100
F=1 kHz
nV/ Hz
pA/ Hz
Input Referred Current Noise
Total Harmonic Distortion
IRV1
HD
0.0002
0.1
F=1 kHz
F=10 kHz
AV=-10
%
RL=2kΩ
VO = 1VPP
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed the substrate bias voltage in the negative direction.
3. Measured with a load as shown in Figure 8.
4. Over a frequency range of 0 - 1 kHz.
5. Load is RL = 600 ΩCL = 10 pF.
6. VDD = +5.0V VB = -5.0V connected as voltage follower with 10V step input and RL = ∞.
7. To achieve best op amp performance, VDD = +5.0V VB = -5.0V and analog ground = 0V. In general
VDD + VB
analog ground =
.
2
8. OP AMPS idle, no load.
9. Valid at 25°C only.
LOAD SCHEMATIC Figure 8
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