DS1110LE-150 [DALLAS]
3V 10-Tap Silicon Delay Line; 3V 10抽头硅延迟线
| 型号： | DS1110LE-150 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 3V 10-Tap Silicon Delay Line |
| 文件： | 总7页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XX-XXXX; Rev 1; 11/03
3V 10-Tap Silicon Delay Line
General Description
Features
The DS1110L 10-tap delay line is a 3V version of the
DS1110. It has 10 equally spaced taps providing delays
from 10ns to 500ns. The DS1110L series delay lines
provide a nominal accuracy of 5ꢀ or ꢁnsꢂ ,hichever
is greaterꢂ at 3.3V and +ꢁ5°C. The DS1110L is character-
ized to operate from ꢁ.7V to 3.6V. The DS1110L
produces both leading- and trailing-edge delays ,ith
equal precision. The device is offered in a standard
14-pin TSSOP.
♦ All-Silicon Delay Line
♦ 3V Version of the DS1110
♦ 10 Taps Equally Spaced
♦ Delays Are Stable and Precise
♦ Leading- and Trailing-Edge Accuracy
♦ Delay Tolerance ±±5 or ±ꢀnsꢁ ,hicheꢂer ꢃs
Greaterꢁ at 3.3V and +ꢀ±°C
♦ Economical
♦ Low-Profile 14-Pin TSSOP
♦ Low-Power CMOS
Applications
♦ TTL/CMOS Compatible
♦ Vapor Phase and ꢃR Solderable
♦ Fast-Turn Prototypes
Communications Equipment
Medical Devices
Automated Test Equipment
PC Peripheral Devices
♦ Delays Specified Oꢂer Commercial and ꢃndustrial
Temperature Ranges
♦ Custom Delays Aꢂailable
Pin Configuration
Ordering Information
TOTAL
DELAY
(ns) *
PꢃN-
PACKAGE
PART
TEMP RANGE
TOP VIEW
DS1110LE-100 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-1ꢁ5 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-150 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-175 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-ꢁ00 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-ꢁ50 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-300 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-350 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-400 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-450 -40°C to +85°C 14 TSSOP (173mil)
DS1110LE-500 -40°C to +85°C 14 TSSOP (173mil)
*Custom delays are available.
100
1ꢁ5
150
175
ꢁ00
ꢁ50
300
350
400
450
500
IN
N.C.
1
2
3
4
5
6
7
14 V
CC
13 TAP1
12 TAP3
11 TAP5
10 TAP7
TAP2
TAP4
TAP6
TAP8
GND
DS1110L
9
8
TAP9
TAP10
TSSOP (173mil)
_____________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3V 10-Tap Silicon Delay Line
ABSOLUTE MAXꢃMUM RATꢃNGS
Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V
Storage Temperature Range.............................-55°C to +1ꢁ5°C
Soldering Temperature...................See IPC/JEDEC J-STD-0ꢁ0A
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRꢃCAL CHARACTERꢃSTꢃCS
(-40°C to +85°Cꢂ V
= ꢁ.7V to 3.6V.)
CC
PARAMETER
Supply Voltage
SYMBOL
CONDꢃTꢃONS
MꢃN
TYP
MAX
UNꢃTS
V
(Note 1)
(Note 1)
(Note 1)
ꢁ.7
3.3
3.6
V
CC
V
CC
High-Level Input Voltage
V
ꢁ.ꢁ
V
IH
+ 0.3
+0.8
+1.0
150
Lo,-Level Input Voltage
Input Leakage Current
Active Current
V
-0.3
-1.0
V
IL
I
0V ≤ V ≤ V
CC
µA
I
I
I
V
V
V
= maxꢂ period = min (Note ꢁ)
40
mA
mA
mA
CC
OH
CC
CC
CC
High-Level Output Current
Lo,-Level Output Current
I
= minꢂ V
= ꢁ.3V
-1.0
OH
I
= minꢂ V = 0.5V
1ꢁ
OL
OL
AC ELECTRꢃCAL CHARACTERꢃSTꢃCS
(-40°C to +85°Cꢂ V
= ꢁ.7V to 3.6V.)
CC
PARAMETER
Input Pulse Width
SYMBOL
CONDꢃTꢃONS
MꢃN
TYP
MAX
UNꢃTS
10ꢀ of
tap 10
t
(Note 6)
ns
WI
+ꢁ5°Cꢂ 3.3V (Notes 3ꢂ 5ꢂ 6ꢂ 7ꢂ 9)
0°C to +70°C (Notes 4–7)
-ꢁ
-3
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+ꢁ
+3
Input to Tap Delay
(Delays ≤ 40ns)
t
t
PLH
ns
ꢀ
PHL
-40°C to +85°C (Notes 4–7)
+ꢁ5°Cꢂ 3.3V (Notes 3ꢂ 5ꢂ 6ꢂ 7ꢂ 9)
0°C to +70°C (Notes 4–7)
-4
+4
-5
+5
Input to Tap Delay
(Delays > 40ns)
t
t
PLH
PHL
-8
+8
-40°C to +85°C (Notes 4–7)
-13
+13
100
Po,er-Up Time
Input Period
t
ms
ns
PU
Period
(Note 8)
ꢁ (t
)
WI
ꢀ
______________________________________________________________________
3V 10-Tap Silicon Delay Line
CAPACꢃTANCE
(T = +ꢁ5°C.)
A
CONDꢃTꢃONS
PARAMETER
Input Capacitance
SYMBOL
MꢃN
TYP
MAX
UNꢃTS
C
5
10
pF
IN
Note 1: All voltages are referenced to ground.
Note ꢀ: Measured ,ith outputs open.
Note 3: Initial tolerances are ,ith respect to the nominal value at +ꢁ5°C and V
= 3.3V for both leading and trailing edges.
CC
Note 4: Temperature and voltage tolerances are ,ith respect to the nominal delay value over stated temperature range and a ꢁ.7V to
3.6V range.
Note ±: Intermediate delay values are available on a custom basis.
Note 6: See Test Conditions section.
Note 7: All tap delays tend to vary unidirectionally ,ith temperature or voltage changes. For exampleꢂ if tap 1 slo,s do,nꢂ all other
taps also slo, do,n; tap 3 can never be faster than tap ꢁ.
Note 8: Pulse ,idth and period specifications may be exceeded; ho,everꢂ accuracy is application sensitive (decouplingꢂ layoutꢂ etc.).
Note 9: For Tap 1 delays greater than ꢁ0nsꢂ the tolerance is 3ns or 5ꢀꢂ ,hichever is greater.
Typical Operating Characteristics
(V
= 3.3Vꢂ T = +ꢁ5°Cꢂ unless other,ise noted.)
A
CC
DELAY CHANGE (%)
DELAY CHANGE (%)
vs. V DS1110L-500
vs. V DS1110L-250
CC
CC
0.10
0.05
0
0.3
0.2
0.1
-0.05
-0.10
0
RAISING EDGE
FALLING EDGE
-0.15
-0.20
-0.25
-0.30
-0.35
-0.1
-0.2
-0.3
-0.4
RAISING EDGE
FALLING EDGE
2.7
3.0
3.3
3.6
2.7
3.0
3.3
3.6
V
(V)
V
(V)
CC
CC
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-500
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-250
6
5
4
3
4
3
2
2
1
1
0
0
RISING EDGE
FALLING EDGE
RISING EDGE
FALLING EDGE
-1
-2
-3
-4
-5
-1
-2
-3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_____________________________________________________________________
3
3V 10-Tap Silicon Delay Line
Typical Operating Characteristics (continued)
= 3.3Vꢂ T = +ꢁ5°Cꢂ unless other,ise noted.)
A
(V
CC
OUTPUT CURRENT HIGH
vs. OUTPUT VOLTAGE HIGH
OUTPUT CURRENT LOW
vs. OUTPUT VOLTAGE LOW
0.00E+0
-2.00E-03
-4.00E-03
-6.00E-03
-8.00E-03
-1.00E-02
-1.20E-02
-1.40E-02
-1.60E-02
-1.80E-02
1.80E-02
1.60E-02
1.40E-02
1.20E-02
1.00E-02
8.00E-03
6.00E-03
4.00E-03
2.00E-03
0.00E+00
V
= 2.7V
V
= 2.7V
CC
CC
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
OUTPUT VOLTAGE HIGH (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
OUTPUT VOLTAGE LOW (V)
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-500
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-250
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
V
= 3.6V
V
= 3.6V
CC
CC
15pF LOAD
ON EACH TAP
15pF LOAD
ON EACH TAP
0
0
0.1
1.0
10
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Pin Description
PꢃN
1
NAME
IN
FUNCTꢃON
Input
ꢁ
N.C.
GND
No Connection
Ground
7
13ꢂ 3ꢂ 1ꢁꢂ 4ꢂ 11ꢂ
5ꢂ 10ꢂ 6ꢂ 9ꢂ 8
Tap 1–Tap 10
Tap Output Number
ꢁ.7V to 3.6V
14
V
CC
4
______________________________________________________________________
3V 10-Tap Silicon Delay Line
Detailed Description
Table 1. Part Number by Delay (t
ꢁ t
)
PHL PLH
The DS1110L 10-tap delay line is a 3V version of
the DS1110. It has 10 equally spaced taps providing
delays from 10ns to 500ns. The device is offered in a
standard 14-pin TSSOP. The DS1110L series delay lines
provide a nominal accuracy of 5ꢀ or ꢁnsꢂ ,hichever is
greaterꢂ at 3.3V and +ꢁ5°C. The DS1110L is character-
ized to operate from ꢁ.7V to 3.6V. The DS1110L repro-
duces the input-logic state at the tap 10 output after a
fixed delay as specified by the dash-number suffix of the
part number (Table 1). The DS1110L produces both lead-
ing- and trailing-edge delays ,ith equal precision. Each
tap is capable of driving up to 10 74LS-type loads. Dallas
Semiconductor can customize standard products to meet
specific needs. Figure 1 is the DS1110_L logic diagram
and Figure ꢁ sho,s the timing diagram for the silicon
delay line.
PART
TOTAL DELAY (ns) DELAY/TAP (ns)
DS1110LE-100
DS1110LE-1ꢁ5
DS1110LE-150
DS1110LE-175
DS1110LE-ꢁ00
DS1110LE-ꢁ50
DS1110LE-300
DS1110LE-350
DS1110LE-400
DS1110LE-450
DS1110LE-500
100
1ꢁ5
150
175
ꢁ00
ꢁ50
300
350
400
450
500
10
1ꢁ.5
15
17.5
ꢁ0
ꢁ5
30
35
40
45
50
TAP1
TAP2
TAP9
TAP10
IN
10%
10%
10%
10%
Figure 1. Logic Diagram
PERIOD
t
FALL
t
RISE
V
IH
IL
2.4V
1.5V
2.4V
1.5V
1.5V
0.6V
0.6V
IN V
t
WI
t
WI
t
PLH
t
PLH
1.5V
1.5V
OUT
Figure 2. Timing Diagram: Silicon Delay Line
_____________________________________________________________________
±
3V 10-Tap Silicon Delay Line
t
(Time Delay Rising): The elapsed time bet,een
Terminology
Period: The time elapsed bet,een the leading edge of
the first pulse and the leading edge of the follo,ing pulse.
PLH
the 1.5V point on the leading edge of the input pulse
and the 1.5V point on the leading edge of any tap out-
put pulse.
t
(Pulse ,idth): The elapsed time on the pulse
,ꢃ
t
(Time Delayꢁ Falling): The elapsed time bet,een
bet,een the 1.5V point on the leading edge and the
1.5V point on the trailing edgeꢂ or the 1.5V point on the
trailing edge and the 1.5V point on the leading edge.
PHL
the 1.5V point on the trailing edge of the input pulse
and the 1.5V point on the trailing edge of any tap out-
put pulse.
t
(ꢃnput Rise Time): The elapsed time bet,een the
RꢃSE
ꢁ0ꢀ and the 80ꢀ point on the leading edge of the
input pulse.
Test Setup Description
Figure 3 illustrates the hard,are configuration used for
measuring the timing parameters on the DS1110L. A
precision pulse generator under soft,are control pro-
duces the input ,aveform. Time delays are measured
by a time interval counter (ꢁ0ps resolution) connected
t
(ꢃnput Fall Time): The elapsed time bet,een the
80ꢀ and the ꢁ0ꢀ point on the trailing edge of the input
pulse.
FALL
PULSE
GENERATOR
START
Z0 = 50Ω
TIME
INTERVAL
COUNTER
STOP
VHF SWITCH
CONTROL UNIT
DEVICE UNDER TEST
Figure 3. Test Circuit
6
______________________________________________________________________
3V 10-Tap Silicon Delay Line
bet,een the input and each tap. Each tap is selected
Chip Information
and connected to the counter by a VHF s,itch-control
unit. All measurements are fully automatedꢂ ,ith each
instrument controlled by a central computer over an
IEEE-488 bus.
TRANSISTOR COUNT: 6813
Output
Each output is loaded ,ith the equivalent of one 450Ω
resistor in parallel ,ith a 15pF capacitor. Delay is mea-
sured at the 1.5V level on the rising and falling edge.
Package Information
For the latest package outline informationꢂ go to www.maxim-ic.
com/packages.
Table ꢀ. Test Conditions
ꢃNPUT
CONDꢃTꢃON
+ꢁ5°C 3°C
Ambient Temperature
Supply Voltage (V
)
CC
3.3V 0.1V
High = 3.0V 0.1V
Lo, = 0.0V 0.1V
50Ω max
Input Pulse
Source Impedance
Rise and Fall Time
Pulse Width
ꢁns max
500ns (1µs for - 500ns)
1µs (ꢁµs for - 500ns)
Period
Note: Above conditions are for test only and do not restrict the
operation of the device under other data sheet conditions.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
© ꢁ00ꢁ Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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