DS1110-80 [DALLAS]
10-Tap Silicon Delay Line; 10抽头硅延迟线
| 型号： | DS1110-80 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 10-Tap Silicon Delay Line |
| 文件： | 总8页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 11/03
10-Tap Silicon Delay Line
General Description
Features
♦ All-Silicon, 5V, 10-Tap Delay Line
The DS1110 delay line is an improved replacement for
the DS1010. It has ten equally spaced taps providing
delays from 5ns to 500ns. The devices are offered in a
standard 16-pin SO or 14-pin TSSOP. The DS1110 series
delay lines provide a nominal accuracy of 5ꢀ or ꢁnsꢂ
whichever is greaterꢂ at 5V and +ꢁ5°C. The DS1110
reproduces the input logic state at the tap 10 output after
a fixed delay as specified by the dash number extension
of the part number. The DS1110 is designed to produce
both leading- and trailing-edge delays with equal preci-
sion. Each tap is capable of driving up to ten 74LS type
loads. Dallas Semiconductor can customize standard
products to meet special needs.
♦ Improved, Drop-In Replacement for the DS1010
♦ 10 Taps Equally Spaced
♦ Delays are Stable and Precise
♦ Leading- and Trailing-Edge Accuracy
♦ Delay Tolerance 5ꢀ or ꢁns, ꢂhichever is
Greater, at 5V and +ꢁ5°C
♦ Economical
♦ Auto-Insertable, Loꢂ Profile
♦ Loꢂ-Poꢂer CMOS
♦ TTL/CMOS Compatible
♦ Vapor Phase, IR, and Wave Solderable
♦ Fast-Turn Prototypes
Applications
Communications Equipment
Medical Devices
♦ Delays Specified Over Commercial and Industrial
Automated Test Equipment
PC Peripheral Devices
Temperature Ranges
♦ Custom Delays Available
♦ Standard 16-Pin SO or 14-Pin TSSOP
Pin Configurations
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TSSOP
16 SO
DS1110E-XXX
DS1110S-XXX
TOP VIEW
IN
N.C.
1
2
3
4
5
6
7
14 V
CC
13 TAP1
12 TAP3
11 TAP5
10 TAP7
TAP2
TAP4
TAP6
TAP8
GND
DS1110E
Selector Guide appears at end of data sheet.
9
8
TAP9
TAP10
TSSOP
Pin Configurations continued at end of data sheet.
_____________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Tap Silicon Delay Line
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V
Storage Temperature Range.............................-55°C to +1ꢁ5°C
Soldering Temperature...................See IPC/JEDEC J-STD-0ꢁ0A
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= 5.0V 5ꢀꢂ T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
(Note 1)
(Note 1)
4.75
5.0
5.ꢁ5
V
CC
V
CC
High-Level Input Voltage
V
ꢁ.4
V
IH
+ 0.3
+0.8
+1.0
150
Low-Level Input Voltage
Input Leakage Current
Active Current
V
-0.3
-1.0
V
IL
I
0V ≤ V ≤ V
CC
µA
I
I
I
V
V
V
= maxꢂ period = min (Note ꢁ)
40
mA
mA
mA
CC
OH
CC
CC
CC
High-Level Output Current
Low-Level Output Current
I
= minꢂ V
= ꢁ.3V
-1.0
OH
I
= minꢂ V = 0.5V
1ꢁ
OL
OL
AC ELECTRICAL CHARACTERISTICS
(V
= 5.0V 5ꢀꢂ T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10ꢀ of
tap 10
Input Pulse Width
t
(Note 6)
ns
WI
+ꢁ5°Cꢂ 5.0V (Notes 3ꢂ 5ꢂ 6ꢂ 7ꢂ 9)
0°C to +70°C (Notes 4–7)
-ꢁ
-3
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+ꢁ
+3
Input-to-Tap Delay
(Delays ≤ 40ns)
t
t
PLH
ns
PHL
-40°C to +85°C (Notes 4–7)
+ꢁ5°Cꢂ 5.0V (Notes 3ꢂ 5ꢂ 6ꢂ 7ꢂ 9)
0°C to +70°C (Notes 4–7)
-4
+4
-5
+5
Input-to-Tap Delay
(Delays > 40ns)
t
t
PLH
PHL
-8
+8
ꢀ
ms
ns
-40°C to +85°C (Notes 4–7)
-13
+13
ꢁ00
Power-Up Time
Input Period
t
PU
ꢁ (t ) or ꢁ0ꢂ
WI
whichever
is greater
Period
(Note 8)
ꢁ
______________________________________________________________________
10-Tap Silicon Delay Line
CAPACITANCE
(T = +ꢁ5°C.)
A
CONDITIONS
PARAMETER
Input Capacitance
SYMBOL
MIN
TYP
MAX
UNITS
C
5
10
pF
IN
Note 1: All voltages are referenced to ground.
Note ꢁ: Measured with outputs open.
Note 3: Initial tolerances are with respect to the nominal value at +ꢁ5°C and V
= 5.0V for both leading and trailing edges.
CC
Note 4: Temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75V
to 5.ꢁ5V range.
Note 5: Intermediate delay values are available on a custom basis.
Note 6: See Test Conditions section.
Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For exampleꢂ if tap 1 slows downꢂ all other
taps also slow down; tap 3 can never be faster than tap ꢁ.
Note 8: Pulse width and period specifications may be exceeded; howeverꢂ accuracy is application sensitive (decouplingꢂ layoutꢂ etc.)
Note 9: For Tap 1 delays greater than ꢁ0nsꢂ the tolerance is 3ns or 5ꢀꢂ whichever is greater.
Typical Operating Characteristics
(V
= 5.0Vꢂ T = +ꢁ5°Cꢂ unless otherwise noted.)
A
CC
DS1110-50 ACTIVE CURRENT
vs. INPUT FREQUENCY
DS1110-500 ACTIVE CURRENT
vs. INPUT FREQUENCY
200
180
160
140
120
100
80
40
35
30
25
20
15
10
60
40
15pF LOAD/TAP
5
15pF LOAD/TAP
= 5.25V
20
V
= 5.25V
CC
V
CC
0
0
0.1
1.0
10
100
0.1
1.0
FREQUENCY (MHz)
10
FREQUENCY (MHz)
DS1110-50 TAP 10 DELAY
vs. TEMPERATURE
DS1110-500 TAP 10 DELAY
vs. TEMPERATURE
54
53
52
51
50
49
48
47
46
575
550
525
500
475
450
425
500kHz INPUT
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_____________________________________________________________________
3
10-Tap Silicon Delay Line
Typical Operating Characteristics (continued)
= 5.0Vꢂ T = +ꢁ5°Cꢂ unless otherwise noted.)
A
(V
CC
DS1110-500 DELAY vs. TAP
DS1110-50 DELAY vs. TAP
500
50
FALLING EDGE
450
FALLING EDGE
45
400
350
300
250
200
150
40
35
30
RISING EDGE
RISING EDGE
25
20
15
10
5
100
500kHz INPUT
50
0
0
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
TAP
TAP
DS1110-50 TAP 10 DELAY
vs. VOLTAGE
DS1110-500 TAP 10 DELAY
vs. VOLTAGE
55
53
51
49
47
45
540
520
500
480
460
FALLING EDGE
FALLING EDGE
RISING EDGE
RISING EDGE
500kHz INPUT
4.750
4.875
5.000
VOLTAGE (V)
5.125
5.250
4.750
4.875
5.000
5.125
5.250
VOLTAGE (V)
Pin Description
PIN
NAME
FUNCTION
TSSOP
SO
1
ꢁ
7
1
IN
Input
ꢁꢂ 3ꢂ 15
N.C.
GND
No Connection
Ground
8
13ꢂ 3ꢂ 1ꢁꢂ 4ꢂ 11ꢂ
5ꢂ 10ꢂ 6ꢂ 9ꢂ 8
14ꢂ 4ꢂ 13ꢂ 5ꢂ 1ꢁꢂ 6ꢂ 11ꢂ
7ꢂ 10ꢂ 9
Tap 1–Tap 10
Tap Output Number
5.0V
14
16
V
CC
4
______________________________________________________________________
10-Tap Silicon Delay Line
Detailed Description
Table 1. Part Number by Delay (t
, t
)
PHL PLH
The DS1110 delay line is an improved replacement for
the DS1010. It has ten equally spaced taps providing
delays from 5ns to 500ns. The devices are offered in a
standard 16-pin SO or 14-pin TSSOP. The DS1110
series delay lines provide a nominal accuracy of 5ꢀ
or ꢁnsꢂ whichever is greaterꢂ at 5V and +ꢁ5°C. The
DS1110 reproduces the input logic state at the tap 10
output after a fixed delay as specified by the dash
number extension of the part number. The DS1110 is
designed to produce both leading- and trailing-edge
delays with equal precision. Each tap is capable of dri-
ving up to ten 74LS type loads. Dallas Semiconductor
can customize standard products to meet special
needs. For special requests call 97ꢁ-371-4348.
PART
DS1110-50
DS1110-60
DS1110-75
DS1110-80
DS1110-100
DS1110-1ꢁ5
DS1110-150
DS1110-175
DS1110-ꢁ00
DS1110-ꢁ50
DS1110-300
DS1110-350
DS1110-400
DS1110-450
DS1110-500
TOTAL DELAY* (ns)
DELAY/TAP (ns)
50
5
6
60
75
7.5
8
80
100
1ꢁ5
150
175
ꢁ00
ꢁ50
300
350
400
450
500
10
1ꢁ.5
15
17.5
ꢁ0
ꢁ5
30
35
40
45
50
*Custom delays are available.
TAP1
TAP2
TAP9
TAP10
IN
10%
10%
10%
10%
Figure 1. Logic Diagram
PERIOD
t
FALL
t
RISE
V
IH
IL
2.2V
1.5V
2.2V
1.5V
1.5V
0.8V
0.8V
IN V
t
t
WI
WI
t
PLH
t
PLH
1.5V
1.5V
OUT
Figure 2. Timing Diagram: Silicon Delay Line
_____________________________________________________________________
5
10-Tap Silicon Delay Line
t
(Time Delay, Rising): The elapsed time between
PLH
the 1.5V point on the leading edge of the input pulse
and the 1.5V point on the leading edge of any tap out-
put pulse.
Terminology
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following pulse.
t
(Time Delay, Falling): The elapsed time between
PHL
t
(Pulse Width): The elapsed time on the pulse
WI
the 1.5V point on the trailing edge of the input pulse
and the 1.5V point on the trailing edge of any tap out-
put pulse.
between the 1.5V point on the leading edge and the
1.5V point on the trailing edgeꢂ or the 1.5V point on the
trailing edge and the 1.5V point on the leading edge.
Test Setup Description
Figure 3 illustrates the hardware configuration used for
measuring the timing parameters on the DS1110. A
precision pulse generator under software control pro-
duces the input waveform. Time delays are measured
by a time interval counter (ꢁ0ps resolution) connected
t
(Input Rise Time): The elapsed time between the
RISE
ꢁ0ꢀ and the 80ꢀ point on the leading edge of the
input pulse.
t
(Input Fall Time): The elapsed time between the
FALL
80ꢀ and the ꢁ0ꢀ point on the trailing edge of the
input pulse.
PULSE
GENERATOR
START
Z0 = 50Ω
TIME
INTERVAL
COUNTER
STOP
VHF SWITCH
CONTROL UNIT
DEVICE UNDER TEST
Figure 3. Test Circuit
6
______________________________________________________________________
10-Tap Silicon Delay Line
between the input and each tap. Each tap is selected
and connected to the counter by a VHF switch-control
unit. All measurements are fully automatedꢂ with each
instrument controlled by a central computer over an
IEEE-488 bus.
Table ꢁ. Test Conditions
INPUT
CONDITION
Ambient Temperature
+ꢁ5°C 3°C
Supply Voltage (V
)
CC
5.0V 0.1V
High = 3.0V 0.1V
Low = 0.0V 0.1V
50Ω max
Output
Each output is loaded with the equivalent of one 74FO4
input gate. Delay is measured at the 1.5V level on the
rising and falling edge.
Input Pulse
Source Impedance
Rise and Fall Time
Pulse Width
3ns max
500ns (1µs for -500ns)
1µs (ꢁµs for -500ns)
Period
Chip Information
Note: The above conditions are for test only and do not restrict
the operation of the device under other data sheet conditions.
TRANSISTOR COUNT: 6813
Selector Guide
TOTAL
PIN-
PACKAGE
TOTAL
PIN-
PACKAGE
DELAY
(ns)*
PART
TEMP RANGE
PART
TEMP RANGE
DELAY
(ns)*
DS1110E-50
DS1110E-60
DS1110E-75
DS1110E-80
DS1110E-100
DS1110E-1ꢁ5
DS1110E-150
DS1110E-175
DS1110E-ꢁ00
DS1110E-ꢁ50
DS1110E-300
DS1110E-350
DS1110E-400
DS1110E-450
DS1110E-500
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
50
DS1110S-50
DS1110S-60
DS1110S-75
DS1110S-80
DS1110S-100
DS1110S-1ꢁ5
DS1110S-150
DS1110S-175
DS1110S-ꢁ00
DS1110S-ꢁ50
DS1110S-300
DS1110S-350
DS1110S-400
DS1110S-450
DS1110S-500
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
50
60
60
75
75
80
80
100
1ꢁ5
150
175
ꢁ00
ꢁ50
300
350
400
450
500
100
1ꢁ5
150
175
ꢁ00
ꢁ50
300
350
400
450
500
*Custom delays are available.
_____________________________________________________________________
7
10-Tap Silicon Delay Line
Pin Configurations (continued)
Package Information
For the latest package outline informationꢂ go to ꢂꢂꢂ.maxim-ic.
com/packages.
TOP VIEW
IN1
N.C.
1
2
3
4
5
6
7
8
16 V
CC
15 N.C.
14 TAP1
13 TAP3
12 TAP5
11 TAP7
10 TAP9
N.C.
TAP2
TAP4
TAP6
TAP8
GND
DS1110S
9
TAP10
SO (300mil)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© ꢁ00ꢁ Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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