DS1007S-001 [DALLAS]
Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16;
| 型号： | DS1007S-001 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16 光电二极管 |
| 文件： | 总6页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1007
7-1 Silicon Delay Line
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ All-silicon time delay
IN1
1
2
16
15
IN3
ꢀ 7 independent buffered delays
ꢀ Delay tolerance ±2 ns
OUT1
OUT3
ꢀ Four delays can be custom set between 3 ns
and 10 ns
ꢀ Three delays can be custom set between 9 ns
and 40 ns
ꢀ Delays are stable and precise
ꢀ Economical
ꢀ Auto-insertable, low profile
ꢀ Surface mount 16-pin SOIC
ꢀ Low-power CMOS
IN2
OUT2
VCC
3
4
5
6
7
8
14
13
12
11
10
9
IN4
IN1
OUT1
IN2
1
2
3
4
5
6
7
8
IN3
OUT3
16
15
14
OUT4
GND
OUT7
IN7
IN4
OUT4
OUT2
VCC
13
12
11
10
9
IN5
OUT5
IN6
GND
OUT7
IN7
IN5
OUT5
IN6
OUT6
OUT6
DS1007 16-Pin DIP (300-mil)
See Mech. Drawings Section
DS1007S 16-Pin SOIC
(300-mil)
ꢀ TTL/CMOS-compatible
ꢀ Vapor phase, IR and wave solderable
ꢀ Custom specifications available
ꢀ Quick turn prototypes
See Mech. Drawings Section
PIN DESCRIPTION
IN1 - IN7
- Inputs
Out1 – Out7 - Outputs
GND
VCC
- Ground
- +5 Volts
DESCRIPTION
The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas
Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an
accuracy of ±2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.
Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to
older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after
the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special
requests and rapid delivery, call (972) 371–4348.
1 of 6
111799
DS1007
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH) Table 1
PART #
OUT1
OUT2
OUT3
OUT4
OUT5
9ns
12
OUT6
13ns
14
OUT7
DS1007-1
DS1007-2
DS1007-3
DS1007-4
DS1007-5
DS1007-6
DS1007-7
DS1007-8
DS1007-9
DS1007-10
DS1007-11
DS1007-12
DS1007-13
DS1007-14
3ns
4
3
4
5
6
7
8
9
10
3
3
3
7
4ns
6
3
4
5
6
7
8
9
10
4
4
4
7
5ns
8
3
4
5
6
7
8
9
10
6
6
6
7
6ns
10
3
4
5
6
7
8
9
10
8
8
8
7
18ns
16
10
12
15
20
25
30
35
40
14
20
20
9
10
12
15
20
25
30
35
40
10
10
12
9
10
12
15
20
25
30
35
40
12
15
15
9
Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only
accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
2 of 6
DS1007
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
TEST CIRCUIT Figure 3
3 of 6
DS1007
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
MIN TYP
MAX
UNITS NOTES
CONDITION
Supply Voltage
High Level Input
Voltage
VCC
VIH
4.75
2.2
5.00
5.25
VCC + 0.5
V
V
1
1
Low Level Input
Voltage
Input Leakage
Current
VIL
II
-0.5
-1.0
0.8
1.0
V
1
uA
0.0V ≤ VI ≤ VCC
Active Current
ICC
IOH
IOL
VCC=Max;
Period=Min.
VCC=Min.
VOH=2.4V
VCC=Min.
VOL=0.5V
40.0
70.0
-1.0
mA
mA
mA
2
High Level Output
Current
Low Level Output
Current
12.0
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
Input Pulse Width
Input to Output
(leading edge)
SYMBOL
tWI
MIN
TYP
MAX UNITS
NOTES
100% of tPLH
ns
ns
tPLH
Table 1
3, 4, 5
Power-up Time
tPU
Period
100
ms
ns
7
6
3 (tWI)
CAPACITANCE
PARAMETER
Input Capacitance
(TA = 25°C)
MAX UNITS
10 pF
SYMBOL
MIN
TYP
5
NOTES
CIN
4 of 6
DS1007
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @25°C. Delays accurate on rising edges within ±2 ns.
4. See Test Conditions below.
5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltage
range (i.e., if Out 2 slows down, all other outputs also slow down).
6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
7. tPU = 0 ms for Out 1 through Out 4.
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each output. Each
output is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
5 of 6
DS1007
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (VCC):
Input Pulse:
25°C ± 3°C
5.0V ± 0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
50 ohm max.
3.0 ns max.
500 ns
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
1 µs
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
6 of 6
相关型号：
DS1007S-008
Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16
DALLAS
DS1007S-1+
Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, LEAD FREE, SOIC-16
MAXIM
DS1007S-1+T&R
Silicon Delay Line, 7-Func, 1-Tap, True Output, CMOS, PDSO16, 0.300 INCH, LEAD FREE, SOIC-16
MAXIM
©2020 ICPDF网 联系我们和版权申明