DS1000 [DALLAS]

5-Tap Silicon Delay Line; 5抽头硅延迟线


型号：	DS1000
厂家：	DALLAS SEMICONDUCTOR
描述：	5-Tap Silicon Delay Line 5抽头硅延迟线延迟线逻辑集成电路光电二极管
文件：	总5页 (文件大小：68K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1000

5-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

ꢀ All-silicon time delay

V_CC

ꢀ 5 taps equally spaced

V_CC

TAP 2

TAP 4

GND

ꢀ Delays are stable and precise

ꢀ Both leading and trailing edge accuracy

ꢀ Delay tolerance ±5% or ±2 ns, whichever is

greater

TAP 1

TAP 3

TAP 5

TAP 2

TAP 1

TAP 3

ꢀ Low-power CMOS

DS1000M 8-Pin DIP (300-mil)

See Mech. Drawings Section

TAP 4

GND

ꢀ TTL/CMOS-compatible

ꢀ Vapor phase, IR and wave solderable

ꢀ Custom delays available

ꢀ Fast turn prototypes

ꢀ Extended temperature range available

(DS1000-IND)

TAP 5

V_CC

TAP 2

TAP 4

GND

DS1000 14-Pin DIP (300-mil)

See Mech. Drawings Section

TAP 1

TAP 3

TAP 5

DS1000Z 8-Pin SOIC (150-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-TAP 5 - TAP Output Number

V_CC

GND

- +5 Volts

- Ground

- No Connection

- Input

DESCRIPTION

The DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These

devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,

8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior

reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and

industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP

packages are available with hybrid lead configurations. The DS1000 series delay lines provide a nominal

accuracy of ±5% or ±2 ns, whichever is greater. The DS1000 5-Tap Silicon Delay Line reproduces the

input logic state at the output after a fixed delay as specified by the extension of the part number after the

dash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each

tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to

meet special needs. For special requests and rapid delivery, call 972-371-4348.

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111799

DS1000

LOGIC DIAGRAM Figure 1

DS1000

PART NUMBER DELAY TABLE (all values in ns) Table 1

TAP 1

TAP 2

TAP 3

TAP 4

TAP 5

TOLERANCE

Init

2.3

2.5

3.8

6.3

7.5

8.8

12.5

PART #

DS1000-

TOLERANCE

Nom

Init

Temp

Init

Temp

Init

Temp

Init

2.4

Temp

-20

-25

100

200

100

125

150

175

200

250

500

-30

-35

1.1

1.2

1.4

1.5

1.8

2.3

3.8

4.5

5.3

-40

-45

1.1

1.2

1.5

1.8

2.4

3.6

4.2

4.8

-50

-60

-75

-100

-125

-150

-175

-200

-250

-500

100

1.1

1.2

1.5

2.5

3.5

1.2

1.5

1.8

2.1

2.4

105

120

150

300

100

120

140

160

200

400

1.1

1.4

1.8

2.3

2.7

3.2

3.6

4.5

2.3

3.8

4.5

5.3

2.5

7.5

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC= 5.0V ± 5%)

PARAMETER

SYM

TEST

MIN TYP

MAX

UNITS NOTES

CONDITION

Supply Voltage

High Level Input

Voltage

V_CC

V_IH

4.75

2.2

5.00

5.25

V_CC+ 0.5

Low Level Input

Voltage

Input Leakage

Current

V_IL

I_I

-0.5

-1.0

0.8

1.0

-1

0.0V ≤ V_I≤ V_CC

Active Current

I_CC

I_OH

I_OL

V_CC=Max;

Period=Min.

V_CC=Min.

V_OH=4

V_CC=Min.

V_OL=0.5

7, 9

High Level Output

Current

Low Level Output

Current

AC ELECTRICAL CHARACTERISTICS

(T_A= 25°C; V_CC= 5V ± 5%)

PARAMETER

Input Pulse Width

Input to Tap Delay

(leading edge)

SYMBOL

t_WI

MIN

TYP

MAX UNITS

NOTES

1, 2, 3, 4,

5, 10

40% of Tap 5 t_PLH

t_PLH

Table 1

Input to Tap Delay

(trailing edge)

t_PHL

1, 2, 3, 4,

5, 10

Power-up Time

Input Period

t_PU

Period

100

4 (t_WI)

2 of 5

DS1000

CAPACITANCE

PARAMETER

Input Capacitance

(T_A= 25°C)

MAX UNITS

10 pF

SYMBOL

MIN

TYP

NOTES

C_IN

NOTES:

1. Initial tolerances are ±=with respect to the nominal value at 25°C and 5V.

2. Temperature tolerance is ±=with respect to the initial delay value over a range of 0°C to 70°C.

3. The delay will also vary with supply voltage, typically by less than 4% over the range 4.75 to 5.25V.

4. All tap delays tend to vary uni-directionally with temperature or voltage changes. For example, if

TAP 1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.

5. Intermediate delay values and packaging variations are available on a custom basis. For further

information, call 972-371–4348.

6. All voltages are referenced to ground.

7. Measured with outputs open.

8. Pulse width and period specifications may be exceeded; however, accuracy may be impaired

depending on application (decoupling, layout, etc.). The device will remain functional with pulse

widths down to 20% of Tap 5 delay, and input periods as short as 2(t_WI).

9. I_CCis a function of frequency and TAP 5 delay. Only a -25 operating with a 40-ns period and V_CC

5.25V will have an I_CC= 75 mA. For example a -100 will never exceed 30 mA, etc.

10. See “Test Conditions” section at the end of this data sheet.

TIMING DIAGRAM: SILICON DELAY LINE Figure 2

3 of 5

DS1000

TEST CIRCUIT Figure 3

TERMINOLOGY

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

t_WI(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the

1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading

edge.

t_RISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

t_FALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the

input pulse.

t_PLH(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input

pulse and the 1.5V point on the leading edge of any tap output pulse.

t_PHL(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input

pulse and the 1.5V point on the trailing edge of any tap output pulse.

TEST SETUP DESCRIPTION

Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1000.

The input waveform is produced by a precision pulse generator under software control. Time delays are

measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each

tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully

automated, with each instrument controlled by a central computer over an IEEE 488 bus.

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DS1000

TEST CONDITIONS

INPUT:

Ambient Temperature:

Supply Voltage (V_CC):

Input Pulse:

25°C ±=3°C

5.0V ±=0.1V

High = 3.0V ±=0.1V

Low = 0.0V ±=0.1V

50 ohm Max.

3.0 ns Max. (measured between 0.6V and 2.4V)

500 ns (1 µs for -500)

1 µs (2 µs for -500)

Source Impedance:

Rise and Fall Time:

Pulse Width:

Period:

OUTPUT:

Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on

the rising and falling edge.

NOTE:

Above conditions are for test only and do not restrict the operation of the device under other data sheet

conditions.

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