UL635H256BSC55 [CYPRESS]
32KX8 NON-VOLATILE SRAM, 55ns, PDSO28, 0.330 INCH, SOP-28;
| 型号： | UL635H256BSC55 |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 55ns, PDSO28, 0.330 INCH, SOP-28 静态存储器 光电二极管 |
| 文件： | 总13页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UL635H256
Advanced Information
Low Voltage PowerStore 32K x 8 nvSRAM
Description
Features
automatically on power up. The
UL635H256 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initiated
under user control via a software
sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The UL635H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The UL635H256 is a fast static
RAM (45 and 55 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
45 and 55 ns Access Times
20 and 25 ns Output Enable
Access Times
ICC = 8 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using system
capacitance
Software initiated STORE
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Wide voltage range: 2.7 ... 3.6 V
Operating temperature range:
0 to 70 °C
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
Packages: SOP28 (330 mil)
TSOP32 (Type I)
Pin Configuration
Pin Description
G
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Signal Name Signal Description
2
3
A0 - A14
Address Inputs
Data In/Out
A8
4
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A13
W
n. c.
VCC
n. c.
A14
A12 11
A7
A6
5
DQ0 - DQ7
6
7
Chip Enable
E
8
SOP
TSOP
9
Output Enable
Write Enable
Power Supply Voltage
Ground
G
10
W
12
13
DQ0 11
DQ1
DQ2 13
VSS
VCC
VSS
12
A5 14
A4
A3
A1
15
16
A2
14
n.c.
Top View
Top View
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December 12, 1997
UL635H256
Advanced Information
Block Diagram
EEPROM Array
512 x (64 x 8)
VCC
VSS
A5
A6
A7
A8
STORE
RECALL
SRAM
Array
Power
Control
VCC
A9
A11
512 Rows x
64 x 8 Columns
A12
A13
A14
Store/
Recall
Control
DQ0
DQ1
Column I/O
DQ2
DQ3
DQ4
Software
Detect
Column Decoder
A0 - A13
DQ5
DQ6
A0 A1 A2 A3 A4 A10
G
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
H
L
L
*
Data Outputs Low-Z
Data Inputs High-Z
Write
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
4.6
VCC+0.5
VCC+0.5
1
V
V
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
K-Type
0
-40
70
85
°C
°C
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
272
December 12, 1997
UL635H256
Advanced Information
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
VCC
VIL
2.7
-0.3
2.2
3.6
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
Input Low Voltage
Input High Voltage
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
VIH
= 3.6 V
= 0.8 V
= 2.2 V
tc
tc
= 45 ns
= 55 ns
35
30
37
32
mA
mA
Average Supply Current duringc
STORE
ICC2
VCC
E
= 3.6 V
≤ 0.2 V
3
4
mA
W
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Operating Supply Currentb
at tcR = 200 ns
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 3.6 V
≥ VCC-0.2 V
≤ 0.2 V
10
2
11
2
mA
mA
≥ VCC-0.2 V
Average Supply Current duringc
PowerStore Cycle
ICC4
VCC
VIL
= 4.5 V
= 0.2 V
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC
E
= 3.6 V
= VIH
tc
tc
= 45 ns
= 55 ns
9
8
10
9
mA
mA
Standby Supply Curentd
ICC(SB) VCC
= 3.6 V
1
1
mA
(Stable CMOS Input Levels)
E
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles.
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
273
December 12, 1997
UL635H256
Advanced Information
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 2.7 V
=-2 mA
= 2 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
2
2.4
2
V
V
0.4
-2
0.4
-2
VCC
VOH
VOL
= 2.7 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 3.6 V
High
Low
IIH
IIL
VIH
VIL
= 3.6 V
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
= 3.6 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 3.6 V
1
1
µA
µA
=
0 V
SRAM MEMORY OPERATIONS
Symbol
45
55
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tELICCH
tEHICCL
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
45
45
20
15
15
55
55
25
20
20
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Address Change
10 Chip Enable to Power Activee
tPU
11 Chip Disable to Power Standbyd, e
tPD
45
55
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
274
December 12, 1997
UL635H256
Advanced Information
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
1
tcR
Ai
Address Valid
2
ta(A)
DQi
Output
Output Data
Valid
Previous
Data Valid
9
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
1
tcR
Address Valid
Ai
2
ta(A)
3
ta(E)
5
tdis(E)
E
7
11
tPD
ten(E)
4
G
ta(G)
6
tdis(G)
8
ten(G)
DQi
Output
High Impedance
Output Data
Valid
10
ICC
tPU
ACTIVE
STANDBY
Symbol
45
55
Switching Characteristics
Write Cycle
No.
Unit
Alt. #1 Alt. #2
IEC
Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
45
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
tsu(A-WH)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
30
30
30
15
0
40
40
40
20
0
tsu(E)
tw(E)
tsu(D)
th(D)
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
th(A)
0
0
tdis(W)
ten(W)
15
20
5
5
275
December 12, 1997
UL635H256
Advanced Information
Write Cycle #1: W-controlledj
12
tcW
Ai
E
Address Valid
21
th(A
17
tsu(E)
)
16
tsu(A-WH)
13
w(W)
t
15
tsu(A)
W
20
th(D)
19
tsu(D)
Input Data
Valid
DQi
Input
23
ten(W)
22
tdis(W)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
12
tcW
Ai
Address Valid
21
th(A)
15
tsu(A)
18
tw(E)
E
14
tsu(W)
W
19
tsu(D)
20
th(D)
Input Data
Valid
DQi
Input
DQi
Output
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
276
December 12, 1997
UL635H256
Advanced Information
NONVOLATILE MEMORY OPERATIONS
MODE SELECTION
A13 - A0
(hex)
E
W
Mode
I/O
Power
Notes
H
L
L
L
X
H
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
m
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k, l
Nonvolatile STORE
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
Nonvolatile RECALL
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the UL635H256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
Symbol
PowerStore
No.
Conditions
Min. Max. Unit
Power Up RECALL
Alt.
IEC
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
tRESTORE
650
10
µs
the power supply decay
rate has to be smaller
than 20 Vs after the
-1
tPDSTORE
ms
start of the STORE
operation
Time allowed to Complete SRAM
26
tDELAY
1
µs
Cyclef
Low Voltage Trigger Level
VSWITCH
2.4
2.7
V
n:
tRESTORE starts from the time VCC rises above VSWITCH.
277
December 12, 1997
UL635H256
Advanced Information
PowerStore and automatic Power Up RECALL
VCC
3.0 V
VSWITCH
t
PowerStore
p
tPDSTORE
Power Up
24
24
RECALL
tRESTORE
tRESTORE
W
p
tDELAY
DQi
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
PowerStore
POWER UP
RECALL
Symbol
45
55
Software Controlled STORE/RECALL
Cyclek, o
No.
Unit
Alt.
IEC
Min. Max. Min. Max.
27 STORE/RECALL Initiation Time
28 Chip Enable to Output Inactivep
29 STORE Cycle Timeq
tAVAV
tELQZ
tcR
45
55
ns
ns
ms
µs
ns
ns
ns
tdis(E)SR
td(E)S
600
10
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
30 RECALL Cycle Timer
td(E)R
20
20
31 Address Setup to Chip Enables
32 Chip Enable Pulse Widths, t
33 Chip Disable to Address Changes
tsu(A)SR
tw(E)SR
th(A)SR
0
30
0
0
40
0
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
278
December 12, 1997
UL635H256
Advanced Information
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v (E = HIGH after STORE initiation)
27
tcR
27
tcR
ADDRESS 1
ADDRESS 6
Ai
E
32
tw(E)SR
31
33
tsu(A)SR
th(A)SR
29
/ 30
td(E)S / td(E)R
High Impedance
VALID
DQi
Output
VALID
28
tdis(E)SR
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v, w (E = LOW after STORE initiation)
29
tcR
Ai
ADDRESS 1
ADDRESS 6
35
th(A)SR
34
tw(E)SR
E
33
35
33
tsu(A)SR
th(A)SR
tsu(A)SR
31
/
32
td(E)S / td(E)R
High Impedance
VALID
VALID
DQi
Output
30
tdis(E)SR
u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL635H256 performs a STORE
or RECALL.
v: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
279
December 12, 1997
UL635H256
Advanced Information
Test Configuration for Functional Check
3 V
X
VCC
A0
A1
A2
A3
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A5
1.1 k
A6
A7
VIH
A8
A9
A10
A11
A12
VIL
VO
A13
A14
30 pF w
E
W
VSS
950
G
w: In measurement of tdis-times and ten-times the capacitance is 5 pF.
x: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 3.0 V
Input Capacitance
CI
8
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All Pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
UL635H256
S
C
45
B
Type
ESD Class
blank > 2000
Vy
B > 1000 V
Package
Access Time
45 = 45 ns
55 = 55 ns (on special request)
S
T
= SOP (330 mil)
= TSOP (Type I)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
y:
ESD protection > 2000 V under development
280
December 12, 1997
UL635H256
Advanced Information
Device Operation
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
The UL635H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
AUTOMATIC RECALL
During power up, an automatic RECALL takes place.
At a low power condition (power supply voltage <
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
VSWITCH) an internal RECALL request may be latched.
As soon as power supply voltage exceeds the sense
voltage of VSWITCH, a requested RECALL cycle will
automatically be initiated and will take tRESTORE to com-
plete.
If the UL635H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
SRAM READ
SOFTWARE NONVOLATILE STORE
The UL635H256 performs a READ cycle whenever E
and G are LOW and W is HIGH. The address specified
on pins A0 - A14 determines which of the 32768 data
bytes will be accessed. When the READ is initiated by
an address transition, the outputs will be valid after a
delay of tcR. If the READ is initiated by E or G, the out-
puts will be valid at ta(E) or at ta(G), whichever is later.
The data outputs will repeatedly respond to address
changes within the tcR access time without the need for
transition on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
The UL635H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the UL635H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all the nonvolatile elements.
Once a STORE cycle is initiated, further inputs and out-
puts are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
To initiate the STORE cycle the following READ
sequence must be performed:
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0FC0 (hex) Initiate STORE
Cycle
t
su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
AUTOMATIC STORE
The UL635H256 uses the intrinsic system capacitance
to perform an automatic STORE on power down. As
long as the decay rate from the system power supply is
-1
smaller than 20 Vs the UL635H256 will safely and
automatically STORE the SRAM data in EEPROM on
power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
281
December 12, 1997
UL635H256
Advanced Information
SOFTWARE NONVOLATILE RECALL
HARDWARE PROTECTION
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
The UL635H256 offers hardware protection against
inadvertent STORE operation through VCC Sense.
When VCC < VSWITCH all software STORE operations
will be inhibited.
LOW AVERAGE ACTIVE POWER
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0C63 (hex) Initiate RECALL
Cycle
The UL635H256 has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
td(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
5. the operating temperature
6. the VCC level
282
December 12, 1997
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be
reliable. However Zentrum Mikroelektronik Dresden GmbH (ZMD) makes no
guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or
reliance upon it. The information in this document describes the type of component
and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not
infringe upon the patent, trademark, copyright, mask work right or other rights of
third parties, and no patent or licence is implied hereby. This document does not in
any way extent ZMD’s warranty on any product beyond that set forth in its standard
terms and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the
products or specifications, or both, presented in this publication at any time and
without notice.
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