U6264AS1C07LG1 [CYPRESS]
8KX8 STANDARD SRAM, 70ns, PDSO28, 0.330 INCH, SOP-28;
| 型号： | U6264AS1C07LG1 |
| 厂家： | 
CYPRESS |
| 描述： | 8KX8 STANDARD SRAM, 70ns, PDSO28, 0.330 INCH, SOP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U6264A
Standard 8K x 8 SRAM
Features
F 8192 x 8 bit static CMOS RAM
F 70 and 100 ns Access Times
F Common data inputs and
outputs
F Three-state outputs
F Typ. operating supply current
70 ns: 45 mA
100 ns: 37 mA
F Data retention current
at 3 V: < 10 µA (standard)
F Standby current standard < 30 µA factured using a CMOS process
F Standby current low power
(L) < 10 µA
F Standby current very low power
(LL) < 1 µA
F Standby current for LL-version
at 25 °C and 5 V: typ. 50 nA
F TTL/CMOS-compatible
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity > 100 mA
F Packages: PDIP28 (600 mil)
SOP28 (300 mil)
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have
no preferred state. If the memory is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
SOP28 (330 mil)
Description
The U6264A is a static RAM manu-
technology with the following ope-
rating modes:
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
F Automatic reduction of power dis- edge of E2 (at E1 = L), or the falling
sipation in long Read or Write
cycles
F Power supply voltage 5 V
F Operating temperature ranges:
0 to 70 °C
-25 to 85 °C
-40 to 85 °C
F Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 µA typ.
Pin Configuration
Pin Description
n.c.
A12
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
VCC
2
W (WE)
E2 (CE2)
A8
Signal Name Signal Description
3
A0 - A12
Address Inputs
Data In/Out
A6
4
DQ0 - DQ7
A5
5
A9
A4
6
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
A11
E1
A3
7
G (OE)
A10
PDIP
SOP
E2
A2
8
G
A1
9
E1 (CE1)
DQ7
W
A0
10
11
12
13
14
VCC
VSS
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
not connected
n.c.
DQ4
DQ3
Top View
November 01, 2001
1
U6264A
Block Diagram
A4
A5
Memory Cell
Array
A6
A7
A8
256 Rows x
A9
256 Columns
A11
A12
A0
A1
A2
A3
A10
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
DQ5
Address
Change
Detector
Clock
Generator
DQ6
DQ7
E2
E1
VSS
W
G
VCC
1
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
Standby/not
selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
-
7
V
V
VCC + 0.5
VCC + 0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
G-Type
K-Type
0
-25
-40
70
85
85
°C
°C
°C
Storage Temperature
Tstg
-55
125
°C
November 01, 2001
2
U6264A
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
Data Retention Voltage
VCC
4.5
2.0
5.5
V
V
VCC(DR)
Input Low Voltage*
VIL
VIH
-0.3
2.2
0.8
V
V
Input High Voltage
VCC + 0.3
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP) VCC
= 5.5 V
= 0.8 V
= 2.2 V
VIL
VIH
Standard
tcW
tcW
= 70 ns
= 100 ns
70
60
mA
mA
Low Power (L)
Very Low Power (LL)
tcW
tcW
= 70 ns
= 100 ns
70
60
mA
mA
tcW
tcW
= 70 ns
= 100 ns
55
45
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB) VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
or VE2
= 0.2 V
Standard
Low Power (L)
Very Low Power (LL)
30
10
1
µA
µA
µA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1 VCC
= 5.5 V
VE1 = VE2 = 2.2 V
or VE2
= 0.2 V
Standard
Low Power (L)
Very Low Power (LL)
5
5
3
mA
mA
mA
Supply Current - Data Retention
Mode
ICC(DR) VCC(DR)
=
3 V
VE1 = VE2 = VCC(DR) - 0.2 V
or VE2 = 0.2 V
Standard
Low Power (L)
Very Low Power (LL)
10
10
1
µA
µA
µA
November 01, 2001
3
U6264A
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Output High Voltage
VOH
VCC
IOH
VCC
IOL
= 4.5 V
= -1.0 mA
= 4.5 V
2.4
V
Output Low Voltage
VOL
0.4
V
= 3.2 mA
Input Leakage Current
Standard &
Low Power (L)
High
Low
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
2
µA
µA
-2
=
0 V
Very Low Power (LL)
High
Low
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
1
µA
µA
-1
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-1
mA
mA
3.2
Output Leakage Current
Standard & Low Power (L)
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
2
µA
µA
Low at Three-State Outputs
-2
-2
=
0 V
Very Low Power (LL)
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
1
-
µA
µA
Low at Three-State Outputs
=
0 V
November 01, 2001
4
U6264A
Symbol
Min.
Max.
Unit
Switching Characteristics
Alt.
IEC
07
10
07
10
Time to Output in Low-Z
tLZ
tt(QX)
5
5
10
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
70
70
100
100
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
-
-
-
-
-
-
70
40
70
100
50
100
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
50
65
70
90
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
0
ns
ns
ns
ns
65
50
35
90
70
40
Data Hold Time
Address Hold from End of Write
t
t
th(D)
th(A)
0
0
0
0
ns
ns
DH
AH
Output Hold Time from Address Change
tOH
tv(A)
5
0
5
0
ns
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
tHZCE
tdis(E)
25
35
G HIGH to Output in High-Z
tHZWE
tHZOE
tdis(W)
tdis(G)
0
0
0
0
30
25
35
35
ns
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
VCC
VCC
E2
4.5 V
4.5 V
V
CC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
Data Retention
E2(DR) ≤ 0.2 V
2.2 V
2.2 V
0 V
trec
tDR
tDR
trec
E1
0.8 V
Data Retention
0.8 V
V
0 V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
CC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
V
Chip Deselect to Data Retention Time tDR
Operating Recovery Time trec
:
min 0 ns
min tcR
:
November 01, 2001
5
U6264A
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
960
VIH
VIL
VO
30 pF1)
E1
E2
W
510
VSS
G
1) In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.
Capacitance
Conditions
Symbol
Min.
Max.
Unit
V
CC = 5.0 V
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U6264A
D
G
07
L
Type
Internal Code
Package
D
S
= PDIP
= SOP (330 mil)
Power Consumption
S1 = SOP (300 mil)
= Standard
L
= Low Power
Operating Temperature Range
C = 0 to 70 °C
LL = Very Low Power
G = -25 to 85 °C
K = -40 to 85 °C
Access Time
07 = 70 ns
10 = 100 ns
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
November 01, 2001
6
U6264A
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
tcR
Addresses Valid
ta(A)
Ai
DQi
Output
Previous Data Valid
tv(A)
Output Data Valid
Read Cycle 2 (during Read cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
tsu(A)
E1
tt(QX)
tdis(E)
tdis(E)
tsu(A)
ta(E)
tt(QX)
E2
G
ta(G)
tdis(G)
tt(QX)
DQi
Output
High-Z
Output Data Valid
Write Cycle 1 (W-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
E2
tsu(E)
tw(W)
tsu(A)
W
tsu(D)
th(D)
DQi
Input
Input Data Valid
tdis(W)
tt(QX)
DQi
High-Z
Output
G
November 01, 2001
7
U6264A
Write Cycle 2 (E1-controlled)
tcW
Ai
Addresses Valid
tw(E)
tsu(A)
th(A)
E1
E2
W
tsu(E)
tsu(W)
th(D)
tsu(D)
DQi
Input
Input Data Valid
High-Z
tdis(W)
tt(QX)
DQi
Output
G
Write Cycle 3 (E2-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
tsu(A)
tw(E)
E2
W
tsu(W)
tsu(D)
th(D)
DQi
Input
Input Data Valid
tdis(W)
tt(QX)
DQi
High-Z
Output
G
L- or H-level
undefined
The information describes the type of component and shall not be considered as assured characteristic. Terms of
delivery and rights to change design reserved.
November 01, 2001
8
U6264A
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
Zentrum Mikroelektronik Dresden AG
November 01, 2001
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de
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