STK11C88-3WF55I [CYPRESS]
32KX8 NON-VOLATILE SRAM, 55ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | STK11C88-3WF55I |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 55ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK11C88-3
32K x 8 nvSRAM
3.3V QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Deisgns
FEATURES
DESCRIPTION
• 35, 45ns and 55ns Access Times
The Simtek STK11C88-3 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent non-
volatile data resides in Nonvolatile Elements. Data
transfers from the SRAM to the Nonvolatile Elements
(the STORE operation), or from Nonvolatile Elements
to SRAM (the RECALL operation) are initiated using a
software sequence. Data transfers from the Nonvol-
atile Elements to the SRAM (the RECALL operation)
also occur upon restoration of power.
• STORE to Nonvolatile Elements Initiated by
Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10 mA Typical Icc at 200 nsec Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention in Nonvolatile Ele-
ments
• Single 3.3V+ 0.3V Operation
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
A
A
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
14
QUANTUM TRAP
2
12
512 x 512
3
A
A
A
A
7
6
5
4
3
2
13
8
A5
A6
A7
A8
4
A
5
A
A
A
A
A
A
DQ
DQ
DQ
9
STORE
6
STORE/
RECALL
CONTROL
11
7
G
STATIC RAM
ARRAY
8
A
E
10
RECALL
A9
9
1
A11
A12
A13
A14
512 x 512
10
11
12
13
14
DQ
DQ
0
7
6
5
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
0
DQ
1
2
DQ
DQ
4
3
SOFTWARE
DETECT
A0 - A13
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
PIN NAMES
COLUMN I/O
A
- A
Address Inputs
Write Enable
Data In/Out
COLUMN DEC
0
14
W
DQ - DQ
0
7
A
A0 A1 A2 A3 A4
10
G
E
Chip Enable
Output Enable
Power (+ 3.3V)
Ground
G
E
V
V
CC
SS
W
March 2006
1
Document Control # ML0013 rev 0.2
STK11C88-3
a
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 4.5V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
(V = 3.0V-3.6V)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
50
42
37
52
44
39
mA
mA
mA
t
t
t
= 35ns
= 45ns
= 55ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V Current During STORE
3
9
3
9
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
3
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3.3V, 25°C, Typical
All Others Cycling, CMOS Levels
d
d
I
Average V Current
CC
(Standby, Cycling TTL Input Levels)
18
16
15
19
17
16
mA
mA
mA
t
t
t
= 35ns, E ≥ V
= 45ns, E ≥ V
= 55ns, E ≥ V
SB
AVAV
AVAV
AVAV
IH
IH
IH
1
2
I
I
I
V
Standby Current
E ≥ (V
- 0.2V)
CC
SB
CC
750
1
750
1
μA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
1
1
= V to V , E or G ≥ V
IN
SS
CC
IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
V
– .5
0.8
V – .5
SS
0.8
IL
SS
2.4
2.4
V
I
I
=– 4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
3.3V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.0V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
317 Ohms
OUTPUT
30 pF
INCLUDING
SCOPE AND
FIXTURE
351 Ohms
e
CAPACITANCE
(T = 25°C, f = 1.0MHz)
A
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
C
Input Capacitance
Output Capacitance
5
7
pF
IN
C
pF
OUT
Figure 1: AC Output Loading
Note e: These parameters are guaranteed but not tested.
March 2006
2
Document Control # ML0013 rev 0.2
STK11C88-3
SRAM READ CYCLES #1 & #2
(V = 3.0V-3.6V)
CC
SYMBOLS
NO.
STK11C88-3-35 STK11C88-3-45 STK11C88-3-55
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
35
45
55
AVAV
RC
AA
g
3
Address Access Time
35
15
45
20
55
25
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
13
13
35
15
15
45
20
20
55
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note h: Measured 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0013 rev 0.2
STK11C88-3
SRAM WRITE CYCLES #1 & #2
(V = 3.0V-3.6V)
CC
SYMBOLS
NO.
STK11C88-3-35 STK11C88-3-45 STK11C88-3-55
PARAMETER
UNITS
#1
#2
Alt.
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
40
40
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
25
0
30
0
40
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
WHAX
h, i
EHAX
WR
t
t
13
15
20
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
19
EHAX
18
AVEL
14
t
ELEH
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
March 2006
4
Document Control # ML0013 rev 0.2
STK11C88-3
STORE INHIBIT/POWER-UP RECALL
(V = 3.0V-3.6V)
CC
SYMBOLS
STK11C88-3
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
μs
ms
V
k
RESTORE
STORE
g
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
2.7
2.95
2.4
SWITCH
RESET
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
V
CC
3.3V
24
V
SWITCH
25
RESET
V
STORE INHIBIT
POWER-UP RECALL
22
RESTORE
t
DQ (DATA OUT)
POWER-UP
BROWN OUT
BROWN OUT
BROWN OUT
RECALL
STORE INHIBIT
STORE INHIBIT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
March 2006
5
Document Control # ML0013 rev 0.2
STK11C88-3
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
l, m
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
l, m
Nonvolatile RECALL
Note l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK11C88-3, only the lower 14 are used to control software modes.
n, o
SOFTWARE STORE/RECALL CYCLE
(V = 3.0V-3.6V)
CC
STK11C88-3-35
STK11C88-3-45
STK11C88-3-55
UNITS
NO.
SYMBOLS
PARAMETER
MIN
35
0
MAX
MIN
45
0
MAX
MIN
55
0
MAX
26
27
28
29
30
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
μs
AVAV
AVEL
n
n
25
20
30
20
45
20
ELEH
n
Address Hold Time
ELAX
n
RECALL Duration
20
20
20
RECALL
Note n: The software sequence is clocked with E controlled READs.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
o
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
t
ELEH
t
E
29
ELAX
t
23
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
March 2006
6
Document Control # ML0013 rev 0.2
STK11C88-3
DEVICE OPERATION
The STK11C88-3 is a versatile 3.3V VCC memory
SOFTWARE NONVOLATILE STORE
chip that provides several modes of operation. The
STK11C88-3 can operate as a standard 32K x 8
SRAM. It has a 32K x 8 Nonvolatile Elements
shadow to which the SRAM information can be cop-
ied or from which the SRAM can be updated in non-
volatile mode.
The STK11C88-3 software STORE cycle is initiated
by executing sequential READ cycles from six spe-
cific address locations. During the STORE cycle an
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the SRAM
data into nonvolatile memory. Once a STORE cycle
is initiated, further input and output are disabled until
the cycle is completed.
NOISE CONSIDERATIONS
Note that the STK11C88-3 is a high-speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
Because a sequence of reads from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
SRAM READ
The STK11C88-3 performs a READ cycle whenever
E and G are low and W is high. The address speci-
fied on pins A0-14 determines which of the 32,768
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence is clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
March 2006
7
Document Control # ML0013 rev 0.2
STK11C88-3
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C88-3 offers hardware protection
against inadvertent STORE operation during low-
voltage conditions. When VCC < VSWITCH, all software
STORE operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 3.6V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for WRITE cycles.If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C88-3 depends on the following
items: 1) CMOS vs. TTL input levels; 2) the duty
cycle of chip enable; 3) the overall cycle rate for
accesses; 4) the ratio of READs to WRITEs; 5) the
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET ), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C88-3 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
operating temperature; 6) the V level; and 7) I/O
CC
loading.
50
40
30
20
50
40
30
TTL
CMOS
20
TTL
10
0
10
CMOS
150 200
0
50
100
Cycle Time (ns)
50
100
150
200
Cycle Time (ns)
Figure 2: I (max) Reads
Figure 3: I (max) Writes
CC
CC
March 2006
8
Document Control # ML0013 rev 0.2
STK11C88-3
ORDERING INFORMATION
W F 25 I
STK11C88-3
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W=Plastic 28-pin 600 mil DIP
P=Plastic 28-pin 300 mil DIP
S=Plastic 28-pin 350 mil SOIC
N=Plastic 28-pin 300 mil SOIC
March 2006
9
Document Control # ML0013 rev 0.2
STK11C88-3
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
Added 35 nsec device; changed Vcc min. to 3.0 volts
Added lead free lead finish
0.1
0.2
Marked as Obsolete, Not recommended for new design.
March 2006
10
Document Control # ML0013 rev 0.2
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