S70KS1281DPBHI020 [CYPRESS]
Memory Circuit,;
| 型号： | S70KS1281DPBHI020 |
| 厂家： | 
CYPRESS |
| 描述： | Memory Circuit, 内存集成电路 |
| 文件： | 总56页 (文件大小：5669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S27KL0641/S27KS0641
S70KL1281/S70KS1281
3.0 V/1.8 V, 64 Mbit (8 Mbyte)/128 Mbit (16 Mbyte),
HyperRAM™ Self-Refresh DRAM
Distinctive Characteristics
HyperRAM™ Low Signal Count Interface
High Performance
3.0 V I/O, 11 bus signals
– Single ended clock (CK)
1.8V I/O, 12 bus signals
– Differential clock (CK, CK#)
Chip Select (CS#)
Up to 333 MB/s
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MB/s) at 1.8 V VCC
100 MHz clock rate (200 MB/s) at 3.0 V VCC
Sequential burst transactions
Configurable Burst Characteristics
– Wrapped burst lengths:
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
– Bidirectional Data Strobe / Mask
– 16 bytes (8 clocks)
– Output at the start of all transactions to indicate refresh
latency
– 32 bytes (16 clocks)
– 64 bytes (32 clocks)
– Output during read transactions as Read Data Strobe
– Input during write transactions as Write Data Mask
RWDS DCARS Timing
– 128 bytes (64 clocks)
– Linear burst
– Hybrid option - one wrapped burst followed by linear burst
– Wrapped or linear burst type selected in each transaction
– Configurable output drive strength
Package
– During read transactions RWDS is offset by a second
clock, phase shifted from CK
– The Phase Shifted Clock is used to move the RWDS
transition edge within the read data eye
– 24-ball FBGA
Performance Summary
Read Transaction Timings
Maximum Clock Rate at 1.8 V VCC/VCC
Q
Q
166 MHz
100 MHz
36 ns
Maximum Clock Rate at 3.0 V VCC/VCC
Maximum Access Time, (tACC at 166 MHz)
Maximum CS# Access Time to first word at
166 MHz (excluding refresh latency)
56 ns
Maximum Current Consumption
64 MB
128 MB
Burst Read or Write (linear burst at 166 MHz, 1.8V) 60 mA
60.3 mA
100 mA
600 µA
N/A
Power On Reset
50 mA
300 µA
40 µA
Standby (CS# = High, 3V, 105 °C)
Deep Power Down (CS# = High, 3V, 105 °C)
Standby (CS# = High, 1.8V, 105 °C)
Deep Power Down (CS# = High, 1.8V, 105 °C)
300 µA
20 µA
600 µA
N/A
Cypress Semiconductor Corporation
Document Number: 001-97964 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 20, 2016
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Logic Block Diagrams
Block Diagram — 64 Mbit
CS#
CK/CK#
RWDS
Memory
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
RESET#
Data Path
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Block Diagram — 128 Mbit
HyperRAM 1
CS#
CS#
Memory
CK/CK#
RWDS
CK/CK#
RWDS
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
DQ[7:0]
RESET#
Data Path
HyperRAM 2
CS#
Memory
CK/CK#
RWDS
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
RESET#
RESET#
Data Path
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HyperRAM Block Diagram
HyperRAM Connections, Including Optional Signals
VCC
VCC
Master
Slave 0
VCCQ
VCCQ
CS0#
CK
CS#
CK
CK#
CK#
DQ[7:0]
DQ[7:0]
RWDS
CS1#
RWDS
RESET#
RESET#
64 Mbit
VSS
VSS
VSS
Q
VSSQ
VCC
Slave 1
VCCQ
CS#
CK
CK#
DQ[7:0]
RWDS
RESET#
64 Mbit
VSS
VSS
Q
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Contents
Distinctive Characteristics .................................................. 1
Performance Summary ........................................................ 1
Logic Block Diagrams.......................................................... 2
Block Diagram — 64 Mbit .................................................... 2
Block Diagram — 128 Mbit .................................................. 3
HyperRAM Block Diagram................................................... 4
12. Revision History.......................................................... 54
Document History Page .................................................54
Sales, Solutions, and Legal Information ......................56
Worldwide Sales and Design Support .......................56
Products ....................................................................56
PSoC® Solutions ......................................................56
Cypress Developer Community .................................56
Technical Support .....................................................56
1.
2.
3.
General Description..................................................... 6
Product Overview ........................................................ 9
Signal Descriptions ................................................... 10
3.1 Input/Output Summary................................................. 10
3.2 Command/Address Bit Assignments ........................... 11
3.3 Read Transactions....................................................... 15
3.4 Write Transactions with Initial Latency (Memory Core
Write) ........................................................................... 16
3.5 Write Transactions without Initial Latency (Register Write)
...................................................................................... 18
4.
5.
Memory Space............................................................ 19
Register Space ........................................................... 19
5.1 Device Identification Registers..................................... 20
5.2 Register Space Access................................................ 20
6.
6.1 Power Conservation Modes......................................... 29
7. Electrical Specifications............................................ 31
Interface States .......................................................... 28
7.1 Absolute Maximum Ratings ......................................... 31
7.2 Latchup Characteristics ............................................... 32
7.3 Operating Ranges........................................................ 32
7.4 DC Characteristics....................................................... 33
7.5 Power-Up Initialization ................................................. 35
7.6 Power Down................................................................. 37
7.7 Hardware Reset........................................................... 38
8.
Timing Specifications................................................ 39
8.1 Key to Switching Waveforms ....................................... 39
8.2 AC Test Conditions...................................................... 39
8.3 AC Characteristics ....................................................... 40
9.
Physical Interface ...................................................... 44
9.1 FBGA 24-Ball 5 x 5 Array Footprint ............................. 44
9.2 Physical Diagrams ....................................................... 45
10. DDR Center Aligned Read Strobe (DCARS)
Functionality............................................................... 46
10.1 HyperRAM Products with DCARS Signal Descriptions 46
10.2 HyperRAM Products with DCARS — FBGA 24-ball, 5x5
Array Footprint ............................................................. 47
10.3 HyperRAM Memory with DCARS Timing..................... 47
11. Ordering Information................................................. 49
11.1 Ordering Part Number.................................................. 49
11.2 Valid Combinations...................................................... 50
11.3 Valid Combinations — Automotive Grade / AEC-Q100 52
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1. General Description
The Cypress® 64-Mbit HyperRAMTM device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface.
The Cypress 128-Mbit HyperRAM is a dual-die stack of 64-Mbit HyperRAM devices in a single package.
The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device
manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the
memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM
(PSRAM).
Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform
read or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The
host is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction,
if the memory indicates a refresh operation is needed.
HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write throughput. The DDR
protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of
a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide, one-half-
clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN) device
versions are available for core (VCC) and IO buffer (VCCQ) supplies of either 1.8 V or 3.0 V (nominal).
Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock is used for information
capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values
are center aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to
transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted.
Figure 1.1 Read Transaction, Single Initial Latency Count
CS#
tRWR=Read Write Recovery
t ACC = Access
Latency Count
CK#,CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:
–
–
when data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency)
when data is being transferred from a HyperRAM device to the master device during read transactions (as a source
synchronous read data strobe)
–
–
when data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency)
data masking during write data transfers
During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HyperRAM device to indicate whether
additional initial access latency is needed in the transaction.
During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of RWDS.
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Figure 1.2 Read Transaction, Additional Latency Count
CS#
CK#, CK
RWDS
tRWR=Read Write Recovery
Additional Latency
Latency Count 1
tACC = Access
Latency Count 2
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
B
A
B
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS High (invalid and prevented
from changing the byte location in a memory) or not masked with RWDS Low (valid and written to a memory). Data masking may be
used by the host to byte align write data within a memory or to enable merging of multiple non-word aligned writes in a single burst
write. During write transactions, data is center aligned with clock transitions.
Figure 1.3 Write Transaction, Single Initial Latency Count
CS#
tRWR =Read Write Recovery
tACC= Access
Latency Count
CK#,CK
CK and Data
are center aligned
High = 2x Latency Count
RWDS
Low = 1x Latency Count
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16
15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0]
and RWDS
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read
or write transaction can use either a wrapped or linear burst sequence.
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Figure 1.4 Linear Versus Wrapped Burst Sequence
16 word group alignment boundaries
Linear Burst
5h 6h 7h 8h 9h Ah Bh
Dh Eh Fh 10h 11h 12h 13h
4h
Ch
Ch
Initial address = 4h
Wrapped Burst
1h 2h 3h
5h 6h 7h 8h 9h Ah Bh
4h
Dh Eh Fh
0h
During wrapped transactions, accesses start at a selected location and continue to the end of a configured word group aligned
boundary, then wrap to the beginning location in the group, then continue back to the starting location. Wrapped bursts are generally
used for critical word first cache line fill read transactions. During linear transactions, accesses start at a selected location and
continue in a sequential manner until the transaction is terminated when CS# returns High. Linear transactions are generally used
for large contiguous data transfers such as graphic images. Since each transaction command selects the type of burst sequence for
that transaction, wrapped and linear bursts transactions can be dynamically intermixed as needed.
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2. Product Overview
The 64-Mbit and 128-Mbit HyperRAM devices are 1.8V or 3.0V core and I/O, synchronous self-refresh Dynamic RAM (DRAM). The
HyperRAM device provides a HyperBus slave interface to the host system. HyperBus has an 8-bit (1 byte) wide DDR data bus and
uses only word-wide (16-bit data) address boundaries. Read transactions provide 16 bits of data during each clock cycle (8 bits on
both clock edges). Write transactions take 16 bits of data from each clock cycle (8 bits on each clock edge).
Figure 2.1 HyperRAM Interface
RESET#
V
CC
V
Q
CC
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
Q
SS
Read and write transactions require two clock cycles to define the target row address and burst type, then an initial access latency of
tACC. During the Command-Address (CA) part of a transaction, the memory will indicate whether an additional latency for a required
refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the High state. During the CA period the third clock
cycle will specify the target word address within the target row. During a read (or write) transaction, after the initial data value has
been output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or
linear sequence. When configured in linear burst mode, the device will automatically fetch the next sequential row from the memory
array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is
in progress, allows for a linear sequential burst operation that can provide a sustained data rate of 333 MB/s (1 byte (8 bit data bus)
* 2 (data clock edges) * 166 MHz = 333 MB/s).
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3. Signal Descriptions
3.1
Input/Output Summary
HyperRAM signals are shown in Table 3.1. Active Low signal names have a hash symbol (#) suffix.
Table 3.1 I/O Summary
Symbol
CS#
Type
Description
Chip Select. Bus transactions are initiated with a High to Low transition. Bus
transactions are terminated with a Low to High transition. The master device has a
separate CS# for each slave.
Master Output, Slave Input
Differential Clock. Command, address, and data information is output with respect
to the crossing of the CK and CK# signals. Differential clock is used on 1.8V I/O
devices.
CK, CK#
Master Output, Slave Input
Single Ended Clock. CK# is not used on 3.0V devices, only a single ended CK is
used.
The clock is not required to be free-running.
Data Input/Output. Command, Address, and Data information is transferred on
these signals during Read and Write transactions.
DQ[7:0]
RWDS
Input/Output
Input/Output
Read Write Data Strobe. During the Command/Address portion of all bus
transactions RWDS is a slave output and indicates whether additional initial latency
is required. Slave output during read data transfer, data is edge aligned with RWDS.
Slave input during data transfer in write transactions to function as a data mask.
(High = additional latency, Low = no additional latency).
Hardware RESET. When Low the slave device will self initialize and return to the
Standby state. RWDS and DQ[7:0] are placed into the High-Z state when RESET# is
Low. The slave RESET# input includes a weak pull-up, if RESET# is left
unconnected it will be pulled up to the High state.
Master Output, Slave Input,
Internal Pull-up
RESET#
VCC
Power Supply
Power Supply
Power Supply
Power Supply
Power.
VCC
VSS
Q
Input/Output Power.
Ground.
VSSQ
Input/Output Power.
Reserved for Future Use. May or may not be connected internally, the signal/ball
location should be left unconnected and unused by PCB routing channel for future
compatibility. The signal/ball may be used by a signal in the future.
RFU
No Connect
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3.2
Command/Address Bit Assignments
All HyperRAM bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low with clock
in idle state (CK=Low and CK#=High). The first three clock cycles transfer three words of Command/Address (CA0, CA1, CA2)
information to define the transaction characteristics. The Command/Address words are presented with DDR timing, using the first six
clock edges. The following characteristics are defined by the Command/Address information:
Read or Write transaction
Address Space: memory array space or register space
–
Register space is used to access Device Identification (ID) registers and Configuration Registers (CR) that identify the
device characteristics and determine the slave specific behavior of read and write transfers on the HyperBus interface.
Whether a transaction will use a linear or wrapped burst sequence.
The target row (and half-page) address (upper order address)
The target column (word within half-page) address (lower order address)
Figure 3.1 Command-Address Sequence
CS#
CK , CK#
DQ[7:0]
CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8]
CA2[7:0]
Notes:
1. Figure shows the initial three clock cycles of all transactions on the HyperBus.
2. CK# of differential clock is shown as dashed line waveform.
3. Command-Address information is “center aligned” with the clock during both Read and Write transactions.
Table 3.2 Command-Address Bit Assignment to DQ Signals
Signal
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
CA0[47:40]
CA[47]
CA[46]
CA[45]
CA[44]
CA[43]
CA[42]
CA[41]
CA[40]
CA0[39:32]
CA[39]
CA[38]
CA[37]
CA[36]
CA[35]
CA[34]
CA[33]
CA[32]
CA1[31:24]
CA[31]
CA[30]
CA[29]
CA[28]
CA[27]
CA[26]
CA[25]
CA[24]
CA1[23:16]
CA[23]
CA[22]
CA[21]
CA[20]
CA[19]
CA[18]
CA[17]
CA[16]
CA2[15:8]
CA2[7:0]
CA[7]
CA[6]
CA[5]
CA[4]
CA[3]
CA[2]
CA[1]
CA[0]
CA[15]
CA[14]
CA[13]
CA[12]
CA[11]
CA[10]
CA[9]
CA[8]
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Table 3.3 Command/Address Bit Assignments
CA Bit#
Bit Name
Bit Function
Identifies the transaction as a read or write.
47
R/W#
R/W#=1 indicates a Read transaction
R/W#=0 indicates a Write transaction
Indicates whether the read or write transaction accesses the memory or register space.
AS=0 indicates memory space
AS=1 indicates the register space
Address Space
(AS)
46
45
The register space is used to access device ID and Configuration registers.
Indicates whether the burst will be linear or wrapped.
Burst Type=0 indicates wrapped burst
Burst Type
Burst Type=1 indicates linear burst
Row & Upper Column component of the target address: System word address bits A31-A3
Row & Upper
Column Address
Any upper Row address bits not used by a particular device density should be set to 0 by the
host controller master interface. The size of Rows and therefore the address bit boundary
between Row and Column address is slave device dependent.
44-16
Reserved for future column address expansion.
15-3
2-0
Reserved
Reserved bits are don’t care in current HyperBus devices but should be set to 0 by the host
controller master interface for future compatibility.
Lower Column component of the target address: System word address bits A2-0 selecting the
starting word within a half-page.
Lower Column
Address
Notes:
1. A Row is a group of words relevant to the internal memory array structure and additional latency may be inserted by RWDS when crossing Row boundaries - this is
device dependent behavior, refer to each HyperBus device data sheet for additional information. Also, the number of Rows may be used in the calculation of a
distributed refresh interval for HyperRAM memory.
2. A Page is a 16-word (32-byte) length and aligned unit of device internal read or write access and additional latency may be inserted by RWDS when crossing Page
boundaries - this is device dependent behavior, refer to each HyperBus device data sheet for additional information.
3. The Column address selects the burst transaction starting word location within a Row. The Column address is split into an upper and lower portion. The upper portion
selects an 8-word (16-byte) Half-page and the lower portion selects the word within a Half-page where a read or write transaction burst starts.
4. The initial read access time starts when the Row and Upper Column (Half-page) address bits are captured by a slave interface. Continuous linear read burst is enabled
by memory devices internally interleaving access to 16 byte half-pages.
5. HyperBus protocol address space limit, assuming:
29 Row &Upper Column address bits
3 Lower Column address bits
Each address selects a word wide (16 bit = 2 byte) data value
29 + 3 = 32 address bits = 4G addresses supporting 8Gbyte (64Gbit) maximum address space
Future expansion of the column address can allow for 29 Row &Upper Column + 16 Lower Column address bits = 35 Tera-word = 70 Tera-byte address space.
Figure 3.2 Data Placement During a Read Transaction
CS#
CK , CK#
DQ[7:0]
CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8]
CA2[7:0]
Notes:
1. Figure shows a portion of a Read transaction on the HyperBus. CK# of differential clock is shown as dashed line waveform.
2. Data is “edge aligned” with the RWDS serving as a read data strobe during read transactions.
3. Data is always transferred in full word increments (word granularity transfers).
4. Word address increments in each clock cycle. Byte A is between RWDS rising and falling edges and is followed by byte B between RWDS falling and rising edges, of
each word.
5. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0.
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Table 3.4 Data Bit Placement During Read or Write Transaction
Word
Data
Bit
Address
Space
Byte
Order
Byte
Position
DQ
Bit Order
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
B
A
B
8
Big-
endian
7
6
5
4
3
2
When data is being accessed in memory space:
The first byte of each word read or written is the “A” byte and the second is the “B” byte.
1
The bits of the word within the A and B bytes depend on how the data was written. If the word
lower address bits 7-0 are written in the A byte position and bits 15-8 are written into the B byte
position, or vice versa, they will be read back in the same order.
0
Memory
7
6
So, memory space can be stored and read in either little-endian or big-endian order.
5
4
3
2
1
0
Little-
endian
15
14
13
12
11
10
9
8
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Table 3.4 Data Bit Placement During Read or Write Transaction (Continued)
Word
Data
Bit
Address
Space
Byte
Order
Byte
Position
DQ
Bit Order
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
When data is being accessed in register space:
During a Read transaction on the HyperBus two bytes are transferred on each clock cycle. The
upper order byte A (Word[15:8]) is transferred between the rising and falling edges of RWDS
(edge aligned). The lower order byte B (Word[7:0]) is transferred between the falling and rising
edges of RWDS.
8
Big-
endian
Register
7
During a write, the upper order byte A (Word[15:8]) is transferred on the CK rising edge and the
lower order byte B (Word[7:0]) is transferred on the CK falling edge.
So, register space is always read and written in Big-endian order because registers have device
dependent fixed bit location and meaning definitions.
6
5
4
B
3
2
1
0
Figure 3.3 Data Placement During a Write Transaction
CS#
CK , CK#
RWDS
DQ[7:0]
DnA
DnB
Dn+1A
Dn+1B
Dn+2A
Notes:
1. Figure shows a portion of a Write transaction on the HyperBus.
2. Data is “center aligned” with the clock during a Write transaction.
3. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last byte is shown to illustrate an unaligned 3 byte write of data.
4. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are always written in this case. RWDS may be driven low or left
High-Z by the slave in this case.
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3.3
Read Transactions
The HyperBus master begins a transaction by driving CS# Low while clock is idle. Then the clock begins toggling while Command-
Address CA words are transfered.
In CA0, CA[47] = 1 indicates that a Read transaction is to be performed. CA[46] = 0 indicates the memory space is being read or
CA[46] = 1 indicates the register space is being read. CA[45] indicates the burst type (wrapped or linear). Read transactions can
begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]).
CA2 (CA(15:0]) identifies the target Word address within the chosen row. However, some HyperBus devices may require a minimum
time between the end of a prior transaction and the start of a new access. This time is referred to as Read-Write-Recovery time
(tRWR). The master interface must start driving CS# Low only at a time when the CA1 transfer will complete after tRWR is satisfied.
The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0.
The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is Low during the CA cycles, one
latency count is inserted. If RWDS is High during the CA cycles, an additional latency count is inserted. Once these latency clocks
have been completed the memory starts to simultaneously transition the Read-Write Data Strobe (RWDS) and output the target
data.
New data is output edge aligned with every transition of RWDS. Data will continue to be output as long as the host continues to
transition the clock while CS# is Low. However, the HyperRAM device may stop RWDS transitions with RWDS Low, between the
delivery of words, in order to insert latency between words when crossing memory array boundaries.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential manner across row
boundaries. When a linear burst read reaches the last address in the array, continuing the burst beyond the last address will provide
undefined data. Read transfers can be ended at any time by bringing CS# High when the clock is idle.
The clock is not required to be free-running. The clock may remain idle while CS# is high.
Figure 3.4 Read Transaction with Additional Initial Latency
CS#
Additional Latency
tRWR= Read Write Recovery
tACC = Access
CK#, CK
High = 2x Latency Count
Low = 1x Latency Count
RWDS
RWDS and Data
are edge aligned
Latency Count 1
Latency Count 2
Dn Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
A
B
A
B
Memory drives DQ[7:0]
and RWDS
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Notes:
1. Transactions are initiated with CS# falling while CK=Low and CK#=High.
2. CS# must return High before a new transaction is initiated.
3. CK# is the complement of the CK signal. 3V devices use a single ended clock (CK only), CK# is used with CK on1.8V devices to provide a differential clock. CK# of a
differential clock is shown as a dashed line waveform.
4. Read access array starts once CA[23:16] is captured.
5. The read latency is defined by the initial latency value in a configuration register.
6. In this read transaction example the initial latency count was set to four clocks.
7. In this read transaction a RWDS High indication during CA delays output of target data by an additional four clocks.
8. The memory device drives RWDS during read transactions.
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Figure 3.5 Read Transaction Without Additional Initial Latency
CS#
CK, CK#
RWDS
tRWR =Read Write Recovery
tACC = Initial Acces
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
4 cycle latency
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Addres
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Notes:
1. RWDS is Low during the CA cycles. In this Read Transaction there is a single initial latency count for read data access because, this read transaction does not begin
at a time when additional latency is required by the slave.
3.4
Write Transactions with Initial Latency (Memory Core Write)
The HyperBus master begins a transaction by driving CS# Low while clock is idle. Then the clock begins toggling while Command-
Address CA words are transfered.
In CA0, CA[47] = 0 indicates that a Write transaction is to be performed. CA[46] = 0 indicates the memory space is being written.
CA[45] indicates the burst type (wrapped or linear). Write transactions can begin the internal array access as soon as the row and
upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within
the chosen row. However, some HyperBus devices may require a minimum time between the end of a prior transaction and the start
of a new access. This time is referred to as Read-Write-Recovery time (tRWR). The master interface must start driving CS# Low only
at a time when the CA1 transfer will complete after tRWR is satisfied.
The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0.
The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is Low during the CA cycles, one
latency count is inserted. If RWDS is High during the CA cycles, an additional latency count is inserted.
Once these latency clocks have been completed the HyperBus master starts to output the target data. Write data is center aligned
with the clock edges. The first byte of data in each word is captured by the memory on the rising edge of CK and the second byte is
captured on the falling edge of CK.
During the CA clock cycles, RWDS is driven by the memory.
During the write data transfers, RWDS is driven by the host master interface as a data mask. When data is being written and RWDS
is High the byte will be masked and the array will not be altered. When data is being written and RWDS is Low the data will be
placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor the HyperRAM device
are able to indicate a need for latency within the data transfer portion of a write transaction. The acceptable write data burst length
setting is also shown in configuration register 0.
Data will continue to be transferred as long as the HyperBus master continues to transition the clock while CS# is Low. Legacy
format wrapped bursts will continue to wrap within the burst length. Hybrid wrap will wrap once then switch to linear burst starting at
the next wrap boundary. Linear burst accepts data in a sequential manner across page boundaries. Write transfers can be ended at
any time by bringing CS# High when the clock is idle.
When a linear burst write reaches the last address in the memory array space, continuing the burst will write to the beginning of the
address range.
The clock is not required to be free-running. The clock may remain idle while CS# is high.
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Figure 3.6 Write Transaction with Additional Initial Latency
CS#
Additional Latency
tRWR = Read Write Recovery
tACC = Initial Access
Latency Count 2
CK, CK#
RWDS
High = 2x Latency Count
Low = 1x Latency Count
Latency Count 1
CK and Data
are center aligned
Dn Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
A
B
A
B
Host drives DQ[7:0]
and RWDS
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Notes:
1. Transactions must be initiated with CK=Low and CK#=High.
2. CS# must return High before a new transaction is initiated.
3. During Command-Address, RWDS is driven by the memory and indicates whether additional latency cycles are required.
4. In this example, RWDS indicates that additional initial latency cycles are required.
5. At the end of Command-Address cycles the memory stops driving RWDS to allow the host HyperBus master to begin driving RWDS. The master must drive RWDS to
a valid Low before the end of the initial latency to provide a data mask preamble period to the slave.
6. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or loaded into the array.
7. The figure shows RWDS masking byte A0 and byte B1 to perform an unaligned word write to bytes B0 and A1.
Figure 3.7 Write Transaction Without Additional Initial Latency
CS#
tRWR=Read Write Recovery
tACC = Access
CK#, CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
CK and Data
are center aligned
Latency Count
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Notes:
1. During Command-Address, RWDS is driven by the memory and indicates whether additional latency cycles are required.
2. In this example, RWDS indicates that there is no additional latency required.
3. At the end of Command-Address cycles the memory stops driving RWDS to allow the host HyperBus master to begin driving RWDS. The master must drive RWDS to
a valid Low before the end of the initial latency to provide a data mask preamble period to the slave.
4. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or loaded into the array.
5. The figure shows RWDS masking byte A0 and byte B1 to perform an unaligned word write to bytes B0 and A1.
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3.5
Write Transactions without Initial Latency (Register Write)
A Write transaction starts with the first three clock cycles providing the Command/Address information indicating the transaction
characteristics. CA0 may indicate that a Write transaction is to be performed and also indicates the address space and burst type
(wrapped or linear).
Writes without initial latency are used for register space writes. HyperRAM device write transactions with zero latency mean that the
CA cycles are followed by write data transfers. Writes with zero initial latency, do not have a turn around period for RWDS. The
HyperRAM device will always drive RWDS during the Command-Address period to indicate whether extended latency is required for
a transaction that has initial latency. However, the RWDS is driven before the HyperRAM device has received the first byte of CA i.e.
before the HyperRAM device knows whether the transaction is a read or write to register space. In the case of a write with zero
latency, the RWDS state during the CA period does not affect the initial latency of zero. Since master write data immediately follows
the Command-Address period in this case, the HyperRAM device may continue to drive RWDS Low or may take RWDS to High-Z
during write data transfer. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use
RWDS as a data mask function. All bytes of write data are written (full word writes).
The first byte of data in each word is presented on the rising edge of CK and the second byte is presented on the falling edge of CK.
Write data is center aligned with the clock inputs. Write transfers can be ended at any time by bringing CS# High when clock is idle.
The clock is not required to be free-running.
Figure 3.8 Write Operation without Initial Latency
CS#
CK, CK#
RWDS
Memory drives RWDS but master ignores it
47:40 39:32 31:24 23:16
Command-Address
Host drives DQ[7:0] with Command-Address and Write Data
15:8
7:0
15:8
7:0
DQ[7:0]
Data
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4. Memory Space
When CA[46] is 0 a read or write transaction accesses the DRAM memory array.
Table 4.1 Memory Space Address Map
System Word
Address Bits
Unit Type
Count
2
CA Bits
35
Notes
CA 35 (A22) = 0, bottom die
CA 35 (A22) = 1, top die
Dies within 128 Mb
device
A22
Rows within 64 Mb
device
8192 (Rows)
A21 - A9
34 - 22
512 (word addresses)
1 kbytes
Row
1 (row)
A8 - A3
A2 - A0
21 - 16
2 - 0
Half-Page
8 (word addresses)
16 bytes
5. Register Space
When CA[46] is 1 a read or write transaction accesses the Register Space.
Table 5.1 Register Space Address Map
System
Address
—
—
—
31-27
44-40
26-19
39-32
00h
18-11
31-24
00h
10-3
23-16
00h
—
2-0
7-0
00h
Register
CA Bits
47
46
45
15-8
00h
Identification Register 0
(read only)
C0h or E0h
Identification Register 1
(read only)
C0h or E0h
00h
00h
00h
00h
01h
Configuration Register 0 Read
Configuration Register 0 Write
Configuration Register 1 Read
Configuration Register 1 Write
C0h or E0h
60h
00h
00h
00h
00h
01h
01h
01h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
01h
C0h or E0h
60h
Note:
1. CA45 may be either 0 or 1 for either wrapped or linear read. CA45 must be 1 as only linear single word register writes are supported.
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5.1
Device Identification Registers
There are two read only, non-volatile, word registers, that provide information on the device selected when CS# is low. The device
information fields identify:
Manufacturer
Type
Density
– Row address bit count
– Column address bit count
Table 5.2 ID Register 0 Bit Assignments
Bits
Function
Settings (Binary)
64 Mb
Reserved
Die Address:
00 = Die 1
01 = Die 2
15-14
13
128 Mb
Reserved
0 - default
00000 - One Row address bit
...
11111 - Thirty-two row address bits
12-8
Row Address Bit Count
01100 - 64 Mbit
01101 - 128 Mbit
0000 - One column address bit
...
1111 - Sixteen column address bits
7-4
3-0
Column Address Bit Count
Manufacturer
0000 - Reserved
0001 - Cypress
0010 to 1111 - Reserved
Table 5.3 ID Register 1 Bit Assignments
Bits
Function
Settings (Binary)
15-4
Reserved
0000_0000_0000b (default)
0000 - HyperRAM
0001 to 1111 - Reserved
3-0
Device Type
5.1.1
Density and Row Boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used for the row and
column addresses as indicated by the Row Address Bit Count and Column Address Bit Count fields in the ID0 register. For example:
a 64-Mbit HyperRAM device has 9 column address bits and 13 row address bits for a total of 22 word address bits = 222 = 4 Mwords
= 8 Mbytes. The 9 column address bits indicate that each row holds 29 = 512 words = 1 kbytes. The row address bit count indicates
there are 8196 rows to be refreshed within each array refresh interval. The row count is used in calculating the refresh interval.
5.2
Register Space Access
Register default values are loaded upon power-up or hardware reset. The registers can be altered at any time while the device is in
the standby state.
Loading a register is accomplished with a single 16-bit word write transaction as shown in Figure 5.1. CA[47] is zero to indicate a
write transaction, CA[46] is a one to indicate a register space write, CA[45] is a one to indicate a linear write, lower order bits in the
CA field indicate the register address.
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Figure 5.1 Loading a Register
CS#
CK,CK#
RWDS
Memory drives RWDS with Refresh Indication
47:40
39:32
31:24
23:16
15:8
7:0
15:8
7:0
DQ[7:0]
Command-Address
RD
Host drives DQ[7:0] with Command-Address and Register Data
Notes:
1. The host must not drive RWDS during a write to register space.
2. The RWDS signal is driven by the memory during the Command-Address period based on whether the memory array is being refreshed. This refresh indication does
not affect the writing of register data. RWDS is driven immediately after CS# goes low, before CA[47:46] are received to indicate that the transaction is a write to
register space, for which the RWDS refresh indication is not relevant.
3. The register value is always provided immediately after the CA value and is not delayed by a refresh latency.
4. The the RWDS signal returns to high impedance after the Command-Address period. Register data is never masked. Both data bytes of the register data are loaded
into the selected register.
Each register is written with a separate single word write transaction. Register write transactions have zero latency, the single word
of data immediately follows the Command-Address. RWDS is not driven by the host during the write because RWDS is always
driven by the memory during the CA cycles to indicate whether a memory array refresh is in progress. Because a register space
write goes directly to a register, rather than the memory array, there is no initial write latency, related to an array refresh that may be
in progress. In a register write, RWDS is also not used as a data mask because both bytes of a register are always written and never
masked.
Reserved register fields must be written with their default value. Writing reserved fields with other than default values may produce
undefined results.
Reading of a register is accomplished with a single 16 bit read transaction with CA[46]=1 to select register space. If more than one
word is read, the same register value is repeated in each word read. The CA[45] burst type is “don’t care” because only a single
register value is read. The contents of the register is returned in the same manner as reading array data, with one or two latency
counts, based on the state of RWDS during the Command-Address period. The latency count is defined in the Configuration
Register 0 Read Latency field (CR0[7:4]).
Note: It is recommended to configure all configuration registers in the 128 Mb dual-die stack identically.
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5.2.1
Configuration Register 0
Configuration Register 0 (CR0) is used to define the power mode and access protocol operating conditions for the HyperRAM
device. Configurable characteristics include:
Wrapped Burst Length (16, 32, 64, or 128-byte aligned and length data group)
Wrapped Burst Type
–
–
Legacy wrap (sequential access with wrap around within a selected length and aligned group)
Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
Initial Latency
Variable Latency
–
Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the memory will
always indicate a refresh latency and delay the read data transfer accordingly. If variable latency is selected, latency
for a refresh is only added when a refresh is required at the same time a new transaction is starting.
Output Drive Strength
Deep Power Down Mode
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Table 5.4 Configuration Register 0 Bit Assignments
CR0 Bit
Function
Settings (Binary)
Deep Power Down Enable 1 - Normal operation (default)
(64 Mbit)
0 - Writing 0 to CR[15] causes the device to enter Deep Power Down
15
Reserved
(128 Mbit)
Reserved for 128 Mb dual-die stack
000 - 34 ohms (default)
001 - 115 ohms
010 - 67 ohms
011 - 46 ohms
100 - 34 ohms
101 - 27 ohms
110 - 22 ohms
111 - 19 ohms
14-12
11-8
Drive Strength
Reserved
1 - Reserved (default)
Reserved for Future Use. When writing this register, these bits should be set
to 1 for future compatibility.
0000 - 5 Clock Latency
0001 - 6 Clock Latency (default)
0010 - Reserved
0011 - Reserved
0100 - Reserved
7-4
Initial Latency
...
1101 - Reserved
1110 - 3 Clock Latency
1111 - 4 Clock Latency
0 - Variable Latency - 1 or 2 times Initial Latency depending on RWDS during
CA cycles.
1 - Fixed 2 times Initial Latency (default)
Fixed Latency Enable
(64 Mbit)
3
Reserved
(128 Mbit)
1 - Fixed 2 times Initial Latency (default)
0: Wrapped burst sequences to follow hybrid burst sequencing
1: Wrapped burst sequences in legacy wrapped burst manner (default)
2
Hybrid Burst Enable
00 - 128 bytes
01 - 64 bytes
10- 16 bytes
1-0
Burst Length
11 - 32 bytes (default)
5.2.1.1
Wrapped Burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching the length of the
configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes alignment and length. During wrapped
transactions, access starts at the Command-Address selected location within the group, continues to the end of the configured word
group aligned boundary, then wraps around to the beginning location in the group, then continues back to the starting location.
Wrapped bursts are generally used for critical word first instruction or data cache line fill read accesses.
5.2.1.2
Hybrid Burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing to the next half-
page of data beyond the end of the wrap group. Continued access is in linear burst order until the transfer is ended by returning CS#
high. This hybrid of a wrapped burst followed by a linear burst starting at the beginning of the next burst group, allows multiple
sequential address cache lines to be filled in a single access. The first cache line is filled starting at the critical word. Then the next
sequential line in memory can be read in to the cache while the first line is being processed.
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Table 5.5 CR0[2] Control of Wrapped Burst Sequence
Bit
Default Value
Name
Hybrid Burst Enable
2
1
CR[2]= 0: Wrapped burst sequences to follow hybrid burst sequencing
CR[2]= 1: Wrapped burst sequences in legacy wrapped burst manner
Table 5.6 Example Wrapped Burst Sequences
Burst Selection
CA[45] CR0[2:0]
Wrap
Start
Address Sequence (Hex)
(Words)
Burst
Type
Boundary Address
(bytes)
(Hex)
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28,
29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B,
3C, 3D, 3E, 3F, 00, 01, 02
(wrap complete, now linear beyond the end of the initial 128 byte wrap
group)
128 Wrap
once then XXXXXX03
Linear
Hybrid
128
0
000
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02,
(wrap complete, now linear beyond the end of the initial 64 byte wrap
group)
64 Wrap
0
0
001
001
Hybrid 64 once then XXXXXX03
Linear
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, ...
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D,
(wrap complete, now linear beyond the end of the initial 64 byte wrap
group)
64 Wrap
Hybrid 64 once then XXXXXX2E
Linear
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
02, 03, 04, 05, 06, 07, 00, 01,
16 Wrap
Hybrid 16 once then XXXXXX02
Linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
group)
0
0
010
010
08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, ...
0C, 0D, 0E, 0F, 08, 09, 0A, 0B,
16 Wrap
Hybrid 16 once then XXXXXX0C
Linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
group)
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ...
32 Wrap
Hybrid 32 once then XXXXXX0A
Linear
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...
1E, 1F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, ...
0
0
011
011
32 Wrap
Hybrid 32 once then XXXXXX1E
Linear
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28,
29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B,
3C, 3D, 3E, 3F, 00, 01, 02, ...
0
0
100
101
Wrap 128
Wrap 64
128
64
XXXXXX03
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ...
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Table 5.6 Example Wrapped Burst Sequences (Continued)
Burst Selection
CA[45] CR0[2:0]
Wrap
Start
Address Sequence (Hex)
Burst
Type
Boundary Address
(Words)
(bytes)
(Hex)
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, ...
0
101
Wrap 64
64
XXXXXX2E
0
0
0
0
110
110
111
111
Wrap 16
Wrap 16
Wrap 32
Wrap 32
16
16
32
32
XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01, ...
XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ...
XXXXXX0A
XXXXXX1E
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...
1E, 1F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, ...
Linear
Burst
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, ...
1
XXX
Linear
XXXXXX03
Note:
1. Linear Burst across die boundary is not supported in 128-Mb dual-die stack.
5.2.1.3
Initial Latency
Memory Space read and write transactions or Register Space read transactions require some initial latency to open the row selected
by the Command-Address. This initial latency is tACC. The number of latency clocks needed to satisfy tACC depends on the
HyperBus frequency and can vary from 3 to 6 clocks. The value in CR0[7:4] selects the number of clocks for initial latency. The
default value is 6 clocks, allowing for operation up to a maximum frequency of 166MHz prior to the host system setting a lower initial
latency value that may be more optimal for the system.
In the event a distributed refresh is required at the time a Memory Space read or write transaction or Register Space read
transaction begins, the RWDS signal goes high during the Command-Address to indicate that an additional initial latency is being
inserted to allow a refresh operation to complete before opening the selected row.
Register Space write transactions always have zero initial latency. RWDS may be High or Low during the Command-Address
period. The level of RWDS during the Command-Address period does not affect the placement of register data immediately after the
Command-Address, as there is no initial latency needed to capture the register data. A refresh operation may be performed in the
memory array in parallel with the capture of register data.
5.2.1.4
Fixed Latency
A configuration register option bit CR0[3] is provided to make all Memory Space read and write transactions or Register Space read
transactions require the same initial latency by always driving RWDS high during the Command-Address to indicate that two initial
latency periods are required. This fixed initial latency is independent of any need for a distributed refresh, it simply provides a fixed
(deterministic) initial latency for all of these transaction types. The fixed latency option may simplify the design of some HyperBus
memory controllers or ensure deterministic transaction performance. Fixed latency is the default POR or reset configuration. The
system may clear this configuration bit to disable fixed latency and allow variable initial latency with RWDS driven high only when
additional latency for a refresh is required.
Note: 128-Mb dual-die stack only supports fixed latency.
5.2.1.5
Drive Strength
DQ signal line loading, length, and impedance vary depending on each system design. Configuration register bits CR0[14:12]
provide a means to adjust the DQ[7:0] signal output impedance to customize the DQ signal impedance to the system conditions to
minimize high speed signal behaviors such as overshoot, undershoot, and ringing. The default POR or reset configuration value is
000b to select the mid point of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process conditions, nominal
operating voltage (1.8Vor 3V) and 50°C. The impedance values may vary by up to ±80% from the typical values depending on the
Process, Voltage, and Temperature (PVT) conditions. Impedance will increase with slower process, lower voltage, or higher
temperature. Impedance will decrease with faster process, higher voltage, or lower temperature.
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Each system design should evaluate the data signal integrity across the operating voltage and temperature ranges to select the best
drive strength settings for the operating conditions.
5.2.1.6
Deep Power Down
When the HyperRAM device is not needed for system operation, it may be placed in a very low power consuming mode called Deep
Power Down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the DPD mode within tDPDIN time and
all refresh operations stop. The data in RAM is lost, (becomes invalid without refresh) during DPD mode. The next access to the
device driving CS# Low then High, POR, or a reset will cause the device to exit DPD mode. Returning to Standby mode requires
tDPDOUT time. For additional details see Section 6.1.3, Deep Power Down on page 29.
Note: The Deep Power Down option is not supported in 128-Mb dual-die stack.
5.2.2
Configuration Register 1
Configuration Register 1 (CR1) is used to define the distributed refresh interval for this HyperRAM device. The core DRAM array
requires periodic refresh of all bits in the array. This can be done by the host system by reading or writing a location in each row
within a specified time limit. The read or write access copies a row of bits to an internal buffer. At the end of the access the bits in the
buffer are written back to the row in memory, thereby recharging (refreshing) the bits in the row of DRAM memory cells.
However, the host system generally has better things to do than to periodically read every row in memory and keep track that each
row is visited within the required refresh interval for the entire memory array. HyperRAM devices include self-refresh logic that will
refresh rows automatically so that the host system is relieved of the need to refresh the memory. The automatic refresh of a row can
only be done when the memory is not being actively read or written by the host system. The refresh logic waits for the end of any
active read or write before doing a refresh, if a refresh is needed at that time. If a new read or write begins before the refresh is
completed, the memory will drive RWDS high during the Command-Address period to indicate that an additional initial latency time
is required at the start of the new access in order to allow the refresh operation to complete before starting the new access.
The required refresh interval for the entire memory array varies with temperature as shown in Table 5.7, Array Refresh Interval per
Temperature on page 26. This is the time within which all rows must be refreshed. Refresh of all rows could be done as a single
batch of accesses at the beginning of each interval, in groups (burst refresh) of several rows at a time, spread throughout each
interval, or as single row refreshes evenly distributed throughout the interval. The self-refresh logic distributes single row refresh
operations throughout the interval so that the memory is not busy doing a burst of refresh operations for a long period, such that the
burst refresh would delay host access for a long period.
Table 5.7 Array Refresh Interval per Temperature
Device Temperature (°C)
Array Refresh Interval (ms)
Array Rows
8192
Recommended tCMS (µs)
85
64
16
4
1
105
8192
Table 5.8 Configuration Register 1 Bit Assignments
CR1 Bit
Function
Settings (Binary)
000000h — Reserved (default)
15-2
Reserved
Reserved for Future Use. When writing this register, these bits should be
cleared to 0 for future compatibility.
10b — default
4 µs for Industrial temperature range devices
1 µs for Industrial Plus temperature range devices
1-0
Distributed Refresh Interval
11b — 1.5 times default
00b — 2 times default
01b — 4 times default
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The distributed refresh method requires that the host does not do burst transactions that are so long as to prevent the memory from
doing the distributed refreshes when they are needed. This sets an upper limit on the length of read and write transactions so that
the refresh logic can insert a refresh between transactions. This limit is called the CS# low maximum time (tCMS). The tCMS value is
determined by the array refresh interval divided by the number of rows in the array, then reducing this calculation by half to ensure
that a distributed refresh interval cannot be entirely missed by a maximum length host access starting immediately before a
distributed refresh is needed. Because tCMS is set to half the required distributed refresh interval, any series of maximum length host
accesses that delay refresh operations will be catching up on refresh operations at twice the rate required by the refresh interval
divided by the number of rows.
The host system is required to respect the tCMS value by ending each transaction before violating tCMS. This can be done by host
memory controller logic splitting long transactions when reaching the tCMS limit, or by host system hardware or software not
performing a single read or write transaction that would be longer than tCMS
.
As noted in Table 5.7, Array Refresh Interval per Temperature on page 26 the array refresh interval is longer at lower temperatures
such that tCMS could be increased to allow longer transactions. The host system can either use the tCMS value from the table for the
maximum operating temperature or, may determine the current operating temperature from a temperature sensor in the system in
order to set a longer distributed refresh interval.
The host system may also effectively increase the tCMS value by explicitly taking responsibility for performing all refresh and doing
burst refresh reading of multiple sequential rows in order to catch up on distributed refreshes missed by longer transactions.
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6. Interface States
Table 6.1 describes the required value of each signal for each interface state.
Table 6.1 Interface States
Interface State
V
CC / VCC
Q
CS#
CK, CK#
D7-D0
RWDS
RESET#
Power-Off with Hardware Data
Protection (Flash memory)
< VLKO
X
X
High-Z
High-Z
X
Power-On (Cold) Reset
Hardware (Warm) Reset
Interface Standby
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
X
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
L
H
Master Output
Valid
Command-Address
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
L
L
L
T
T
T
X
L
H
H
H
Read Initial Access Latency (data
bus turn around period)
High-Z
High-Z
Write Initial Access Latency (RWDS
turn around period)
High-Z
Slave
Output
Valid
Read data transfer
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
L
L
L
T
T
T
Slave Output Valid
H
H
H
X or T
Master
Output
Valid
Write data transfer with Initial
Latency
Master Output
Valid
X or T
Slave
Output
L or
Write data transfer without Initial
Latency (1)
Master Output
Valid
High-Z
Master or Slave
Output Valid or
High-Z
Active Clock Stop (2)
VCC / VCCQ min
VCC / VCCQ min
L
Idle
X
H
H
Slave Output
High-Z
Deep Power Down(2)
H
X or T
High-Z
Legend
L = V
IL
H = V
IH
X = either V or V
IL
IH
L/H = rising edge
H/L = falling edge
T = Toggling during information transfer
Idle = CK is low and CK# is high.
Valid = all bus signals have stable L or H level
Notes:
1. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The HyperRAM device will always drive RWDS during the
Command-Address period to indicate whether extended latency is required. Since master write data immediately follows the Command-Address period the HyperRAM
device may continue to drive RWDS Low or may take RWDS to High-Z. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do
not use RWDS as a data mask function. All bytes of write data are written (full word writes).
2. Active Clock Stop is described in Section 6.1.2, Active Clock Stop on page 29. DPD is described in Section 6.1.3, Deep Power Down on page 29.
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6.1
Power Conservation Modes
Interface Standby
6.1.1
Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CS#= High). All
inputs, and outputs other than CS# and RESET# are ignored in this state.
6.1.2
Active Clock Stop
The Active Clock Stop mode reduces device interface energy consumption to the ICC6 level during the data transfer portion of a read
or write operation. The device automatically enables this mode when clock remains stable for tACC + 30 ns. While in Active Clock
Stop mode, read data is latched and always driven onto the data bus. ICC6 shown in Section 7.4, DC Characteristics on page 33.
Active Clock Stop mode helps reduce current consumption when the host system clock has stopped to pause the data transfer.
Even though CS# may be Low throughout these extended data transfer cycles, the memory device host interface will go into the
Active Clock Stop current level at tACC + 30 ns. This allows the device to transition into a lower current mode if the data transfer is
stalled. Active read or write current will resume once the data transfer is restarted with a toggling clock. The Active Clock Stop mode
must not be used in violation of the tCSM limit. CS# must go high before tCSM is violated.
6.1.3
Deep Power Down
In the Deep Power Down (DPD) mode, current consumption is driven to the lowest possible level (iDPD). DPD mode is entered by
writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop. The data in Memory Space is
lost, (becomes invalid without refresh) during DPD mode. The next access to the device, driving CS# Low then High, will cause the
device to exit DPD mode. A read or write transaction used to drive CS# Low then High to exit DPD mode is a dummy transaction that
is ignored by the device. Also, POR, or a hardware reset will cause the device to exit DPD mode. Only the CS# and RESET# signals
are monitored during DPD mode. Returning to Standby mode following a dummy transaction or reset requires tDPDOUT time.
Returning to Standby mode following a POR requires tVCS time, as with any other POR. Following the exit from DPD due to any of
these events, the device is in the same state as following POR.
Table 6.2 Deep Power Down Timing Parameters
Parameter
tDPDIN
Description
Min
10
Max
Unit
µs
Deep Power Down CR0[15]=0 register write to DPD power level
Length of CS# Low period to cause an exit from Deep Power Down
CS# Low then High to Standby wakeup time
tDPDCSL
tDPDOUT
200
ns
150
µs
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Figure 6.1 Deep Power Down Entry Timing
CS#
CK, CK#
DQ[7:0]
tDPDIN
Enter DPD Mode DPD mode
Phase
Write Command-Address
CR Value
Figure 6.2 Deep Power Down CS# Exit Timing
tDPDCSL
CS#
CK, CK#
DQ[7:0]
tDPDOUT
Phase
Exit DPD Mode
Standby
New Transaction
DPD mode
Dummy Transaction to Exit DPD
Note: The Deep Power Down option is not supported in 128-Mb dual-die stack.
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7. Electrical Specifications
7.1
Absolute Maximum Ratings
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
Voltage with Respect to Ground
All signals (1)
65 °C to +150 °C
65°C to +115 °C
0.5V to +(VCC + 0.5V)
100 mA
Output Short Circuit Current (2)
VCC
0.5V to +4.0V
Notes:
1. Minimum DC voltage on input or I/O signal is 1.0V. During voltage transitions, input or I/O signals may undershoot VSS
to -1.0V for periods of up to 20 ns. See Figure 7.1. Maximum DC voltage on input or I/O signals is VCC +1.0V. During
voltage transitions, input or I/O signals may overshoot to VCC +1.0V for periods up to 20 ns. See Figure 7.2.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one
second.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
7.1.1
Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VDD. During voltage transitions, inputs or I/Os
may negative overshoot VSS to 1.0V or positive overshoot to VDD +1.0V, for periods up to 20 ns.
Figure 7.1 Maximum Negative Overshoot Waveform
VSSQ to VCC
Q
- 1.0V
20 ns
≤
Figure 7.2 Maximum Positive Overshoot Waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCC
Q
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7.2
Latchup Characteristics
Table 7.1 Latchup Specification
Description
Min
1.0
1.0
100
Max
Unit
V
Input voltage with respect to VSSQ on all input only connections
Input voltage with respect to VSSQ on all I/O connections
VCCQ Current
VCCQ + 1.0
VCCQ + 1.0
+100
V
mA
Note:
1. Excludes power supplies V /V Q. Test conditions: V
CC CC CC
= V Q = 1.8 V, one connection at a time tested, connections not being tested are at V
CC
.
SS
7.3
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
7.3.1
Temperature Ranges
Spec
Parameter
Symbol
Device
Unit
Min
–40
–40
–40
–40
Max
85
Industrial (I)
Industrial Plus (V)
105
85
Ambient Temperature
TA
°C
Automotive, AEC-Q100 Grade 3 (A)
Automotive, AEC-Q100 Grade 2 (B)
105
7.3.2
Power Supply Voltages
VCC and VCC
VCC and VCC
Q
Q
1.7v to 1.95V
2.7V to 3.6V
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7.4
DC Characteristics
Table 7.2 DC Characteristics (CMOS Compatible)
64 Mb
128 Mb
Parameter
Description
Test Conditions
Typ
(1)
Typ
(1)
Min
Max Min
Max
Unit
Input Leakage Current
3V Device Reset Signal High Only VCC = VCC max
VIN = VSS to VCC
,
ILI
0.1
0.1
0.2 µA
0.2 µA
Input Leakage Current
VIN = VSS to VCC
1.8V Device Reset Signal High
VCC = VCC max
,
ILI
Only
Input Leakage Current
VIN = VSS to VCC
,
ILI
3V Device Reset Signal Low Only
+20.0
+20.0
+40.0 µA
+40.0 µA
VCC = VCC max
(2)
Input Leakage Current
1.8V Device Reset Signal Low
Only (2)
VIN = VSS to VCC
VCC = VCC max
,
ILI
CS# = VIL, @166 MHz, VCC
1.9V
=
=
=
=
20
20
15
60
35
60
20.1 60.3 mA
20.1 35.3 mA
15.1 60.3 mA
15.1 35.3 mA
ICC1
VCC Active Read Current
VCC Active Write Current
CS# = VIL, @100 MHz, VCC
3.6V
CS# = VIL, @166 MHz, VCC
1.9V
ICC2
CS# = VIL, @100 MHz, VCC
3.6V
15
35
VCC Standby Current for Industrial
(40 °C to +85 °C)
VCC Standby Current for Industrial
Plus
(40 °C to +105 °C)
ICC4I
ICC4IP
ICC5
CS# = VIH, VCC = VCC max,
135
200
270
270
20
400
600
40
µA
µA
CS# = VIH, VCC = VCC max
135
10
5.3
5.3
300
20
8
CS# = VIH, RESET# = VIL,
VCC = VCC max
Reset Current
mA
mA
Active Clock Stop Current for
Industrial
(40 °C to +85 °C)
CS# = VIL, RESET# = VIH,
VCC = VCC max
ICC6I
ICC6IP
ICC7
5.4
5.4
8.2
Active Clock Stop Current for
CS# = VIL, RESET# = VIH,
12
35
12.3 mA
Industrial Plus(40 °C to +105 °C) VCC = VCC max
CS# = VIH, VCC = VCC max,
VCC = VCCQ = 1.95V or 3.6V
VCC Current during power up (1)
70
mA
(Note 7.4.1)
Deep Power Down Current 3V
85°C
CS# = VIH, VCC = 3.6V, TA =
85 °C
IDPD
IDPD
IDPD
IDPD
20
10
40
20
N/A
N/A
N/A
N/A
µA
µA
µA
µA
Deep Power Down Current 1.8V
85°C
CS# = VIH, VCC = 1.9V, TA =
85 °C
Deep Power Down Current 3V
105°C
CS# = VIH, VCC = 3.6V, TA =
105 °C
Deep Power Down Current 1.8V
105°C
CS# = VIH, VCC = 1.9V, TA =
105 °C
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Table 7.2 DC Characteristics (CMOS Compatible) (Continued)
64 Mb
128 Mb
Parameter
Description
Test Conditions
Typ
(1)
Typ
(1)
Min
Max Min
Max
Unit
0.3 x
-0.5
VCC
0.3 x
VCC
VIL
Input Low Voltage
-0.5
V
0.7 x
VCC
VCC 0.7 x
+ 0.3 VCC
VCC
+ 0.3
VIH
Input High Voltage
Output Low Voltage
V
V
0.15
x
VCC
0.15
x
VCC
VOL
IOL = 100 µA for DQ[7:0]
IOH = 100 µA for DQ[7:0]
0.85
x
VCC
0.85
x
VCC
VOH
Output High Voltage
V
Notes:
1. Not 100% tested.
2. RESET# low initiates exits from DPD mode and initiates the draw of I
reset current, making I during Reset# Low insignificant.
LI
CC5
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7.4.1
Capacitance Characteristics
Table 7.3 1.8V Capacitive Characteristics
64 Mb
128 Mb
Description
Parameter
Min
3
Max
4.5
0.25
4
Min
6
Max
9
Unit
pF
Input Capacitance (CK, CK#, CS#)
Delta Input Capacitance (CK, CK#)
Output Capacitance (RWDS)
IO Capacitance (DQx)
CI
CID
CO
0.5
8
pF
3
6
pF
CIO
CIOD
3
4
6
8
pF
IO Capacitance Delta (DQx)
0.5
1
pF
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. V
applied and all other signals (except the signal under test) floating. DQ’s should be in the high impedance state.
V
Q are
CC
CC,
3. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance values to allow for signal propagation
time matching in the system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active
(Low) and data being presented on the DQs bus.
Table 7.4 3.0V Capacitive Characteristics
64 Mb
128 Mb
Description
Input Capacitance (CK, CS#)
Output Capacitance (RWDS)
IO Capacitance (DQx)
IO Capacitance Delta (DQx)
Notes:
Parameter
CI
Min
3
Max
4.5
4
Min
6
Max
Unit
pF
9
8
8
1
CO
3
6
pF
CIO
3
4
6
pF
CIOD
0.5
pF
1. These values are guaranteed by design and are tested on a sample basis only.
2. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. V
applied and all other signals (except the signal under test) floating. DQ’s should be in the high impedance state.
V
Q are
CC
CC,
3. The capacitance values for the CK, RWDS and DQx signals must have similar capacitance values to allow for signal propagation time matching
in the system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active (Low) and data
being presented on the DQs bus.
7.5
Power-Up Initialization
HyperRAM products include an on-chip voltage sensor used to launch the power-up initialization process. VCC and VCCQ must be
applied simultaneously. When the power supply reaches a stable level at or above VCC(min), the device will require tVCS time to
complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is reached during
power-up, and then CS# must remain high for a further delay of tVCS. A simple pull-up resistor from VCCQ to Chip Select (CS#) can
be used to insure safe and proper power-up.
If RESET# is Low during power up, the device delays start of the tVCS period until RESET# is High. The tVCS period is used primarily
to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
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Figure 7.3 Power-up with RESET# High
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 7.4 Power-up with RESET# Low
Vcc_VccQ
CS#
VCC Minimum
Device
Access Allowed
tVCS
RESET#
Table 7.5 Power Up and Reset Parameters
Parameter
Description
1.8V VCC Power Supply
Min
Max
1.95
3.6
Unit
V
VCC
VCC
1.7
2.7
3V VCC Power Supply
V
VCC and VCCQ minimum and RESET# High to first
access
tVCS
150
µs
Notes:
1. Bus transactions (read and write) are not allowed during the power-up reset time (t
).
VCS
2.
3.
V
V
Q must be the same voltage as V
.
CC
CC
CC
ramp rate may be non-linear.
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7.6
Power Down
HyperRAM devices are considered to be powered-off when the core power supply (VCC) drops below the VCC Lock-Out voltage
(VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or equal to VCC. At the VLKO level, the
HyperRAM device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC VCCQ).
During Power-Down or voltage drops below VLKO, the core power supply voltages must also drop below VCC Reset (VRST) for a
Power Down period (tPD) for the part to initialize correctly when the power supply again rises to VCC minimum. See Figure 7.5.
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is again above VCC
minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no assurance that the POR process
will be performed. In this case, a hardware reset will be required ensure the HyperBus device is properly initialized.
Figure 7.5 Power Down or Voltage Drop
V
(Max)
(Min)
CC
V
CC
No Device Access Allowed
V
CC
Device Access
Allowed
t
VCS
V
LKO
V
RST
t
PD
Time
The following section describes HyperRAM device dependent aspects of power down specifications.
Table 7.6 1.8V Power-Down Voltage and Timing
Symbol
VCC
Parameter
Min
1.7
1.7
0.8
30
Max
1.95
Unit
V
VCC Power Supply
VLKO
VRST
tPD
VCC Lock-out below which re-initialization is required
VCC Low Voltage needed to ensure initialization will occur
Duration of VCC VRST
V
V
µs
Note:
1.
V
ramp rate can be non-linear.
CC
Table 7.7 3.0V Power-Down Voltage and Timing
Symbol
VCC
Parameter
Min
2.7
2.7
0.8
50
Max
3.6
Unit
V
VCC Power Supply
VLKO
VRST
tPD
VCC Lock-out below which re-initialization is required
VCC Low Voltage needed to ensure initialization will occur
Duration of VCC VRST
V
V
µs
Note:
1.
V
ramp rate can be non-linear.
CC
Document Number: 001-97964 Rev. *I
Page 37 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
7.7
Hardware Reset
The RESET# input provides a hardware method of returning the device to the standby state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held Low beyond tRPH, the device draws CMOS standby
current (ICC4). While RESET# is Low (during tRP), and during tRPH, bus transactions are not allowed.
A hardware reset will:
cause the configuration registers to return to their default values,
halt self-refresh operation while RESET# is low,
and force the device to exit the Deep Power Down state.
After RESET# returns High, the self-refresh operation will resume. Because self-refresh operation is stopped during RESET# Low,
and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required array refresh
interval per Table 5.7, Array Refresh Interval per Temperature on page 26. This may result in the loss of DRAM array data during or
immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware reset and reload
any required data.
Figure 7.6 Hardware Reset Timing Diagram
tRP
RESET#
tVCS - if RESET# Low > tRP max
tRH
tRPH
CS#
Table 7.8 Power Up and Reset Parameters
Parameter
tRP
Description
RESET# Pulse Width
Min
200
200
400
Max
Unit
ns
tRH
Time between RESET# (high) and CS# (low)
RESET# Low to CS# Low
ns
tRPH
ns
Document Number: 001-97964 Rev. *I
Page 38 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
8. Timing Specifications
The following section describes HyperRAM device dependent aspects of timing specifications.
8.1
Key to Switching Waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
8.2
AC Test Conditions
Figure 8.1 Test Setup
Device
Under
Test
CL
Table 8.1 Test Specification
Parameter
All Speeds
Units
pF
V/ns
V
Output Load Capacitance, CL
20
Minimum Input Rise and Fall Slew Rates (Note 1)
Input Pulse Levels
2.0
0.0-VCC
Q
Input timing measurement reference levels
Output timing measurement reference levels
VCCQ/2
VCCQ/2
V
V
Notes:
1. All AC timings assume an input slew rate of 2V/ns. CK/CK# differential slew rate of at least 4V/ns.
2. Input and output timing is referenced to V Q/2 or to the crossing of CK/CK#.
CC
Figure 8.2 Input Waveforms and Measurement Levels
VccQ
Vss
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Note:
1. Input timings for the differential CK/CK# pair are measured from clock crossings.
Document Number: 001-97964 Rev. *I
Page 39 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
8.3
AC Characteristics
Read Transactions
8.3.1
Table 8.2 HyperRAM Specific 1.8V Read Timing Parameters
166 MHz
133 MHz
100 MHz
Unit
Parameter
Symbol
Min
Max
–
Min
Max
–
Min
10.0
40
Max
–
Chip Select High Between Transactions
HyperRAM Read-Write Recovery Time
tCSHI
tRWR
6
7.5
ns
ns
36
37.5
Chip Select Setup to next CK Rising
Edge
tCSS
3
–
3
–
3
–
ns
Data Strobe Valid
tDSV
tIS
–
12
–
–
0.8
0.8
37.5
0
12
–
–
12
–
ns
ns
ns
ns
ns
Input Setup
0.6
0.6
36
0
1.0
1.0
40
0
Input Hold
tIH
–
–
–
HyperRAM Read Initial Access Time
Clock to DQs Low Z
tACC
tDQLZ
–
–
–
CK transition to DQ Valid (64 Mb)
CK transition to DQ Valid (128 Mb)
CK transition to DQ Invalid (64 Mb)
CK transition to DQ Invalid (128 Mb)
5.5
6.0
4.6
5.6
5.5
6.0
4.5
5.5
5.5
6.0
4.3
5.3
tCKD
1
0
1
0
1
0
ns
ns
tCKDI
Data Valid (tDV min = the lessor of:
tCKHP min - tCKD max + tCKDI max) or
tDV
1.7
1
–
2.375
1
–
3.3
1
–
ns
ns
t
CKHP min - tCKD min + tCKDI min)
CK transition to RWDS valid (64 Mb)
CK transition to RWDS valid (128 Mb)
RWDS transition to DQ Valid
5.5
6.0
+0.45
+0.45
–
5.5
6.0
+0.6
+0.6
–
5.5
6.0
+0.8
+0.8
–
tCKDS
tDSS
tDSH
tCSH
tDSZ
tOZ
-0.45
-0.6
-0.6
0
-0.8
-0.8
0
ns
ns
ns
ns
ns
RWDS transition to DQ Invalid
-0.45
Chip Select Hold After CK Falling Edge
Chip Select Inactive to RWDS High-Z
Chip Select Inactive to DQ High-Z
0
–
–
6
–
6
–
6
6
–
6
–
6
HyperRAM Chip Select Maximum Low
Time - Industrial Temperature
-
4.0
-
4.0
-
4.0
us
tCSM
HyperRAM Chip Select Maximum Low
Time - Industrial Plus Temperature
-
1.0
-
1.0
-
1.0
us
ns
Refresh Time
tRFH
36
37.5
40
Document Number: 001-97964 Rev. *I
Page 40 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Table 8.3 HyperRAM Specific 3.0V Read Timing Parameters
100 MHz
Unit
Parameter
Symbol
Min
10.0
40
3
Max
–
Chip Select High Between Transactions
HyperRAM Read-Write Recovery Time
Chip Select Setup to next CK Rising Edge
Data Strobe Valid
tCSHI
tRWR
tCSS
tDSV
tIS
ns
ns
ns
ns
ns
ns
ns
ns
-
–
–
12
–
Input Setup
1.0
1.0
40
0
Input Hold
tIH
–
HyperRAM Read Initial Access Time
Clock to DQs Low Z
tACC
tDQLZ
–
–
HyperRAM CK transition to DQ Valid (64 Mb)
HyperRAM CK transition to DQ Valid (128 Mb)
HyperRAM CK transition to DQ Invalid (64 Mb)
HyperRAM CK transition to DQ Invalid (128 Mb)
Data Valid (tDV min = the lessor of:
7
tCKD
1
ns
ns
8
5.2
6.2
tCKDI
0.5
t
t
CKHP min - tCKD max + tCKDI max) or
CKHP min - tCKD min + tCKDI min)
tDV
2.7
1
ns
ns
CK transition to RWDS valid (64 Mb)
CK transition to RWDS valid (128 Mb)
RWDS transition to DQ Valid
7
8
tCKDS
tDSS
tDSH
tCSH
tDSZ
tOZ
-0.8
-0.8
0
+0.8
+0.8
–
ns
ns
ns
ns
ns
us
us
ns
RWDS transition to DQ Invalid
Chip Select Hold After CK Falling Edge
Chip Select Inactive to RWDS High-Z
Chip Select Inactive to DQ High-Z
–
7
–
7
HyperRAM Chip Select Maximum Low Time - Industrial Temperature
HyperRAM Chip Select Maximum Low Time - Industrial Plus Temperature
Refresh Time
-
4.0
1.0
tCSM
tRFH
-
40
Document Number: 001-97964 Rev. *I
Page 41 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Figure 8.3 Read Timing Diagram — No Additional Latency Required
tCSHI
tCSM
CS#
tCSS
tCSH
tCSS
tRWR =Read Write Recovery
tACC = Access
4 cycle latency
CK, CK#
RWDS
tDSV
tCKDS
tDSZ
High = 2x Latency Count
Low = 1x Latency Count
tDSS
tOZ
tIS
tIH
tDQLZ
tCKD
tDSH
Dn
A
Dn
Dn+1 Dn+1
DQ[7:0]
47:40 39:32 31:24 23:16 15:8 7:0
B
A
B
RWDS and Data
are edge aligned
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Document Number: 001-97964 Rev. *I
Page 42 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
8.3.2
Write Transactions
Table 8.4 1.8V Write Timing Parameters
166 MHz
133 MHz
100 MHz
Unit
Parameter
Symbol
Min
Max
Min
Max
Min
40
Max
Read-Write Recovery Time
Access Time
tRWR
tACC
tRFH
36
36
36
37.5
37.5
37.5
ns
ns
ns
40
Refresh Time
40
Chip Select Maximum Low Time
4.0
1.0
4.0
1.0
4.0
1.0
µs
µs
Industrial Temperature
tCSM
Chip Select Maximum Low Time
Industrial Plus Temperature
Table 8.5 3.0V Write Timing Parameters
100 MHz
Parameter
Symbol
Unit
Min
40
40
40
Max
Read-Write Recovery Time
Access Time
tRWR
tACC
tRFH
ns
ns
ns
µs
µs
Refresh Time
Chip Select Maximum Low Time Industrial Temperature
Chip Select Maximum Low Time Industrial Plus Temperature
4.0
1.0
tCSM
Figure 8.4 Write Timing Diagram — No Additional Latency
tCSHI
tCSM
CS#
CK,CK#
RWDS
tCSS
tRWR =Read Write Recovery
tCSH
tCSS
tACC = Access
tDSV
4 cycle latency
tDSZ
tIS
tDMV
tIH
High = 2x Latency Count
Low = 1x Latency Count
tIS
tIS
tIH
tIH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
39:32 31:24 23:16 15:8
7:0
DQ[7:0]
47:40
Command-Address
CK and Data
are center aligned
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Document Number: 001-97964 Rev. *I
Page 43 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
9. Physical Interface
9.1
FBGA 24-Ball 5 x 5 Array Footprint
HyperRAM devices are provided in Fortified Ball Grid Array (FBGA), 1 mm pitch, 24-ball, 5 x 5 ball array footprint, with 6mm x 8mm
body.
Figure 9.1 24-Ball FBGA, 6 x 8 mm, 5x5 Ball Footprint, Top View
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
RFU
RFU
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Notes:
1. B1 is assigned to CK# on the 1.8V device.
2. B1 is a RFU on the 3.0V device.
Document Number: 001-97964 Rev. *I
Page 44 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
9.2
Physical Diagrams
9.2.1
Fortified Ball Grid Array 24-ball 6 x 8 x 1.0 mm (VAA024)
NOTES:
DIMENSIONS
SYMBOL
MIN.
-
NOM.
MAX.
1.00
-
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
A
-
-
A1
D
0.20
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D1
E1
MD
ME
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
5
24
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
b
0.35
0.45
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
JEDEC SPECIFICATION NO. REF: N/A
10.
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 24 BALL BGA
8.0X6.0X1.0 MM VAA024/ELA024/E2A024
DRAWN BY
KOTA
DATE
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
SPEC NO.
REV
30-AUG-16
PACKAGE
CODE(S)
002-15550
SCALE :
TO FIT
VAA024 ELA024 E2A024
APPROVED BY
BESY
DATE
*A
30-AUG-16
SHEET
OF
1
2
Document Number: 001-97964 Rev. *I
Page 45 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
10. DDR Center Aligned Read Strobe (DCARS) Functionality
The HyperRAM device offers an optional feature that enables independent skewing (phase shifting) of the RWDS signal with respect
to the read data outputs. This feature is provided in certain devices, based on the Ordering Part Number (OPN).
When the DDR Center Aligned Read Strobe (DCARS) feature is provided, a second differential Phase Shifted Clock input PSC/
PSC# is used as the reference for RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase
shifted 90 degrees to place the RWDS edges centered within the DQ signals valid data window. However, other degrees of phase
shift between CK/CK# and PSC/PSC# may be used to optimize the position of RWDS edges within the DQ signals valid data
window so that RWDS provides the desired amount of data setup and hold time in relation to RWDS edges.
PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven Low and High respectively or, both may be driven
Low during write transactions.
The PSC/PSC# differential clock is used only in HyperBus devices with 1.8 V nominal core and I/O voltage. HyperBus devices with
3 V nominal core and I/O voltage use only PSC as a single-ended clock.
10.1 HyperRAM Products with DCARS Signal Descriptions
Figure 10.1 HyperBus Product with DCARS Signal Diagram
RESET#
VCC
VCCQ
CS#
CK
DQ[7:0]
RWDS
CK#
PSC
PSC#
VSS
VSSQ
Signal Descriptions
Symbol
Type
Description
Chip Select. HyperBus transactions are initiated with a High to Low transition. HyperBus transactions
are terminated with a Low to High transition.
CS#
Input
Differential Clock. Command-Address/Data information is input or output with respect to the crossing
of the CK and CK# signals. CK# is not used on the 3.0 V device, only a single ended CK is used.
CK, CK# Input
Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS signal with respect to
the CK/CK# inputs. PSC# is only used on the 1.8 V device. PSC (and PSC#) may be driven High and
Low respectively or both may be driven Low during write transactions.
PSC,
Input
PSC#
Read-Write Data Strobe. Data bytes output during read transactions are aligned with RWDS based
on the phase shift from CK, CK# to PSC, PSC#. PSC, PSC# cause the transitions of RWDS, thus the
phase shift from CK, CK# to PSC, PSC# is used to place RWDS edges within the data valid window.
RWDS is an input during write transactions to function as a data mask. At the beginning of all bus
transactions RWDS is an output and indicates whether additional initial latency count is required
(1 = additional latency count, 0 = no additional latency count).
RWDS
Output
Data Input/Output. Command-Address/Data information is transferred on these DQs during Read
and Write transactions.
DQ[7:0] Input/Output
RESET# Input
Hardware RESET. When Low the device will self initialize and return to the idle state. RWDS and
DQ[7:0] are placed into the High-Z state when RESET# is Low. RESET# includes a weak pull-up, if
RESET# is left unconnected it will be pulled up to the High state.
VCC
VCC
VSS
Power Supply
Power Supply
Power Supply
Power Supply
Power.
Q
Input/Output Power.
Ground.
VSSQ
Input/Output Ground.
Document Number: 001-97964 Rev. *I
Page 46 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
10.2 HyperRAM Products with DCARS — FBGA 24-ball, 5x5 Array Footprint
Figure 10.2 24-ball FBGA, 5x5 Ball Footprint, Top View
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
PCS
PCS#
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Notes:
1. B1 is an RFU on the 3.0 V device and is assigned to CK# on the 1.8 V device.
2. C5 is an RFU on the 3.0 V device and is assigned to PSC# on the 1.8 V device.
10.3 HyperRAM Memory with DCARS Timing
The illustrations and parameters shown here are only those needed to define the DCARS feature and show the relationship between
the Phase Shifted Clock, RWDS, and data.
Figure 10.3 HyperRAM Memory DCARS Timing Diagram
tCSHI
CS#
tCSH
tCSS
tCSS
tACC = Access time
4 cycle latency
CK, CK#
PSC, PSC#
RWDS
tDSV
tPSCRWDS
tDSZ
High = 2x Latency Count
Low = 1x Latency Count
tIS
tIH
tDQLZ
tCKD
tOZ
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
RWDS aligned
by PSC
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Notes:
1. Transactions must be initiated with CK = Low and CK# = High. CS# must return High before a new transaction is initiated.
2. CK# and PSC# are only used on the 1.8 V device. The 3 V device uses a single ended CK and PSC input.
3. The memory drives RWDS during read transactions.
4. This example demonstrates a latency code setting of four clocks and no additional initial latency required.
Document Number: 001-97964 Rev. *I
Page 47 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Figure 10.4 DCARS Data Valid Timing
CS#
tCKHP
tCSH
tCSS
CK,CK#
PSC,PSC#
tPSCRWDS
tDSZ
RWDS
tCKDI
tCKD
tDQLZ
tDV
tOZ
tCKD
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
RWDS and Data are driven by the memory
Notes:
1. This figure shows a closer view of the data transfer portion of Figure 10.1, HyperBus Product with DCARS Signal Diagram on page 46 in order to more clearly show
the Data Valid period as affected by clock jitter and clock to output delay uncertainty.
2. CK# and PSC# are only used on the 1.8 V device. The 3 V device uses a single ended CK and PSC input.
3. The delay (phase shift) from CK to PSC is controlled by the HyperBus master interface (Host) and is generally between 40 and 140 degrees in order to place the
RWDS edge within the data valid window with sufficient set-up and hold time of data to RWDS. The requirements for data set-up and hold time to RWDS are
determined by the HyperBus master interface design and are not addressed by the HyperBus slave timing parameters.
4. The HyperBus timing parameters of t
, and t
define the beginning and end position of the data valid period. The t
and t
values track together (vary by the
CKDI
CKD
CKDI
CKD
same ratio) because RWDS and Data are outputs from the same device under the same voltage and temperature conditions.
DCARS Read Timings (3.0 V)
100 MHz
Parameter
Symbol
Unit
Min
Max
7
HyperRAM PSC transition to RWDS transition
tPSCRWDS
1
ns
ns
Time delta between CK to DQ valid and PSC to RWDS
tPSCRWDS - tCKD
-1.0
+0.5
Note:
1. Sampled, not 100% tested.
DCARS Read Timings (1.8 V)
133 MHz
100 MHz
Parameter
Symbol
Unit
Min
Max
Min
Max
HyperRAM PSC transition to RWDS transition
tPSCRWDS
1
5.5
1
5.5
ns
ns
Time delta between CK to DQ valid and PSC to
RWDS
tPSCRWDS - tCKD
-1.0
+0.5
-1.0
+0.5
Note:
1. Sampled, not 100% tested.
Document Number: 001-97964 Rev. *I
Page 48 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
11. Ordering Information
11.1 Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S27KS 064
1
DP
B
H
I
02
0
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
02 = Standard 6 8 1.0 mm package (VAA024)
03 = DDR Center Aligned Read Strobe (DCARS) 6 8 1.0 mm package
(VAA024)
Temperature Range / Grade
I = Industrial (–40 °C to + 85 °C)
V = Industrial Plus (–40 °C to + 105 °C)
A = Automotive, AEC-Q100 Grade 3 (–40 °C to + 85 °C)
B = Automotive, AEC-Q100 Grade 2 (–40 °C to + 105 °C)
Package Materials
H = Low-Halogen, Lead (Pb)-free
Package Type
B = 24-ball FBGA, 1.00 mm pitch (5x5 ball footprint)
Speed
DA = 100 MHz
DG = 133 MHz
DP = 166 MHz
Device Technology
1 = 63 nm DRAM Process Technology
Density
064 = 64 Mb
128 = 128Mb
Device Family
S27KS, S70KS
Cypress Memory 1.8V-only, HyperRAM Self-refresh DRAM
S27KL, S70KL
Cypress Memory 3.0V-only, HyperRAM Self-refresh DRAM
Document Number: 001-97964 Rev. *I
Page 49 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
11.2 Valid Combinations
The Recommended Combinations table lists configurations planned to be available in volume. The table below will be updated as
new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check
on newly released combinations.
Table 11.1 Valid Combinations — Standard
Package,
Device
Family
Model Packing
Density Technology Speed Material and
Ordering Part Number Package Marking
Number
Type
Temperature
S27KL
S27KL
S27KL
S27KL
S70KL
S70KL
S70KL
S70KL
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHI
BHI
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KL0641DABHI020
S27KL0641DABHI023
7KL0641DAHI02
7KL0641DAHI02
BHV
BHV
BHI
S27KL0641DABHV020 7KL0641DAHV02
S27KL0641DABHV023 7KL0641DAHV02
S70KL1281DABHI020
S70KL1281DABHI023
7KL1281DAHI02
7KL1281DAHI02
BHI
BHV
BHV
S70KL1281DABHV020 7KL1281DAHV02
S70KL1281DABHV023 7KL1281DAHV02
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DP
DP
DP
DP
DP
DP
DP
DP
BHI
BHI
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KS0641DPBHI020
S27KS0641DPBHI023
7KS0641DPHI02
7KS0641DPHI02
BHV
BHV
BHI
S27KS0641DPBHV020 7KS0641DPHV02
S27KS0641DPBHV023 7KS0641DPHV02
S70KS1281DPBHI020
S70KS1281DPBHI023
7KS1281DPHI02
7KS1281DPHI02
BHI
BHV
BHV
S70KS1281DPBHV020 7KS1281DPHV02
S70KS1281DPBHV023 7KS1281DPHV02
Document Number: 001-97964 Rev. *I
Page 50 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Table 11.2 Valid Combinations — DCARS
Package,
Device
Family
Model Packing
Density Technology Speed Material and
Temperature
Ordering Part Number Package Marking
Number
Type
S27KL
S27KL
S27KL
S27KL
S70KL
S70KL
S70KL
S70KL
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHI
BHI
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KL0641DABHI030
S27KL0641DABHI033
7KL0641DAHI03
7KL0641DAHI03
BHV
BHV
BHI
S27KL0641DABHV030 7KL0641DAHV03
S27KL0641DABHV033 7KL0641DAHV03
S70KL1281DABHI030
S70KL1281DABHI033
7KL1281DAHI03
7KL1281DAHI03
BHI
BHV
BHV
S70KL1281DABHV030 7KL1281DAHV03
S70KL1281DABHV033 7KL1281DAHV03
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHI
BHI
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KS0641DABHI030
S27KS0641DABHI033
7KS0641DAHI03
7KS0641DAHI03
BHV
BHV
BHI
S27KS0641DABHV030 7KS0641DAHV03
S27KS0641DABHV033 7KS0641DAHV03
S70KS1281DABHI030
S70KS1281DABHI033
7KS1281DAHI03
7KS1281DAHI03
BHI
BHV
BHV
S70KS1281DABHV030 7KS1281DAHV03
S70KS1281DABHV033 7KS1281DAHV03
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DG
DG
DG
DG
DG
DG
DG
DG
BHI
BHI
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KS0641DGBHI030
S27KS0641DGBHI033
7KS0641DGHI03
7KS0641DGHI03
BHV
BHV
BHI
S27KS0641DGBHV030 7KS0641DGHV03
S27KS0641DGBHV033 7KS0641DGHV03
S70KS1281DGBHI030
S70KS1281DGBHI033
7KS1281DGHI03
7KS1281DGHI03
BHI
BHV
BHV
S70KS1281DGBHV030 7KS1281DGHV03
S70KS1281DGBHV033 7KS1281DGHV03
Document Number: 001-97964 Rev. *I
Page 51 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
11.3 Valid Combinations — Automotive Grade / AEC-Q100
The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The
table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 11.3 Valid Combinations — Automotive Grade / AEC-Q100
Package,
Device
Family
Model Packing
Density Technology Speed Material and
Temperature
Ordering Part Number Package Marking
Number
Type
S27KL
S27KL
S27KL
S27KL
S70KL
S70KL
S70KL
S70KL
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHA
BHA
BHB
BHB
BHA
BHA
BHB
BHB
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KL0641DABHA020 7KL0641DAHA02
S27KL0641DABHA023 7KL0641DAHA02
S27KL0641DABHB020 7KL0641DAHB02
S27KL0641DABHB023 7KL0641DAHB02
S70KL1281DABHA020 7KL1281DAHA02
S70KL1281DABHA023 7KL1281DAHA02
S70KL1281DABHB020 7KL1281DAHB02
S70KL1281DABHB023 7KL1281DAHB02
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DP
DP
DP
DP
DP
DP
DP
DP
BHA
BHA
BHB
BHB
BHA
BHA
BHB
BHB
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KS0641DPBHA020 7KS0641DPHA02
S27KS0641DPBHA023 7KS0641DPHA02
S27KS0641DPBHB020 7KS0641DPHB02
S27KS0641DPBHB023 7KS0641DPHB02
S70KS1281DPBHA020 7KS1281DPHA02
S70KS1281DPBHA023 7KS1281DPHA02
S70KS1281DPBHB020 7KS1281DPHB02
S70KS1281DPBHB023 7KS1281DPHB02
Document Number: 001-97964 Rev. *I
Page 52 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Table 11.4 Valid Combinations — DCARS Automotive Grade / AEC-Q100
Package,
Device
Family
Model Packing
Density Technology Speed Material and
Temperature
Ordering Part Number Package Marking
Number
Type
S27KL
S27KL
S27KL
S27KL
S70KL
S70KL
S70KL
S70KL
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHA
BHA
BHB
BHB
BHA
BHA
BHB
BHB
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KL0641DABHA030 7KL0641DAHA03
S27KL0641DABHA033 7KL0641DAHA03
S27KL0641DABHB030 7KL0641DAHB03
S27KL0641DABHB033 7KL0641DAHB03
S70KL1281DABHA030 7KL1281DAHA03
S70KL1281DABHA033 7KL1281DAHA03
S70KL1281DABHB030 7KL1281DAHB03
S70KL1281DABHB033 7KL1281DAHB03
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DA
DA
DA
DA
DA
DA
DA
DA
BHA
BHA
BHB
BHB
BHA
BHA
BHB
BHB
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KS0641DABHA030 7KS0641DAHA03
S27KS0641DABHA033 7KS0641DAHA03
S27KS0641DABHB030 7KS0641DAHB03
S27KS0641DABHB033 7KS0641DAHB03
S70KS1281DABHA030 7KS1281DAHA03
S70KS1281DABHA033 7KS1281DAHA03
S70KS1281DABHB030 7KS1281DAHB03
S70KS1281DABHB033 7KS1281DAHB03
S27KS
S27KS
S27KS
S27KS
S70KS
S70KS
S70KS
S70KS
064
064
064
064
128
128
128
128
1
1
1
1
1
1
1
1
DG
DG
DG
DG
DG
DG
DG
DG
BHA
BHA
BHB
BHB
BHA
BHA
BHB
BHB
03
03
03
03
03
03
03
03
0
3
0
3
0
3
0
3
S27KS0641DGBHA030 7KS0641DGHA03
S27KS0641DGBHA033 7KS0641DGHA03
S27KS0641DGBHB030 7KS0641DGHB03
S27KS0641DGBHB033 7KS0641DGHB03
S70KS1281DGBHA030 7KS1281DGHA03
S70KS1281DGBHA033 7KS1281DGHA03
S70KS1281DGBHB030 7KS1281DGHB03
S70KS1281DGBHB033 7KS1281DGHB03
Document Number: 001-97964 Rev. *I
Page 53 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
12. Revision History
Document History Page
Document Title: S27KL0641/S27KS0641/S70KL1281/S70KS1281, 3.0 V/1.8 V, 64 Mbit (8 Mbyte)/128 Mbit (16 Mbyte),
HyperRAM™ Self-Refresh DRAM
Document Number: 001-97964
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
MAMC
MAMC
05/01/2015 Initial release
*A
06/05/2015 Read Transactions: Maximum Operating Frequency For Latency Code
Options table: updated ‘Latency Code’ 0010 values
Device Identification Registers: Updated ‘ID Register 1 Bit Assignments’ table
Electrical Specifications: Updated Ambient Temperature with Power Applied
HyperRAM Hardware Interface: Updated the following:
Power-On Reset: removed section
Power Down: removed section
DC Characteristics (CMOS Compatible) table: updated ICC5, ICC6I, and ICC6IP
Test Conditions
Electrical Specifications/Power Down:
1.8V Power-Down Voltage and Timing table: changed VRST and TPD MIn
3.0V Power-Down Voltage and Timing table: changed VRST and TPD MIn
Key to Switching Waveforms: removed section
AC Test Conditions: removed section
AC Characteristics: updated section
HyperBus Specification: Removed section. Refer to the HyperBus specification
for all non-device specific information on the HyperBus interface.
*B
MAMC
07/10/2015 Physical Interface: Updated section.
Ordering Information: Updated Valid Combinations table.
*C
*D
4854266
5041839
MAMC
MAMC
07/29/2015 Updated to Cypress template.
12/08/2015 Updated Electrical Specifications:
Updated DC Characteristics:
Updated details of ILI parameter.
Added values of IDPD parameter corresponding to “Test Condition” TA = 105°C.
*E
*F
5155616
5327405
RYSU
SZZX
03/01/2016 Added Errata.
06/28/2016 Complete update.
Removed Errata.
*G
5430299
RYSU
09/08/2016 Changed status from “Advance” to “Final”.
Updated Electrical Specifications:
Updated Operating Ranges:
Updated Temperature Ranges:
Added Automotive Grade.
Updated Ordering Information:
Added Valid Combinations — Automotive Grade / AEC-Q100.
Updated to new template.
*H
5500343
SZZX
11/03/2016 Updated Electrical Specifications:
Updated DC Characteristics:
Updated Table 7.2.
Updated Physical Interface:
Updated Physical Diagrams:
Updated Fortified Ball Grid Array 24-ball 6 x 8 x 1.0 mm (VAA024).
Document Number: 001-97964 Rev. *I
Page 54 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Document History Page (Continued)
Document Title: S27KL0641/S27KS0641/S70KL1281/S70KS1281, 3.0 V/1.8 V, 64 Mbit (8 Mbyte)/128 Mbit (16 Mbyte),
HyperRAM™ Self-Refresh DRAM
Document Number: 001-97964
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*I
5560735
SZZX
12/20/2016 Updated Document Title to read as “S27KL0641/S27KS0641/S70KL1281/
S70KS1281, 3.0 V/1.8 V, 64 Mbit (8 Mbyte)/128 Mbit (16 Mbyte), HyperRAM™
Self-Refresh DRAM”.
Added S70KL1281 and S70KS1281 part numbers related information in all
instances across the document.
Updated Performance Summary:
Updated Maximum Current Consumption table.
Added Block Diagram — 128 Mbit.
Updated General Description:
Updated description.
Updated Product Overview:
Updated description.
Updated Memory Space:
Updated Table 4.1.
Updated Register Space:
Updated Table 5.1.
Updated Register Space Access:
Updated Configuration Register 0:
Updated Table 5.4.
Updated Hybrid Burst:
Added Note below Table 5.6.
Updated Fixed Latency:
Updated description.
Updated Deep Power Down:
Updated description.
Updated Interface States:
Updated description.
Updated Electrical Specifications:
Updated DC Characteristics:
Updated Table 7.2.
Updated Capacitance Characteristics:
Updated Table 7.3.
Updated Table 7.4.
Updated Timing Specifications:
Updated AC Characteristics:
Updated Read Transactions:
Updated Table 8.2.
Updated Table 8.3.
Added Figure 8.3.
Updated Write Transactions:
Added Figure 8.4.
Updated Ordering Information:
Updated Ordering Part Number:
Added 128 Mb details.
Updated Valid Combinations on page 50:
Updated Table 11.1.
Updated Table 11.2.
Updated Valid Combinations — Automotive Grade / AEC-Q100:
Updated Table 11.3.
Updated Table 11.4.
Document Number: 001-97964 Rev. *I
Page 55 of 56
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
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cypress.com/arm
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cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
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USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-97964 Rev. *I
Revised December 20, 2016
Page 56 of 56
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