S6AP412AB8GN1C000 [CYPRESS]
3ch DC/DC Converter with I2C Interface and Internal SW FETs;
| 型号： | S6AP412AB8GN1C000 |
| 厂家： | 
CYPRESS |
| 描述： | 3ch DC/DC Converter with I2C Interface and Internal SW FETs |
| 文件： | 总68页 (文件大小：3357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6AP412A
3ch DC/DC Converter with I2C Interface
and Internal SW FETs
S6AP412A contains 2ch buck DC/DC converter and 1ch buck-boost DC/DC converter. One of the buck DC/DC converter is
available for Multi-phase method. Multi-phase DC/DC converter is possible to load high current until 4A. S6AP412A can supply the
main power line in several systems by using only its chip. The current mode control is adopted for the DC/DC converter, and it is
possible to use the small chip inductor with the high switching frequency operation which contains internal switching FETs.
S6AP412A contains the output setting resistor and the phase compensation circuit, and contributes to reduce the number of
external components and its mount area. Also it contains the CTL input pin which can control the ON/OFF for each DC/DC converter,
the Power Good signal output pin and I2C communication interface, therefore it is easy to design the power supply sequence. It is
possible to tune in the output voltage exactly using the I2C communication.
Features
Operating input voltage range: 2.5V to 5.5V (Maximum rating: 6.5V)
Output voltage setting range:
DD1*:0.7V to 1.32V (20mV/step)
DD2*:1.2V to 1.95V (50mV/step)
DD3*:2.8Vto 3.5V (100mV/step)
Maximum output current: DD1:4A, DD2:1.2A, DD3:0.6A
Internal switching FETs, output voltage setting resistor, phase compensation circuit and output discharge resistor (all DC/DC
converters)
Buck-boost DC/DC converter is seamless to change operation mode
Soft start time setting range: 1 ms to 16 ms (approximately 1ms/step)
Switching frequency for the DC/DC converter: 3 MHz
Communication interface: I2C (ON/OFF, Output voltage, Soft start time)
Internal PFM/PWM auto switching mode
Each DC/DC converter Power Good function (open drain)
Several protection functions: Under voltage lockout (UVLO), Over current protection (OCP), Thermal shut down (TSD)
Small package: QFN32 (5mm × 5mm × 0.71mm, 0.5mm pitch)
*: DD1, DD2, DD3 : DC/DC converter block 1,2,3
Applications
Network equipment, Factory automation, Security system, Surveillance camera, Electrical music instrument, Multi-function printer,
Scanner, Printer, Copy machine, Home appliances,Data storage (HDD, SSD), Mobile equipment for Li+ battery (1 cell)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 002-08447 Rev.*A
Revised March 28, 2016
S6AP412A
Contents
1. Application Circuit Example ............................................................................................................................................ 4
2. Recommended Application Specification....................................................................................................................... 5
3. Pin Configuration.............................................................................................................................................................. 7
4. Pin Descriptions................................................................................................................................................................ 8
5. Block Diagram................................................................................................................................................................. 10
6. Absolute Maximum Ratings........................................................................................................................................... 11
7. Recommended Operating Conditions........................................................................................................................... 12
8. Electrical Characteristics ............................................................................................................................................... 13
8.1
8.2
8.3
8.4
8.5
Reference Control Block.............................................................................................................................................. 13
DD1 ............................................................................................................................................................................. 14
DD2 ............................................................................................................................................................................. 15
DD3 ............................................................................................................................................................................. 16
Digital Block................................................................................................................................................................. 17
9. Operation Mode List ....................................................................................................................................................... 18
10. State Transition Diagram................................................................................................................................................ 19
11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3)..................................................................... 20
12. Turning ON and OFF Sequence (AVCC →CTLMAIN→CTL1→CTL2→ CTL3) ............................................................ 21
13. Turning ON and OFF Sequence (AVCC→CTLMAIN→I2C) ........................................................................................... 22
14. CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage.................................................................................................. 23
15. Protection Operation Sequence..................................................................................................................................... 24
16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit..................................................... 25
17. DD Soft Start Operation.................................................................................................................................................. 26
18. Discharge Operation....................................................................................................................................................... 27
19. PG Function..................................................................................................................................................................... 28
20. I2C Interface..................................................................................................................................................................... 29
20.1 Structure of I2C Interface............................................................................................................................................. 29
20.2 Definition of Signal Lines............................................................................................................................................. 29
20.3 Validity of Data ............................................................................................................................................................ 30
20.4 Definition of Start and Stop Condition.......................................................................................................................... 30
20.5 ACK Signal.................................................................................................................................................................. 31
20.6 I2C Interface Input Timing............................................................................................................................................ 32
20.7 Slave Address ............................................................................................................................................................. 33
20.8 Bit Structure of Data on I2C Interface .......................................................................................................................... 34
21. Structure of I2C Interface and Data................................................................................................................................ 36
21.1 About DD1 Output Voltage Setting.............................................................................................................................. 37
21.2 About DD2 Output Voltage Setting.............................................................................................................................. 38
21.3 About DD3 Output Voltage Setting.............................................................................................................................. 39
21.4 About Soft Start Time .................................................................................................................................................. 40
21.5 DC/DC Operation Mode .............................................................................................................................................. 41
21.6 ON/OFF for DC/DC ..................................................................................................................................................... 42
21.7 About Error Monitor ..................................................................................................................................................... 43
21.8 About Power Good Monitor ......................................................................................................................................... 44
22. I/O Pin Equivalent Circuit Diagram................................................................................................................................ 45
23. Measurement Circuit for Characteristics of General Operation ................................................................................. 48
24. Reference Data................................................................................................................................................................ 50
25. Ordering Information ...................................................................................................................................................... 62
26. Preset Code List.............................................................................................................................................................. 63
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 2 of 68
S6AP412A
27. Layout .............................................................................................................................................................................. 64
28. Package Dimensions ...................................................................................................................................................... 65
29. Major Changes ................................................................................................................................................................ 66
Document History................................................................................................................................................................. 67
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 3 of 68
S6AP412A
1. Application Circuit Example
Figure 1. Application Circuit
Document Number: 002-08447 Rev.*A
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S6AP412A
2. Recommended Application Specification
[Input Voltage Range]
Input voltage Vin(V)
Min
Typ
Max
2.5
3.3
5.5
(Ta=+25°C)
[Output specification]
Output Voltage (V)
Min
Typ
Max
Max
Min
0.692 0.700 0.708
0.711 0.720 0.729
0.731 0.740 0.749
0.751 0.760 0.769
0.771 0.780 0.789
0.790 0.800 0.810
0.810 0.820 0.830
0.830 0.840 0.850
0.850 0.860 0.870
0.869 0.880 0.891
0.889 0.900 0.911
(*1)
(*1)
(*1)
0.909 0.920 0.931
0.929 0.940 0.951
0.948 0.960 0.972
0.968 0.980 0.992
0.988 1.000 1.012
1 to 16ms
Multi
PhaseBuilt-in
SWFET
Built-in output
setting resistors
Built-in phase
compensation
circuit
At the
time of
1.0V
setting,
the
details
are cf.
Contents
17
Buck
(synchronous
rectification)
Multi Phase
C-mode
(*1)
(*1)
(*1)
4000
(4800)
3.0
1.0
22
5.0
DD1 VO1 ±1.2%
1.008 1.020 1.032
1.028 1.040 1.052
1.047 1.060 1.073
1.067 1.080 1.093
1.087 1.100 1.113
(*1)
(*1)
(*1)
1.107 1.120 1.133
1.126 1.140 1.154
1.146 1.160 1.174
1.166 1.180 1.194
1.186 1.200 1.214
(*1)
(*1)
(*1)
1.205 1.220 1.235
1.225 1.240 1.255
1.245 1.260 1.275
1.265 1.280 1.295
1.284 1.300 1.316
1.304 1.320 1.336
Document Number: 002-08447 Rev.*A
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Page 5 of 68
S6AP412A
Output Voltage (V)
Min
Typ
Max
Max
Min
1.186
(*1)
1.200
(*1)
1.214
(*1)
1.235
1.284
1.250
1.300
1.265
1.316
1.334
(*1)
1.350
(*1)
1.366
(*1)
1.383
1.433
1.400
1.450
1.417
1.467
1 to 16ms
Built-in SWFET
Built-in output
setting resistors
Built-in phase
compensation
circuit
1.482
(*1)
1.500
(*1)
1.518
(*1)
Buck
At the time
of 1.8V
setting, the
details are
cf. Contents
17
(synchronous
rectification)
C-mode
DD2
VO2 ±1.2%
1200
(1500)
3.0 1.0 10
5.0
1.531
1.581
1.630
1.680
1.729
1.550
1.600
1.650
1.700
1.750
1.569
1.619
1.670
1.720
1.771
1.778
(*1)
1.800
(*1)
1.822
(*1)
1.828
1.877
1.927
1.850
1.900
1.950
1.872
1.923
1.973
2.74
(*1)
2.80
(*1)
2.86
(*1)
2.84
2.90
2.96
1 to 16ms
2.94
(*1)
3.00
(*1)
3.06
(*1)
Built-in SWFET
Built-in output
Buck-boost
(synchronous
rectification)
C-mode
At the time
of 3.3V
setting, the
details are
cf. Contents
17
3.04
3.14
3.10
3.20
3.16
3.26
setting resistors
Built-in phase
DD3
VO3 ±1.8%
600
(750)
3.0 1.0 22
5.0
compensation
circuit
3.23
(*1)
3.30
(*1)
3.37
(*1)
3.33
3.40
3.47
3.43
(*1)
3.50
(*1)
3.57
(*1)
*1: default (It is selectable with the default output voltage)
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 6 of 68
S6AP412A
3. Pin Configuration
(TOP VIEW)
32
31
30
29
28
27
26
25
1
24
23
22
21
20
19
18
17
LX3-2
IN1
2
PGND3
PVCC1A
LX1A
3
LX3-1
4
PVCC3
PGND1A
PGND1B
LX1B
5
PVCC2
6
LX2
7
PGND2
EP(Exposed Pad)
PVCC1B
ADDSEL
8
IN2
9
10
11
12
13
14
15
16
(WNT032)
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March 28, 2016
Page 7 of 68
S6AP412A
4. Pin Descriptions
Pin
Num
ber
Unus
ed
DD1
Pull-
down
Resistor
Unused
I2C
Pin
Block
Unused Unused
DD2 DD3
I/O
Description
Name
IN1
24
I
DD1 output voltage feedback
-
-
GND
-
-
-
-
-
-
DD1 Phase1 output block power
supply
PVCC1A 23
-
AVCC
DD1 Phase1 inductor
connection
LX1A
PG1
22
28
O
O
-
-
-
-
Open
GND
GND
-
-
-
-
-
-
-
-
-
DD1 Power Good output
DD1
DD1 Phase1 output block
ground
PGND1A 21
PVCC1B 18
Multi-phase
DD1 Phase2 output block power
supply
-
-
-
-
AVCC
Open
GND
-
-
-
-
-
-
-
-
-
DD1 Phase2 inductor
connection
LX1B
19
O
-
DD1 Phase2 output block
ground
PGND1B 20
IN2
8
I
DD2 output voltage feedback
DD2 output block power supply
DD2 inductor connection
-
-
-
-
-
-
-
-
-
-
-
-
GND
AVCC
Open
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
PVCC2
LX2
5
-
DD2
6
O
O
-
Buck
PG2
29
7
DD2 Power Good output
PGND2
IN3
DD2 output block ground
DD3 output voltage feedback
31
I
GND
Power supply for DD3 output
block
PVCC3
4
-
-
-
-
AVCC
-
VO3
32
3
O
O
O
O
-
Output voltage for DD3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
Open
Open
GND
GND
-
-
-
-
-
DD3
Buck-boost
LX3-1
LX3-2
PG3
DD3 inductor connection1
DD3 inductor connection2
Output for DD3 Power Good
Ground for DD3 output block
1
30
2
PGND3
CTLMAI
N
Control for reference voltage
output
25
I
Exist
-
-
-
-
CTL1
CTL2
CTL3
9
I
I
I
DD1 control
DD2 control
DD3 control
Exist
Exist
Exist
Open
-
-
-
-
-
CTL
10
11
-
-
Open
-
-
Open
Power supply for I2C
communication
DVCC
16
I
-
-
-
-
GND
Clock for I2C communication
Data for I2C communication
Switch for slave address
-
-
-
-
-
-
-
-
-
-
Open
Open
Open
I2C
SCL
SDA
14
15
I
I/O
I
Exist
-
ADDSEL 17
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 8 of 68
S6AP412A
Pull-
down
Resist
or
Unus
Pin
Numb
er
Pin
Name
I/
O
Unuse Unused Unused
d DD1 DD2 DD3
ed
Block
Description
I2C
Power supply for reference
voltage
AVCC
27
12
-
-
-
-
-
-
-
-
-
Select for DC/DC converter
operation mode (H: PFM/PWM
mode, L=PWM mode, common
for all DCDC converter )
MODE
I
Exist
-
Reference
control
VREF18
GND
26
13
EP
O
-
Output reference voltage
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Ground for reference voltage
Ground for reference voltage
GND
-
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 9 of 68
S6AP412A
5. Block Diagram
PVCC1A
LX1A
<<DD1>>
IN1
VCC:2.5V to 5.5V
L
Priority
A
VCC
VCC
PWM
Logic
Control
VCC
A
ErrAMP
ctl1
AST
ICOMP
UVLO
POR
VREF18
DAC
LV
CNV
PGND1A
PG1
SLP
CMP
mode clk
PVCC1B
VCC
VCC
PWM
Logic
LX1B
AST
Control
ICOMP
LV
CNV
PGND1B
SLP
CMP
cs1
scp1
VCC
xclk
PVCC2
LX2
<<DD2>>
IN2
L
Priority
B
VCC
VCC
B
PWM
Logic
Control
ErrAMP
ctl2
AST
ICOMP
UVLO
POR
VREF18
DAC
LV
CNV
PGND2
PG2
SLP
CMP
cs2
scp2
VCC
mode clk
PVCC3
LX3-1
<<DD3>>
IN3
L
Priority
C
VCC
VCC
PWM
Logic
Control
ErrAMP
ctl3
AST
ICOMP
UVLO
POR
VREF18
DAC
LV
CNV
SLP
CMP
C
VO3
LX3-2
AST
PGND3
PG3
mode xclk
cs3
scp3
VREF18
DVCC
SCL
SDA
Logic Control
Output Voltage Ajuster
AVCC
CTL1
CTL2
CTL3
ctl1
ctl2
ctl3
Common Block
CTLMAIN
Logic
Control
VREF
BGR
Under
Voltage
Thermal
Shut
Locked-Out
Down
ADDSEL
MODE
VREF18
mode
(1.8V)
Short Circuit Protection
scp*
(Timer
& Latch)
Soft Start Control
cs*
OSC
clk
xclk
CT
RT
GND
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 10 of 68
S6AP412A
6. Absolute Maximum Ratings
Rating
Parameter
Symbol
Condition
Unit
Max
Min
VVCC1
VVCC2
VCTL1
VCTL2
VMODE
VLOGIC
VADD
VPG
AVCC,PVCC input voltage
DVCC input voltage
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-1.0
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
V
V
V
V
V
V
V
V
V
V
Power supply voltage
CTL1,CTL 2,CTL3 input voltage
CTLMAIN input voltage
MODE input voltage
Terminal voltage
SDA,SCL input voltage
ADDSEL input voltage
PG1, PG2, PG3 drain voltage
IN1, IN2, IN3 input voltage
LX1, LX2, LX3 voltage
VOUT
VLX
LX voltage
Ta≤+25°C
Permission loss
PD
0
3420
mW
Thermal resistance (θja): (29.2°C /W(*1))
Maximum junction temperature
Storage temperature
Tjmax
TSTG
-
-
-
+125
+125
°C
°C
-55
*1: When the IC is mounted on 74mm × 74mm four-layer square epoxy board. IC is mounted on a four-layer
epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board.
WARNING:
1. Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of
these ratings.
Figure 2. Power Dissipation vs. Operation Ambient Temperature
Power dissipation vs. Operation ambient temperature
4000
3500
3000
2500
2000
1500
1000
500
0
-40
-20
0
20
40
60
80
100
Temperature[˚C]
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 11 of 68
S6AP412A
7. Recommended Operating Conditions
Value
Typ
Parameter
Symbol
Condition
Unit
Max
Min
1. Reference control block
Power supply voltage
VVCC
IREF
Ta
AVCC
VREF18
-
2.5
-1
3.3
5.5
0
V
Output current for reference voltage
Operating temperature
-
mA
°C
-30
+25
+85
2. DC/DC channel
Power supply voltage
Input voltage
VVCC
VOUT
VOUT
VPG
PVCC1, PVCC2, PVCC3
IN1,IN2
2.5
0
3.3
5.5
V
V
V
V
-
-
-
AVCC
5.5
Input voltage
IN3
0
PG input voltage
PG1, PG2, PG3
0
5.5
3. Input block
VCTL
VMODE
CTL1, CTL 2, CTL3, MODE
CTLMAIN
Input voltage
0
-
AVCC
V
4. I2C communication block
Power supply voltage
Input voltage
VVCC
DVCC
1.70
0
-
-
-
3.50
V
V
V
VLOGIC
VADD
SDA,SCL
ADDSEL
DVCC
AVCC
Input voltage
0
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 12 of 68
S6AP412A
8. Electrical Characteristics
8.1 Reference Control Block
(AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply,
PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. )
Value
Parameter
Symbol
Condition
[ VREF18 ]
Unit
Min
Typ
Max
1. Reference voltage
VVREF1
VVREF2
VREF18 pin = 0mA
1.773
1.768
1.800
1.800
1.827
1.832
V
AVCC pin = 2.5V to 5.5V
VREF18 pin = 0mA
V
V
Output voltage
VVREF3
VREF18 pin = 0mA to -1mA
[ VCC UVLO ]
1.768
1.800
1.832
2. Under voltage lockout
Threshold voltage
Hysteresis width
VTH
VH
AVCC rising
-
2.156
-
2.20
2.244
-
V
V
0.20(*1)
3. Over current protection
Timer
[ OCP ]
tOCP1
DD1, DD2, DD3
0.9
1
1.1
-
ms
°C
4. Thermal shut down
Stop temperature
[ TSD ]
TTSDH
-
125(*2)
150
5. Input block (CTL,MODE,CTLMAIN)
[ CTL,MODE,CTLMAIN ]
CTL1, CTL2, CTL3,MODE pin
CTLMAIN pin
AVCC
×0.7
Input voltage
Input voltage
VIH
VIL
-
AVCC
0.4
V
CTL1, CTL2, CTL3,MODE pin
CTLMAIN pin
0
-
V
ICTLH
IMODEH
CTL1, CTL2, CTL3,MODE pin = 3.3V
CTLMAIN pin = 3.3V
2.5
3.3
4.7
µA
Input current
ICTLL
IMODEL
CTL1, CTL2, CTL3,MODE pin = 0V
CTLMAIN pin = 0V
-
-
-
1
-
µA
CTL1, CTL2, CTL3,MODE pin
CTLMAIN pin
Input pull-down resistor
RP
1(*1)
MΩ
6. Consumption current (DC/DC converter block)
CTL1, CTL2, CTL3 pin = 0V
IVCCS1
-
-
0
1.0
45
µA
µA
CTLMAIN pin = 0V
CTL1, CTL2, CTL3 pin = 0V
CTLMAIN pin =3.3V
IVCCS2
30
DD1,DD2,DD3=ON,MODE=3.3V,
All DD are 0mA
Power supply current
IVCC
-
-
430
18
630
27
µA
(operation mode: PFM/PWM mode)
DD1,DD2,DD3=ON,MODE=0V
All DD are 0mA
IVCC
mA
(operation mode: Fixed PWM mode)
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 13 of 68
S6AP412A
8.2 DD1
AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply,
PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. )
Value
Parameter
Symbol
Condition
Unit
Min
Typ
Max
1. DC/DC converter block
Output voltage
[ DD1 ]
IOUT = -10mA,
VOUT
VLINE
VLOAD
0.988
1.000
1.012
+5
V
Output voltage setting: 1.0V
IOUT = -10mA,
Input stability
Load stability
-5
-
-
mV
mV
PVCC1= 2.5V to 5.5V
IOUT = -1mA to -4000mA
(Fixed PWM mode)
-10
+10
IOUT = -1mA to -4000mA
(PFM/PWM mode)
Load stability
VLOAD
RIN
-10
-
+15
mV
kΩ
IN1 input impedance
IN1 = 2.0V
-
-
190(*1)
120(*1)
-
-
SW PMOS-Tr
on resistance
RPMOS
LX1A,1B = -30mA
mΩ
SW NMOS-Tr
on resistance
RNMOS
ILEAK
ILEAK
ILIMIT
IPFM
LX1A,1B = 30mA
LX1A,1B = 0V
LX1A,1B = 3.3V
L=1.0µH
-
80(*1)
-
mΩ
µA
SW PMOS-Tr
-3
-
-
leakage current
SW NMOS-Tr
Leakage current
-
-
3
-
µA
Over current
protection value
4900(*2)
-
-
mA
mA
PFM/PWM mode
L=1.0µH
100(*1)
-
changeover current
Discharge resistor
Soft start time
RDIS
Tss
fOSC
-
-
5(*1)
1
-
kΩ
Soft start time setting: 1ms
-
0.9
2.7
1.1
3.3
ms
Switching frequency
3.0
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
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8.3 DD2
(AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply,
PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. )
Value
Parameter
Symbol
Condition
Unit
Min
Typ
Max
2. DC/DC converter block
[ DD2 ]
IOUT = -10mA,
Output voltage
Input stability
Load stability
VOUT
VLINE
VLOAD
1.778
1.800
1.822
V
Output voltage setting:1.8V
IOUT = -10mA
PVCC2= 2.5V to 5.5V
-5
-
-
+5
mV
mV
IOUT = -1mA to -1200mA
(Fixed PWM mode)
-10
+10
IOUT = -1mA to -1200mA
(PFM/PWM mode)
Load stability
VLOAD
RIN
-10
-
+20
mV
kΩ
IN2 input impedance
IN2 = 2.0V
-
-
150(*1)
190(*1)
-
-
SW PMOS-Tr
on resistance
RPMOS
LX2 = -30mA
mΩ
SW NMOS-Tr
on resistance
RNMOS
ILEAK
ILEAK
ILIMIT
IPFM
LX2 = 30mA
LX2 = 0V
LX2 = 3.3V
L=1.0µH
-
135(*1)
-
mΩ
µA
SW PMOS-Tr
-3
-
-
leakage current
SW NMOS-Tr
-
-
3
-
μA
leakage current
Over current
1500(*2)
-
-
mA
mA
protection value
PFM/PWM mode
L=1.0µH
65(*1)
-
changeover current
Discharge resistor
Soft start time
RDIS
Tss
fOSC
-
-
5
-
kΩ
Soft start time setting:1ms
-
0.9
2.7
1
1.1
3.3
ms
Switching frequency
3.0
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
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8.4 DD3
(AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V,
supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. )
Value
Parameter
Symbol
Condition
Unit
Min
Typ
Max
3. DC/DC converter block
Output voltage
[ DD3 ]
IOUT = -10mA,
Output voltage
setting:3.3V
VOUT
3.241
3.300
3.359
V
IOUT = -10mA,
PVCC3= 2.5V to 5.5V
IOUT = -1mA to -600mA
(Fixed PWM mode)
IOUT = -1mA to -600mA
(PFM/PWM mode)
IN3 = 2.0V
Input stability
Load stability
Load stability
VLINE
-5
-
-
+5
mV
mV
VLOAD
-10
+10
VLOAD
RIN
-10
-
+15
mV
kΩ
IN2 input impedance
SW PMOS-Tr
on resistance
SW NMOS-Tr
on resistance
SW PMOS-Tr
on resistance
SW NMOS-Tr
on resistance
SW PMOS-Tr
-
-
550(*1)
115(*1)
-
-
RPMOS
LX3-1 = -30mA
LX3-1 = 30mA
LX3-2 = -30mA
LX3-2 = 30mA
LX3-1 = 0V
mΩ
RNMOS
RPMOS
RNMOS
ILEAK
-
140(*1)
-
mΩ
mΩ
mΩ
μA
-
155(*1)
-
-
220(*1)
-
-3
-
-
leakage current
SW NMOS-Tr
leakage current
SW PMOS-Tr
leakage current
ILEAK
LX3-1 = 3.3V
LX3-2 = 0V
-
-
1
-
μA
ILEAK
-3
-
μA
SW NMOS-Tr
leakage current
Over current
protection value
PFM/PWM mode
changeover current
Discharge resistor
Soft start time
ILEAK
LX3-2 = 3.3V
L=1.0µH
-
-
1
-
μA
ILIMIT
1000(*2)
-
mA
mA
IPFM
L=1.0µH
-
-
-
200(*1)
-
RDIS
Tss
fOSC
5(*1)
1
3.0
-
kΩ
ms
MHz
Soft start time setting:1ms 0.9
2.7
1.1
3.3
Switching frequency
-
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
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8.5 Digital Block
(AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply,
PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. )
Value
Parameter
Symbol
Condition
[ Power Good ]
Unit
Min
Typ
Max
1. Power Good block
Output voltage
Output current
VOL
IOL
PG1, PG2, PG3 IOL = 1mA
PG1, PG2, PG3
-
-
0.4
-
V
1
-
mA
Vo
×0.90(*1)
Low voltage detection VTH
IN1, IN2, IN3 = falling
IN1, IN2, IN3 = rising
[ I2C ]
-
-
-
-
V
Vo
×0.93(*1)
Power on detection
2. I2C block
VTH
V
DVCC
×0.7
VIH
VIL
IIH
SCL,SDA
-
-
-
DVCC
V
Input voltage
Input current
DVCC
×0.3
SCL,SDA
0
V
SCL,SDA
-
10
-
µA
DVCC = 3.3V
SCL,SDA
DVCC = 3.3V
IIL
-10
-
µA
Output voltage
Output current
VOL
IOL
SDA IOL = 3mA
SDA
-
-
-
0.4
-
V
3
mA
3. ADDSEL block
[ ADDSEL ]
ADDSEL
AVCC
×0.7
Input voltage
Input voltage
VIH
-
AVCC
V
VIL
ADDSEL
0
-
0.4
4.7
1
V
IADD
IADD
ADDSEL = 3.3V
ADDSEL = 0V
2.5
-
3.3
-
µA
µA
Input current
Input pull-down
resistor
RP
ADDSEL
-
1(*1)
-
MΩ
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
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9. Operation Mode List
Table 1. Operation Mode List
Mode
CTLMAIN (external)
Stand-by
Stand-by2
Normal
Error Detection
H
L
L
L
L
H
L
L
L
H
CTL1
CTL2
CTL3
Reference
Digital
DD1
(external/I2C)
H/L(*1)
H/L(*1)
H/L(*1)
ON
X
CTL signal
(external/I2C)
(external/I2C)
X
X
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
Operation Block
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
DD2
DD3
I2C communication
I2C communication
disable
enable
enable
enable
Thermal shut down (TSD)
Not available Not available
available
available
(*2)
(*2)
Protection
operating
Over current protection (OCP) Not available Not available
*1: normal mode means that CTLMAIN pin is "H" level and each DD CTL pin is "H" level
*2: This state is after each err detection. Error state will release, when the power supply voltage or CTLMAIN
pin will turn off and on.
Priority of the External CTL pin and I2C Communication
CTLMAIN
(External)
CTL1, CTL2, CTL3
(External)
30h Resistor
(I2C)
Relevant
Channel
H
H
H
H
L
H
H
L
1
0
1
0
ON
ON
ON
L
OFF
OFF
X
disable
Priority of the External MODE pin and I2C Communication
20h Resistor
(I2C)
MODE
(External)
Operation Mode
H
H
L
1
0
1
0
PFM/PWM
PFM/PWM
PFM/PWM
Fixed PWM
L
Notes:
• The I2C communication is valid after the reference control block and digital block activation setting the external CTLMAIN pin
to "H" level.
• Please attention below note about ON/OFF control of DD1, DD2, DD3 by I2C communication.
When each DD control is turned off by I2C communication and external CTL pin remains "H" level, DCDC converter keep
operating.
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10.State Transition Diagram
Stand-by
Stand-by 2
General
(1)
(3)
(2)
(4)
(2)
(6)
(5)
Error
detection
(1) External CTLMAIN pin is "H" level.
(2) External CTLMAIN pin is "L" level.
(3) External CTL pin or I2C communication "relevant CH_ON"
(4) External CTL pin or I2C communication "relevant CH_OFF"
(5) Error detection (TSD, OCP 1ms continuation)
(6) Turning on the power supply again (equal to or less than uvlo_vcc rest voltage) or setting CTLMAIN to
"L" level
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11.Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3)
2.0V
2.2V
AVCC
CTLMAIN
CTL*
1.8V
VREF18
osc
(IC internal signal)
uvlo_vcc
(IC internal signal)
93%
Discharge
DD1
PG1
93%
93%
Discharge
Discharge
DD2
PG2
DD3
PG3
UVLO release to DD* activation
Soft-start time
Time till start (*1)
Typ : (820)µs
Max : TBD µs
*1: CTL1, CTL2, CTL3
*2: DD1, DD2, DD3
*3: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
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12.Turning ON and OFF Sequence (AVCC →CTLMAIN→CTL1→CTL2→ CTL3)
AVCC
3.3V
CTLMAIN
1.8V
VREF18
osc
(IC internal signal)
uvlo_vcc
(IC internal signal)
CTL1
93%
Discharge
DD1
PG1=CTL2
93%
Discharge
Discharge
DD2
PG2=CTL3
DD3
93%
PG3
UVLO release to DD* activation
Time till start (*1)
Typ : (820)µs
Max : TBD µs
*1: DD1, DD2, DD3
*2: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
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13.Turning ON and OFF Sequence (AVCC→CTLMAIN→I2C)
AVCC
3.3V
CTLMAIN
1.8V
VREF18
osc
(IC internal signal)
uvlo_vcc
(IC internal signal)
I2C(DD ON/OFF)
OFF
ON
OFF
ctl*
93%
Discharge
DD1
PG1
93%
93%
Discharge
Discharge
DD2
PG2
DD3
PG3
UVLO release to DD* activation
Soft-start time
Time till start (*1)
Typ : (820)µs
Max : TBD µs
*1: CTL1, CTL2, CTL3
*2: DD1, DD2, DD3
*3: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
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14.CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage
The input circuit structure for the CTL(*1) pin is the schmitt trigger style, and the threshold voltage shows the hysteresis
characteristics when CTL(*1) OFF to ON and ON to OFF.
(See "CTL(*1) pin equivalent circuit diagram" below.)
Also, the threshold voltage level depends on the VCC pin voltage.
Moreover, make sure to input either the "H" level (>"VCC×0.7"V) or "L" level (<0.4V) to the CTL(*1) and MODE and ADDSEL pin
when in use.
Figure 3. CTL (*1), MODE, ADDSEL Pin Equivalent Circuit Diagram
The CTL threshold voltage
shows the hysteresis
characteristics.
AVCC
ESD protection
element
(*1)
CTL
MODE
ADDSEL
ESD protection
element
GND
*1: CTLMAIN, CTL1, CTL2, CTL3
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15.Protection Operation Sequence
Over Current Protection (DD channel)
The DD channel monitors the peak current of FET at any time during the operation. When the DD output becomes the over current
state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress.
When one of each DD channel stops operation by over current protection, all DD channels stop operation.
Thermal Shut Down
If the temperature at the junction part reaches +150°C, the thermal shutdown protection circuit turns all channels off.
Error Detection Sequence
Figure 4. Error Detection Sequence
DD1,DD2,DD3
The whole IC
Normal
Normal
operation
operation
Over current
detection
Thermal
shutdown
protection
Voltage drop
1ms
No
Continue for 1ms?
Yes
Error detection mode
Error signal output (I2C address 40h)
Error Detection Mode Release
It is necessary to turn the power supply turning on again, or to turn CTLMAIN turning on again to release the error detection mode.
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16.Operation Condition, Stop Circuit and Release Condition for Protection Circuit
Operation
Whilst
Under
Under Voltage
Lockout Protection
(UVLO)
Over Current Protection
(OCP)
Thermal Shutdown
Protection (TSD)
Channel
Protection
Operating condition:
Chip temperature increment
Operating condition: Input
voltage drop
Operating condition:
After about 1ms progress in
the over current condition
Process during protection
operation:
DD1, DD2, DD3 stop
Process during protection
operation:
Process during protection
operation:
DD1, DD2, DD3 stop
DD1, DD2, DD3 stop
Recovery condition:
(1) Power supply reasserted
(2) CTLMAIN reasserted
DD1,DD2,DD3 Discharge
Recovery condition:
Input voltage rise
Recovery condition:
(1) Power supply reasserted
(2) CTLMAIN reasserted
Only when CTLMAIN is in the
"H" state and CTL(*1) is in the
"H" state, or when DD(*2) in
operating condition by I2C,
will operate.
UVLO operates only when
CTLMAIN is "H" (at VREF18
output).
Error output
(address 40h)
Write "1" when detecting
OCP
-
No change
Write "1" when detecting TSD
Thermal shutdown protection (TSD) operation during over current protection timer operation
When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal
shutdown protection has priority.
Operation when releasing under voltage lockout protection (UVLO)
• DD1,DD2,DD3,DD4: Activation following the condition for CTL(*1) pin or I2C
Note:
• When VREF18 decreases at the time of UVLO operation, I2C register is reset, and all DD does OFF.
It is necessary to let you do ON by CTL(*1) pin and communication again to let DD have ON."
*1: CTL1, CTL2, CTL3
*2: DD1, DD2, DD3
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17.DD Soft Start Operation
The soft-start operation for DD1, DD2 and DD3 is enabled in order to prevent the rush current during the DD activation. The
soft-start time can be controlled by I2C.
About output voltage changing option, soft start time is showed by follow equation.
Tss=Tslp × Vset/Vdef (ms)
Tss: soft start time
Tslp: slope coefficient of soft start
Vset: output voltage setting
Vdef: DD1=1.0, DD2=1.8, DD3=3.3
Figure 5. DD Soft Start
Output voltage2 setting value
Output voltage1 setting value
Output voltage3 setting value
Soft-start time
Channel ON/OFF signal (internal signal)
t
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18.Discharge Operation
DD Channel
When executing the DD OFF operation at the channel ON/OFF signal, the DC/DC smooth capacitance charged for each output
voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the
discharge time changes depending on the DC/DC converter load current.
The discharge time is calculated by the following equation.
Discharge time (time till the output becomes 10% without load)
toff(s) ≈2.3 ×R_DIS ×COUT (F)
Note:
• See the table in Electrical Characteristics for the discharge resistor value.
IN(*1)
A
PVCC(*2)
Resistor for discharge
R1
R2
A
Error
Amp
LX(*3)
Cout
Reference
voltage
DAC
PGND(*4)
Channel ON/OFF Cont.
*1: IN1, IN2, IN3
*2: PVCC1, PVCC2, PVCC3
*3: LX1, LX2, LX3
*4: PGND1, PGND2, PGND3
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19.PG Function
The following pins for each channel Power Good output are prepared.
PG1
It is the pin for DD1 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD1 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD1 OFF mode.
PG2
It is the pin for DD2 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD2 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD2 OFF mode.
PG3
It is the pin for DD3 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD3 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD3 OFF mode.
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20.I2C Interface
20.1 Structure of I2C Interface
The I2C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a
SDA (serial data line).
This bus is connected to multiple devices;
master: device to generate the clock signal and to control the data transfer (CPU and so on)
slave: device that an address is specified by a master.
This IC is set as the slave and has no function to be the master.
Each device is defined due to the communication direction as described below.
transmitter: device to send data to bus
receiver: device to receive data from bus
The IC has the function both transmitter and receiver.
SCL
SDA
transmitter
receiver
transmitter
receiver
maser
slave1
slave2
The IC defines the followings;
Write : data is transmitted from master and the IC receives data
Read : The IC transmits data and master receives data.
20.2 Definition of Signal Lines
SCL and SDA are connected to the power supply by the pull-up resistor.
The output circuit is the open Drain output.
When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state.
Note:
• SCL and SDA pins adopt a different ESD protection system from standard I2C specification because of ESD enhancement
(see 22 I/O Pin Equivalent Circuit Diagram). When the power supply is in the bus line, do not shut off the power supply for an
IC (DVCC).
I2C bus line power supply
R
R
Pull Up
SCL
SDA
input
input
Inside of IC
output
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20.3 Validity of Data
Data has the following characteristics;
Change when SCL is the "L" level
Valid if the state is kept while SCL is the "H" level.
SCL
SDA
data
state
data
change
data
state
The SDA signal change means the start or stop condition when SCL is the "H" level.
20.4 Definition of Start and Stop Condition
The start and stop conditions are output from the master and shows start and stop of communications to the slave.
Start: SDA changes from "H" to "L" when SCL is "H".
Stop: SDA changes from "L" to "H" when SCL is "H".
SCL
SDA
S
P
start
stop
condition
condition
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20.5 ACK Signal
This is a signal to confirm the data reception during communication.
The receiver replies the ACK signal to show the data reception to a transmitter every time
1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master
generates.
A transmitter keeps SDA output "open H" in SCL9clk.
A receiver informs the data reception situation to a transmitter outputting the followings in SCL
9 clk;
when data was received : SDA output "L" (ACK)
when no data was received : SDA output "open H" (NACK)
However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open
stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the
stop condition reception waiting state from the master.
SCL
from master
1
8
9
10
SDA
by transmitter
H hold
NACK
bit0
bit7
bit0
SDA
by receiver
ACK
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20.6 I2C Interface Input Timing
(within recommended operating conditions)
Value
Parameter
Symbol
SCL=100kHz
Min Max
SCL=400kHz
Min Max
Unit
SCL clock frequency
Start condition hold time
Restart condition setup time
Stop condition setup time
Stop to Start bus open time
SCL "L" time
fSCL
-
100
-
400
kHz
tHD:start
tSU:start
tSU:stop
tbuf
4.0
4.7
4.0
4.7
4.7
4.0
-
-
0.6
0.6
0.6
1.3
1.3
0.6
-
-
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
-
-
-
-
-
-
tLow
-
-
SCL "H" time
tHigh
tr
-
-
SCL/SDA rising time
SCL/SDA falling time
Data hold time
1.0
0.3
-
0.3
0.3
-
tf
-
-
tHD:data
tSU:data
Cb
0.0
0.25
-
0.0
0.10
-
Data setup time
-
-
SCL/SDA capacitor load
VIH/VIL level reference
400
400
Conform to I2C bus specifications
tr
tf
S
Sr
P
tHigh tLow
SCL
SDA
tbuf
tHD:start
tSU:data tHD:data
tSU:start
tSU:stop
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20.7 Slave Address
This is a slave address when communicating with the I2C interface.
The slave address of this IC is set by the first seven bits as shown below.
The seventh bit follows the ADDSEL pin and "0"/"1" are variable.
The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will
be written from the master to the slave.
The bit "1" shows that the master reads information from the slave.
This does not support the general call address.
When the ADDSEL pin is in "H"
slave address
S
S
T
A
R
T
A
C
K
T
O
P
0
1
0
1
1
0
1
R/W
MSB
LSB
When the ADDSEL pin is in "L"
slave address
S
T
A
R
T
S
T
O
P
A
C
K
0
1
0
1
1
0
0
R/W
MSB
LSB
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 33 of 68
S6AP412A
20.8 Bit Structure of Data on I2C Interface
1. Writing Data to Register and Reading Data
The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB).
S
T
S
A
C
K
A
C
K
T
O
P
A
R
T
A
C
K
register address
slave address
data
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
No.
S 0 1 0 1 1 0 0 W
0 0 0 0 0 0 1 0
a b c d e f g h
P
register
data
D07 D06 D05 D04 D03 D02 D01 D00
00H
01H
02H
a
b
c
d
e
f
g
h
address
03H
04H
:
:
Output the "stop" condition after sending the Write data.
: Signal which a master sends,
: Signal which this IC sends
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S6AP412A
2. I2C Interface Data Format
About I2C Communication
1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address.
2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting.
3. If a non-existing register address is specified, data is not written to a register.
4. Output the "stop" condition after sending the write data.
<Write(W)>
S
S
T
O
P
T
A
R
T
A
C
K
A
C
K
A
C
K
register address
slave address
data
S
0
1
0
1
1
0
0 W
P
Write is allowed per one address. (Sequential writing is not allowed.)
Send register address and data as one unit.
: Signal which a master sends,
: Signal which this IC sends
<Read(R)>
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
slave address
register address
slave address
data
S
0
1
0
1
1
0
0 W
S
0
1
0
1
1
0
0
R
P
Read is allowed per one address. Be sure to perform read by specifying the register addresses.
(Sequential reading is not allowed.)
: Signal which a master sends,
: Signal which this IC sends
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 35 of 68
S6AP412A
21.Structure of I2C Interface and Data
Table 2. Register Map
Data
d03
Writin
g
Timing
Address
Remarks
d07
d06
d05
d04
d02
d01
d00
Default
0FH
DD1 output voltage
setting
00H
01H
0
0
0
D04
D03
D03
D02
D01
D00
ACK
ACK
DD2 output voltage
setting
0
0
0
0
D02
D01
D00
0CH
Output
voltage
DD3 output voltage
setting
02H
03H
10H
0
0
0
0
0
0
0
0
0
0
0
D02
(*1)
D02
D01
(*1)
D01
D00
(*1)
D00
05H
0FH
00H
ACK
ACK
ACK
(*1)
0
(*1)
D03
Unused
DD1 soft-start time
setting
DD2 soft-start time
setting
11H
0
0
0
0
D03
D02
D01
D00
00H
ACK
Soft start
DD3 soft-start time
setting
12H
13H
0
0
0
0
0
0
0
0
D03
(*1)
D02
(*1)
D01
(*1)
D00
(*1)
00H
00H
ACK
ACK
Unused
DD operation mode
setting
DD
"0": Fixed PWM
mode,
operation 20H
mode
0
0
0
0
0
0
0
0
0
0
(*1)
(*1)
(*1)
D02
D02
D02
D01
D01
D01
D00
D00
D00
00H
00H
00H
ACK
ACK
-
"1": PFM/PWM mode
DD output ON/OFF
setting
"0": Output OFF / "1":
Output ON
ON/OFF
Error
30H
40H
0
DD error state
monitoring register
(read only)
D04
"0": Normal / "1": Error
detection
DD PG state
monitoring register
(read only)
PG
50H
0
0
0
0
(*1)
D02
D01
D00
00H
-
"0": Non-output / "1":
output
For test
For test
EXH
FXH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Disabled
Disabled
*1: Unused register. Write/read is possible, but does not influence IC movement.
Note:
• Address FXH and address EXH are for test.
Donot write/read FXH and EXH.
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 36 of 68
S6AP412A
21.1 About DD1 Output Voltage Setting
Address 00H DD1 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD1 is controlled by writing data to address 00H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
D04 D03 D02 D01 D00
MSB
LSB
Address 00H: For DD1 output voltage setting
D04 to D00: Set the output voltage
DD1 Output Voltage Setting Table
Data
00H
Output Voltage (V)
Data
10H
Output Voltage (V)
0.700
1.020
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
0.720
0.740
0.760
0.780
0.800
0.820
0.840
0.860
0.880
0.900 (*1)
0.920
0.940
0.960
0.980
1.000 (*1)
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
1.040
1.060
1.080
1.100 (*1)
1.120
1.140
1.160
1.180
1.200 (*1)
1.220
1.240
1.260
1.280
1.300
1.320
*1: Preset value
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March 28, 2016
Page 37 of 68
S6AP412A
21.2 About DD2 Output Voltage Setting
Address 01H DD2 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD2 is controlled by writing data to address 01H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
D03 D02 D01 D00
MSB
LSB
address01H: For DD2 output voltage setting
D03 to D00: Set the output voltage
DD2 Output Voltage Setting Table
Output Voltage
Data
(V)
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
1.200 (*1)
1.250
1.300
1.350 (*1)
1.400
1.450
1.500 (*1)
1.550
1.600
1.650
1.700
1.750
1.800 (*1)
1.850
1.900
1.950
*1: Preset value
Document Number: 002-08447 Rev.*A
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S6AP412A
21.3 About DD3 Output Voltage Setting
Address 02H DD3 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD3 is controlled by writing data to address 02H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
0
D02 D01 D00
MSB
LSB
address02H: For DD3 output voltage setting
D02 to D00: Set the output voltage
DD3 Output Voltage Setting Table
Data
00H
Output Voltage(V)
2.80 (*1)
2.90
01H
02H
03H
04H
05H
06H
07H
3.00 (*1)
3.10
3.20
3.30 (*1)
3.40
3.50 (*1)
*1: Preset value
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S6AP412A
21.4 About Soft Start Time
Address 10H to 12H are allocated as registers for the soft start time control.
The soft start time control is controlled by writing data to addresses 10H to 12H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
D03 D02 D01 D00
MSB
LSB
address10H: For DD1 soft start time setting
address11H: For DD2 soft start time setting
address12H: For DD3 soft start time setting
D03 to D00: Set the soft start time
Tss=Tslp × Vset/Vdef (ms)
Tss: soft start time
Tslp: slope coefficient of soft start:refer to follow table
Vset: output voltage setting
Vdef: DD1=1.0, DD2=1.8, DD3=3.3
Soft Start Time Setting
Data
Tslp
1.0
Remarks
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
DD1,DD2,DD3 (*1)
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
*1: Preset value
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March 28, 2016
Page 40 of 68
S6AP412A
21.5 DC/DC Operation Mode
Address 20H is allocated as a register for the DC/DC operation mode control.
The DC/DC operation mode is controlled by writing data to address 20H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
D03 D02 D01 D00
MSB
LSB
address20H: For DC/DC operation mode setting
D01 to D00: Set the DC/DC operation mode
Address
Bit
D00
Description
0: DD1 Fixed PWM (*1)
1: DD1 PFM/PWM
20H
0: DD2 Fixed PWM (*1)
1: DD2 PFM/PWM
20H
D01
0: DD3 Fixed PWM (*1)
1: DD3 PFM/PWM
20H
20H
D02
D03
Out of use
*1: Preset value
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 41 of 68
S6AP412A
21.6 ON/OFF for DC/DC
Address 30H is allocated as a register for the DC/DC ON/OFF.
The DC/DC ON/OFF is controlled by writing data to address 30H.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
D03 D02 D01 D00
MSB
LSB
address30H: For DC/DC ON/OFF
D02 to D00: Set ON/OFF for DC/DC
Address Bit
Description
0: DD1 output OFF (*1)
1: DD1 output ON
30H
30H
D00
D01
0: DD2 output OFF (*1)
1: DD2 output ON
0: DD3 output OFF (*1)
1: DD3 output ON
30H
30H
D02
D03
Out of use
*1: Preset value
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 42 of 68
S6AP412A
21.7 About Error Monitor
Address 40H is allocated as error status monitor of each DC/DC output and thermal shut down.
Address 40H is read only resistor.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
D04 D03 D02 D01 D00
MSB
LSB
address40H: For error monitor of each DC/DC output and thermal shut down
D04 to D00: read only resistor. (Not allowed write resistor)
Address
Bit
D00
Description
0: DD1 OCP non detection (*1)
1: DD1 OCP detection
40H
0: DD2 OCP non detection (*1)
1: DD2 OCP detection
40H
D01
0: DD3 OCP non detection (*1)
1: DD3 OCP detection
40H
40H
40H
D02
D03
D04
Out of use
0: TSD non detection (*1)
1: TSD detection
*1:Preset value
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 43 of 68
S6AP412A
21.8 About Power Good Monitor
Address 50H is allocated as output monitor of each DC/DC output.
Address 50H is read only resistor.
Data
S
T
A
R
T
S
T
O
P
A
C
K
0
0
0
0
D03 D02 D01 D00
MSB
LSB
address50H: For output monitor of each DC/DC output.
Detection level is over 93% of DCDC output voltage setting.
D04 to D00: read only resistor. (Not allowed write resistor)
Address
Bit
D00
Description
0: DD1 non output (*1)
1: DD1 output
50H
0: DD2 non output (*1)
1: DD2 output
50H
D01
0: DD3 non output (*1)
1: DD3 output
50H
50H
D02
D03
Out of use
*1: Preset value
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 44 of 68
S6AP412A
22.I/O Pin Equivalent Circuit Diagram
<<AVCC>>
AVCC
ESD
protection
element
GND
<<VREF18>>
AVCC
VREF18
GND
<<IN1,IN2, LX1,LX2, PGND1<PGND2>>
AVCC
IN*
GND
IN*: IN1, IN2
LX*: LX1, LX2
PGND*: PGND1, PGND2
LX*
PGND*
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Page 45 of 68
S6AP412A
<<PVCC1,PVCC2>
AVCC
PVCC*: PVCC1, PVCC2
LX*: LX1, LX2
PGND*: PGND1, PGND2
PVCC*
LX*
PGND*
GND
<<IN3,PGND3 >
IN3
GND
PGND3
<<PVCC3,LX3-1,LX3-2,VO3>>
AVCC
PVCC3
LX3-1
VO3
LX3-2
PGND3
GND
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 46 of 68
S6AP412A
<<CTL*, ADDSEL, MODE>>
<<PG*>>
AVCC
AVCC
PG*: PG1, PG2, PG3
PG*
CTL*
ADDSEL
MODE
GND
GND
CTL*: CTLMAIN, CTL1,
CTL2, CTL3
<<SCL>>
<<SDA>>
DVCC
DVCC
SCL
SDA
GND
GND
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 47 of 68
S6AP412A
23.Measurement Circuit for Characteristics of General Operation
S6AP412A
Input Voltage:
2.5V to 5.5V
IN1
AVCC
C1
0.1mF
L1
DD1:1.0V
LX1A
Io(max):4000mA
PVCC1A
C7
C8
1.0mH
C2
4.7mF
22mF 22mF
PGND1A
PVCC1B
CTL1
C3
4.7mF
L2
LX1B
1.0mH
PGND1B
R1
100kW
PG1
PG1
IN2
PVCC2
CTL2
C4
4.7mF
L3
DD2:1.80V
Io(max):1200mA
LX2
C9
22mF
1.0mH
PGND2
R2
100kW
PG2
PG2
PVCC3
CTL3
C5
4.7mF
LX3-1
L4
1.0mH
LX3-2
IN3
CTLMAIN
DVCC
3.3V
SCL
SDA
SCL
SDA
DD3:3.30V
Io(max):600mA
VO3
C10
33mF
PGND3
MODE
R3
100kW
ADDSEL
PG3
PG3
VREF18
GND
C6
1.0mF
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 48 of 68
S6AP412A
Table 3. Parts list
Symbol
Parts
Part number
1276AS-H-1R0M
1276AS-H-1R0M
1276AS-H-1R0M
1276AS-H-1R0M
C1608X5R1H104K
C1608X5R1V475K
C1608X5R1V475K
C1608X5R1V475K
C1608X5R1V475K
C2012X5R1A336M
C1608X5R1H105K
C1608X5R1H105K
C1608X5R1H105K
C2012X5R1A336M
RR0816P-104-D
RR0816P-104-D
RR0816P-104-D
Specifications
1.0µH
Vendor
TOKO
L1
Inductor
L2
Inductor
Inductor
Inductor
1.0µH
1.0µH
1.0µH
0.1µF
4.7µF
4.7µF
4.7µF
4.7µF
1.0µF
22µF
TOKO
TOKO
TOKO
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
SSM
SSM
SSM
L3
L4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
R1
R2
R3
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Resistor
22µF
22µF
33µF
100kΩ
100kΩ
100kΩ
Resistor
Resistor
TOKO
TDK
: TOKO, INC.
: TDK Corporation
SSM
: SUSUMU CO., LTD.
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 49 of 68
S6AP412A
24.Reference Data
DCDC Convertor Efficiency Data
Inductor and capacitor value refer to section 26.
DD1
Input voltage = 3.3V, Vo=1.0V setting
Input voltage = 3.3V, Vo=1.2V setting
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Fixed PWM
PFM/PWM
Fixed PWM
PFM/PWM
0.00001
0.001
0.1
10
0.00001
0.001
0.1
10
Load current[A]
Load current[A]
Input voltage = 5.5V, Vo = 1.0V setting
Input voltage = 5.5V, Vo = 1.2V setting
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Fixed PWM
PFM/PWM
Fixed PWM
PFM/PWM
0.00001
0.001
0.1
10
0.00001
0.001
0.1
10
Load current[A]
Load current[A]
DD2
Input Voltage = 3.3V, Vo = 1.5V setting
Input voltage = 3.3V, Vo = 1.8V setting
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
Fixed PWM
PFM/PWM
Fixed PWM
PFM/PWM
10
0
0.00001
0.001
0.1
10
0.00001
0.001
0.1
10
Load current[A]
Load current[A]
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S6AP412A
DD2
Input voltage = 5.5V, Vo = 1.5V setting
Input Voltage = 5.5V, Vo = 1.8V setting
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
Fixed PWM
PFM/PWM
Fixed PWM
PFM/PWM
10
0
0.00001
0.001
0.1
10
0.00001
0.001
0.1
10
Load current[A]
Load current[A]
DD3
Input voltage = 3.3V, Vo = 3.3V setting
Input Voltage = 5.5V, Vo = 3.3V setting
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Fixed PWM
PFM/PWM
Fixed PWM
PFM/PWM
0.00001
0.001
0.1
10
0.00001
0.001
0.1
10
Load current[A]
Load current[A]
Document Number: 002-08447 Rev.*A
March 28, 2016
Page 51 of 68
S6AP412A
DCDC Convertor Regulation Data
DD1
Input voltage = 3.3V, Vo = 1.0V setting
Input voltage = 3.3V, Vo=1.2V setting
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.220
1.215
1.210
1.205
1.200
1.195
Fixed PWM
PFM/PWM
Fixed PWM
1.190
1.185
1.180
PFM/PWM
0.0
1.0
2.0
Load current[A]
3.0
4.0
0.0
1.0
2.0
3.0
4.0
Load current[A]
Input voltage = 5.5V, Vo = 1.0V setting
Input voltage = 5.5V, Vo = 1.2V setting
1.220
1.215
1.210
1.205
1.200
1.195
1.020
1.015
1.010
1.005
1.000
0.995
Fixed PWM
1.190
1.185
1.180
Fixed PWM
0.990
0.985
0.980
PFM/PWM
PFM/PWM
0.0
1.0
2.0
3.0
4.0
0.0
1.0
2.0
3.0
4.0
Load current[A]
Load current[A]
DD2
Input Voltage = 3.3V, Vo = 1.5V setting
Input voltage = 3.3V, Vo = 1.8V setting
1.520
1.515
1.510
1.505
1.500
1.495
1.820
1.815
1.810
1.805
1.800
1.795
Fixed PWM
1.490
1.485
1.480
Fixed PWM
1.790
1.785
1.780
PFM/PWM
PFM/PWM
0.0
0.4
0.8
1.2
0.0
0.4
0.8
1.2
Load current[A]
Load current[A]
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DD2
Input voltage = 5.5V, Vo = 1.5V setting
Input Voltage = 5.5V, Vo = 1.8V setting
1.520
1.515
1.510
1.505
1.500
1.495
1.820
1.815
1.810
1.805
1.800
1.795
Fixed PWM
Fixed PWM
1.490
1.485
1.480
1.790
1.785
1.780
PFM/PWM
PFM/PWM
0.0
0.4
0.8
1.2
0.0
0.4
0.8
1.2
Load current[A]
Load current[A]
DD3
Input voltage = 3.3V, Vo = 3.3V setting
Input Voltage = 5.5V, Vo = 3.3V setting
3.320
3.315
3.310
3.305
3.300
3.295
3.320
3.315
3.310
3.305
3.300
3.295
Fixed PWM
Fixed PWM
3.290
3.285
3.280
3.290
3.285
3.280
PFM/PWM
0.4
PFM/PWM
0.4
0.0
0.2
Load current[A]
0.6
0.0
0.2
Load current[A]
0.6
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S6AP412A
DCDC Convertor Output Ripple Voltage
DD1
Input voltage = 3.3V, Vo = 1.0V setting
Load current = 0mA , Fixed PWM
Input voltage = 3.3V, Vo=1.0V setting
Load current = 4000mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 1.0V setting
Load current = 0mA , Fixed PWM
Input voltage = 5.5V, Vo = 1.0V setting
Load current = 4000mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 3.3V, Vo = 1.0V setting
Load current = 0mA , PFM/PWM
Input voltage = 3.3V, Vo=1.0V setting
Load current = 4000mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 1.0V setting
Load current = 0mA , PFM/PWM
Input voltage = 5.5V, Vo = 1.0V setting
Load current = 4000mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
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DD2
Input voltage = 3.3V, Vo = 1.8V setting
Load current = 0mA , Fixed PWM
Input voltage = 3.3V, Vo=1.8V setting
Load current = 1200mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 1.8V setting
Load current = 0mA , Fixed PWM
Input voltage = 5.5V, Vo = 1.8V setting
Load current =1200mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 3.3V, Vo = 1.8V setting
Load current = 0mA , PFM/PWM
Input voltage = 3.3V, Vo=1.8V setting
Load current =1200mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 1.8V setting
Load current = 0mA , PFM/PWM
Input voltage = 5.5V, Vo = 1.8V setting
Load current = 1200mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
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Input voltage = 3.3V, Vo = 3.3V setting
Load current = 0mA , Fixed PWM
Input voltage = 3.3V, Vo=3.3V setting
Load current = 600mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 3.3V setting
Load current = 0mA , Fixed PWM
Input voltage = 5.5V, Vo = 3.3V setting
Load current =600mA, Fixed PWM
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Input voltage = 3.3V, Vo = 3.3V setting
Load current = 0mA , PFM/PWM
Input voltage = 3.3V, Vo=3.3V setting
Load current = 600mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
Input voltage = 5.5V, Vo = 1.0V setting
Load current = 0mA , PFM/PWM
Input voltage = 3.3V, Vo =3.3V setting
Load current = 600mA,PFM/PWM
10mV/div, 2ms/div
10mV/div, 0.5μs/div
Document Number: 002-08447 Rev.*A
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S6AP412A
DCDC Convertor Enable/Disable
DD1(Fixed PWM)
Input voltage = 3.3V, Vo = 1.0V setting
Load current = 4000mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=1.0V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
PG1(6V/div)
SCL(3V/div)
PG1(6V/div)
Vo(0.5V/div)
1.01ms
Vo(0.5V/div)
200us/div
510ms
200ms/div
IIN(1.0A/div)
IIN(40mA/div)
DD1(PFM/PWM)
Input voltage = 3.3V, Vo = 1.0V setting
Load current = 4000mA, Tss = 1ms setting
8
Input voltage = 3.3V, Vo=1.0V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
SCL(3V/div)
PG1(6V/div)
PG1(6V/div)
1.01ms
Vo(0.5V/div)
200us/div
Vo(0.5V/div)
515ms
200ms/div
IIN(1.0A/div)
IIN(40mA/div)
DD2(Fixed PWM)
Input voltage = 3.3V, Vo = 1.8V setting
Load current = 1200mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=1.8V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
SCL(3V/div)
PG2(6V/div)
PG2(6V/div)
1.02ms
Vo(1V/div)
200us/div
Vo(1V/div)
50ms/div
200ms
IIN(500mA/div)
IIN(40mA/div)
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DD2(PFM/ PWM)
Input voltage = 3.3V, Vo = 1.8V setting
Load current = 1200mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=1.8V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
SCL(3V/div)
PG2(6V/div)
PG2(6V/div)
1.03ms
Vo(1V/div)
200us/div
Vo(1V/div)
50ms/div
204ms
IIN(500mA/div)
IIN(40mA/div)
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting
Load current = 600mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=3.3 V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
PG3(6V/div)
SCL(3V/div)
PG3(6V/div)
0.99ms
Vo(2V/div)
200us/div
Vo(2V/div)
270ms
100ms/div
IIN(500mA/div)
IIN(40mA/div)
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting
Load current = 600mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=3.3 V setting
Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
PG3(6V/div)
SCL(3V/div)
PG3(6V/div)
1.0ms
Vo(2V/div)
200us/div
Vo(2V/div)
270ms
100ms/div
IIN(500mA/div)
IIN(40mA/div)
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S6AP412A
DCDConvertor Load Transient
DD1(Fixed PWM)
Input voltage = 3.3V, Vo = 1.0V setting
Input voltage = 3.3V, Vo=1.0V setting
Load current = from 0mA to 4000mA per 10us
Load current = from 4000mA to 0mA per 10us
Vo1(100mV/div)
offset：1.000V
82.5mV
Vo1(100mV/div)
offset：1.000V
82.5mV
10us
10us
Io(2.0A/div)
Io(2.0A/div)
DD1(PFM/PWM)
Input voltage = 3.3V, Vo = 1.0V setting
Input voltage = 3.3V, Vo=1.0V setting
Load current = from 0mA to 4000mA per 10us
Load current = from 4000mA to 0mA per 10us
Vo1(100mV/div)
offset：1.000V
84.1mV
Vo1(100mV/div)
offset：1.000V
82.5mV
50ms
10us
Io(2.0A/div)
Io(2.0A/div)
DD2(Fixed PWM)
Input voltage = 3.3V, Vo = 1.8V setting
Input voltage = 3.3V, Vo=1.8V setting
Load current = from 0mA to 1200mA per 10us
Load current = from 1200mA to 0mA per 10us
54.1mV
Vo2(50mV/div)
offset：1.8V
Vo1(50mV/div)
offset：1.8V
54.8mV
10us
10us
Io(1.0A/div)
Io(1.0A/div)
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S6AP412A
DD2(PFM/ PWM)
Input voltage = 3.3V, Vo = 1.8V setting
Load current = from 0mA to 1200mA per 10us
Input voltage = 3.3V, Vo=1.8V setting
Load current = from 1200mA to 0mA per 10us
57.1mV
Vo2(50mV/div)
offset：1.8V
Vo1(50mV/div)
offset：1.8V
54.0mV
10ms
10us
Io(1.0A/div)
Io(1.0A/div)
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting
Load current = 600mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=3.3 V setting
Load current = 0mA, Tss = 1ms setting
Vo3(50mV/div)
offset：3.3V
Vo3(50mV/div)
offset：3.3V
54.7mV
59.5mV
10us
10us
Io(500mA/div)
Io(500mA/div)
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting
Load current = 600mA, Tss = 1ms setting
Input voltage = 3.3V, Vo=3.3 V setting
Load current = 0mA, Tss = 1ms setting
Vo3(50mV/div)
offset：3.3V
Vo3(50mV/div)
offset：3.3V
84mV
83mV
20ms
10us
Io(500mA/div)
Io(500mA/div)
Document Number: 002-08447 Rev.*A
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S6AP412A
DCDC Convertor DVFS Function
DD1 (Fixed PWM)
Input voltage = 3.3V,
Vo =from 0.7V to 1.32V setting by I2C
Input voltage = 3.3V
Vo =from 1.32V to 0.7V setting by I2C
SCL
(2V/div)
SCL
(2V/div)
PG
(5V/div)
PG
(5V/div)
100us
Vo1
(200mV/div)
offset0.7V
100us
Vo1
(200mV/div)
offset0.7V
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S6AP412A
25.Ordering Information
Table 4. Ordering Information
Part Number
Package
Remarks
S6AP412A18GN1C000
S6AP412A28GN1C000
S6AP412A38GN1C000
S6AP412A58GN1C000
S6AP412A68GN1C000
S6AP412A78GN1C000
S6AP412A98GN1C000
S6AP412AA8GN1C000
S6AP412AB8GN1C000
S6AP412AD8GN1C000
S6AP412AE8GN1C000
S6AP412AF8GN1C000
32-pin plastic QFN
(WNT032)
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26.Preset Code List
DD1 Output Voltage
Preset Code Value
0.90V
DD2 Output Voltage
Preset Code Value
DD3 Output Voltage
Preset Code Value
Preset Code
18
1.35V
3.30V
28
38
58
68
78
98
A8
B8
D8
E8
F8
0.90V
0.90V
1.00V
1.00V
1.00V
1.10V
1.10V
1.10V
1.20V
1.20V
1.20V
1.50V
1.80V
1.35V
1.50V
1.80V
1.35V
1.50V
1.80V
1.35V
1.50V
1.80V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
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S6AP412A
27.Layout
Consider the points listed below and do the layout design.
Provide the ground plane as much as possible on the IC mounted face. GND and PGNDx provide the through hole proximal to
GND and PGNDx pins of IC, and connect it with GND of internal layer.
Provide the power plane as much as possible to lower impedance of VCC.
Play the most attention to the loop composed of input capacitor (CPVCCx) and SWFET. Input capacitor (CPVCCx) connected
with PVCCx should be placed close to the pin as much as possible to make the current loop as small as possible. Also connect
the GND pin of the input capacitor with PGNDx.
Output capacitor (CVO3) connected with VO3 should be placed close to the pin as much as possible. Also connect the GND pin
of the output capacitor with PGND3.
GND pins of the switching system parts provide the through hole at the proximal place, and connect it with GND of internal layer.
By-pass capacitor (CVREF, CAVCC) connected with VREF and AVCC should be placed close to the pin as much as possible.
Also connect the GND pin of the by-pass capacitor with GND of internal layer in the proximal through-hole.
Pull the feedback line to be connected to the INx pin of the IC separately from near the output capacitor pin, whenever possible.
Consider the line connected with INx pins to keep away from a switching system parts as much as possible because it is
sensitive to the noise.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor.
Line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with
inductor).
Switching system parts: Input capacitor(CPVCCx), Inductor(L), Output capacitor(CVOx)
Note:
• x: Each channel number
Figure 6. Layout Example
Layout example of IC
Layout example of switching components 1
GND
CPVCC1A
CPVCC1B
PGNDx
PVCCx
CPVCCx
To the LXx pin
C
VREF
L
VREF
AVCC
Through Hole
Output voltage
VOx feedback
CAVCC
CVOx
GND
(Top View)
Layout example of switching components 2
EP(Exposed Pad)
Output voltage
VO3 feedback
VO3
CVO3
C
VO3
To the LX3-2 pin
To the LX3-1 pin
PVCC3
PGND3
GND
C
PVCC3
1pin
CPVCC3
CPVCC2
L
Surface
Layer
Inner
Layer
GND
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S6AP412A
28.Package Dimensions
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29.Major Changes
Spansion Publication Number: S6AP412A_DS405-00018
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 1.0
-
-
Preliminary → Full production
Revised the Parts number of Component list
26. Measurement Circuit for Characteristics of General
Operation
50
1278AS-H-1R0M → 1276AS-H-1R0M
Revised the Part number of Ordering
Information
63
28. Ordering Information
NOTE: Please see “Document History” about later revised information.
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S6AP412A
Document History
Document Title: S6AP412A 3ch DC/DC Converter with I2C Interface and Internal SW FETs
Document Number: 002-08447
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
Migrated to Cypress and assigned document number 002-08447.
No change to document contents or format.
**
TAOA
12/26/2014
*A
5157734
TAOA
03/28/2016 Updated to Cypress template
Document Number: 002-08447 Rev.*A
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S6AP412A
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2014-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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