PALCE20V8L-25JIT [CYPRESS]
Flash PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | PALCE20V8L-25JIT |
| 厂家： | 
CYPRESS |
| 描述： | Flash PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28 时钟 输入元件 可编程逻辑 |
| 文件： | 总14页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PALCE20V8
Flash-Erasable Reprogrammable
CMOS PAL® Device
• QSOP package available
Features
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— Proven Flash technology
— 65 mA max. military/industrial
(15, 25 ns)
— 100% programming and functional testing
• Standard version has low power
Functional Description
— 90 mA max. commercial
(15, 25 ns)
The Cypress PALCE20V8 is a CMOS Flash Erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and a
24-lead quarter size outline. The device provides up to 20
inputs and 8 outputs. The PALCE20V8 can be electrically
erased and reprogrammed. The programmable macrocell
enables the device to function as a superset to the familiar
24-pin PLDs such as 20L8, 20R8, 20R6, 20R4.
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
CLK/I
0
12
11
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(64 x 40)
8
8
8
8
8
8
8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13
OE/I
14
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
24
I
12
I
13
V
CC
11
0
1
2
3
4
5
6
7
Cypress Semiconductor Corporation
Document #: 38-03026 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 19, 2004
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PALCE20V8
Pin Configuration
PLCC/LCC
Top View
DIP/QSOP
Top View
CLK/I
1
2
3
4
5
6
24
23
22
V
0
CC
I
13
I
1
I
2
I/O
4
3
2
1
2827 26
25
7
I
I/O
3
21
20
19
18
17
6
I
5
6
7
8
9
10
11
3
I/O
6
I/O
5
I
4
I/O
I/O
I
5
4
24
23
22
21
20
19
I
5
4
I
5
I/O
4
I
6
I/O
I/O
7
8
3
NC
NC
I/O
I
7
2
I
6
3
I/O
I
I
9
9
1
16
15
14
13
I
8
I/O
2
I/O
1
7
I
8
10
11
12
I/O
0
121314 1516 1718
I
I
12
10
OE/I
GND
11
Selection Guide
tPD ns
tS ns
tCO ns
Com’l/Ind
ICC mA
Generic Part Number
PALCE20V8−5
Com’l/Ind
Mil
Com’l/Ind
Mil
Mil
Com’l
115
115
115
90
Mil/Ind
5
3
4
5
PALCE20V8−7
7.5
10
15
25
15
25
7
PALCE20V8−10
PALCE20V8−15
PALCE20V8−25
PALCE20V8L−15
PALCE20V8L−25
10
15
25
15
25
10
12
15
12
15
10
7
10
12
20
12
20
130
130
130
65
12
20
12
20
10
12
10
12
90
55
55
65
Shaded areas contain preliminary information.
Document #: 38-03026 Rev. *B
Page 2 of 14
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PALCE20V8
Electronic Signature
Functional Description
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
Security Bit
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Power-Up Reset
Input and I/O Pin Pull-Ups
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active HIGH
state (logical 1). All unused inputs and three-stated I/O pins
should be connected to another active input, VCC, or Ground
to improve noise immunity and reduce ICC
.
Configuration Table
CG0
CG1
CL0x
Cell Configuration
Registered Output
Devices Emulated
Registered Med PALs
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
Combinatorial I/O
Combinatorial Output
Input
Registered Med PALs
Small PALs
Small PALs
Combinatorial I/O
20L8 only
Macrocell
To
1 1
Adjacent
Macrocell
OE
1 0
0 0
1 1
V
CC
0 X
1 0
0 1
CL0
x
CG
1
1 1
0 X
I/O
x
D
Q
Q
1 0
V
CC
CLK
1 0
1 1
0 X
CL1
x
From
Adjacent
Pin
CG for pin 16 to 21 (DIP)
1
CL0
x
CG for pin 15 and 22 (DIP)
0
Document #: 38-03026 Rev. *B
Page 3 of 14
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PALCE20V8
DC Input Voltage.................................................−0.5V to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current......................................................>200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Operating Range[1]
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +75°C
VCC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
5V ±5%
5V ±10%
5V ±10%
−40°C to +85°C
−55°C to +125°C
DC Voltage Applied to Outputs
in High-Z State.....................................................−0.5V to +7.0V
Military[2]
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
IOH = −3.2 mA
IOH = −2 mA
IOL = 24 mA
Min.
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
VIN = VIH or VIL
Com’l
Mil/Ind
Com’l
Mil/Ind
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
0.5
V
IOL = 12 mA
VIH
Input HIGH Level
Input LOW Level
Guaranteed Input Logical HIGH Voltage for All Inputs[4]
Guaranteed Input Logical LOW Voltage for All Inputs[4]
2.0
V
V
[5]
VIL
−0.5
0.8
10
IIH
Input or I/O HIGH Leakage 3.5V < VIN < VCC
Current
µA
[6]
IIL
Input or I/O LOW Leakage
Current
0V < VIN < VIN (Max.)
−100 µA
ISC
ICC
Output Short Circuit Current VCC = Max., VOUT = 0.5V[7,8]
−30
−150 mA
Operating Power Supply
Current
VCC = Max.,
IL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
(counter)
5, 7, 10 ns
15, 25 ns
Com’l
115
90
mA
mA
mA
mA
mA
V
15L, 25L ns
10, 15, 25 ns
15L, 25L ns
55
Mil/Ind
Mil/Ind
130
65
Capacitance[8]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
Unit
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
5
5
pF
pF
COUT
Endurance Characteristics[8]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Min.
100
Max.
Unit
N
Normal Programming Conditions
Cycles
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. T is the “instant on” case temperature.
A
3. See the last page of this specification for Group A subgroup testing information.
4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
5. V (Min.) is equal to −3.0V for pulse durations less than 20 ns.
IL
6. The leakage current is due to the internal pull-up resistor on all pins.
7. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
caused by tester ground degradation.
= 0.5V has been chosen to avoid test problems
OUT
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03026 Rev. *B
Page 4 of 14
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PALCE20V8
AC Test Loads and Waveforms
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
GND
≤ 2 ns
≤ 2 ns
5V
S1
R1
OUTPUT
TEST POINT
R2
C
L
Commercial
R1 R2
200Ω 390Ω
Military
Specification
tPD, tCO
PZX, tEA
S1
CL
R1
R2
Measured Output Value
Closed
50 pF
390Ω
750Ω
1.5V
1.5V
t
Z ⎜ H: Open
Z ⎜ L: Closed
tPXZ, tER
H ⎜ Z: Open
L ⎜ Z: Closed
5 pF
H ⎜ Z: VOH − 0.5V
L ⎜ Z: VOL + 0.5V
Commercial and Industrial Switching Characteristics[3]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
tPD
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Input to Output
1
5
1
7.5
1
10
1
15
1
25
ns
Propagation Delay[9]
OE to Output Enable
OE to Output Disable
tPZX
tPXZ
tEA
5
5
6
6
6
9
10
10
10
15
15
15
20
20
25
ns
ns
ns
Input to Output Enable
Delay[8]
tER
Input to Output
6
4
9
5
10
7
15
10
25
12
ns
Disable Delay[8,10]
tCO
tS
Clock to Output Delay[9]
1
3
1
7
1
1
1
ns
ns
Input or Feedback Set-up
Time
10
12
15
tH
tP
Input Hold Time
0
7
0
0
0
0
ns
ns
External Clock Period
(tCO + tS)
12
17
22
27
Shaded areas contain preliminary information.
Notes:
9. Min. times are tested initially and after any design or process changes that may affect these parameters.
10. This parameter is measured as the time after OEpin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below V min. or a previous LOW level has risen to 0.5 volts above V max.
OH
OL
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
internal (1/f
) as measured (see Note 7 above) minus t .
MAX
MAX3 S
Document #: 38-03026 Rev. *B
Page 5 of 14
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PALCE20V8
Commercial and Industrial Switching Characteristics (continued)[3]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
tWH
Description
Clock Width HIGH[8]
Clock Width LOW[8]
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
3
3
5
5
8
8
8
8
12
12
37
ns
ns
tWL
fMAX1
External Maximum
143
83
58
45.5
MHz
Frequency (1/(tCO + tS))[8,11]
fMAX2
fMAX3
tCF
Data Path Maximum
166.6
100
100
62.5
62.5
62.5
50
41.6
40
MHz
MHz
ns
Frequency (1/(tWH + tWL))[8, 12]
Internal Feedback Maximum 166.6
Frequency (1/(tCF + tS))[8,13]
Register Clock to
3
3
6
8
10
Feedback Input[8, 14]
tPR
Power-Up Reset Time[8]
1
1
1
1
1
µs
Military Switching Characteristics[3]
20V8−10
Min. Max.
20V8−15
20V8−25
Parameter
Description
Input to Output Propagation Delay[9]
Min.
Max.
15
Min.
Max.
25
Unit
tPD
tPZX
tPXZ
tEA
tER
tCO
tS
1
10
10
10
10
10
10
1
1
ns
ns
OE to Output Enable
15
20
OE to Output Disable
15
20
ns
Input to Output Enable Delay[8]
Input to Output Disable Delay[8,10]
Clock to Output Delay[9]
Input or Feedback Set-Up Time
Input Hold Time
15
25
ns
15
25
ns
1
10
0
1
12
0
12
1
20
ns
20
0
ns
tH
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[8]
Clock Width LOW[8]
20
8
24
10
10
41.7
40
15
15
25
ns
tWH
tWL
ns
8
ns
fMAX1
fMAX2
fMAX3
tCF
External Maximum Frequency
(1/(tCO + tS)[8,11]
50
MHz
Data Path Maximum Frequency
(1/(tWH + tWL))[8, 12 ]
62.5
62.5
50
50
33.3
33.3
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[8,13]
Register Clock to
6
8
10
Feedback Input[8, 14]
tPR
Power-Up Reset Time[8]
1
1
1
µs
Document #: 38-03026 Rev. *B
Page 6 of 14
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PALCE20V8
Switching Waveform
INPUTS, I/O,
REGISTERED
FEEDBACK
tWH
tWL
tS
tH
CP
tCO
tP
[11]
[11]
[11]
t
t
, t
t
, t
EA PZX
PXZ ER
REGISTERED
OUTPUTS
[11]
EA PZX
tPD
, t
t
, t
PXZ ER
COMBINATORIAL
OUTPUTS
Power-Up Reset Waveform
VCC
90%
10%
POWER
SUPPLY VOLTAGE
tPR
REGISTERED
ACTIVE LOW
OUTPUTS
tS
CLOCK
tWL
t
MAX = 1 µs
PR
Document #: 38-03026 Rev. *B
Page 7 of 14
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PALCE20V8
Functional Logic Diagram for PALCE20V8
PIN NUMBERS DIP(PLCC) PACKAGE
PIN NUMBERS DIP(PLCC)PACKAGE
1 (2)
2 (3)
0
4
8
12
16
20
24
28
32
32
PTD
1
0
23 (27)
22 (26)
CG
0
0
MC7
CL1=2560
CL0=2632
280
320
3 (4)
4 (5)
5 (6)
MC6
CL1=2561
CL0=2633
21 (25)
20 (24)
19 (23)
18 (21)
17 (20)
600
640
MC5
CL1=2562
CL0=2634
920
960
MC4
CL1=2563
CL0=2635
1240
1280
6 (7)
7 (9)
MC3
CL1=2564
CL0=2636
1560
1600
MC2
CL1=2565
CL0=2637
1880
1920
8 (10)
MC1
CL1=2566
CL0=2638
16 (19)
15 (18)
2200
2240
9 (11)
MC0
CL1=2567
CL0=2639
2520
10 (12)
11 (13)
0
1
14 (17)
13 (16)
CG
0
ELECTRONIC SIGNATURE ROW
2569. . . . . . 2630
. . . BYTE1
2568
2631
CG =2704
CG =2705
1
0
BYTE7 BYTE6 . . .
MSB LSB
BYTE0
Document #: 38-03026 Rev. *B
Page 8 of 14
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PALCE20V8
Ordering Information for PALCE20V8
ICC
tPD
tS
tCO
Package
Name
Operating
Range
(mA) (ns)
(ns)
(ns)
Ordering Code
PALCE20V8−5JC
PALCE20V8−7JC
PALCE20V8−7PC
PALCE20V8−10JC
PALCE20V8−10PC
PALCE20V8−10QC
Package Type
115
115
5
3
7
4
5
J64
J64
P13
J64
P13
Q13
J64
P13
D14
L64
J64
P13
Q13
J64
P13
Q13
D14
L64
J64
P13
Q13
J64
P13
Q13
D14
L64
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
Commercial
Commercial
7.5
115
130
10
10
10
10
7
10 PALCE20V8−10JI
PALCE20V8−10PI
Industrial
Military
PALCE20V8−10DMB
PALCE20V8−10LMB
10 PALCE20V8−15JC
PALCE20V8−15PC
PALCE20V8−15QC
12 PALCE20V8−15JI
PALCE20V8−15PI
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
90
15
15
12
12
Commercial
130
Industrial
PALCE20V8−15QI
PALCE20V8−15DMB
PALCE20V8−15LMB
12 PALCE20V8−25JC
PALCE20V8−25PC
PALCE20V8−25QC
20 PALCE20V8−25JI
PALCE20V8−25PI
Military
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
90
25
25
15
20
Commercial
130
Industrial
Military
PALCE20V8−25QI
PALCE20V8−25DMB
PALCE20V8−25LMB
28-Pin Square Leadless Chip Carrier
Shaded areas contain preliminary information.
Ordering Information for PALCE20V8L
ICC
tPD
tS
(ns)
tCO
(ns)
Package
Name
Operating
Range
(mA) (ns)
Ordering Code
Package Type
55
65
15
15
12
10 PALCE20V8L−15JC
PALCE20V8L−15PC
PALCE20V8L−15QC
12 PALCE20V8L−15JI
PALCE20V8L−15PI
J64
P13
Q13
J64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
Commercial
12
Industrial
P13
Q13
D14
L64
J64
PALCE20V8L−15QI
PALCE20V8L−15DMB
PALCE20V8L−15LMB
12 PALCE20V8L−25JC
PALCE20V8L−25PC
PALCE20V8L−25QC
Military
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
55
25
15
Commercial
P13
Q13
Document #: 38-03026 Rev. *B
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PALCE20V8
Ordering Information for PALCE20V8L (continued)
ICC
tPD
tS
(ns)
tCO
(ns)
Package
Name
Operating
Range
(mA) (ns)
Ordering Code
Package Type
65 25
20
20 PALCE20V8L−25JI
PALCE20V8L−25PI
J64
P13
Q13
D14
L64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
Industrial
PALCE20V8L−25QI
PALCE20V8L−25DMB
PALCE20V8L−25LMB
Military
28-Pin Square Leadless Chip Carrier
Document #: 38-03026 Rev. *B
Page 10 of 14
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PALCE20V8
MILITARY SPECIFICATIONS
Group Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
IIX
IOZ
ICC
Switching Characteristics
Parameter
Subgroups
9, 10, 11
tPD
tCO
tS
9, 10, 11
9, 10, 11
9, 10, 11
tH
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
Document #: 38-03026 Rev. *B
Page 11 of 14
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Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
Document #: 38-03026 Rev. *B
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PALCE20V8
Package Diagrams (continued)
24-Lead (300-Mil) PDIP P13
51-85013-*B
24-Lead Quarter Size Outline Q13
51-85055-B
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices,
Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03026 Rev. *B
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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PALCE20V8
Document History Page
Document Title: PALCE20V8 Flash-Erasable Reprogrammable CMOS PAL® Device
Document Number: 38-03026
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106371
122231
213375
07/11/01
12/28/02
See ECN
SZV
RBI
Changed from Spec Number: 38-00367 to 38-03026
*A
Added power-up requirements to Operating Range Information
Added note to title page: “Use Ultra37000 For All New Designs”
*B
FSG
Document #: 38-03026 Rev. *B
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