PALCE20V8L-15JCT [CYPRESS]
Flash PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | PALCE20V8L-15JCT |
| 厂家： | 
CYPRESS |
| 描述： | Flash PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28 闪存 |
| 文件： | 总14页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20V8
PALCE20V8
Flash Erasable,
Reprogrammable CMOS PAL Device
• QSOP package available
Features
— 10, 15, and 25 ns com’l version
—15, and 25 ns military/industrial versions
• High reliability
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
—Proven Flash technology
— 65 mA max. military/industrial
(15, 25 ns)
—100% programming and functional testing
• Standard version has low power
Functional Description
— 90 mA max. commercial
(15, 25 ns)
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
— Individually selectable for registered or combinato-
rial operation
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
CLK/I
0
12
11
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(64 x 40)
8
8
8
8
8
8
8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13
OE/I
14
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
24
I
12
I
13
V
CC
11
0
1
2
3
4
5
6
7
20V8–1
PAL is a registered trademark of Advanced Micro Devices, Inc.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03026 Rev. **
Revised March 26, 1997
PALCE20V8
Pin Configuration
PLCC/LCC
Top View
DIP/QSOP
Top View
CLK/I
1
2
3
4
5
6
24
23
22
V
0
CC
I
13
I
1
I
2
I/O
4
3
2
1
2827 26
25
7
I
I/O
3
21
20
19
18
17
6
I
3
5
I/O
6
I
4
I/O
I/O
I
I
5
5
6
7
8
9
10
11
4
I/O
5
24
23
22
21
20
19
I
5
4
I/O
4
I
6
I/O
I/O
7
8
3
NC
NC
I/O
I
7
2
I
6
3
I/O
I
I
9
9
1
16
15
14
13
I
8
I/O
2
I/O
1
7
I
8
10
11
12
I/O
0
121314 1516 1718
I
I
12
10
OE/I
GND
11
20V8–3
20V8–2
Selection Guide
tPD ns
tS ns
tCO ns
ICC mA
Generic Part Number
PALCE20V8−5
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l
115
115
115
90
Mil/Ind
5
3
4
5
PALCE20V8−7
7.5
10
15
25
15
25
7
PALCE20V8−10
PALCE20V8−15
PALCE20V8−25
PALCE20V8L−15
PALCE20V8L−25
10
15
25
15
25
10
12
15
12
15
10
12
20
12
20
7
10
12
20
12
20
130
130
130
65
10
12
10
12
90
55
55
65
Shaded area contains preliminary information.
Electronic Signature
Functional Description (continued)
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
Security Bit
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Power-Up Reset
Input and I/O Pin Pull-Ups
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, VCC, or
Ground to improve noise immunity and reduce ICC
.
Document #: 38-03026 Rev. **
Page 2 of 14
PALCE20V8
Configuration Table
CG0
CG1
CL0x
Cell Configuration
Registered Output
Devices Emulated
Registered Med PALs
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
Combinatorial I/O
Combinatorial Output
Input
Registered Med PALs
Small PALs
Small PALs
Combinatorial I/O
20L8 only
Macrocell
To
1 1
Adjacent
Macrocell
OE
1 0
0 0
1 1
V
CC
0 X
1 0
0 1
CL0
x
CG
1
1 1
0 X
I/O
x
D
Q
Q
1 0
V
CC
CLK
1 0
1 1
0 X
CL1
x
From
Adjacent
Pin
CG for pin 16 to 21 (DIP)
1
CL0
x
20V8–4
CG for pin 15 and 22 (DIP)
0
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.................................................. −55°C to +125°C
Range
Commercial
Industrial
Temperature
VCC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
0°C to +75°C
5V ±5%
5V ±10%
5V ±10%
−40°C to +85°C
−55°C to +125°C
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
Military[1]
Note:
DC Input Voltage .................................................−0.5V to +7.0V
1. TA is the “instant on” case temperature.
Document #: 38-03026 Rev. **
Page 3 of 14
PALCE20V8
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
IOH = −3.2 mA
IOH = −2 mA
IOL = 24 mA
Min.
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
VIN = VIH or VIL
Com’l
Mil/Ind
Com’l
Mil/Ind
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
0.5
V
IOL = 12 mA
VIH
Input HIGH Level
Input LOW Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
2.0
V
V
[4]
VIL
−0.5
0.8
10
IIH
Input or I/O HIGH Leakage 3.5V < VIN < VCC
Current
µA
[5]
IIL
Input or I/O LOW Leakage
Current
0V < VIN < VIN (Max.)
−100 µA
ISC
ICC
Output Short Circuit Current VCC = Max., VOUT = 0.5V[6,7]
−30
−150 mA
Operating Power Supply
Current
VCC = Max.,
VIL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
5, 7, 10 ns
15, 25 ns
Com’l
115
90
mA
mA
mA
mA
mA
15L, 25L ns
10, 15, 25 ns
15L, 25L ns
55
(counter)
Mil/Ind
Mil/Ind
130
65
Capacitance[7]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
Unit
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
5
5
pF
pF
COUT
Endurance Characteristics[7]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Min.
100
Max.
Unit
N
Normal Programming Conditions
Cycles
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
VIL (Min.) is equal to −3.0V for pulse durations less than 20 ns.
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03026 Rev. **
Page 4 of 14
PALCE20V8
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
3.0V
90%
10%
10%
GND
≤ 2 ns
≤ 2 ns
20V8–5
5V
S1
R1
OUTPUT
TEST POINT
R2
C
L
20V8–6
Commercial
R1 R2
200Ω 390Ω
Military
Specification
tPD, tCO
tPZX, tEA
S1
CL
R1
390Ω
R2
Measured Output Value
Closed
50 pF
750Ω
1.5V
1.5V
Z ➧ H: Open
Z ➧ L: Closed
tPXZ, tER
H ➧ Z: Open
L ➧ Z: Closed
5 pF
H ➧ Z: VOH − 0.5V
L ➧ Z: VOL + 0.5V
Document #: 38-03026 Rev. **
Page 5 of 14
PALCE20V8
Commercial and Industrial Switching Characteristics[2]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPD
Input to Output
1
5
1
7.5
1
10
1
15
1
25
ns
Propagation Delay[8]
OE to Output Enable
OE to Output Disable
tPZX
tPXZ
tEA
5
5
6
6
6
9
10
10
10
15
15
15
20
20
25
ns
ns
ns
Input to Output
Enable Delay[7]
tER
Input to Output
6
4
9
5
10
7
15
10
25
12
ns
Disable Delay[7,9]
tCO
tS
Clock to Output Delay[8]
1
3
1
7
1
1
1
ns
ns
Input or Feedback
Set-Up Time
10
12
15
tH
tP
Input Hold Time
0
7
0
0
0
0
ns
ns
External Clock Period
(tCO + tS)
12
17
22
27
tWH
Clock Width HIGH[7]
Clock Width LOW[7]
3
3
5
5
8
8
8
8
12
12
37
ns
ns
tWL
fMAX1
External Maximum
143
83
58
45.5
MHz
Frequency (1/(tCO + tS))[7,10]
fMAX2
Data Path Maximum
Frequency
166.
6
100
100
62.5
62.5
62.5
50
41.6
40
MHz
(1/(tWH + tWL))[7, 11]
fMAX3
tCF
Internal Feedback Maximum 166.
MHz
ns
Frequency (1/(tCF + tS))[7,12]
6
Register Clock to
3
3
6
8
10
Feedback Input[7, 13]
tPR
Power-Up Reset Time[7]
1
1
1
1
1
µs
Shaded area contains preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max.
10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
13. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.
Document #: 38-03026 Rev. **
Page 6 of 14
PALCE20V8
Military Switching Characteristics[2]
20V8−10
20V8−15
20V8−25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
1
10
1
15
1
25
ns
Propagation Delay[8]
tPZX
tPXZ
tEA
tER
tCO
tS
OE to Output Enable
10
10
10
10
10
15
15
15
15
12
20
20
25
25
20
ns
ns
OE to Output Disable
Input to Output Enable Delay[7]
Input to Output Disable Delay[7,9]
Clock to Output Delay[8]
Input or Feedback Set-Up Time
Input Hold Time
ns
ns
1
10
0
1
12
0
1
ns
20
0
ns
tH
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[7]
Clock Width LOW[7]
20
8
24
10
10
41.7
40
15
15
25
ns
tWH
tWL
ns
8
ns
fMAX1
fMAX2
fMAX3
tCF
External Maximum Frequency
(1/(tCO + tS)[7,10]
50
MHz
Data Path Maximum Frequency
(1/(tWH + tWL))[7, 11 ]
62.5
62.5
50
50
33.3
33.3
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[7,12]
Register Clock to
6
8
10
Feedback Input[7, 13]
tPR
Power-Up Reset Time[7]
1
1
1
µs
Shaded area contains preliminary information.
Document #: 38-03026 Rev. **
Page 7 of 14
PALCE20V8
Switching Waveform
INPUTS, I/O,
REGISTERED
FEEDBACK
tWH
tWL
tS
tH
CP
tCO
tP
[10]
[10]
[10]
t
t
, t
t
, t
EA PZX
PXZ ER
REGISTERED
OUTPUTS
[10]
tPD
, t
t
, t
PXZ ER
EA PZX
COMBINATORIAL
OUTPUTS
20V8–7
Power-Up Reset Waveform
VCC
90%
10%
POWER
SUPPLY VOLTAGE
tPR
REGISTERED
ACTIVE LOW
OUTPUTS
tS
CLOCK
tWL
t
MAX= 1 µs
20V8–8
PR
Document #: 38-03026 Rev. **
Page 8 of 14
PALCE20V8
Functional Logic Diagram for PALCE20V8
PIN NUMBERS DIP(PLCC) PACKAGE
PIN NUMBERS DIP(PLCC)PACKAGE
1 (2)
0
4
8
12
16
20
24
28
32
32
PTD
1
0
2 (3)
23 (27)
22 (26)
CG
0
0
MC7
CL1=2560
CL0=2632
280
320
3 (4)
4 (5)
5 (6)
MC6
CL1=2561
CL0=2633
21 (25)
20 (24)
600
640
MC5
CL1=2562
CL0=2634
920
960
MC4
CL1=2563
CL0=2635
19 (23)
18 (21)
17 (20)
16 (19)
15 (18)
1240
1280
6 (7)
7 (9)
MC3
CL1=2564
CL0=2636
1560
1600
MC2
CL1=2565
CL0=2637
1880
1920
8 (10)
MC1
CL1=2566
CL0=2638
2200
2240
9 (11)
MC0
CL1=2567
CL0=2639
2520
10 (12)
11 (13)
0
1
14 (17)
13 (16)
CG
0
ELECTRONIC SIGNATURE ROW
2569. . . . . . 2630
. . . BYTE1
2568
2631
CG =2704
1
0
BYTE7 BYTE6 . . .
MSB LSB
BYTE0
CG =2705
20V8–9
Document #: 38-03026 Rev. **
Page 9 of 14
PALCE20V8
Ordering Information for PALCE20V8
ICC
tPD
tS
tCO
Package
Name
Operating
Range
(mA) (ns)
(ns)
(ns)
Ordering Code
PALCE20V8−5JC
PALCE20V8−7JC
PALCE20V8−7PC
PALCE20V8−10JC
PALCE20V8−10PC
PALCE20V8−10QC
Package Type
115
115
5
3
7
4
5
J64
J64
P13
J64
P13
Q13
J64
P13
D14
L64
J64
P13
Q13
J64
P13
Q13
D14
L64
J64
P13
Q13
J64
P13
Q13
D14
L64
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
Commercial
Commercial
7.5
115
130
10
10
10
10
7
10 PALCE20V8−10JI
PALCE20V8−10PI
Industrial
Military
PALCE20V8−10DMB
PALCE20V8−10LMB
10 PALCE20V8−15JC
PALCE20V8−15PC
PALCE20V8−15QC
12 PALCE20V8−15JI
PALCE20V8−15PI
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
90
15
15
12
12
Commercial
130
Industrial
PALCE20V8−15QI
PALCE20V8−15DMB
PALCE20V8−15LMB
12 PALCE20V8−25JC
PALCE20V8−25PC
PALCE20V8−25QC
20 PALCE20V8−25JI
PALCE20V8−25PI
Military
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
90
25
25
15
20
Commercial
130
Industrial
Military
PALCE20V8−25QI
PALCE20V8−25DMB
PALCE20V8−25LMB
28-Pin Square Leadless Chip Carrier
Shaded area contains preliminary information.
Document #: 38-03026 Rev. **
Page 10 of 14
PALCE20V8
Ordering Information for PALCE20V8L
ICC
tPD
tS
(ns)
tCO
(ns)
Package
Name
Operating
Range
(mA) (ns)
Ordering Code
Package Type
55
65
15
15
12
10 PALCE20V8L−15JC
PALCE20V8L−15PC
PALCE20V8L−15QC
12 PALCE20V8L−15JI
PALCE20V8L−15PI
J64
P13
Q13
J64
P13
Q13
D14
L64
J64
P13
Q13
J64
P13
Q13
D14
L64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
Commercial
12
Industrial
PALCE20V8L−15QI
PALCE20V8L−15DMB
PALCE20V8L−15LMB
12 PALCE20V8L−25JC
PALCE20V8L−25PC
PALCE20V8L−25QC
20 PALCE20V8L−25JI
PALCE20V8L−25PI
Military
28-Pin Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Quarter-Size Outline
24-Lead (300-Mil) CerDIP
55
65
25
25
15
20
Commercial
Industrial
Military
PALCE20V8L−25QI
PALCE20V8L−25DMB
PALCE20V8L−25LMB
28-Pin Square Leadless Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
1, 2, 3
ICC
DC Characteristics
Parameter
VOH
Subgroups
1, 2, 3
Switching Characteristics
Parameter
Subgroups
9, 10, 11
VOL
VIH
VIL
IIX
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tPD
tCO
tS
9, 10, 11
9, 10, 11
9, 10, 11
tH
IOZ
Document #: 38-03026 Rev. **
Page 11 of 14
PALCE20V8
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL−STD−1835 D−9 Config.A
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL−STD−1835 C−4
Document #: 38-03026 Rev. **
Page 12 of 14
PALCE20V8
Package Diagrams (continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead Quarter Size Outline Q13
Document #: 38-03026 Rev. **
Page 13 of 14
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PALCE20V8
Document Title: PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL® Device
Document Number: 38-03026
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
Change from Spec Number: 38-00367 to 38-03026
**
106371
07/11/01
SZV
Document #: 38-03026 Rev. **
Page 14 of 14
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明