MB9BF124MPMC [CYPRESS]
RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 72MHz, CMOS, PQFP80,;型号: | MB9BF124MPMC |
厂家: | CYPRESS |
描述: | RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 72MHz, CMOS, PQFP80, 微控制器 外围集成电路 |
文件: | 总104页 (文件大小:2802K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MB9B120M Series
32-bit ARMTM CortexTM-M3 based Microcontroller
MB9BF124K/L/M, MB9BF122K/L/M,
MB9BF121K/L/M
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9BF124M_DS706-00050
Revision 2.0
Issue Date April 17, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
MB9B120M Series
32-bit ARMTM CortexTM-M3 based Microcontroller
MB9BF124K/L/M, MB9BF122K/L/M,
MB9BF121K/L/M
Data Sheet (Full Production)
DESCRIPTION
The MB9B120M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO,
I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9BF124M_DS706-00050
Revision 2.0
Issue Date April 17, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
FEATURES
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Dual Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240Kbytes upper bank + 16Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max 8channels)
4 channels with 16steps×9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)
Operation mode is selectable from the followings for each channel.
UART
CSIO
LIN
I2C
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit length)
LIN break delimiter generation (can be changed to 1 to 4-bit length)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[I2C]
Standard mode (Max 100kbps) / Fast mode (Max 400kbps) supported
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D a t a S h e e t
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 26channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 0.8μs @ 5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
D/A Converter (Max 2channels)
R-2R type
10-bit resolution
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover,
the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 65 high-speed general-purpose I/O Ports @ 80pin Package
Some ports are 5V tolerant.
See "LIST OF PIN FUNCTIONS" and "I/O CIRCUIT TYPE" to confirm the
corresponding pins
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
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D a t a S h e e t
Quadrature Position/Revolution Counter (QPRC) (Max 2channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
Output compare × 6ch./unit
A/D activation compare × 2ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
Up to 23 external interrupt input pins @ 80pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the
"Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby
RTC, Deep standby STOP modes.
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D a t a S h e e t
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock
Sub Clock
Built-in high-speed CR Clock
Built-in low-speed CR Clock
Main PLL Clock
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is asserted.
If external frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable between keeping the value of RAM and not)
Deep standby STOP (selectable between keeping the value of RAM and not)
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41 bits) is set.
Power Supply
Wide range voltage: VCC = 2.7V to 5.5V
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D a t a S h e e t
PRODUCT LINEUP
Memory size
Product name
MB9BF121K/L/M
MB9BF122K/L/M
MB9BF124K/L/M
On-chip
Flash
memory
Main area
64 Kbytes
32 Kbytes
128 Kbytes
256 Kbytes
Work area
32 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
SRAM0
SRAM1
Total
8 Kbytes
8 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
On-chip
SRAM
Function
MB9BF121K
MB9BF122K
MB9BF124K
48
MB9BF121L
MB9BF122L
MB9BF124L
64
Cortex-M3
72 MHz
MB9BF121M
MB9BF122M
MB9BF124M
80/96
Product name
Pin count
CPU
Freq.
Power supply voltage range
DMAC
2.7V to 5.5V
8ch.
4ch. (Max)
ch.0/1/3: FIFO
ch.5: No FIFO
8ch. (Max)
ch.0/1/3/4 FIFO
ch.2/5/6/7: No FIFO
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
(In ch.1/5, only UART
and LIN are available.)
(In ch.1, only UART and LIN are available.)
Base Timer
(PWC/Reload timer/PWM/PPG)
8ch. (Max)
A/D activation
compare
2ch.
Input capture
Free-run timer
Output compare
Waveform
generator
4ch.*
3ch.
6ch.
MF-
Timer
1 unit
3ch.
3ch.
PPG
QPRC
1ch.
2ch. (Max)
Dual Timer
1 unit
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
14pins (Max) +
NMI × 1
35pins (Max)
14ch. (2 units)
19pins (Max) +
NMI × 1
50pins (Max)
23ch. (2 units)
2ch. (Max)
Yes
23pins (Max) +
NMI × 1
65pins (Max)
26ch. (2 units)
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
2ch.
High-speed
Low-speed
4 MHz
Built-in CR
100 kHz
SWJ-DP
Yes
Debug Function
Unique ID
*: The external input channel which can be used is shown as follws.
ch.0 to ch.3 : MB9BF121M/F122M/F124M
ch.0, ch.2, ch.3 : MB9BF121K/F122K/F124K, MB9BF121L/F122L/F124L
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation
Characteristics" for accuracy of built-in CR.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
PACKAGES
MB9BF121K
MB9BF122K
MB9BF124K
MB9BF121L
MB9BF122L
MB9BF124L
MB9BF121M
MB9BF122M
MB9BF124M
-
Product name
Package
LQFP: FPT-48P-M49 (0.5mm pitch)
QFN: LCC-48P-M73 (0.5mm pitch)
LQFP: FPT-64P-M38 (0.5mm pitch)
LQFP: FPT-64P-M39 (0.65mm pitch)
QFN: LCC-64P-M24 (0.5mm pitch)
LQFP: FPT-80P-M37 (0.5mm pitch)
LQFP: FPT-80P-M40 (0.65mm pitch)
BGA: BGA-96P-M07 (0.5mm pitch)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
: Supported
Note: See "PACKAGE DIMENSIONS" for detailed information on each package.
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
PIN ASSIGNMENT
FPT-80P-M37/M40
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
60 P20/INT05_0/CROUT_0/AIN1_1
59 P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2
58 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
57 P23/AN12/SCK0_0/TIOA7_1
56 P1B/AN11/SOT4_1/INT20_2/IC01_1
55 P1A/AN10/SIN4_1/INT05_1/IC00_1
54 P19/AN09/SCK2_2
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P53/SIN6_0/TIOA1_2/INT07_2
P54/SOT6_0/TIOB1_2/INT18_1
P55/SCK6_0/ADTG_1/INT19_1
P56/INT08_2
53 P18/AN08/SOT2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
52 AVRL
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 10
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 12
P39/DTTI0X_0/INT06_0/ADTG_2 13
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 14
P3B/RTO01_0/TIOA1_1 15
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1
48 P16/AN06/SCK0_1/INT15_0
47 P15/AN05/SOT0_1/INT14_0/IC03_2
46 P14/AN04/SIN0_1/INT03_1/IC02_2
45 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2 16
P3D/RTO03_0/TIOA3_1 17
44 P12/AN02/SOT1_1/IC00_2
43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
42 P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2 18
P3F/RTO05_0/TIOA5_1 19
VSS 20
41 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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D a t a S h e e t
FPT-64P-M38/M39
(TOP VIEW)
VCC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P21/AN14/SIN0_0/INT06_1/WKUP2
P22/AN13/SOT0_0/TIOB7_1
P23/AN12/SCK0_0/TIOA7_1
P19/AN09/SCK2_2
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P30/AN25/AIN0_0/TIOB0_1/INT03_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
3
4
5
P18/AN08/SOT2_2
6
AVRL
7
AVRH
LQFP - 64
8
AVCC
9
P17/AN07/SIN2_2/INT04_1
P15/AN05/SOT0_1/INT14_0/IC03_2
P14/AN04/SIN0_1/INT03_1/IC02_2
AVSS
10
11
12
13
14
15
16
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
VSS
VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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D a t a S h e e t
LCC-64P-M24
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
48 P21/AN14/SIN0_0/INT06_1/WKUP2
47 P22/AN13/SOT0_0/TIOB7_1
46 P23/AN12/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVRL
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P30/AN25/AIN0_0/TIOB0_1/INT03_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/DTTI0X_0/INT06_0/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05/SOT0_1/INT14_0/IC03_2
38 P14/AN04/SIN0_1/INT03_1/IC02_2
37 AVSS
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10
P3B/RTO01_0/TIOA1_1 11
P3C/RTO02_0/TIOA2_1/INT18_2 12
P3D/RTO03_0/TIOA3_1 13
36 P12/AN02/SOT1_1/IC00_2
35 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
34 P10/AN00
P3E/RTO04_0/TIOA4_1/INT19_2 14
P3F/RTO05_0/TIOA5_1 15
VSS 16
33 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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D a t a S h e e t
FPT-48P-M49
(TOP VIEW)
VCC
1
2
36
P21/AN14/SIN0_0/INT06_1/WKUP2
P22/AN13/SOT0_0/TIOB7_1
P23/AN12/SCK0_0/TIOA7_1
AVRL
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/INT06_0/ADTG_2
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
35
34
33
32
31
30
29
28
27
26
25
3
4
5
AVRH
6
AVCC
LQFP - 48
7
P15/AN05/SOT0_1/INT14_0/IC03_2
P14/AN04/SIN0_1/INT03_1/IC02_2
AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
8
9
P3E/RTO04_0/TIOA4_1/INT19_2
P3F/RTO05_0/TIOA5_1
10
11
12
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
P10/AN00
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
LCC-48P-M73
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
36 P21/AN14/SIN0_0/INT06_1/WKUP2
35 P22/AN13/SOT0_0/TIOB7_1
34 P23/AN12/SCK0_0/TIOA7_1
33 AVRL
P50/AN22/INT00_0/AIN0_2/SIN3_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/INT06_0/ADTG_2
32 AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
P3B/RTO01_0/TIOA1_1
31 AVCC
QFN - 48
30 P15/AN05/SOT0_1/INT14_0/IC03_2
29 P14/AN04/SIN0_1/INT03_1/IC02_2
28 AVSS
P3C/RTO02_0/TIOA2_1/INT18_2
P3D/RTO03_0/TIOA3_1
P3E/RTO04_0/TIOA4_1/INT19_2 10
P3F/RTO05_0/TIOA5_1 11
VSS 12
27 P12/AN02/SOT1_1/IC00_2
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1
25 P10/AN00
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
13
D a t a S h e e t
BGA-96P-M07
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
TRSTX
VSS
VSS
VCC
AN22
P53
P81
VSS
AN23
P54
AN25
VSS
P33
P3B
P3E
VSS
C
P80
AN24
VSS
P55
VCC
AN20
AN21
Index
VSS
P63
AN18
P0D
P0E
VSS
AN17
AN16
P07
VSS
TDI
TDO/
SWO
TCK/
SWCLK
AN19
AN15
VSS
AN13
AN11
AN08
AN06
P20
AN14
VSS
AN09
AN12
AN10
P56
AN26
VSS
P39
VSS
P32
AN07 AVRH
AN05 AVRL
G
H
J
P3A
P3D
VCC
VSS
P3C
VSS
X1A
X0A
AN04 AVSS AVCC
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
VSS
MD1
X0
AN01
VSS
X1
AN00
VCC
VSS
K
L
MD0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
LIST OF PIN FUNCTIONS
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
I/O circuit Pin state
Pin Name
LQFP-64 LQFP-48
type
type
LQFP-80
BGA-96
QFN-64
QFN-48
1
B1
1
1
VCC
P50
-
INT00_0
AIN0_2
SIN3_1
AN22
2
3
C1
C2
2
3
2
3
F
N
P51
INT01_0
BIN0_2
F
F
N
N
SOT3_1
(SDA3_1)
AN23
P52
INT02_0
ZIN0_2
4
B3
4
4
SCK3_1
(SCL3_1)
AN24
P53
SIN6_0
TIOA1_2
INT07_2
P54
5
6
D1
D2
-
-
-
-
E
E
L
L
SOT6_0
(SDA6_0)
TIOB1_2
INT18_1
P55
SCK6_0
(SCL6_0)
7
8
9
D3
E1
E2
-
-
-
-
-
E
E
F
L
L
N
ADTG_1
INT19_1
P56
INT08_2
P30
AIN0_0
TIOB0_1
INT03_2
AN25
5
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
15
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin Name
LQFP-64
LQFP-48
QFN-48
type
type
LQFP-80
BGA-96
QFN-64
P31
BIN0_0
TIOB1_1
10
E3
6
-
-
F
N
SCK6_1
(SCL6_1)
INT04_2
AN26
P32
ZIN0_0
TIOB2_1
11
G1
7
E
L
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
P39
12
13
G2
G3
8
9
-
E
E
L
L
DTTI0X_0
INT06_0
ADTG_2
P3A
5
RTO00_0
(PPG00_0)
TIOA0_1
INT07_0
SUBOUT_2
RTCCO_2
P3B
14
H1
10
6
G
L
RTO01_0
(PPG00_0)
15
16
17
H2
H3
J1
11
12
13
7
8
9
G
G
G
K
L
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
INT18_2
P3D
RTO03_0
(PPG02_0)
K
TIOA3_1
16
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin Name
LQFP-64
QFN-64
LQFP-48
QFN-48
type
type
LQFP-80
BGA-96
P3E
RTO04_0
(PPG04_0)
18
J2
14
10
G
L
TIOA4_1
INT19_2
P3F
RTO05_0
(PPG04_0)
19
J4
15
11
G
K
TIOA5_1
20
21
L1
L5
16
-
12
-
VSS
P44
TIOA4_0
INT10_0
P45
TIOA5_0
INT11_0
C
-
G
G
L
L
22
K5
-
-
23
24
25
L2
L4
K1
17
-
13
-
-
-
-
VSS
VCC
18
14
P46
26
L3
19
15
D
F
X0A
P47
27
28
K3
K4
20
21
16
17
D
B
G
C
X1A
INITX
P48
29
J5
-
-
18
-
INT14_1
SIN3_2
P49
E
L
TIOB0_0
INT20_1
DA0_0
30
K6
22
L
L
SOT3_2
(SDA3_2)
AIN0_1
P4A
TIOB1_0
INT21_1
DA1_0
19
-
31
J6
23
L
L
SCK3_2
(SCL3_2)
BIN0_1
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
17
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
I/O circuit Pin state
Pin Name
type
type
LQFP-80
BGA-96
QFN-64
QFN-48
P4B
TIOB2_0
INT22_1
IGTRG_0
ZIN0_1
P4C
32
L7
24
-
E
L
TIOB3_0
SCK7_1
(SCL7_1)
33
K7
25
-
I*
L
INT12_0
AIN1_2
P4D
TIOB4_0
SOT7_1
(SDA7_1)
34
35
J7
26
27
-
-
I*
I*
L
L
INT13_0
BIN1_2
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MD1
K8
36
37
38
K9
L8
L9
28
29
30
20
21
22
C
K
A
E
D
A
PE0
MD0
X0
PE2
X1
39
L10
31
23
A
F
F
B
M
N
PE3
40
41
L11
K11
32
33
24
-
VSS
-
-
VCC
P10
42
J11
34
25
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
WKUP1
P12
43
J10
35
26
AN02
44
J8
36
27
F
M
SOT1_1
(SDA1_1)
IC00_2
18
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin Name
LQFP-64 LQFP-48
type
type
LQFP-80
BGA-96
QFN-64
QFN-48
45
H10
37
28
AVSS
P14
-
AN04
INT03_1
IC02_2
SIN0_1
P15
46
47
H9
38
39
29
30
F
N
AN05
IC03_2
G10
F
N
SOT0_1
(SDA0_1)
INT14_0
P16
AN06
48
49
G9
-
-
-
F
F
N
N
SCK0_1
(SCL0_1)
INT15_0
P17
AN07
SIN2_2
INT04_1
AVCC
AVRH
AVRL
P18
F10
40
50
51
52
H11
F11
G11
41
42
43
31
32
33
-
-
-
AN08
53
54
F9
44
45
-
-
F
F
M
M
SOT2_2
(SDA2_2)
P19
AN09
E11
SCK2_2
(SCL2_2)
P1A
AN10
55
E10
-
-
SIN4_1
INT05_1
IC00_1
F
N
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
19
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
I/O circuit Pin state
Pin Name
type
type
LQFP-80
BGA-96
QFN-64
QFN-48
P1B
AN11
SOT4_1
(SDA4_1)
56
E9
D10
D9
-
-
F
N
IC01_1
INT20_2
P23
SCK0_0
(SCL0_0)
57
58
46
34
F
F
M
M
TIOA7_1
AN12
P22
SOT0_0
(SDA0_0)
47
-
35
-
TIOB7_1
AN13
ZIN1_1
P21
SIN0_0
INT06_1
WKUP2
BIN1_1
AN14
P20
59
60
C11
C10
48
36
F
E
N
N
INT05_0
CROUT_0
AIN1_1
P00
-
-
61
62
63
64
A10
B9
49
50
51
52
37
38
39
40
E
E
E
E
J
J
J
J
TRSTX
P01
TCK
SWCLK
P02
B11
A9
TDI
P03
TMS
SWDIO
P04
65
66
B8
A8
53
-
41
-
TDO
E
E
J
SWO
P07
ADTG_0
INT23_1
L
20
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
I/O circuit Pin state
Pin Name
LQFP-64 LQFP-48
type
type
LQFP-80
BGA-96
QFN-64
QFN-48
P0A
SIN4_0
INT00_2
AN15
67
C8
54
-
J*
N
P0B
SOT4_0
(SDA4_0)
68
69
C7
B7
55
56
-
-
J*
J*
N
N
TIOB6_1
AN16
INT18_0
P0C
SCK4_0
(SCL4_0)
TIOA6_1
INT19_0
AN17
P0D
RTS4_0
TIOA3_2
INT20_0
P0E
70
71
B6
C6
-
-
-
-
E
E
L
L
CTS4_0
TIOB3_2
INT21_0
P0F
NMIX
SUBOUT_0
CROUT_1
RTCCO_0
WKUP0
AN18
72
A6
57
42
F
I
P63
73
74
B5
C5
-
-
-
E
F
L
INT03_0
P62
SCK5_0
(SCL5_0)
58
M
ADTG_3
AN19
P61
SOT5_0
(SDA5_0)
75
B4
59
43
F
M
TIOB2_2
DTTI0X_2
AN20
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
21
D a t a S h e e t
Pin No
LQFP-64
I/O circuit Pin state
Pin Name
LQFP-48
QFN-48
type
type
LQFP-80
BGA-96
QFN-64
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
IGTRG_1
AN21
76
C4
60
44
J*
N
77
78
A4
A3
61
62
45
46
VCC
-
P80
H
H
H
H
INT16_1
P81
79
80
A2
A1
63
64
47
48
INT17_1
VSS
-
-
A5, A7, A11,
B2, B10, C3,
C9, F1, F2,
F3, J3, J9, K2,
K10, L6
-
-
-
VSS
*: 5V tolerant I/O
22
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
List of functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin
function
Pin name
Function description
LQFP-64 LQFP-48
QFN-64 QFN-48
LQFP-80 BGA-96
ADC
ADTG_0
ADTG_1
66
7
A8
D3
G3
C5
G2
J11
J10
J8
H9
G10
G9
F10
F9
-
-
9
58
8
34
35
36
38
39
-
40
44
45
-
-
-
5
-
-
25
26
27
29
30
-
ADTG_2 A/D converter external trigger input pin
13
74
12
42
43
44
46
47
48
49
53
54
55
56
57
58
59
67
68
69
72
74
75
76
2
ADTG_3
ADTG_6
AN00
AN01
AN02
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
-
-
-
-
E11
E10
E9
-
-
D10
D9
C11
C8
C7
B7
A6
C5
B4
C4
C1
C2
B3
E2
46
47
48
54
55
56
57
58
59
60
2
34
35
36
-
-
-
42
-
43
44
2
A/D converter analog input pin.
ANxx describes ADC ch.xx.
3
4
9
10
3
4
5
6
3
4
-
-
E3
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
23
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
Base Timer
0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOB4_0
TIOA5_0
TIOA5_1
TIOB5_0
TIOA6_1
TIOB6_1
TIOA7_1
TIOB7_1
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
14
30
9
15
5
31
10
6
H1
K6
E2
H2
D1
J6
E3
D2
H3
C4
L7
G1
B4
J1
B6
K7
G2
C6
L5
J2
10
22
5
11
-
23
6
-
12
60
24
7
59
13
-
25
8
-
6
18
-
7
-
19
-
-
8
44
-
-
43
9
-
-
-
-
-
10
-
Base Timer
1
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base Timer
2
16
76
32
11
75
17
70
33
12
71
21
18
34
22
19
35
69
68
57
58
Base Timer
3
Base Timer
4
-
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
14
26
-
15
27
56
55
46
47
J7
K5
J4
K8
B7
C7
D10
D9
Base Timer
5
-
11
-
-
-
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input
pin
Base Timer
6
Base Timer
7
Debugger
34
35
SWCLK
SWDIO
62
64
B9
A9
50
52
38
40
Serial wire debug interface data input /
output pin
SWO
TCK
TDI
TDO
TMS
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
J-TAG test reset input pin
65
62
63
65
64
61
B8
B9
B11
B8
A9
A10
53
50
51
53
52
49
41
38
39
41
40
37
TRSTX
24
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
External
Interrupt
INT00_0
INT00_2
INT01_0
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_2
INT08_2
INT10_0
INT11_0
INT12_0
INT13_0
INT14_0
INT14_1
INT15_0
INT15_1
INT16_1
INT17_1
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
INT19_2
INT20_0
INT20_1
INT20_2
INT21_0
INT21_1
INT22_1
INT23_1
NMIX
2
C1
C8
C2
B3
J10
B5
H9
E2
2
54
3
4
35
-
38
5
8
40
6
-
-
7
9
48
27
10
-
-
-
2
-
3
4
26
-
29
-
-
-
-
-
-
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
67
3
4
43
73
46
9
12
49
10
60
55
11
13
59
35
14
5
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
G2
F10
E3
P20
E10
G1
G3
C11
K8
H1
D1
E1
-
5
36
-
6
-
-
-
-
-
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
8
21
22
33
34
47
29
48
76
78
79
68
6
L5
K5
K7
J7
G10
J5
G9
C4
A3
A2
C7
D2
H3
C11
D3
J2
B6
K6
E9
C6
J6
L7
A8
A6
-
25
26
39
-
-
30
-
External interrupt request 14 input pin
External interrupt request 15 input pin
-
-
60
62
63
55
-
12
56
-
14
-
22
-
44
46
47
-
-
8
-
-
10
-
18
-
-
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
16
59
7
18
70
30
56
71
31
32
66
72
External interrupt request 20 input pin
External interrupt request 21 input pin
-
23
24
-
19
-
-
External interrupt request 22 input pin
External interrupt request 23 input pin
Non-Maskable Interrupt input pin
57
42
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
25
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
GPIO
P00
P01
P02
P03
P04
P07
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P14
P15
P16
P17
P18
P19
P1A
P1B
P20
P21
P22
P23
P30
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
61
A10
B9
B11
A9
B8
A8
C8
C7
B7
B6
C6
A6
J11
J10
J8
H9
G10
G9
F10
F9
E11
E10
E9
49
50
51
52
53
-
54
55
56
-
37
38
39
40
41
-
-
-
-
-
62
63
64
65
66
67
68
69
70
71
72
42
43
44
46
47
48
49
53
54
55
56
60
59
58
57
9
General-purpose I/O port 0
-
-
57
34
35
36
38
39
-
40
44
45
-
-
-
48
47
46
5
6
7
8
9
10
11
12
13
14
15
42
25
26
27
29
30
-
-
-
-
-
-
-
36
35
34
-
-
-
-
5
General-purpose I/O port 1
General-purpose I/O port 2
General-purpose I/O port 3
C10
C11
D9
D10
E2
10
11
12
13
14
15
16
17
18
19
E3
G1
G2
G3
H1
H2
H3
J1
6
7
8
9
10
11
J2
J4
26
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
GPIO
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
-
-
-
-
15
16
-
18
19
-
-
-
-
2
3
4
-
-
-
-
44
43
-
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
-
46
47
20
22
23
General-purpose I/O port 8
General-purpose I/O port E
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
27
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
Multi-
function
Serial
0
SIN0_0
SIN0_1
59
46
C11
H9
48
38
36
29
Multi-function serial interface ch.0
input pin
Multi-function serial interface ch.0
output pin.
SOT0_0
(SDA0_0)
58
47
57
D9
47
39
46
35
30
34
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1
input pin
Multi-function serial interface ch.1
output pin.
SOT0_1
(SDA0_1)
G10
D10
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
48
43
G9
-
-
Multi-
function
Serial
1
SIN1_1
J10
35
26
SOT1_1
(SDA1_1)
This pin operates as SOT1 when it is
used in a UART/LIN (operation
modes 0,1,3) .
Multi-function serial interface ch.2
input pin
44
49
J8
36
40
27
-
Multi-
function
Serial
2
SIN2_2
F10
Multi-function serial interface ch.2
output pin.
SOT2_2
This pin operates as SOT2 when it is
53
54
F9
44
45
-
-
(SDA2_2) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.2
clock I/O pin.
SCK2_2
(SCL2_2)
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
E11
Multi-
function
Serial
3
SIN3_1
SIN3_2
2
29
C1
J5
2
-
2
-
Multi-function serial interface ch.3
input pin
Multi-function serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
SOT3_1
(SDA3_1)
3
30
4
C2
K6
B3
J6
3
-
3
-
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
4
-
4
-
SCK3_2
(SCL3_2)
31
28
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
Multi-
function
Serial
4
SIN4_0
SIN4_1
67
55
C8
E10
54
-
-
-
Multi-function serial interface ch.4
input pin
Multi-function serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.4
clock I/O pin.
SOT4_0
(SDA4_0)
68
56
C7
E9
55
-
-
-
SOT4_1
(SDA4_1)
SCK4_0
(SCL4_0)
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
69
B7
56
-
Multi-function serial interface ch.4
RTS output pin
Multi-function serial interface ch.4
CTS input pin
Multi-function serial interface ch.5
input pin
RTS4_0
CTS4_0
SIN5_0
70
71
76
B6
C6
C4
-
-
-
-
Multi-
function
Serial
5
60
44
Multi-function serial interface ch.5
output pin.
SOT5_0
This pin operates as SOT5 when it is
75
74
B4
C5
59
58
43
(SDA5_0) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.5
clock I/O pin.
SCK5_0
(SCL5_0)
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
-
Multi-
function
Serial
6
SIN6_0
SIN6_1
5
12
D1
G2
-
8
-
-
Multi-function serial interface ch.6
input pin
Multi-function serial interface ch.6
output pin.
SOT6_0
(SDA6_0)
6
11
7
D2
G1
D3
E3
-
7
-
-
-
-
-
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
10
6
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
29
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
Multi-
function
Serial
7
Multi-function serial interface ch.7
input pin
Multi-function serial interface ch.7
output pin.
SIN7_1
35
K8
27
-
SOT7_1
This pin operates as SOT7 when it is
34
J7
26
-
(SDA7_1) used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.7
clock I/O pin.
SCK7_1
(SCL7_1)
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
33
K7
25
-
Multi-
function
Timer
0
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
Multi-function timer 0.
16-bit free-run timer ch.0 external
clock input pin
DTTI0X_0
DTTI0X_2
13
75
G3
B4
9
5
59
43
FRCK0_2
43
J10
35
26
IC00_1
IC00_2
IC01_1
IC02_2
IC03_2
55
44
56
46
47
E10
J8
E9
H9
G10
-
36
-
38
39
-
27
-
29
30
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
Waveform generator output pin of
Multi-function timer 0.
(PPG00_0) This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
(PPG00_0) This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
(PPG02_0) This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
(PPG04_0) This pin operates as PPG04 when it is
used in PPG0 output mode.
RTO00_0
14
15
16
17
18
19
H1
H2
H3
J1
10
11
12
13
14
15
6
7
RTO01_0
RTO02_0
8
RTO03_0
9
RTO04_0
J2
10
11
RTO05_0
J4
IGTRG_0
IGTRG_1
32
76
L7
C4
24
60
-
44
PPG IGBT mode external trigger input
pin
30
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
Function description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
LQFP-80 BGA-96
QFN-64 QFN-48
Quadrature
Position/
Revolution
Counter 0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
9
30
2
10
31
3
11
32
4
60
33
59
34
58
35
72
14
72
14
E2
K6
C1
E3
J6
C2
G1
L7
B3
C10
K7
C11
J7
D9
K8
A6
H1
A6
H1
5
22
2
6
23
3
7
24
4
-
25
-
-
-
2
-
-
3
-
-
4
-
-
-
-
-
-
42
6
42
6
Quadrature
Position/
Revolution
Counter 1
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
26
-
ZIN1_2
27
57
10
57
10
Real-time
clock
RTCCO_0
RTCCO_2
SUBOUT_0
SUBOUT_2
0.5 seconds pulse output pin of
Real-time clock
Sub clock output pin
Low-Power
Consumption
Mode
Deep standby mode return signal
input pin 0
Deep standby mode return signal
input pin 1
Deep standby mode return signal
input pin 2
Deep standby mode return signal
input pin 3
WKUP0
WKUP1
WKUP2
WKUP3
72
43
59
76
A6
J10
C11
C4
57
35
48
60
42
26
36
44
DAC
DA0
DA1
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
External Reset Input pin.
A reset is valid when INITX="L".
30
31
K6
J6
22
23
18
19
RESET
INITX
28
K4
21
17
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
31
D a t a S h e e t
Pin No
LQFP-64 LQFP-48
Pin
function
Pin name
MD0
Function description
LQFP-80 BGA-96
QFN-64 QFN-48
Mode
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
Mode 1 pin.
37
L8
29
21
MD1
During serial programming to Flash
memory, MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
GND Pin
36
K9
28
20
POWER
GND
VCC
VCC
VCC
VCC
VSS
1
25
41
77
-
B1
K1
K11
A4
F1
1
18
33
61
-
1
14
-
45
-
VSS
GND Pin
-
F2
-
-
VSS
GND Pin
-
F3
-
-
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
-
20
-
B2
L1
K2
J3
-
16
-
-
12
-
-
-
-
VSS
GND Pin
-
L6
-
-
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
24
40
-
L4
-
32
-
-
24
-
L11
K10
J9
-
-
-
VSS
VSS
GND Pin
GND Pin
-
-
B10
C9
-
-
-
-
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
-
-
-
-
D11
A11
A7
C3
-
-
-
-
-
-
-
-
VSS
VSS
X0
X0A
X1
GND Pin
GND Pin
-
A5
A1
L9
-
-
80
38
26
39
27
60
72
64
30
19
31
20
-
48
22
15
23
16
-
CLOCK
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
L3
L10
K3
C10
A6
X1A
CROUT_0
CROUT_1
57
42
Analog
POWER
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference
voltage input pin
A/D converter and D/A converter
GND pin
A/D converter analog reference
voltage input pin
Power supply stabilization capacity
pin
AVCC
AVRH
AVSS
AVRL
C
50
51
45
52
23
H11
F11
H10
G11
L2
41
42
37
43
17
31
32
28
33
13
Analog
GND
C pin
32
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1MΩ
With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
R
: Approximately 50kΩ
IOH= -4mA, IOL= 4mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
R
Digital output
P-ch
P-ch
N-ch
X0
Digital output
Pull-up resistor control
B
CMOS level hysteresis input
Pull-up resistor
: Approximately 50kΩ
Pull-up resistor
Digital input
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
33
D a t a S h e e t
Type
Circuit
Remarks
C
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5MΩ
With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
CMOS level output.
N-ch
R
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH= -4mA, IOL= 4mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
R
Digital output
P-ch
P-ch
N-ch
X0A
Digital output
Pull-up resistor control
34
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
: Approximately 50kΩ
Digital output
Digital output
IOH= -4mA, IOL= 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH= -4mA, IOL= 4mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
35
D a t a S h e e t
Type
Circuit
Remarks
G
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
P-ch
P-ch
IOH= -12mA, IOL= 12mA
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
H
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -18mA, IOL= 16.5mA
P-ch
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
36
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Type
Circuit
Remarks
CMOS level output
CMOS level hysteresis input
5V tolerant
I
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH= -4mA, IOL= 4mA
Available to control PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
J
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5V tolerant
Digital output
Digital output
P-ch
P-ch
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH= -4mA, IOL= 4mA
Available to control PZR
registers.
N-ch
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
K
CMOS level hysteresis input
Mode input
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
37
D a t a S h e e t
Type
L
Circuit
Remarks
CMOS level output
CMOS level hysteresis input
With input control
Analog output
P-ch
P-ch
Digital output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
IOH = -4mA, IOL= 4mA
N-ch
Digital output
Pull-up resistor control
Digital input
R
Standby mode Control
Analog output
38
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
39
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
40
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
41
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
HANDLING DEVICES
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
・ Surface mount type
Size : More than 3.2mm × 1.5mm
Load capacitance : Approximately 6pF to 7pF
・
Lead type
Load capacitance : Approximately 6pF to 7pF
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
43
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
• Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
45
D a t a S h e e t
BLOCK DIAGRAM
MB9BF121K/L/M, F122K/L/M, F124K/L/M
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8/16 Kbytes
SWJ-DP
ROM Table
Cortex-M3ꢀCore
@72MHz(Max)
I
SRAM1
8/16 Kbytes
D
Sys
NVIC
On-Chip Flash
64+32 Kbytes/
128+32 Kbytes/
256+32 Kbytes
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
RST
Main
Osc
X0
X1
PLL
Sub
Osc
CR
4MHz
CR
100kHz
X0A
X1A
AVCC,
AVSS,
AVRH,
AVRL
ANxx
12-bit A/D Converter
Unit 0
Unit 1
Power-On
Reset
ADTGx
DAx
10-bit D/A Converter
2units
LVD
LVD Ctrl
C
Regulator
IRQ-Monitor
Base Timer
16-bit 8ch./
32-bit 4ch.
TIOAx
TIOBx
CRC
Accelerator
AINx
BINx
ZINx
RTCCO_x,
SUBOUT_x
QPRC
2ch.
Real-Time Colck
Watch Counter
A/D Activation
Compare 2ch.
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
16-bit Input Capture
4ch.
IC0x
MD0,
MD1
MODE-Ctrl
16-bit Free-run Timer
3ch.
FRCKx
WKUPx
Deep Standby Ctrl
16-bit Output
Compare 6ch.
P0x,
P1x,
・
・
・
GPIO
PIN-Function-Ctrl
DTTI0X
RTO0x
Waveform Generator
3ch.
PFx
SCKx
Multi-Function Serial I/F
8ch.
(with FIFO ch.0/1/3/4)
HW flow control(ch.4)
SINx
16-bit PPG
3ch.
IGTRG_x
SOTx
CTS4
RTS4
Multi-function Timer
MEMORY SIZE
See " Memory size" in "PRODUCT LINEUP" to confirm the memory size.
46
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
MEMORY MAP
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
External Device
Area
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
RTC
Watch Counter
CRC
0x6000_0000
MFS
Reserved
Reserved
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
0x2008_0000
0x2000_0000
0x1FF8_0000
A/DC
QPRC
Base Timer
PPG
SRAM1
SRAM0
Reserved
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
Reserved
Flash(Work area)
Reserved
Security/CR Trim
0x4002_1000
0x4002_0000
See " Memory Map (2)"
for the memory size
details.
MFT unit0
Reserved
Dual Timer
Reserved
0x4001_6000
0x4001_5000
Flash(Main area)
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x0000_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
47
D a t a S h e e t
MB9BF122K/L/M
Memory Map (2)
MB9BF124K/L/M
MB9BF121K/L/M
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
16Kbytes
SRAM1
8Kbytes
SRAM1
8Kbytes
SRAM0
8Kbytes
SRAM0
8Kbytes
SRAM0
16Kbytes
Reserved
Reserved
Reserved
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
Flash(Work area)
32Kbytes
Flash(Work area)
32Kbytes
Flash(Work area)
32Kbytes
Reserved
Reserved
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
Reserved
Reserved
0x0004_0000
0x0002_0000
0x0000_0000
Flash(Main area)
256Kbytes
0x0001_0000
0x0000_0000
Flash(Main area)
128Kbytes
Flash(Main area)
64Kbytes
0x0000_0000
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
Flash Memory I/F register
AHB
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
APB1
D/A Converter
Reserved
built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
APB2 Deep standby mode Controller
Reserved
Multi-function serial Interface
CRC
Watch Counter
Real-time clock
Reserved
Reserved
AHB
DMAC register
Reserved
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
49
D a t a S h e e t
PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
List of Pin Status
Power-on
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
reset or
low-voltage
detection
state
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
A
Main crystal
oscillator input
pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
External main
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
B
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Main crystal
oscillator output
pin
Internal
Internal
fixed at
"0"/
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
or Input
enable
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
at "0"
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
INITX
C
D
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
Hi-Z /
Input
GPIO
Setting
Setting
Setting
GPIO
GPIO
selected
disabled
disabled
disabled
selected
selected
enabled
enabled
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
51
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
F
Sub crystal
oscillator input
pin /
Input
Input
Input
Input
Input
Input
Input
Input
Input
External sub
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
External sub
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
G
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When
Maintain oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Sub crystal
oscillator output
pin
Internal
Internal
fixed at
"0"/
previous
state
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at "0"
at "0"
or Input
enable
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at "0"
at "0"
at "0"
at "0"
at "0"
Maintain
previous
state
External interrupt
enabled selected
Setting
Setting
Setting
GPIO
selected
Internal
input fixed
at "0"
disabled
disabled
disabled
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
GPIO
H
Hi-Z /
Internal
input fixed
at "0"
selected
Hi-Z /
Input
Hi-Z /
Input
GPIO
Hi-Z
selected
enabled
enabled
Maintain
previous
state
Setting
Setting
Setting
NMIX selected
disabled
disabled
disabled
GPIO
Hi-Z /
WKUP
input
selected
Resource other
than above
selected
Maintain
previous
state
Maintain
previous
state
WKUP
input
I
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
enabled
enabled
Hi-Z
Maintain
previous
state
enabled
enabled
GPIO
selected
52
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Pull-up /
Input
Pull-up /
Input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
Hi-Z
selected
enabled
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at "0"
J
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Resource selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
GPIO
K
Hi-Z
selected
GPIO
enabled
enabled
selected
Analog output
selected
*3
*4
Setting
Setting
Setting
Maintain
previous
state
disabled
disabled
disabled
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
GPIO
L
Maintain
previous
state
Resource other
than above
selected
selected
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
enabled
enabled
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
M
Resource other
than above
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
GPIO
selected
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
53
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return from
Deep
standby
Device Run mode
internal or SLEEP
reset state mode state STOP mode state
Timer mode,
RTC mode, or
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
at "0" /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
N
Maintain
previous
state
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
*1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep
standby RTC mode, and Deep standby STOP mode.
*2 : Oscillation is stopped at STOP mode and Deep standby STOP mode.
*3 : Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*4 : Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
54
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit Remarks
Min
Max
Power supply voltage*1, *2
VCC
AVCC
AVRH
Vss - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
10
V
V
V
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
Input voltage*1
VI
V
V
5V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
mA 4mA type
mA 12mA type
mA P80/P81 pin
mA 4mA type
mA 12mA type
mA P80/P81 pin
mA
"L" level maximum output current*4
"L" level average output current*5
IOL
-
20
39
4
IOLAV
-
12
16.5
100
50
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
mA
- 10
- 20
- 39
- 4
- 12
- 18
- 100
- 50
300
+ 150
mA 4mA type
mA 12mA type
mA P80/P81 pin
mA 4mA type
mA 12mA type
mA P80/P81 pin
mA
mA
mW
°C
"H" level maximum output current*4
IOH
-
-
"H" level average output current*5
IOHAV
"H" level total maximum output current
"H" level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1 : These parameters are based on the condition that VSS = AVSS = 0V.
*2 : VCC must not drop below VSS - 0.5V.
*3 : Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5 : The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6 : The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms period.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
55
D a t a S h e e t
2. Recommended Operating Conditions
(VSS = AVSS = AVRL = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
2.7*2
2.7
Max
5.5
Power supply voltage
VCC
AVCC
AVRH
CS
-
-
-
-
-
V
V
V
μF
°C
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
5.5
AVCC = VCC
2.7
1
AVCC
10
For Regulator*1
Operating temperature
Ta
- 40
+ 105
*1 : See " C Pin" in "HANDLING DEVICES" for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or
more, instruction execution and low voltage detection function by built-in High-speed CR(including Main
PLL is used) or bulit-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
56
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
3. DC Characteristics
(1) Current Rating
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Min Typ Max
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
CPU : 72MHz,
Peripheral : 36MHz
4MHz crystal oscillator
*1, *5
-
32.5
18
41
mA
Normal operation
(PLL)
CPU:72MHz,
Peripheral: clock stops
4MHz crystal oscillator
NOP operation
*1, *5
-
23
mA
ICC
Normal operation
(built-in high-speed
CR)
CPU/ Peripheral : 4MHz*2
*1
-
-
-
2.5
3.4
mA
μA
μA
Normal operation
(sub oscillation)
CPU/ Peripheral : 32kHz
*1, *5
110
980
Normal operation
(built-in low-speed
CR)
CPU/ Peripheral : 100kHz
*1
130 1030
Peripheral : 36MHz
mA 4MHz crystal oscillator
*1, *5
SLEEP operation
(PLL)
-
22
28
SLEEP operation
(built-in high-speed
CR)
SLEEP operation
(sub oscillation)
SLEEP operation
(built-in low-speed
CR)
Peripheral : 4MHz*2
-
-
-
1.6
96
2.6
955
975
mA
*1
Power
supply
current
ICCS
VCC
Peripheral : 32kHz
*1, *5
μA
Peripheral : 100kHz
*1
115
μA
Ta = + 25°C,
-
-
-
-
-
-
14
-
53
600
66
μA
μA
μA
μA
μA
μA
When LVD is off
*1
Ta = + 105°C,
When LVD is off
*1
Ta = + 25°C,
When LVD is off
*1, *5
Ta = + 105°C,
When LVD is off
*1, *5
Ta = + 25°C,
When LVD is off
*1, *5
Ta = + 105°C,
When LVD is off
*1, *5
ICCH
ICCT
ICCR
STOP mode
17
-
TIMER mode
(sub oscillation)
835
61
15
-
RTC mode
(sub oscillation)
680
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
57
D a t a S h e e t
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Min
Ta = + 25°C,
When LVD is off,
When RAM is off
*1, *3
1.6
5.6
9.6
μA
-
Ta = + 25°C,
When LVD is off,
When RAM is on
*1, *3
Ta = + 105°C,
When LVD is off,
When RAM is off
*1, *3
Ta = + 105°C,
When LVD is off,
When RAM is on
*1, *3
22
μA
μA
μA
μA
μA
μA
μA
Deep Standby
STOP mode
ICCHD
150
210
11
-
-
-
-
Power
supply
current
Ta = + 25°C,
When LVD is off,
When RAM is off
*1, *3, *5
2.2
6.2
Ta = + 25°C,
When LVD is off,
When RAM is on
*1, *3, *5
Ta = + 105°C,
When LVD is off,
When RAM is off
*1, *3, *5
Ta = + 105°C,
When LVD is off,
When RAM is on
*1, *3, *5
23
Deep Standby
RTC mode
VCC
ICCRD
(sub oscillation)
155
215
-
For occurrence of
reset
-
-
-
0.13
0.13
9.5
0.3
0.3
μA
μA
Low-voltage
detection
circuit (LVD)
power supply
current
ICCLVD
At operation
For occurrence of
interrupt
Flash
memory
write/erase
current
ICCFLASH
At Write/Erase
11.2
mA *4
*1: When all ports are fixed.
*2: When setting it to 4MHz by trimming.
*3: RAM on/off setting is on-chip SRAM only.
*4: The current at which to write or erase Flash memory, "ICCFLASH" is added to "ICC".
*5: Inclucing the current of Main oscillation IO or Sub oscillation IO.
58
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
(2) Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Parameter Symbol Pin name
Conditions
Unit Remarks
Min
Max
CMOS
"H" level
hysteresis
input
-
-
-
-
VCC × 0.8
-
VCC + 0.3
V
V
V
V
input pin,
voltage
(hysteresis
input)
VIHS
MD0, MD1
5V tolerant
input pin
VCC × 0.8
VSS - 0.3
VSS - 0.3
-
-
-
VSS + 5.5
VCC × 0.2
VCC × 0.2
CMOS
"L" level
input
voltage
(hysteresis
input)
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
VILS
VCC ≥ 4.5 V,
IOH = - 4mA
4mA type
12mA type
P80, P81
VCC - 0.5
VCC - 0.5
VCC - 0.4
VSS
-
-
-
-
-
VCC
VCC
VCC
0.4
V
V
V
V
V
V
VCC < 4.5 V,
IOH = - 2mA
VCC ≥ 4.5 V,
IOH = - 12mA
VCC < 4.5 V,
IOH = - 8mA
VCC ≥ 4.5 V,
IOH = - 18.0mA
VCC < 4.5 V,
IOH = - 12.0mA
VCC ≥ 4.5 V,
IOL = 4mA
VCC < 4.5 V,
IOL = 2mA
VCC ≥ 4.5 V,
IOL = 12mA
VCC < 4.5 V,
IOL = 8mA
"H" level
output voltage
VOH
4mA type
12mA type
P80, P81
"L" level
output voltage
VOL
VSS
0.4
VCC ≥ 4.5 V,
IOL = 16.5mA
VCC < 4.5 V,
IOL = 10.5mA
VSS
- 5
-
-
0.4
+ 5
Input leak
current
IIL
-
-
μA
kΩ
Pull-up
resistance
value
VCC ≥ 4.5 V
33
-
50
-
90
RPU
Pull-up pin
VCC < 4.5 V
180
Other than
VCC,
VSS,
Input
capacitance
CIN
AVCC,
AVSS,
AVRH,
AVRL
-
-
5
15
pF
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
59
D a t a S h e e t
4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
Min
Max
48
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
PWH/tCYLH,
PWL/tCYLH
4
4
4
4
When crystal oscillator
is connected
When using external
Clock
When using external
Clock
When using external
Clock
MHz
MHz
ns
20
48
20
250
250
FCH
20.83
50
X0,
X1
tCYLH
-
Input clock pulse
width
45
55
%
Input clock rising
time and falling
time
tCF,
tCR
When using external
Clock
-
-
5
ns
FCM
FCC
-
-
-
-
-
-
72
72
MHz Master clock
Base clock
(HCLK/FCLK)
MHz
Internal operating
clock frequency*1
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
Base clock
tCYCC
-
-
13.8
-
ns
(HCLK/FCLK)
Internal operating
clock cycle time*1
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter:Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data
sheet.
X0
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D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected
Input frequency
1/ tCYLL
When using
external clock
When using
external clock
When using
external clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
X0A,
X1A
Input clock cycle
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
%
* : See " Sub crystal oscillator" in "HANDLING DEVICES" for the crystal oscillator used.
X0A
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
61
D a t a S h e e t
(3) Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Ta = + 25°C
3.92
3.9
4
4.08
Ta = 0°C to + 85°C
4
4
4
4.1
Ta = -40°C to + 105°C 3.88
4.12
When trimming*1
Ta = + 25°C
3.94
Clock frequency
FCRH
4.06 MHz
VCC ≤ 3.6V
Ta = - 20°C to + 85°C
VCC ≤ 3.6V
Ta = - 20°C to + 105°C
3.92
4
4
4
-
4.08
4.1
3.9
VCC ≤ 3.6V
Ta = - 40°C to + 105°C
-
2.8
-
5.2
When not trimming
Frequency
stabilization time
2
tCRWT
30
μs
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
FCRL
-
50
100
150
kHz
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D a t a S h e e t
(4-1) Operating Conditions of Main and PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
FPLLO
FCLKPLL
4
5
75
-
-
-
-
-
16
MHz
37 multiplier
150
72
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family
PERIPHERAL MANUAL".
(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock
of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
FPLLO
FCLKPLL
3.8
19
72
-
4
-
-
4.2
MHz
35 multiplier
150
72
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
-
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency
has been trimmed.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
63
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
0
Max
Power supply rising time
Tr
-
-
ms
ms
Power supply shut down time
Toff
1
VCC
Time until releasing
Power-on reset
Tprt
1.34
18.6
ms
VCC_minimum
VDH_minimum
VCC
0.2V
0.2V
0.2V
Tr
Tprt
Toff
Internal RST
RST Active
Release
start
CPU Operation
Glossary
VCC_minimum: Minimum VCC of recommended operating conditions
VDH_minimum : Minimum detection voltage of Low-Voltage detection reset
See "8. Low-Voltage Detection Characteristics"
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
(7) Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see " BLOCK DIAGRAM" in this
data sheet.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
(8) CSIO Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Symbol
tSCYC
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx Internal shift
SCKx,
SINx
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
clock
operation
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
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D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
SOT
SIN
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
67
D a t a S h e e t
Synchronous serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
tSCYC
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Internal shift
clock
operation
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
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D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
SOT
SIN
VOH
VOL
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
69
D a t a S h e e t
Synchronous serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
tSCYC
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
SCKx, Internal shift
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tIVSLI
tSLIXI
tSOVLI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SINx
SCKx,
SINx
SCKx,
SOTx
clock
operation
2tCYCP
30
-
2tCYCP
30
-
-
-
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
70
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
tSCYC
VOH
VOL
VOL
SCK
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
71
D a t a S h e e t
Synchronous serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Pin
name
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSOVHI
tSLSH
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2tCYCP
30
2tCYCP
10
tCYCP
10
-
2tCYCP
30
2tCYCP
10
tCYCP
10
-
-
-
-
-
SCKx
SCKx
-
-
+
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "BLOCK
DIAGRAM" in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30pF.
72
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
VIH
SCK
VIH
VIH
VIL
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
External clock (EXT = 1) : asynchronous only
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol Conditions
Min
Max
Unit Remarks
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30pF
tF
-
-
SCK rising time
tR
tR
VIL
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
73
D a t a S h e e t
(9) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Min
Parameter Symbol Pin name Conditions
Unit
Remarks
Max
A/D converter
trigger input
ns Free-run timer input
clock
ADTG
1
-
2tCYCP
*
-
FRCKx
tINH,
tINL
Input pulse width
ICxx
DTTIxX
INT00 to INT23,
NMIX
Input capture
ns Waveform generator
External interrupt
NMI
ns
1
-
-
2tCYCP
*
-
-
-
2tCYCP + 100*1
ns
500*2
*1 : tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "BLOCK DIAGRAM" in this data sheet.
*2 : When in stop mode, in timer mode.
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D a t a S h e e t
(10) Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rising time from
AIN pin "H" level
AIN falling time from
BIN pin "H" level
BIN falling time from
AIN pin "L" level
AIN rising time from
BIN pin "L" level
AIN rising time from
BIN pin "H" level
BIN falling time from
AIN pin "H" level
AIN falling time from
BIN pin "L" level
BIN rising time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and falling
time from determined ZIN
level
tAHL
tALL
tBHL
tBLL
-
-
-
-
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR:CGSC="0"
QCR:CGSC="0"
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
2tCYCP
*
-
ns
tZHL
tZLL
tZABE
QCR:CGSC="1"
QCR:CGSC="1"
Determined ZIN level from
AIN/BIN rise and falling
time
tABEZ
*: tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see
"BLOCK DIAGRAM" in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
75
D a t a S h e e t
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
(11) I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Standard-
mode
Fast-
mode
Parameter
Symbol Conditions
Unit Remarks
Min
Max Min Max
SCL clock frequency
(Repeated) START condition
hold time
FSCL
0
100
0
400 kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START condition
setup time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
Data hold time
CL = 30pF,
R = (Vp/IOL)*1
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tSUDAT
tSUSTO
250
4.0
-
-
100
0.6
-
-
ns
μs
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tBUF
4.7
-
-
1.3
-
-
μs
4
4
tSP
-
2 tCYCP
*
2 tCYCP
*
ns
*1 :R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2 :The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 :A Fast-speed mode I2C bus device can be used on a Standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 :tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use Standard-mode, set the APB bus clock at 2MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
(12) JTAG Timing
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)
Value
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
TMS, TDI setup
time
TCK,
TMS, TDI
tJTAGS
15
-
TCK,
TMS, TDI
TMS, TDI hold time tJTAGH
TDO delay time tJTAGD
15
-
ns
-
-
25
45
TCK,
TDO
ns
VCC < 4.5V
Note: When the external load capacitance CL = 30pF.
TCK
TMS/TDI
TDO
78
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Unit
Remarks
Min
-
- 4.5
- 2.5
Max
12
+ 4.5
+ 2.5
Resolution
Integral Nonlinearity
Differential Nonlinearity
-
-
-
-
-
-
-
-
-
bit
LSB
LSB
AVRH = 2.7V
to 5.5V
ANxx to
ANxx
ANxx to
ANxx
-
Zero transition voltage
V0T
- 15
-
-
+ 15
mV
Full-scale transition
voltage
Conversion time
VFST
-
AVRH - 15
AVRH + 15 mV
0.8*1
0.24
0.3
-
-
-
-
-
-
μs
μs
AVCC ≥ 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
Sampling time*2
Ts
-
-
-
10
40
Compare clock cycle*3
Tcck
Tstt
1000
1.0
ns
50
State transition time to
operation permission
-
-
μs
A/D 1unit
operation
When A/D stop
A/D 1unit
operation
-
-
0.69
0.25
0.90
mA
Power supply current
(analog + digital)
-
-
AVCC
AVRH
25.84
μA
Reference power supply
current
(AVRH)
-
1.1
1.97
mA
AVRH=5.5V
When A/D stop
-
-
0.2
-
3.4
9.7
μA
Analog input capacity
Analog input resistor
CAIN
RAIN
-
-
pF
1.7
2.4
AVCC ≥ 4.5V
AVCC < 4.5V
-
-
kΩ
Interchannel disparity
Analog port input current
Analog input voltage
Reference voltage
-
-
-
-
-
-
-
-
-
-
-
4
5
LSB
μA
V
Axx
ANxx
AVRH
AVSS
2.7
AVRH
AVCC
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 240ns, the value of
compare time: 560ns (AVCC ≥ 4.5V).
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter: A/D Converter" in "FM3 Family
PERIPHERAL MANUAL Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
For the number of the APB bus to which the A/D Converter is connected, see "BLOCK DIAGRAM".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
Comparator
ANxx
Analog input pin
Rext
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistor of A/D = 1.5kΩ at 4.5 < AVCC < 5.5 ch.0 to ch.7
input resistor of A/D = 1.6kΩ at 4.5 < AVCC < 5.5 ch.8 to ch.15
input resistor of A/D = 1.7kΩ at 4.5 < AVCC < 5.5 ch.16 to ch.26
input resistor of A/D = 2.2kΩ at 2.7 < AVCC < 4.5 ch.0 to ch.7
input resistor of A/D = 2.3kΩ at 2.7 < AVCC < 4.5 ch.8 to ch.15
input resistor of A/D = 2.4kΩ at 2.7 < AVCC < 4.5 ch.16 to ch.26
CAIN : input capacity of A/D = 9.7pF at 2.7 < AVCC < 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
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Definition of 12-bit A/D Converter Terms
Resolution
Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Linearity error
Differential linearity error
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
0x003
0x002
0x001
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVRL
AVRH
AVRL
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N
VZT
: A/D converter digital output value.
: Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
6. 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 105°C)
Value
Typ Max
Parameter
Symbol Pin name
Unit
Remarks
Min
-
0.47
2.37
- 4.0
Resolution
-
-
10
0.69
3.43
bit
μs
μs
tc20
tc100
INL
0.58
2.90
-
Load 20pF
Load 100pF
Conversion time
Integral Nonlinearity*1
Differential
+ 4.0 LSB
DNL
DAx
- 0.9
-
+ 0.9 LSB
Nonlinearity*1,*2
-
- 20.0
3.10
2.0
-
-
10.0
mV Code is 0x000
Output Voltage offset
VOFF
+ 5.4 mV Code is 0x3FF
4.50
-
3.80
-
-
kΩ D/A operation
MΩ D/A stop
ns
Analog output
impedance
Output undefined period
RO
tR
-
70
D/A 1unit operation
AVCC=3.3V
D/A 1unit operation
AVCC=5.0V
250
315
380
μA
μA
IDDA*2
AVCC
Power supply current*1
380
-
475
-
580
16
IDSA
μA D/A stop
*1: No-load
*2: Generates the max current by the CODE about 0x200
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MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
7. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
SVHR*1=
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
2.25
2.30
2.39
2.48
2.48
2.58
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.45
2.50
2.60
2.70
2.70
2.80
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
2.65
2.70
2.81
2.92
2.92
3.02
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
00000
SVHR*1=
00001
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
SVHR*1=
00010
SVHR*1=
00011
SVHR*1=
00100
SVHR*1=
00101
SVHR*1=
00110
SVHR*1=
00111
SVHR*1=
01000
SVHR*1=
01001
SVHR*1=
01010
LVD stabilization
wait time
8160 ×
TLVDW
-
-
-
μs
2
tCYCP
*
LVD detection delay
time
TLVDDL
-
-
-
200
μs
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by
Low-Voltage Detection Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(Ta = - 40°C to + 105°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 00011
VDH
VDL
SVHI = 00100
VDH
VDL
SVHI = 00101
VDH
VDL
SVHI = 00110
VDH
VDL
SVHI = 00111
VDH
VDL
VDH
VDL
VDH
SVHI = 01000
SVHI = 01001
VDL
SVHI = 01010
VDH
LVD stabilization
wait time
8160×
tCYCP
TLVDW
-
-
-
-
-
-
μs
μs
*
LVD detection
delay time
TLVDDL
200
*: tCYCP indicates the APB2 bus clock cycle time.
84
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
8. Flash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Typ
Parameter
Unit
Remarks
Min
Max
Large Sector
Small Sector
1.1
2.7
Sector erase
time
Includes write time prior to internal
erase
-
s
0.3
16
0.9
Half word (16-bit)
write time
Not including system-level overhead
time
Includes write time prior to internal
erase
-
-
310
μs
Chip erase time
6.8
18
s
Write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year)
Remarks
1,000
20*
10*
10,000
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C) .
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
9. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
tCYCC
μs
High-speed CR TIMER mode,
Main TIMER mode,
40
80
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
340
680
680
860
μs
μs
Ticnt
RTC mode,
STOP mode
268
503
μs
308
268
583
503
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
86
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Operation example of return from Low-Power consumption mode (by internal resource
interrupt*)
Internal
Resource INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes: The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes"
in FM3 Family PERIPHERAL MANUAL.
When interrupt recoveries, the operation mode that CPU recoveries depends on the
state before the Low-Power consumption mode transition. See "CHAPTER: Low
Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
148
263
μs
High-speed CR TIMER mode,
Main TIMER mode,
148
263
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
248
312
268
463
496
503
μs
μs
μs
Trcnt
RTC/STOP mode
308
268
583
503
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
88
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes: The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes"
in FM3 Family PERIPHERAL MANUAL.
When interrupt recoveries, the operation mode that CPU recoveries depends on the
state before the Low-Power consumption mode transition. See "CHAPTER: Low
Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
The time during the power-on reset/low-voltage detection reset is excluded. See "(6)
Power-on Reset Timing in 4. AC Characteristics in ELECTRICAL
CHARACTERISTICS" for the detail on the time during the power-on reset/low
-voltage detection reset.
When in recovery from reset, CPU changes to the high-speed CR run mode. When
using the main clock or the PLL clock, it is necessary to add the main clock
oscillation stabilization wait time or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
ORDERING INFORMATION
Part number
Package
MB9BF121KQN
Plastic QFN(0.5mm pitch),48-pin
MB9BF122KQN
(LCC-48P-M73)
MB9BF124KQN
MB9BF121KPMC
MB9BF122KPMC
MB9BF124KPMC
MB9BF121LQN
Plastic LQFP(0.5mm pitch),48-pin
(FPT-48P-M49)
Plastic QFN(0.5mm pitch),64-pin
MB9BF122LQN
(LCC-64P-M24)
MB9BF124LQN
MB9BF121LPMC1
MB9BF122LPMC1
MB9BF124LPMC1
MB9BF121LPMC
MB9BF122LPMC
MB9BF124LPMC
MB9BF121MPMC
MB9BF122MPMC
MB9BF124MPMC
MB9BF121MPMC1
MB9BF122MPMC1
MB9BF124MPMC1
MB9BF121MBGL
MB9BF122MBGL
MB9BF124MBGL
Plastic LQFP(0.5mm pitch),64-pin
(FPT-64P-M38)
Plastic LQFP(0.65mm pitch),64-pin
(FPT-64P-M39)
Plastic LQFP(0.5mm pitch),80-pin
(FPT-80P-M37)
Plastic LQFP(0.65mm pitch),80-pin
(FPT-80P-M40)
Plastic PFBGA(0.5mm pitch),96-pin
(BGA-96P-M07)
90
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
PACKAGE DIMENSIONS
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551± .008)SQ
*12.00± 0.10(.472± .004)SQ
0.145± 0.055
(.006± .002)
60
41
Details of "A" part
61
40
1.50+–00..1200
(Mounting height)
.059+–..000048
0.25(.010)
0~8°
0.08(.003)
0.50± 0.20
(.020± .008)
0.60± 0.15
0.10± 0.05
(.004± .002)
(Stand off)
(.024± .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22± 0.05
M
0.08(.003)
(.009± .002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
91
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.65 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
0.145±0.055
(.006±.002)
60
41
Details of "A" part
61
40
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
0.10±0.05
80
21
(.004±.002)
0.60±0.15
(.024±.006)
20
1
0.65(.026)
0.32±0.06
M
0.13(.005)
(.013±.002)
Dimensions in mm (inches).
Note: The values in parentheses are referencevalues.
C
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
92
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
0.145 ± 0.055
(.006 ± .002)
48
33
Details of "A" part
1.50+–00..1200
49
32
0.08(.003)
(Mounting height)
.059+–..000084
0.25(.010)
0~8°
INDEX
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
0.10 ± 0.10
(.004±.004)
(Stand off)
64
17
"A"
1
16
0.50(.020)
0.22±0.05
M
0.08(.003)
(.009±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
93
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
33
Details of "A" part
49
32
1.50+–00..1200
.059–+..000048
0~8˚
0.10(.004)
0.10±0.10
(.004±.004)
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)BSC
64
17
1
16
"A"
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
Dimensions in mm (inches).
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Note: The values in parentheses are referencevalues.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
94
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
9.00 mm × 9.00 mm
Plastic mold
0.90 mm MAX
-
Package width ×
package length
Sealing method
Mounting height
Weight
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.50 (.020)
(TYP)
0.40±0.05
(.016±.002)
0.85±0.05
(.033±.002)
0.05 (.002) MAX
(0.20 (.008))
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
95
D a t a S h e e t
48-pin plastic LQFP
Lead pitch
0.50 mm
7.00 mm × 7.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.17 g
Sealing method
Mounting height
Weight
(FPT-48P-M49)
48-pin plastic LQFP
(FPT-48P-M49)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00± 0.20(.354 ± .008)SQ
*7.00± 0.10(.276 ± .004)SQ
0.145± 0.055
(.006± .002)
36
25
37
24
Details of "A" part
0.08(.003)
1.50+–00..2100
(Mounting height)
.059+–..000084
INDEX
48
13
0.10± 0.10
(.004± .004)
(Stand off)
"A"
0°~8°
1
12
0.50(.020)
0.25(.010)
0.22± 0.05
(.008± .002)
M
0.08(.003)
0.60± 0.15
(.024± .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
96
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
48-pin plastic QFN
Lead pitch
0.5 mm
7.00 mm × 7.00 mm
Plastic mold
0.90 mm MAX
–
Package width ×
package length
Sealing method
Mounting height
Weight
(LCC-48P-M73)
48-pin plastic QFN
(LCC-48P-M73)
7.00±0.10
5.50±0.10
(.276±.004)
(.217±.004)
0.25±0.05
(.010±.002)
7.00±0.10
(.276±.004)
5.50±0.10
(.217±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.50 (.020)
(TYP)
0.40±0.05
(.016±.002)
0.05 (.002) MAX
(0.20(.008))
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC48-73Sc-2-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
97
D a t a S h e e t
96-pin plastic FBGA
Lead pitch
0.5 mm
6.00 mm × 6.00 mm
Ball
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.30 mm MAX
0.08 g
(BGA-96P-M07)
96-pin plastic FBGA
(BGA-96P-M07)
5.00(.197)
REF
B
6.00±0.10(.236±.004)
0.50
(.020)
TYP
0.20(.008) S
B
11
10
9
8
A
7
5.00(.197)
REF
6.00±0.10
(.236±.004)
6
5
0.50(.020)
TYP
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
(INDEX AREA)
0.20(.008) S
INDEX
A
96-ø0.30±0.10
(96-ø.012±.004)
M
ø0.05(.002)
S A B
S
1.15±0.15
(.045±.006)
(Seated height)
0.08(.003) S
0.25±0.10
(.010±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1
98
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
MAJOR CHANGES
Page
Section
Change Results
Revision 1.0
-
-
Preliminary → Data Sheet
FEATURES
• A/D Converter (Max 26channels)
Revised the conversion time: 1.0μs → 0.8μs
3
• UniqueID
Added the "Unique ID".
Added the "Unique ID".
5
PRODUCT LINEUP
• Function
6
LIST OF PIN FUNCTIONS
• List of pin numbers
• List of pin functions
• Corrected the I/O circuit type.
• Corrected the Pin state type.
Corrected the Pin function.
15 to 17
32
I/O CIRCUIT TYPE
BLOCK DIAGRAM
Added the "Type: L".
38
Corrected the figure.
45
- TIOA: input → input/output
- TIOB: output → input
Revised the value of "TBD".
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
54
55
Revised the Condition of "Operating temperature".
3. DC Characteristics
(1) Current Rating
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
(4-2) Operating Conditions of Main PLL (In the
case of using built-in high-speed CR for input clock
of main PLL)
• Revised the value of "TBD".
• Added "Flash memory write/erase current".
• Revised the Condition.
• Revised the footnote.
Revised the value of "TBD".
56, 57
60
61
5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
• Deleted "(Preliminary value)".
• Revised the conversion time.
Min: 1.0μs → 0.8μs
• Revised the value of "Compare clock cycle
77
(AV CC ≥ 4.5V)".
Min: 50ns → 40ns
• Revised the footnote.
6. 10-bit D/A Converter
Deleted "(Preliminary value)".
80
81
7. Low-Voltage Detection Characteristics
8. MainFlash Memory Write/Erase Characteristics
Revised the value of "TBD".
• Revised the value of "TBD".
• Revised the value of "Sector erase time".
- Large Sector Typ: 1.065s → 1.1s
- Small Sector Typ: 0.606s → 0.3s
• Revised the value of "Chip erase time".
Typ: 9.11s → 6.8s
82
• Deleted "(targeted value)".
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
FEATURES
• On-chip Memories [Flash memory]
Revised the features of Dual operation Flash memory
2
Corrected the mode.
• Multi-function Serial Interface [I2C]
• General-Purpose I/O Port
• Multi-function Timer
High speed mode → Fast mode
Revised the features of 5V tolerant I/O.
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
3
4
• Corrected the number of A/D activating compare channels.
3ch. → 2ch.
6
• Revised Built-in CR.
PRODUCT LINEUP
• Function
High-speed: 4MHz(± 2%) → 4MHz
Low-speed: 100kHz(Typ) → 100kHz
Revised the footnote.
7
LIST OF PIN FUNCTIONS
• List of pin numbers
20
Corrected the pin number of ZIN1_1.
23
28
30
Corrected the pin number of ADTG_2.
Corrected pin numbers of SIN0_1 and SOT0_1.
Corrected the pin number of DTTI0X_2.
TYPE H :
• List of pin functions
I/O CIRCUIT TYPE
36
Revised the value of "TBD".
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
99
D a t a S h e e t
Page
Section
HANDLING DEVICES
Change Results
43
Added the descriptions.
• Sub crystal oscillator
Corrected the figure.
-A/D Activation Compare: 3ch → 2ch
46
BLOCK DIAGRAM
MEMORY MAP
• Memory Map (2)
48
53
54
Added the explanatory note.
Added the pin function of selected Analog output about type L.
• Corrected the footnote.
PIN STATUS IN EACH CPU STATE
• List of Pin Status
Sub CR timer→ Low-speed CR tim
• Added the note and footnote.
• Corrected the value of Analog reference voltage “AVR H ”.
Min.: AVss → 2.7
ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
56
• Added notes and footnotes.
• Added the remarks of Icc.
• Added the frequency of main clock crystal oscillator in remarks.
3. DC Characteristics
(1) Current Rating
57
4. AC Characteristics
61
62
64
Added the footnote.
(2) Sub clock input Characteristics
(3) Built-in CR Oscillation Characteristics
• Built-in High-speed CR
• Added "Frequency stabilization time"
• Added notes and footnotes.
• Added "Timing until releaseing Power-on reset"
• Added the timing chart
(6) Power-on Reset Timing
• Corrected the title.
UART Timing → CSIO Timing
• Corrected the notefoot.
UART → Multi-function serial
66
(8) CSIO Timing
Corrected the notefoot.
UART → Multi-function serial
68,70,72
• Revised the Condition.
• Revised the footnote.
77
(11) I2C Timing
• Changed the name of parameter.
•Non Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• Changed the Symbol. Of Zero transition voltage.
VoT → VZT
79
5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
• Changed the pin name.
AN00 to AN26 → ANxx
• Corrected the value of V0T, VFST, Ts, Tstt, and reference voltage.
• Revides footnotes.
Change the figure.
AN00 to AN26 → ANxx
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• V0T → VZT
80
81
• Difinition of 12-bit A/D Converter Terms
•Revised the remark of IDDA.
D/A operation → D/A 1unit operation
• Changed the name of parameter.
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
• Corrected the condition and the value.
• Added the note and the footnote.
• Added “LVD detection delay time”.
• Corrected the condition and the value.
• Added “LVD detection delay time”.
Changed the title of Chapter.
6. 10-bit D/A Converter
• Electrical characteristics for the D/A converter
82
7. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
83
84
(2) Interrupt of Low-Voltage Detection
85
8. Flash Memory Write/Erase Characteristics
9. Return Time Low-Power Consumption Mode
Main Flash Memory Write/Erase Characteristics →
Flash Memory Write/Erase Characteristics
Added the Chapter “Return Time from Low-Power Consumption Mode”.
86
100
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
D a t a S h e e t
April 17, 2014, MB9BF124M_DS706-00050-2v0-E
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the
United States and other countries. Other names used are for informational purposes only and may be trademarks of their
respective owners.
102
MB9BF124M_DS706-00050-2v0-E, April 17, 2014
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