MB9BF118SPMC-GK7E1 [CYPRESS]
32-bit ARM® Cortex®-M3 FM3 Microcontroller;
| 型号： | MB9BF118SPMC-GK7E1 |
| 厂家： | 
CYPRESS |
| 描述： | 32-bit ARM® Cortex®-M3 FM3 Microcontroller 微控制器 |
| 文件： | 总133页 (文件大小：3827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B110T Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B110TSeries are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive
cost.
These series are based on theARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as Motor
Control Timers,ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed intoTYPE2 product categories in "FM3 Family PERIPHERALMANUAL".
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Multi-function Serial Interface (Max 8 channels)
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
Up to 144 MHz Frequency Operation
Operation mode is selectable from the followings for each
Memory Protection Unit (MPU): improves the reliability of
channel.
an embedded system
UART
CSIO
LIN
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
I2C
24-bit System timer (Sys Tick): System timer for OS task
management
[UART]
Full-duplex double buffer
On-chip Memories
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
[Flash memory]
Up to 1 Mbyte
Hardware Flow control: Automatically controls the
Built-in Flash memory Accelerator System with 16 Kbyte
trace buffer memory
transmission/reception with CTS/RTS (only for ch.4)
The read access to Flash memory can be achieved without
wait cycle up to the operation frequency of 72MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash memory
Accelerator System.
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAMs (SRAM0, SRAM1) . SRAM0 is connected to I-code
bus and D-code bus of Cortex-M3 core. SRAM1 is connected
to System bus.
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
SRAM0: Up to 64 Kbytes.
SRAM1: Up to 64 Kbytes.
LIN break field generation (can be changed to 13-bit length
to 16-bit)
External Bus Interface
LIN break delimiter generation (can be changed to 1-bit
length to 4-bit)
Supports SRAM, NOR and NAND Flash memory devices
Up to 8 chips selected
Various error detection functions available (parity errors,
framing errors, and overrun errors)
8-/16-bit Data width
[I2C]
Up to 25-bit Address bit
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
supported
Cypress Semiconductor Corporation
Document Number: 002-04683 Rev.*C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB9B110T Series
DMA Controller (8 channels)
Multi-function Timer (Max 3 units)
The DMA Controller has a dedicated bus independent from the
CPU, so CPU and DMA Controller can process
simultaneously.
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
8 independently configured and operated channels
Output compare × 6 ch./unit
A/D activation compare × 3 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32 bits (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
The following function can be used to achieve the motor
control.
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
PWM signal output function
Number of transfers: 1 to 65536
DC chopper waveform output function
Dead time function
A/D Converter (Max 32 channels)
[12-bit A/D Converter]
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Successive Approximation type
Built-in 3units
Quadrature Position/Revolution Counter (QPRC)
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
(Max 3 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use the counter as the up/down counter.
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
The detection edge of three external event input pins AIN,
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
16-bit PWM timer
16-bit PPG timer
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.Operation mode is selectable from the followings for
each channel.
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as I/O ports when they are not
used for an external bus or peripherals. Moreover, the port
relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from low-power
consumption mode.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port relocate function
Up to 154 fast I/O Ports@ 176 pin Package
Interval timer: up to 64 s(Max)@ Sub Clock: 32.768 kHz
Some ports are 5 V tolerant I/O.
See "Pin Assignment" to confirm the corresponding pins.
External Interrupt Controller Unit
Up to 32 external interrupt input pins
One non-maskable interrupt (NMI) pin
Document Number: 002-04683 Rev.*C
Page 2 of 132
MB9B110T Series
Voltage Detector generates an interrupt or reset.
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
The "Hardware" watchdog timer is operated by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption mode except STOP
mode.
Sleep
Timer
Stop
Debug
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).
Power Supply
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Wide range voltage VCC = 2.7 V to 5.5 V
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Main Clock: 4 MHz to 48 MHz
Sub Clock: 32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
When external clock failure (clock stop) is detected, reset is
asserted.
When external frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage set, Low
Document Number: 002-04683 Rev.*C
Page 3 of 132
MB9B110T Series
Contents
Features..........................................................................................................................................................................1
1.
Product Lineup......................................................................................................................................................6
Packages................................................................................................................................................................7
Pin Assignment.....................................................................................................................................................8
List of Pin Functions........................................................................................................................................... 11
I/O Circuit Type.................................................................................................................................................... 58
Handling Precautions ......................................................................................................................................... 65
Precautions for Product Design.......................................................................................................................... 65
Precautions for Package Mounting..................................................................................................................... 67
Precautions for Use Environment....................................................................................................................... 68
Handling Devices ................................................................................................................................................ 69
Block Diagram..................................................................................................................................................... 72
Memory Size ........................................................................................................................................................ 73
2.
3.
4.
5.
6.
6.1
6.2
6.3
7.
8.
9.
10. Memory Map ........................................................................................................................................................ 73
11. Pin Status in Each CPU State............................................................................................................................. 76
12. Electrical Characteristics ................................................................................................................................... 80
12.1 Absolute Maximum Ratings................................................................................................................................ 80
12.2 Recommended Operating Conditions................................................................................................................. 82
12.3 DC Characteristics.............................................................................................................................................. 83
12.3.1 Current Rating..................................................................................................................................................... 83
12.3.2 Pin Characteristics .............................................................................................................................................. 85
12.4 AC Characteristics.............................................................................................................................................. 87
12.4.1 Main Clock Input Characteristics......................................................................................................................... 87
12.4.2 Sub Clock Input Characteristics .......................................................................................................................... 88
12.4.3 Internal CR Oscillation Characteristics................................................................................................................ 88
12.4.4 Operating Conditions of Main and USB PLL ....................................................................................................... 89
12.4.5 Reset Input Characteristics................................................................................................................................. 90
12.4.6 Power-on Reset Timing....................................................................................................................................... 90
12.4.7 External Bus Timing............................................................................................................................................ 91
12.4.8 Base Timer Input Timing................................................................................................................................... 101
12.4.9 CSIO/UART Timing........................................................................................................................................... 102
12.4.10 External Input Timing..................................................................................................................................... 110
12.4.11 Quadrature Position/Revolution Counter timing............................................................................................. 111
12.4.12 I2C Timing...................................................................................................................................................... 113
12.4.13 ETM Timing ................................................................................................................................................... 114
12.4.14 JTAG Timing.................................................................................................................................................. 115
12.5 12-bit A/D Converter......................................................................................................................................... 116
12.6 Low-Voltage Detection Characteristics............................................................................................................. 119
12.6.1 Low-Voltage Detection Reset............................................................................................................................ 119
12.6.2 Interrupt of Low-Voltage Detection.................................................................................................................... 119
12.7 Flash Memory Write/Erase Characteristics ...................................................................................................... 120
12.7.1 Write / Erase time.............................................................................................................................................. 120
12.7.2 Write cycles and data hold time ........................................................................................................................ 120
12.8 Return Time from Low-Power Consumption Mode........................................................................................... 121
12.8.1 Return Factor: Interrupt..................................................................................................................................... 121
Document Number: 002-04683 Rev.*C
Page 4 of 132
MB9B110T Series
12.8.2 Return Factor: Reset......................................................................................................................................... 123
13. Ordering Information ........................................................................................................................................ 125
14. Package Dimensions ........................................................................................................................................ 126
15. Major Changes .................................................................................................................................................. 129
Document History...................................................................................................................................................... 131
Sales, Solutions, and Legal Information.................................................................................................................. 132
Document Number: 002-04683 Rev.*C
Page 5 of 132
MB9B110T Series
1.
Product Lineup
Memory size
Product name
MB9BF116S/T
MB9BF117S/T
MB9BF118S/T
On-chip Flash memory
On-chip SRAM
512 Kbytes
768 Kbytes
1 Mbytes
64 Kbytes
96 Kbytes
128 Kbytes
Function
MB9BF116S
MB9BF117S
MB9BF118S
144
MB9BF116T
MB9BF117T
MB9BF118T
176/192
Product name
Pin count
CPU
Cortex-M3
144 MHz
2.7 V to 5.5 V
8 ch
Freq.
Supply voltage range
DMAC
Addr:19-bit (Max)
R/Wdata:8-/16-bit (Max)
CS: 8 (Max)
Addr:25-bit (Max)
R/Wdata:8-/16-bit (Max)
CS:8 (Max)
External Bus Interface
Support: SRAM, NOR & NAND
Flash memory
Support: SRAM, NOR &
NAND Flash memory
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps ×9 bits)
ch.0 to ch.3: No FIFO
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
16 ch. (Max)
A/D activation compare
3 ch.
Input capture
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
Free-run timer
Output compare
Waveform generator
PPG
MF-Timer
3 units (Max)
QPRC
3 ch. (Max)
Dual Timer
1 unit
1 unit
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
Yes
1 ch. (SW) + 1 ch. (HW)
32 pins (Max) + NMI pin× 1
122 pins (Max)
24 ch. (3 units)
154 pins (Max)
32 ch. (3 units)
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Yes
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in CR
Debug Function
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated due to the pin count restriction of a package. It is
necessary to use the port relocate function of the I/O port according to functions use. See "Electrical Characteristics 12.4 AC
Characteristics 12.4.3 Internal CR Oscillation Characteristics" for accuracy of built-in CR.
Document Number: 002-04683 Rev.*C
Page 6 of 132
MB9B110T Series
2.
Packages
MB9BF116S
MB9BF117S
MB9BF118S
MB9BF116T
MB9BF117T
MB9BF118T
Product name
Package
LQFP:
LQS144 (0.5 mm pitch)
LQP176 (0.5 mm pitch)
LBE192 (0.8 mm pitch)
-
-
LQFP:
BGA:
-
: Supported
Note:
−
See "Package Dimensions" for detailed information on each package.
Document Number: 002-04683 Rev.*C
Page 7 of 132
MB9B110T Series
3.
Pin Assignment
LQP176
(TOP VIEW)
VCC
PA0/RTO20_0/TIOA08_0/FRCK1_0
PA1/RTO21_0/TIOA09_0/IC10_0
PA2/RTO22_0/TIOA10_0/IC11_0
PA3/RTO23_0/TIOA11_0/IC12_0
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
PA5/RTO25_0/TIOA13_0/INT10_2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VSS
2
P83
3
P82
4
VCC
5
PF6/FRCK2_0/NMIX
6
P20/INT05_0/CROUT_0/AIN1_1/MAD18_0
P21/SIN0_0/INT06_1/BIN1_1
7
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
8
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P27/AN26/INT02_2/RTO04_1/MAD14_0
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P29/AN24/MAD12_0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P08/TRACED3/TIOA00_2/CTS4_2
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
P5C/TIOA06_2/INT28_0/IC20_1
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
PB3/AN19/TIOB10_1/INT19_0
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
VSS
LQFP - 176
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
VSS
AVRH
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P19/AN09/SCK2_2/INT22_1/MAD05_0
P18/AN08/SOT2_2/INT21_1/MAD04_0
P17/AN07/SIN2_2/INT04_1/MAD03_0
P16/AN06/SCK0_1/INT20_1/MAD02_0
P15/AN05/SOT0_1/IC03_2/MAD01_0
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
P10/AN00/MCSX7_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
P34/FRCK0_0/TIOB04_1
P35/IC03_0/TIOB05_1/INT08_1
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
P39/DTTI0X_0/ADTG_2
98
97
96
P3A/RTO00_0/TIOA00_1
95
P3B/RTO01_0/TIOA01_1
94
P3C/RTO02_0/TIOA02_1
93
P3D/RTO03_0/TIOA03_1
92
P3E/RTO04_0/TIOA04_1
91
P3F/RTO05_0/TIOA05_1
90
VSS
89
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 8 of 132
MB9B110T Series
LQS144
(TOP VIEW)
VCC
PA0/RTO20_0/TIOA08_0/FRCK1_0
PA1/RTO21_0/TIOA09_0/IC10_0
1
108
107
106
105
104
103
102
101
100
99
VSS
P83
P82
VCC
2
3
PA2/RTO22_0/TIOA10_0/IC11_0
4
PA3/RTO23_0/TIOA11_0/IC12_0
5
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
PA5/RTO25_0/TIOA13_0/INT10_2
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
6
P20/INT05_0/CROUT_0/AIN1_1/MAD18_0
P21/SIN0_0/INT06_1/BIN1_1
7
8
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P27/AN26/INT02_2/RTO04_1/MAD14_0
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P29/AN24/MAD12_0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P08/TRACED3/TIOA00_2/CTS4_2
98
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
VSS
97
96
95
94
93
VSS
92
AVSS
91
AVRH
LQFP - 144
90
AVCC
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P19/AN09/SCK2_2/INT22_1/MAD05_0
P18/AN08/SOT2_2/INT21_1/MAD04_0
P17/AN07/SIN2_2/INT04_1/MAD03_0
P16/AN06/SCK0_1/INT20_1/MAD02_0
P15/AN05/SOT0_1/IC03_2/MAD01_0
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
P10/AN00/MCSX7_0
88
87
86
85
84
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
P39/DTTI0X_0/ADTG_2
83
82
81
80
P3A/RTO00_0/TIOA00_1
79
P3B/RTO01_0/TIOA01_1
78
P3C/RTO02_0/TIOA02_1
77
P3D/RTO03_0/TIOA03_1
76
P3E/RTO04_0/TIOA04_1
75
P3F/RTO05_0/TIOA05_1
74
VSS
73
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 9 of 132
MB9B110T Series
LBE192
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
P81 P80 VCC VSS PCD PCB VSS VCC PC8 VSS TCK VCC
TRSTX
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
VSS
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6 P83
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 P82
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 VCC
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
G
H
J
K
L
M
N
P
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS X0
X1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 10 of 132
MB9B110T Series
4.
List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, the same function is provided on the same channel. Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-144
1
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
1
C1
VCC
PA0
-
RTO20_0
TIOA08_0
FRCK1_0
PA1
2
3
4
5
2
3
4
5
B2
C2
C3
D5
G
G
G
G
I
I
I
I
RTO21_0
TIOA09_0
IC10_0
PA2
RTO22_0
TIOA10_0
IC11_0
PA3
RTO23_0
TIOA11_0
IC12_0
PA4
RTO24_0
TIOA12_0
IC13_0
6
7
8
6
7
8
D2
D1
D3
G
G
E
H
H
F
INT03_0
PA5
RTO25_0
TIOA13_0
INT10_2
P05
TRACED0
TIOA05_2
SIN4_2
INT00_1
Document Number: 002-04683 Rev.*C
Page 11 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P06
TRACED1
TIOB05_2
SOT4_2
INT01_1
P07
9
9
D4
E
F
TRACED2
ADTG_0
SCK4_2
P08
10
11
10
11
E2
E3
E
E
G
G
TRACED3
TIOA00_2
CTS4_2
P09
TRACECLK
TIOB00_2
RTS4_2
DTTI2X_0
P50
12
12
E4
E
G
INT00_0
AIN0_2
SIN3_1
RTO10_0
IC20_0
13
13
E5
E
H
MOEX_0
P51
INT01_0
BIN0_2
SOT3_1
RTO11_0
IC21_0
14
14
F1
E
H
MWEX_0
Document Number: 002-04683 Rev.*C
Page 12 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P52
INT02_0
ZIN0_2
15
15
F2
SCK3_1
RTO12_0
IC22_0
E
H
MDQM0_0
P53
SIN6_0
TIOA01_2
INT07_2
RTO13_0
IC23_0
16
16
F3
E
H
MDQM1_0
P54
SOT6_0
TIOB01_2
RTO14_0
MALE_0
P55
17
18
17
18
F4
F5
E
E
I
I
SCK6_0
ADTG_1
RTO15_0
MRDY_0
P56
SIN1_0
INT08_2
TIOA09_2
DTTI1X_0
MNALE_0
P57
19
19
F6
E
H
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
20
20
G2
E
H
Document Number: 002-04683 Rev.*C
Page 13 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P58
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
21
21
22
23
G3
E
H
H
H
H
SIN7_0
TIOB11_2
INT09_2
MNREX_0
P5A
22
23
G4
G5
E
E
E
SOT7_0
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
24
25
24
G6
H1
TIOA06_2
INT28_0
IC20_1
-
E
E
H
H
P5D
TIOB06_2
INT29_0
DTTI2X_1
VSS
26
27
28
-
25
-
H2
J1
-
P30
AIN0_0
TIOB00_1
INT03_2
H3
E
H
Document Number: 002-04683 Rev.*C
Page 14 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P31
BIN0_0
TIOB01_1
SCK6_1
INT04_2
P32
29
-
-
-
H4
E
H
H
H
ZIN0_0
TIOB02_1
SOT6_1
INT05_2
P33
30
31
H5
H6
E
E
INT04_0
TIOB03_1
SIN6_1
ADTG_6
P34
32
33
-
-
J5
J4
FRCK0_0
TIOB04_1
P35
E
E
I
IC03_0
TIOB05_1
INT08_1
P36
H
IC02_0
SIN5_2
INT09_1
TIOA12_2
MCSX2_0
P37
34
26
J3
E
H
IC01_0
SOT5_2
INT10_1
TIOB12_2
MCSX3_0
35
27
J2
E
H
Document Number: 002-04683 Rev.*C
Page 15 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P38
IC00_0
36
28
K1
SCK5_2
INT11_1
MCLKOUT_0
P39
E
H
37
38
39
40
41
42
43
29
30
31
32
33
34
35
K2
K3
K4
L1
L2
L3
M2
DTTI0X_0
ADTG_2
P3A
E
G
G
G
G
G
G
I
I
I
I
I
I
I
RTO00_0
TIOA00_1
P3B
RTO01_0
TIOA01_1
P3C
RTO02_0
TIOA02_1
P3D
RTO03_0
TIOA03_1
P3E
RTO04_0
TIOA04_1
P3F
RTO05_0
TIOA05_1
VSS
44
45
36
37
M1
N1
-
-
VCC
P40
TIOA00_0
RTO10_1
INT12_1
46
38
N2
G
H
Document Number: 002-04683 Rev.*C
Page 16 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P41
TIOA01_0
RTO11_1
INT13_1
P42
47
39
40
41
N3
G
H
48
49
M3
L4
TIOA02_0
RTO12_1
P43
G
G
I
TIOA03_0
RTO13_1
ADTG_7
P44
I
50
51
42
43
M4
N4
TIOA04_0
RTO14_1
P45
G
G
I
I
TIOA05_0
RTO15_1
C
52
53
54
44
45
46
P2
P3
P4
-
-
-
VSS
VCC
P46
55
47
P5
D
M
X0A
P47
56
57
48
49
P6
N5
D
B
N
C
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
P49
58
50
M5
E
H
TIOB00_0
IC10_1
AIN0_1
SOT3_2
59
51
L5
E
I
Document Number: 002-04683 Rev.*C
Page 17 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P4A
TIOB01_0
IC11_1
60
52
53
54
K5
E
I
I
I
BIN0_1
SCK3_2
MADATA00_0
P4B
TIOB02_0
IC12_1
61
N6
E
ZIN0_1
MADATA01_0
P4C
TIOB03_0
IC13_1
62
M6
E
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
FRCK1_1
SOT7_1
BIN1_2
63
55
L6
E
I
MADATA03_0
P4E
TIOB05_0
INT06_2
SIN7_1
64
65
56
57
K6
J6
E
E
H
ZIN1_2
MADATA04_0
P70
TIOA04_2
MADATA05_0
I
Document Number: 002-04683 Rev.*C
Page 18 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P71
INT13_2
TIOB04_2
MADATA06_0
P72
66
58
59
N8
E
H
H
SIN2_0
67
M8
INT14_2
AIN2_0
E
MADATA07_0
P73
SOT2_0
INT15_2
BIN2_0
68
69
70
60
61
62
L8
K8
P8
E
E
E
H
MADATA08_0
P74
SCK2_0
ZIN2_0
I
MADATA09_0
P75
SIN3_0
ADTG_8
INT07_1
MADATA10_0
P76
H
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
71
72
63
64
J8
E
E
H
H
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P9
Document Number: 002-04683 Rev.*C
Page 19 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P78
AIN1_0
TIOA15_0
MADATA13_0
P79
73
65
66
N9
E
I
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
74
M9
E
H
-
-
-
-
E1
G1
-
-
VSS
P7A
ZIN1_0
75
67
L9
E
H
INT24_1
MADATA15_0
P7B
76
77
-
-
K9
TIOB07_0
INT10_0
P7C
E
E
H
H
P10
TIOA07_0
INT11_0
P7D
TIOA14_1
FRCK2_1
INT12_0
P7E
78
79
80
-
-
-
N10
L10
K10
E
E
E
H
H
H
TIOB14_1
IC21_1
INT24_0
P7F
TIOA15_1
IC22_1
INT25_0
Document Number: 002-04683 Rev.*C
Page 20 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
PF0
TIOB15_1
SIN1_2
INT13_0
IC23_1
PF1
*1
81
-
M10
H
I
TIOA08_1
SOT1_2
INT14_0
PF2
*1
82
83
-
-
N11
M11
H
H
I
TIOB08_1
SCK1_2
INT15_0
PE0
*1
I
84
85
86
68
69
70
N13
N12
P12
C
J
P
D
A
MD1
MD0
PE2
A
X0
PE3
87
71
P13
A
B
X1
88
89
-
72
73
-
N14
M14
L7
VSS
-
-
-
-
VCC
VSS
-
-
K7
VSS
P10
90
74
M13
AN00
F
F
K
L
MCSX7_0
P11
AN01
SIN1_1
INT02_1
FRCK0_2
MCSX6_0
91
75
M12
Document Number: 002-04683 Rev.*C
Page 21 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P12
AN02
92
76
77
L13
SOT1_1
IC00_2
MCSX5_0
P13
F
K
K
AN03
93
L12
SCK1_1
IC01_2
MCSX4_0
P14
F
AN04
SIN0_1
INT03_1
IC02_2
MAD00_0
P15
94
78
L11
F
L
AN05
95
96
97
79
80
81
K13
K12
K14
SOT0_1
IC03_2
MAD01_0
P16
F
F
F
K
L
L
AN06
SCK0_1
INT20_1
MAD02_0
P17
AN07
SIN2_2
INT04_1
MAD03_0
VSS
-
-
-
-
-
-
P7
P11
L14
-
-
-
VSS
VSS
Document Number: 002-04683 Rev.*C
Page 22 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P18
AN08
98
82
83
K11
SOT2_2
INT21_1
MAD04_0
P19
F
L
L
AN09
99
J13
SCK2_2
INT22_1
MAD05_0
P1A
F
AN10
SIN4_1
INT05_1
TIOA13_2
IC00_1
MAD06_0
P1B
100
84
85
86
J12
F
L
L
L
AN11
SOT4_1
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
101
J11
F
AN12
SCK4_1
INT26_1
TIOA14_2
IC02_1
MAD08_0
102
J10
F
Document Number: 002-04683 Rev.*C
Page 23 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P1D
AN13
CTS4_1
INT27_1
TIOB14_2
IC03_1
MAD09_0
P1E
103
87
88
89
J9
F
L
L
L
AN14
RTS4_1
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
P1F
104
H10
F
AN15
ADTG_5
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
AVCC
105
H9
F
106
107
108
109
90
91
92
93
J14
H14
G14
F14
-
-
-
-
AVRH
AVSS
VSS
PB0
AN16
110
111
-
-
H13
H12
TIOA09_1
SIN7_2
INT16_0
PB1
F
F
L
L
AN17
TIOB09_1
SOT7_2
INT17_0
Document Number: 002-04683 Rev.*C
Page 24 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
PB2
AN18
112
-
-
-
H11
TIOA10_1
SCK7_2
INT18_0
PB3
F
L
L
L
AN19
113
114
G13
G12
F
F
TIOB10_1
INT19_0
PB4
AN20
TIOA11_1
SIN0_2
INT20_0
PB5
AN21
TIOB11_1
SOT0_2
INT21_0
AIN2_2
VSS
115
-
G11
F
L
-
-
-
-
G7
J7
-
-
VSS
PB6
AN22
TIOA12_1
SCK0_2
INT22_0
BIN2_2
PB7
116
-
G10
F
L
AN23
117
118
-
G9
TIOB12_1
INT23_0
ZIN2_2
P29
F
F
L
94
F10
AN24
K
MAD12_0
Document Number: 002-04683 Rev.*C
Page 25 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P28
AN25
ADTG_4
INT09_0
RTO05_1
MAD13_0
P27
119
95
F11
F
L
AN26
120
121
122
96
97
98
F12
F13
E10
INT02_2
RTO04_1
MAD14_0
P26
F
F
F
L
K
K
AN27
SCK2_1
RTO03_1
MAD15_0
P25
AN28
SOT2_1
RTO02_1
MAD16_0
P24
AN29
SIN2_1
INT01_2
RTO01_1
MAD17_0
P23
123
99
E11
F
L
AN30
124
100
E12
SCK0_0
TIOA07_1
RTO00_1
F
K
Document Number: 002-04683 Rev.*C
Page 26 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P22
AN31
SOT0_0
TIOB07_1
ZIN1_1
P21
125
101
102
E13
F
K
H
SIN0_0
INT06_1
BIN1_1
P20
126
D12
E
E
INT05_0
CROUT_0
AIN1_1
MAD18_0
PF6
127
128
103
104
D13
C13
H
J
*1
FRCK2_0
NMIX
VCC
I
129
130
131
132
133
105
106
107
108
109
E14
D14
C14
B14
A13
-
P82
H
H
O
O
P83
VSS
-
-
VCC
P00
134
135
136
137
110
111
112
113
B13
A12
C12
B12
E
E
E
E
E
E
E
E
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
138
114
B11
TDO
E
E
SWO
Document Number: 002-04683 Rev.*C
Page 27 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
P90
TIOB08_0
RTO20_1
INT30_0
MAD19_0
VSS
139
-
-
-
C11
E
H
-
A8
-
P91
TIOB09_0
RTO21_1
INT31_0
MAD20_0
P92
140
D11
E
E
E
H
TIOB10_0
RTO22_1
SIN5_1
MAD21_0
P93
141
142
-
-
B10
C10
I
TIOB11_0
RTO23_1
SOT5_1
MAD22_0
P94
I
TIOB12_0
RTO24_1
SCK5_1
INT26_0
MAD23_0
P95
143
-
D10
E
H
TIOB13_0
RTO25_1
INT27_0
MAD24_0
PC0
144
-
B9
E
H
145
146
147
115
116
117
C9
B8
D9
K
K
K
Q
Q
Q
PC1
PC2
Document Number: 002-04683 Rev.*C
Page 28 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
PC3
TIOA06_1
PC4
148
118
119
E9
K
Q
Q
Q
149
F9
K
K
TIOA08_2
PC5
150
-
120
-
C8
A5
D8
TIOA10_2
VSS
-
PC6
151
121
K
L
Q
Q
TIOA14_0
PC7
152
122
E8
CROUT_1
PC8
153
154
155
156
157
158
159
160
123
124
125
126
127
128
129
130
A10
F8
K
K
K
Q
Q
Q
PC9
B7
PCA
A9
VCC
-
-
A11
A7
VSS
PCB
L
K
K
Q
Q
Q
C7
A6
PCC
PCD
PCE
161
162
131
132
D7
E7
RTS4_0
TIOB06_1
PCF
L
L
Q
Q
CTS4_0
TIOB08_2
PD0
SCK4_0
TIOB10_2
INT30_1
PD1
163
164
133
134
F7
B6
L
L
R
R
SOT4_0
TIOB14_0
INT31_1
VSS
-
-
-
-
-
-
-
-
N7
G8
H7
H8
-
-
-
-
VSS
VSS
VSS
Document Number: 002-04683 Rev.*C
Page 29 of 132
MB9B110T Series
Pin No
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
LQFP-144
BGA-192
PD2
SIN4_0
TIOA03_2
INT00_2
PD3
165
135
C6
L
R
166
167
136
137
D6
E6
L
Q
Q
TIOB03_2
P62
SCK5_0
ADTG_3
P61
E
168
169
138
139
B5
C5
SOT5_0
TIOB02_2
P60
E
E
I
SIN5_0
TIOA02_2
INT15_1
PF3
H
TIOA06_0
SIN6_2
INT06_0
AIN2_1
PF4
*1
170
-
B4
H
I
TIOB06_0
SOT6_2
INT07_0
BIN2_1
PF5
*1
171
172
-
C4
B3
H
H
I
SCK6_2
INT08_0
ZIN2_1
*1
140
I
Document Number: 002-04683 Rev.*C
Page 30 of 132
MB9B110T Series
Pin No
LQFP-144
141
I/O circuit
Pin state
type
Pin Name
type
LQFP-176
BGA-192
173
A4
VCC
P80
P81
VSS
VSS
-
174
142
143
144
-
A3
A2
B1
M7
H
H
O
O
175
176
-
-
-
*1: 5 V tolerant I/O
Document Number: 002-04683 Rev.*C
Page 31 of 132
MB9B110T Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, the same function is provided on the same channel. Use the extended port function register (EPFR) to select the pin.
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
10
10
E2
18
37
18
29
137
95
89
-
F5
K2
E6
F11
H9
H6
L4
167
119
105
31
A/D converter external trigger input pin
49
41
62
70
P8
Document Number: 002-04683 Rev.*C
Page 32 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
90
74
M13
91
92
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
-
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
93
94
95
96
97
98
99
100
101
102
103
104
105
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
H10
H9
A/D converter analog input pin
ANxx describes ADC ch.xx
ADC
H13
H12
H11
G13
G12
G11
G10
G9
-
-
-
-
-
-
-
94
95
96
97
98
99
100
101
F10
F11
F12
F13
E10
E11
E12
E13
Document Number: 002-04683 Rev.*C
Page 33 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
Base Timer 0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
46
38
N2
Base timer ch.0 TIOA pin
38
11
59
28
12
47
39
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
30
11
51
-
K3
E3
L5
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
H3
E4
N3
K4
F3
K5
H4
F4
M3
L1
12
39
31
16
52
-
Base Timer 1
Base Timer 2
Base Timer 3
Base Timer 4
17
40
32
139
53
-
C5
N6
H5
B5
L4
138
41
33
135
54
-
L2
C6
M6
H6
D6
M4
L3
136
42
34
57
55
-
J6
L6
J5
58
N8
Document Number: 002-04683 Rev.*C
Page 34 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
Base Timer 5
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA07_0
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
TIOA08_1
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
51
43
N4
Base timer ch.5 TIOA pin
43
8
35
M2
D3
8
64
56
K6
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
33
-
J4
9
9
D4
Base Timer 6
Base Timer 7
Base Timer 8
Base Timer 9
170
148
25
-
B4
118
E9
-
H1
171
161
26
-
131
-
C4
D7
H2
77
-
P10
E12
J8
124
71
100
63
-
76
K9
125
72
101
64
2
E13
P9
2
B2
82
-
N11
F9
149
139
83
119
-
C11
M11
E7
-
162
3
132
3
C2
110
19
-
H13
F6
19
-
140
111
20
D11
H12
G2
-
20
Document Number: 002-04683 Rev.*C
Page 35 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
Base Timer
10
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
4
4
C3
Base timer ch.10 TIOA pin
112
150
141
113
163
5
-
120
-
H11
C8
B10
G13
F7
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
Base timer ch.14 TIOA pin
Base timer ch.14 TIOB pin
-
133
5
Base Timer
11
D5
114
21
-
G12
G3
21
-
142
115
22
C10
G11
G4
-
22
6
Base Timer
12
6
D2
116
34
-
G10
J3
26
-
143
117
35
D10
G9
-
27
7
J2
Base Timer
13
7
D1
23
23
84
-
G5
100
144
24
J12
B9
24
85
121
-
G6
101
151
78
J11
D8
Base Timer
14
N10
J10
B6
102
164
79
86
134
-
L10
J9
103
87
Document Number: 002-04683 Rev.*C
Page 36 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
Base Timer
15
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
SWCLK
SWDIO
73
65
N9
Base timer ch.15 TIOA pin
80
104
74
-
K10
H10
M9
88
66
Base timer ch.15 TIOB pin
81
-
M10
H9
105
135
137
138
135
136
138
137
12
89
Debugger
Serial wire debug interface clock input
Serial wire debug interface data input / output
Serial wire viewer output
111
113
114
111
112
114
113
12
A12
B12
B11
A12
C12
B11
B12
E4
SWO
TCK
JTAG test clock input
TDI
JTAG test data input
TDO
JTAG debug data output
TMS
JTAG test mode state input/output
Trace CLK output of ETM
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
8
8
D3
9
9
D4
Trace data output of ETM
JTAG test reset input
10
10
E2
11
11
E3
134
110
B13
Document Number: 002-04683 Rev.*C
Page 37 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
94
78
L11
95
96
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
103
-
K13
K12
K14
K11
J13
J12
J11
J10
J9
97
98
99
100
101
102
103
104
105
118
119
120
121
122
123
127
139
140
141
142
143
144
23
H10
H9
External bus interface address bus
F10
F11
F12
F13
E10
E11
D13
C11
D11
B10
C10
D10
B9
External
Bus
-
-
-
-
-
23
24
26
27
77
76
75
74
G5
24
G6
34
J3
35
J2
External bus interface chip select output pin
93
L12
L13
M12
M13
92
91
90
Document Number: 002-04683 Rev.*C
Page 38 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
MDQM0_0
MDQM1_0
15
15
F2
External bus interface byte mask signal output
16
13
16
13
F3
E5
External bus interface read enable signal for
SRAM
MOEX_0
MWEX_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
External bus interface write enable signal for
SRAM
14
19
20
22
21
14
19
20
22
21
F1
F6
G2
G4
G3
External bus interface ALE signal to control
NAND Flash memory output pin
External bus interface CLE signal to control
NAND Flash memory output pin
External bus interface read enable signal to
control NAND Flash memory
External bus interface write enable signal to
control NAND Flash memory
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MALE_0
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
17
18
36
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
17
18
28
K5
N6
M6
L6
External
Bus
K6
J6
N8
M8
L8
External bus interface data bus
(Multiplexed bus to address output for
multiplex)
K8
P8
J8
P9
N9
M9
L9
Address Latch enable signal for multiplex
External RDY input signal
F4
F5
K1
MRDY_0
MCLKOUT_0
External bus clock output
Document Number: 002-04683 Rev.*C
Page 39 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
13
13
E5
External interrupt request 00 input pin
8
8
135
14
9
D3
C6
F1
165
14
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
9
D4
E11
F2
123
15
99
15
75
96
6
91
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
120
6
94
78
-
28
31
-
97
81
-
29
127
100
30
103
84
-
External
Interrupt
170
126
64
-
102
56
-
D12
K6
171
70
C4
P8
62
16
140
-
16
F3
172
33
B3
J4
19
19
95
26
22
-
F6
119
34
F11
J3
22
G4
K9
76
35
27
7
J2
7
D1
Document Number: 002-04683 Rev.*C
Page 40 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
External
Interrupt
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
77
-
P10
External interrupt request 11 input pin
36
71
28
63
-
K1
J8
78
N10
N2
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
46
38
64
-
72
P9
81
M10
N3
47
39
58
-
66
N8
82
N11
M5
58
50
59
-
67
M8
83
M11
C5
169
68
139
60
-
L8
110
20
H13
G2
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
20
-
111
21
H12
G3
21
-
112
23
H11
G5
23
-
113
24
G13
G6
24
-
114
96
G12
K12
G11
K11
G10
J13
G9
80
-
115
98
82
-
116
99
83
-
117
74
66
-
M9
79
L10
L9
75
67
-
80
K10
J11
101
85
Document Number: 002-04683 Rev.*C
Page 41 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
External
Interrupt
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
143
-
D10
External interrupt request 26 input pin
102
144
103
25
86
-
J10
B9
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
87
-
J9
H1
104
26
88
-
H10
H2
105
139
163
140
164
128
134
135
136
137
138
8
89
-
H9
C11
F7
133
-
D11
B6
External interrupt request 31 input pin
Non-Maskable Interrupt input
134
104
110
111
112
113
114
8
C13
B13
A12
C12
B12
B11
D3
GPIO
P00
P01
P02
P03
P04
General-purpose I/O port 0
P05
P06
9
9
D4
P07
10
10
11
12
E2
P08
11
E3
P09
12
E4
Document Number: 002-04683 Rev.*C
Page 42 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
90
74
M13
91
92
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
93
94
95
96
97
General-purpose I/O port 1
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
GPIO
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
General-purpose I/O port 2
Document Number: 002-04683 Rev.*C
Page 43 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
28
-
H3
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
-
H4
H5
H6
J5
-
-
-
-
J4
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
J3
J2
General-purpose I/O port 3
K1
K2
K3
K4
L1
L2
L3
GPIO
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
General-purpose I/O port 4
K5
N6
M6
L6
K6
Document Number: 002-04683 Rev.*C
Page 44 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
13
13
E5
14
15
16
17
18
19
20
21
22
23
24
25
26
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
14
15
16
17
18
19
20
21
22
23
24
-
F1
F2
F3
F4
F5
F6
General-purpose I/O port 5
G2
G3
G4
G5
G6
H1
H2
C5
B5
E6
J6
-
139
138
137
57
58
59
60
61
62
63
64
65
66
67
-
General-purpose I/O port 6
GPIO
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
General-purpose I/O port 7
K9
P10
N10
L10
K10
-
-
-
-
Document Number: 002-04683 Rev.*C
Page 45 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
174
142
A3
175
130
131
139
140
141
142
143
144
2
143
A2
D14
C14
C11
D11
B10
C10
D10
B9
General-purpose I/O port 8
106
107
-
-
-
General-purpose I/O port 9
-
-
-
2
3
4
5
6
7
-
B2
3
C2
GPIO
4
C3
General-purpose I/O port A
5
D5
6
D2
7
D1
110
111
112
113
114
115
116
117
H13
H12
H11
G13
G12
G11
G10
G9
-
-
-
General-purpose I/O port B
-
-
-
-
Document Number: 002-04683 Rev.*C
Page 46 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
145
115
C9
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
B8
D9
E9
F9
C8
D8
E8
General-purpose I/O port C
A10
F8
B7
A7
C7
A6
D7
GPIO
E7
F7
B6
General-purpose I/O port D
General-purpose I/O port E
C6
D6
N13
P12
P13
M10
N11
M11
B4
86
70
87
71
81
-
82
-
83
-
*1
170
171
172
128
-
General-purpose I/O port F
-
C4
140
104
B3
C13
Document Number: 002-04683 Rev.*C
Page 47 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
SIN0_0
SIN0_1
SIN0_2
126
102
D12
Multi-function serial interface ch.0 input pin
94
78
-
L11
114
G12
SOT0_0
125
101
E13
(SDA0_0)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA0 when it is used in an I2C (operation
mode 4).
SOT0_1
95
79
-
K13
G11
E12
(SDA0_1)
Multi-Function
Serial 0
SOT0_2
115
124
(SDA0_2)
SCK0_0
100
Multi-function serial interface ch.0 clock
I/O pin.
(SCL0_0)
SCK0_1
This pin operates as SCK0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL0 when it is used in an I2C
96
80
-
K12
G10
(SCL0_1)
SCK0_2
(operation mode 4).
116
(SCL0_2)
Multi-Function
Serial 1
SIN1_0
SIN1_1
SIN1_2
19
91
81
19
75
-
F6
Multi-function serial interface ch.1 input pin
M12
M10
SOT1_0
20
92
82
21
93
83
20
76
-
G2
L13
N11
G3
(SDA1_0)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA1 when it is used in an I2C
SOT1_1
(SDA1_1)
(operation mode 4).
SOT1_2
(SDA1_2)
SCK1_0
21
77
-
(SCL1_0)
Multi-function serial interface ch.1 clock
I/O pin.
SCK1_1
This pin operates as SCK1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL1 when it is used in an I2C (operation
mode 4).
L12
M11
(SCL1_1)
SCK1_2
(SCL1_2)
Document Number: 002-04683 Rev.*C
Page 48 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
SIN2_0
SIN2_1
SIN2_2
67
59
M8
Multi-function serial interface ch.2 input pin
123
97
99
81
E11
K14
SOT2_0
68
122
98
60
98
82
61
97
83
L8
E10
K11
K8
(SDA2_0)
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA2 when it is used in an I2C
(operation mode 4).
SOT2_1
(SDA2_1)
Multi-Function
Serial 2
SOT2_2
(SDA2_2)
SCK2_0
69
Multi-function serial interface ch.2 clock
I/O pin.
(SCL2_0)
SCK2_1
This pin operates as SCK2 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL2 when it is used in an I2C
(operation mode 4).
121
99
F13
J13
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SIN3_2
70
13
58
62
13
50
P8
E5
M5
Multi-function serial interface ch.3 input pin
SOT3_0
71
14
59
72
15
60
63
14
51
64
15
52
J8
F1
L5
P9
F2
K5
(SDA3_0)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA3 when it is used in an I2C
(operation mode 4).
SOT3_1
(SDA3_1)
Multi-Function
Serial 3
SOT3_2
(SDA3_2)
SCK3_0
Multi-function serial interface ch.3 clock
I/O pin.
(SCL3_0)
SCK3_1
This pin operates as SCK3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL3 when it is used in an I2C
(SCL3_1)
SCK3_2
(operation mode 4).
(SCL3_2)
Document Number: 002-04683 Rev.*C
Page 49 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
SIN4_0
SIN4_1
SIN4_2
165
135
C6
Multi-function serial interface ch.4 input pin
100
8
84
8
J12
D3
SOT4_0
164
101
9
134
85
9
B6
J11
D4
F7
(SDA4_0)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA4 when it is used in an I2C
SOT4_1
(SDA4_1)
SOT4_2
(operation mode 4).
(SDA4_2)
SCK4_0
163
102
10
133
86
10
Multi-function serial interface ch.4 clock I/O
pin.
Multi-Function
Serial 4
(SCL4_0)
SCK4_1
This pin operates as SCK4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL4 when it is used in an I2C
(operation mode 4).
J10
E2
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
161
104
12
131
88
12
132
87
11
139
-
D7
H10
E4
Multi-function serial interface ch.4 RTS output
pin
162
103
11
E7
Multi-function serial interface ch.4 CTS input
pin
J9
E3
169
141
34
C5
B10
J3
Multi-function serial interface ch.5 input pin
26
SOT5_0
(SDA5_0)
168
138
B5
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA5 when it is used in an I2C
SOT5_1
(SDA5_1)
142
35
-
C10
J2
(operation mode 4).
Multi-Function
Serial 5
SOT5_2
(SDA5_2)
27
SCK5_0
(SCL5_0)
167
137
E6
Multi-function serial interface ch.5 clock
I/O pin.
This pin operates as SCK5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL5 when it is used in an I2C
(operation mode 4).
SCK5_1
(SCL5_1)
143
36
-
D10
K1
SCK5_2
(SCL5_2)
28
Document Number: 002-04683 Rev.*C
Page 50 of 132
MB9B110T Series
Pin No
LQFP-176 LQFP-144 BGA-192
Module
Pin name
Function
SIN6_0
SIN6_1
SIN6_2
16
31
16
-
F3
H6
B4
Multi-function serial interface ch.6 input pin
170
-
SOT6_0
17
30
17
-
F4
H5
C4
F5
H4
B3
(SDA6_0)
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA6 when it is used in an I2C
SOT6_1
(SDA6_1)
Multi-Function
Serial 6
(operation mode 4).
SOT6_2
171
18
-
(SDA6_2)
SCK6_0
18
-
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C
SCK6_1
29
(SCL6_1)
SCK6_2
(operation mode 4).
172
140
(SCL6_2)
SIN7_0
SIN7_1
SIN7_2
22
64
22
56
-
G4
K6
Multi-function serial interface ch.7 input pin
110
H13
SOT7_0
23
63
23
55
-
G5
L6
(SDA7_0)
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA7 when it is used in an I2C
SOT7_1
(SDA7_1)
(operation mode 4).
Multi-Function
Serial 7
SOT7_2
111
24
H12
G6
(SDA7_2)
SCK7_0
24
(SCL7_0)
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL7 when it is used in an I2C
SCK7_1
62
54
-
M6
(SCL7_1)
(operation mode 4).
SCK7_2
112
H11
(SCL7_2)
Document Number: 002-04683 Rev.*C
Page 51 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-1
LQFP-144 BGA-192
76
DTTI0X_0
37
29
K2
Input signal of waveform generator to control outputs
RTO00 to RTO05 of multi-function timer 0.
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
104
32
88
-
H10
J5
16-bit free-run timer ch.0 external clock input pin
105
91
89
75
28
84
76
27
85
77
26
86
78
-
H9
M12
K1
36
IC00_1
100
92
J12
L13
J2
IC00_2
IC01_0
35
IC01_1
101
93
J11
L12
J3
IC01_2
16-bit input capture input pin of multi-function timer 0
ICxx describes channel number.
IC02_0
34
IC02_1
102
94
J10
L11
J4
IC02_2
IC03_0
33
Multi-Function
Timer 0
IC03_1
103
95
87
79
30
J9
IC03_2
K13
K3
RTO00_0 (PPG00_0)
Waveform generator output of multi-function timer 0
38
This pin operates as PPG00 when it is used in PPG0
output modes.
RTO00_1 (PPG00_1)
RTO01_0 (PPG00_0)
RTO01_1 (PPG00_1)
RTO02_0 (PPG02_0)
RTO02_1 (PPG02_1)
RTO03_0 (PPG02_0)
RTO03_1 (PPG02_1)
RTO04_0 (PPG04_0)
RTO04_1 (PPG04_1)
RTO05_0 (PPG04_0)
RTO05_1 (PPG04_1)
124
39
100
31
99
32
98
33
97
34
96
35
95
E12
K4
Waveform generator output of multi-function timer 0
This pin operates as PPG00 when it is used in PPG0
output modes.
123
40
E11
L1
Waveform generator output of multi-function timer 0
This pin operates as PPG02 when it is used in PPG0
output modes.
122
41
E10
L2
Waveform generator output of multi-function timer 0
This pin operates as PPG02 when it is used in PPG0
output modes.
121
42
F13
L3
Waveform generator output of multi-function timer 0
This pin operates as PPG04 when it is used in PPG0
output modes.
120
43
F12
M2
F11
Waveform generator output of multi-function timer 0
This pin operates as PPG04 when it is used in PPG0
output modes.
119
Document Number: 002-04683 Rev.*C
Page 52 of 132
MB9B110T Series
Pin No
Module
Pin name
DTTI1X_0
DTTI1X_1
Function
LQFP-176 LQFP-144 BGA-192
Multi-Function
Timer 1
19
58
19
50
F6
Input signal of waveform generator to
control outputs RTO10 to RTO15 of
multi-function timer 1.
M5
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
2
63
3
2
55
3
B2
L6
16-bit free-run timer ch.1 external clock
input pin
C2
L5
59
4
51
4
C3
K5
D5
N6
D2
M6
16-bit input capture input pin of
multi-function timer 1.
ICxx describes channel number
60
5
52
5
61
6
53
6
62
54
RTO10_0
(PPG10_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG10 when it is used
in PPG1 output modes.
13
46
14
47
15
48
16
13
38
14
39
15
40
16
E5
N2
F1
N3
F2
M3
F3
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG10 when it is used
in PPG1 output modes.
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG12 when it is used
in PPG1 output modes.
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG12 when it is used
in PPG1 output modes.
RTO13_1
49
17
41
17
L4
F4
(PPG12_1)
RTO14_0
(PPG14_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG14 when it is used
in PPG1 output modes.
RTO14_1
(PPG14_1)
50
42
M4
RTO15_0
(PPG14_0)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG14 when it is used
in PPG1 output modes.
18
51
18
43
F5
N4
RTO15_1
(PPG14_1)
Document Number: 002-04683 Rev.*C
Page 53 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144 BGA-192
Multi-Function
Timer 2
DTTI2X_0
12
12
E4
Input signal of waveform generator to
control outputs RTO20 to RTO25 of
multi-function timer 2.
DTTI2X_1
26
-
H2
FRCK2_0
FRCK2_1
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
IC23_0
IC23_1
128
78
13
25
14
79
15
80
16
81
104
-
C13
N10
E5
16-bit free-run timer ch.2 external clock
input pin
13
-
H1
14
-
F1
16-bit input capture input pin of
multi-function timer 2.
L10
F2
15
-
ICxx describes channel number.
K10
F3
16
-
M10
RTO20_0
Waveform generator output of
multi-function timer 2.
2
139
3
2
-
B2
C11
C2
(PPG20_0)
This pin operates as PPG20 when it is
used in PPG2 output modes.
RTO20_1
(PPG20_1)
RTO21_0
Waveform generator output of
multi-function timer 2.
3
-
(PPG20_0)
This pin operates as PPG20 when it is
used in PPG2 output modes.
RTO21_1
140
4
D11
C3
(PPG20_1)
RTO22_0
Waveform generator output of
multi-function timer 2.
4
-
(PPG22_0)
This pin operates as PPG22 when it is
used in PPG2 output modes.
RTO22_1
141
5
B10
D5
(PPG22_1)
RTO23_0
Waveform generator output of
multi-function timer 2.
5
-
(PPG22_0)
This pin operates as PPG22 when it is
used in PPG2 output modes.
RTO23_1
142
6
C10
D2
(PPG22_1)
RTO24_0
6
Waveform generator output of
multi-function timer 2.
(PPG24_0)
This pin operates as PPG24 when it is
used in PPG2 output modes.
RTO24_1
143
-
D10
(PPG24_1)
RTO25_0
Waveform generator output of
multi-function timer 2.
7
7
-
D1
B9
(PPG24_0)
This pin operates as PPG24 when it is
used in PPG2 output modes.
RTO25_1
144
(PPG24_1)
Document Number: 002-04683 Rev.*C
Page 54 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144 BGA-192
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
AIN2_0
AIN2_1
AIN2_2
BIN2_0
BIN2_1
BIN2_2
ZIN2_0
ZIN2_1
ZIN2_2
28
-
51
13
-
H3
QPRC ch.0 AIN input pin
59
13
L5
E5
29
H4
K5
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
QPRC ch.2 ZIN input pin
60
52
14
-
14
F1
30
H5
N6
F2
61
53
15
65
103
54
66
102
55
67
101
56
59
-
15
Quadrature
Position/
Revolution
Counter
1
73
N9
D13
M6
M9
D12
L6
127
62
74
126
63
75
L9
125
64
E13
K6
Quadrature
Position/
Revolution
Counter
2
67
M8
B4
170
115
68
-
G11
L8
60
-
171
116
69
C4
G10
K8
-
61
140
-
172
117
B3
G9
Reset
Mode
External Reset Input. A reset is valid when
INITX="L".
INITX
57
49
N5
Mode 0 Pin.
During normal operation, MD0="L" must
be input. During serial programming to
Flash memory, MD0="H" must be input.
MD0
85
69
N12
Mode 1 Pin.
MD1
84
68
N13
During serial programming to Flash
memory, MD1="L" must be input.
Document Number: 002-04683 Rev.*C
Page 55 of 132
MB9B110T Series
Pin No
LQFP-144 BGA-192
Module
Pin name
Function
LQFP-176
VCC
VCC
VCC
VCC
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
1
1
C1
N1
45
54
89
37
46
73
P4
M14
Power
VCC
VCC
VCC
VCC
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
133
173
129
156
109
141
105
126
A13
A4
E14
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
GND Pin
GND Pin
27
25
J1
M1
P3
44
36
GND Pin
53
45
GND Pin
88
72
N14
F14
B14
A11
B1
GND Pin
109
93
GND Pin
132
108
GND Pin
157
127
GND Pin
176
144
GND Pin
-
-
-
-
E1
GND Pin
G1
P7
GND Pin
-
-
GND Pin
-
-
P11
L14
A8
GND
GND Pin
-
-
GND Pin
-
-
GND Pin
-
-
A5
GND Pin
-
-
N7
GND Pin
-
-
M7
L7
GND Pin
-
-
GND Pin
-
-
K7
GND Pin
-
-
J7
GND Pin
-
-
G7
H7
GND Pin
-
-
GND Pin
-
-
H8
GND Pin
-
-
G8
P12
P5
Clock
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
86
55
87
56
70
47
71
48
X0A
X1
P13
P6
X1A
CROUT_0
CROUT_1
AVCC
127
152
106
103
122
90
D13
E8
Built-in high-speed CR oscillation clock
output port
Analog
Power
A/D converter analog power supply pin
J14
A/D converter analog reference voltage
input pin
AVRH
107
91
H14
Document Number: 002-04683 Rev.*C
Page 56 of 132
MB9B110T Series
Pin No
LQFP-144 BGA-192
Module
Pin name
Function
LQFP-176
Analog
GND
AVSS
C
A/D converter GND pin
108
92
44
G14
P2
C pin
Power supply stabilization capacity pin
52
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04683 Rev.*C
Page 57 of 132
MB9B110T Series
5.
I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
A
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is selected.
−
Oscillation feedback resistor:
Approximately 1 MΩ
Digital output
Digital output
−
With Standby mode control
P-ch
P-ch
X1
When the GPIO is selected.
−
−
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
N-ch
R
Pull-up resistor
control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode
control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
Document Number: 002-04683 Rev.*C
Page 58 of 132
MB9B110T Series
Type
Circuit
Remarks
B
−
−
CMOS level hysteresis input
Pull-up resistor: Approximately 50 kΩ
Pull-up resistor
Digital input
C
−
−
Open drain output
CMOS level hysteresis input
Digital input
Control pin
N-ch
Document Number: 002-04683 Rev.*C
Page 59 of 132
MB9B110T Series
Type
Circuit
Remarks
It is possible to select the sub
D
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is selected.
−
Oscillation feedback resistor:
Approximately 5 MΩ
−
With Standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
−
−
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-04683 Rev.*C
Page 60 of 132
MB9B110T Series
Type
Circuit
Remarks
E
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
P-ch
P-ch
Digital output
−
+B input is available
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
Digital output
P-ch
P-ch
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
−
−
N-ch
Digital output
−
+B input is available
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04683 Rev.*C
Page 61 of 132
MB9B110T Series
Type
Circuit
Remarks
G
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -12 mA, IOL= 12 mA
P-ch
P-ch
Digital output
Digital output
+B input is available
N-ch
R
Pull-up resistor
control
Digital input
Standby mode control
H
−
−
−
−
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH= -20.5 mA, IOL=18.5 mA
P-ch
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 62 of 132
MB9B110T Series
Type
Circuit
Remarks
I
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
5 V tolerant
With standby mode control
IOH= -4 mA, IOL= 4 mA
P-ch
Digital output
Available to control PZR registers.
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
N-ch
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
K
−
−
−
−
−
−
CMOS level output
TTL level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH = -4 mA, IOL= 4 mA
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor
control
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 63 of 132
MB9B110T Series
Type
Circuit
Remarks
L
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH = -8 mA, IOL= 8 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
P-ch
P-ch
Digital output
Digital output
−
+B input is available
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 64 of 132
MB9B110T Series
6.
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and
in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such
conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.
Document Number: 002-04683 Rev.*C
Page 65 of 132
MB9B110T Series
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
Document Number: 002-04683 Rev.*C
Page 66 of 132
MB9B110T Series
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04683 Rev.*C
Page 67 of 132
MB9B110T Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04683 Rev.*C
Page 68 of 132
MB9B110T Series
7.
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 μF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1 and X1A pins should be kept
open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
Document Number: 002-04683 Rev.*C
Page 69 of 132
MB9B110T Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
Cs
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on: VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
Document Number: 002-04683 Rev.*C
Page 70 of 132
MB9B110T Series
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.Therefore, design a
printed circuit board so as to avoid noise.Consider the case of receiving wrong data due to noise, perform error detection such as
by applying a checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip layout
and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input
(TGIN). Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to
be "0b00" in order to disable trigger input.
Document Number: 002-04683 Rev.*C
Page 71 of 132
MB9B110T Series
8.
Block Diagram
MB9BF116/117/118
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
TPIU
ETM
SRAM0
32/48/64Kbyte
ROM
Table
TRACED[3:0],
TRACECLK
On-chip Flash
512Kbyte/
768Kbyte/
Cortex-M3ꢀCore
144MHz(Max)
I
Flash I/F
Security
D
1024Kbyte
MPU NVIC
Trace Buffer
(16Kbyte)
Sys
SRAM1
32/48/64Kbyte
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
CSV
CLK
DMAC
8ch.
Main
Source Clock
X0
PLL
Osc
Sub
Osc
X1
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
12-bit A/D Converter
Unit 0
AN[31:00]
Unit 1
Unit 2
ADTG[8:0]
MAD[24:00]
External Bus I/F
MADATA[15:00]
TIOA[15:00]
TIOB[15:00]
Base Timer
16-bit 16ch./
32-bit 8ch.
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
AIN[2:0]
BIN[2:0]
ZIN[2:0]
QPRC
3ch.
Power On
Reset
MCLKOUT
LVD
LVD Ctrl
A/D Activation
Compare
3ch.
Regulator
C
IRQ-Monitor
IC0[3:0]
IC1[3:0]
IC2[3:0]
16-bit Input Capture
4ch.
CRC
Accelerator
16-bit Free-run Timer
3ch.
FRCK[2:0]
Watch Counter
External Interrupt
Controller
32-pin + NMI
16-bit Output
Compare
6ch.
INT[31:00]
NMIX
DTTI[2:0]X
Waveform Generator
3ch.
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
MD[1:0]
MODE-Ctrl
GPIO
P0x,
P1x,
.
16-bit PPG
3ch.
PIN-Function-Ctrl
.
.
PFx
Multi-function Timer ×3
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
RTS4
Note:
−
The following items vary depending on the package.
•
•
External bus interface pin numbers
12-bit A/D converter channel numbers
Document Number: 002-04683 Rev.*C
Page 72 of 132
MB9B110T Series
9.
Memory Size
See "Memory size" in "Product Lineup" to confirm the memory size.
10.
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
Reserved
0x4004_0000
0x4003_F000
EXT-bus I/F
Reserved
0x7000_0000
0x6000_0000
External Device
Area
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
Watch Counter
CRC
Reserved
MFS
0x4400_0000
0x4200_0000
0x4000_0000
Reserved
32Mbyte
Bit band alias
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
LVD Ctrl
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
0x2400_0000
0x2200_0000
32Mbyte
Bit band alias
Reserved
CR Trim
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
A/DC
QPRC
Base Timer
PPG
Reserved
MFT unit2
MFT unit1
MFT unit0
0x2008_0000
0x2000_0000
0x1FFF_0000
SRAM1
SRAM0
Reserved
0x0010_2000
0x0010_0000
See the next page
Security/CR Trim
“●Memory Map (2)” for
the memory size details.
On-chip Flash
Reserved
Dual Timer
Reserved
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-04683 Rev.*C
Page 73 of 132
MB9B110T Series
Memory Map (2)
MB9BF118S/T
MB9BF117S/T
MB9BF116S/T
0x2008_0000
0x2001_0000
0x2008_0000
0x2001_C000
0x2000_0000
0x2008_0000
Reserved
Reserved
Reserved
SRAM1
64Kbyte
0x2000_8000
0x2000_0000
0x1FFF_8000
SRAM1
48Kbyte
SRAM1
32Kbyte
0x2000_0000
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-23(64KBx14)
0x0008_0000
SA10-19(64KBx10)
SA10-15(64KBx6)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
0x0000_0000
0x0000_0000
0x0000_0000
See "MB9BD10T/610T/510T/410T/310T/210T/110T Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04683 Rev.*C
Page 74 of 132
MB9B110T Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Flash memory I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Multi-function timer unit2
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
Reserved
Low-Voltage Detector
Reserved
APB2
Multi-function serial Interface
CRC
Watch Counter
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
Document Number: 002-04683 Rev.*C
Page 75 of 132
MB9B110T Series
11.
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.If a built-in peripheral function is operating, the
output follows the peripheral function.If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-04683 Rev.*C
Page 76 of 132
MB9B110T Series
List of Pin Status
Power-on reset
or low-voltage
detection state
Run mode or
sleep mode
state
INITX input
state
Device internal
reset state
Timer mode or stop mode
state
Pin
Power supply
unstable
Power supply
stable
status Function group
type
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
GPIO selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
A
Main crystal
Input enabled
Input enabled
Input enabled Input enabled
Input
Input enabled
oscillator input
pin
enabled
GPIO selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
B
Main crystal
oscillator output
pin
Hi-Z/
Hi-Z/
Hi-Z/
Maintain
previous state
Maintain
previous
Maintain
previous
Internal input fixed Internal input
Internal input
fixed at "0"
state/ Hi-Z at state/ Hi-Z at
oscillation oscillation
at "0"/
fixed at "0"
or Input enable
*1
*1
stop
Internal input Internal input
fixed at "0" fixed at "0"
Pull-up/ Input Pull-up/ Input Pull-up/ Input
/
stop /
INITX input pin
C
Pull-up/
Input
Pull-up/ Input
enabled
Pull-up/ Input
enabled
enabled
enabled
enabled
enabled
Mode input pin
D
Input enabled
Input enabled
Input enabled Input enabled
Input
enabled
Input enabled
JTAG
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
selected
E
GPIO
Setting disabled Setting disabled Setting disabled
Hi-Z/ Internal
input fixed at
"0"
selected
Trace selected Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Trace output
External
interrupt enabled
selected
Maintain
previous state
F
GPIO
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
selected, or
resource other
than above
selected
Input enabled
Input enabled
Internal input
fixed at "0"
Trace selected Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Trace output
Hi-Z/
GPIO selected,
or resource
Hi-Z
Hi-Z/
Hi-Z/
G
Input enabled
Input enabled
Internal input
fixed at "0"
other than above
selected
Document Number: 002-04683 Rev.*C
Page 77 of 132
MB9B110T Series
Power-on reset
or low-voltage
detection state
Run mode or
sleep mode
state
INITX input
state
Device internal
reset state
Timer mode or stop mode
state
Pin
Power supply
unstable
Power supply
stable
status Function group
type
Power supply stable
Power supply stable
INITX=1
-
INITX=0
-
INITX=1
-
INITX=1
-
-
SPL=0
SPL=1
External
interrupt enabled
selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
H
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z/
Internal input
fixed at "0"
GPIO selected,
resource
Hi-Z/
Input enabled
Hi-Z/
Maintain
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
I
Input enabled previous state
selected
NMIX selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
J
Input enabled
Input enabled
Internal input
fixed at "0"
Analog input
selected
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input Internal input Internal input
fixed at "0"/ fixed at "0"/ fixed at "0"/
Analog input Analog input Analog input
enabled
enabled
enabled
K
GPIO selected, Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
or resource
other than above
selected
Internal input
fixed at "0"
External
interrupt enabled
selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
Analog input
selected
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input Internal input Internal input
fixed at "0"/ fixed at "0"/ fixed at "0"/
Analog input Analog input Analog input
L
enabled
enabled
enabled
GPIO selected, Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
or resource
other than above
selected
GPIO selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
M
Sub crystal
oscillator input
pin
Input enabled
Input enabled
Input enabled Input enabled
Input
enabled
Input enabled
Document Number: 002-04683 Rev.*C
Page 78 of 132
MB9B110T Series
Power-on reset
or low-voltage
detection state
Run mode or
sleep mode
state
INITX input
state
Device internal
reset state
Timer mode or stop mode
state
Pin
Power supply
unstable
Power supply
stable
status Function group
type
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
INITX=1
-
SPL=0
SPL=1
GPIO selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Sub crystal
oscillator output
pin
Hi-Z/
Hi-Z/
Hi-Z/
Maintain
previous state
Maintain
previous
Maintain
previous
N
Internal input fixed Internal input
Internal input
fixed at "0"
state/ Hi-Z at state/ Hi-Z at
oscillation oscillation
at "0"/
fixed at "0"
*2
*2
or Input enable
stop
/
stop /
Internal input Internal input
fixed at "0"
fixed at "0"
GPIO selected
Hi-Z
Hi-Z/
Hi-Z/
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Input enabled
Input enabled
O
Mode input pin
GPIO selected
Input
Input enabled
Input enabled Input enabled
Input
Input
enabled
enabled
enabled
P
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
Hi-Z/
Input enabled
state
GPIO selected,
resource
Hi-Z
Hi-Z/
Hi-Z/
Maintain
previous state
Maintain
previous
Hi-Z/
Input enabled
Input enabled
Internal input
fixed at "0"
Q
selected
state
External
interrupt enabled
selected
Setting disabled Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
Maintain
previous
state
state
Hi-Z/
R
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Internal input
fixed at "0"
*1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
Document Number: 002-04683 Rev.*C
Page 79 of 132
MB9B110T Series
12.
Electrical Characteristics
12.1
Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage*1, *2
Analog power supply voltage*1, *3
Analog reference voltage *1, *3
Vcc
Vss - 0.5
Vss + 6.5
Vss + 6.5
V
V
V
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5 V)
Vss + 6.5
AVcc + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
+2
Vss - 0.5
Vss - 0.5
Vss - 0.5
V
V
V
Input voltage*1
VI
5 V tolerant
Analog pin input voltage *1
Output voltage *1
VIA
VO
Vss - 0.5
-2
V
Clamp maximum current
ICLAMP
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*7
Clamp total maximum current
Σ[ICLAMP
]
+20
*7
10
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
20
"L" level maximum output current *4
"L" level average output current *5
IOL
-
-
20
39
4
8
IOLAV
12
18.5
"L" level total maximum output current
"L" level total average output current *6
∑IOL
-
-
100
∑IOLAV
50
- 10
4 mA type
8 mA type
- 20
"H" level maximum output current *4
IOH
-
-
- 20
12 mA type
- 39
P80,P81,P82,P83
4 mA type
- 4
- 8
8 mA type
"H" level average output current *5
IOHAV
- 12
12 mA type
- 20.5
- 100
- 50
P80,P81,P82,P83
"H" level total maximum output current
"H" level total average output current *6
∑IOH
∑IOHAV
PD
-
-
-
Power consumption
1000
+ 150
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
Document Number: 002-04683 Rev.*C
Page 80 of 132
MB9B110T Series
*7:
•
See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin
does not exceed rated values, either instantaneously or for prolonged periods.
•
•
•
•
•
•
•
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may
pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from
the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
N-ch
Limiting
resistor
Digital output
Digital input
+B input (0V to 16V)
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess
of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04683 Rev.*C
Page 81 of 132
MB9B110T Series
12.2
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.7 *2
2.7
Max
Power supply voltage
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
Vcc
AVcc
AVRH
CS
-
-
-
-
5.5
V
V
5.5
AVcc = Vcc
2.7
AVcc
10
V
for built-in regulator *1
1
μF
When
mounted on
four-layer
LQS144,
Operating
LQP176,
LBE192
TA
- 40
+ 85
°C
temperature
PCB
*1: See "0 C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.Always use
semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely
affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04683 Rev.*C
Page 82 of 132
MB9B110T Series
12.3
DC Characteristics
12.3.1
Current Rating
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
CPU: 144 MHz,
Unit
Remarks
name
Typ*3
Max*4
Peripheral: 72 MHz,
Flash 2 Wait,
TraceBuffer: ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
100
180
mA
*1, *5
PLL
RUN mode
CPU: 72 MHz,
Peripheral: 72 MHz,Flash 0
Wait,
TraceBuffer: OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
65
135
mA
*1, *5
RUN
mode
Icc
current
CPU/ Peripheral: 4 MHz[2],
Flash 0 Wait,
High-speed
CR
RUN mode
6
57.8
51.7
mA
mA
*1
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz,
Flash 0 Wait,
VCC
Sub
1.3
*1, *6
RUN mode
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz,
Flash 0 Wait,
Low-speed
CR
RUN mode
1.3
30
51.7
89
mA
mA
mA
mA
mA
*1
*1, *5
*1
FRWTR.RWT = 00,
FSYNDN.SD = 000
PLL
SLEEP
mode
High-speed
CR
SLEEP
mode
Sub
SLEEP
mode
Low-speed
CR
SLEEP
mode
Peripheral: 72 MHz
Peripheral: 4 MHz*2
Peripheral: 32 kHz
Peripheral: 100 kHz
4.5
1.2
1.2
55.9
51.6
51.6
SLEEP mode
current
Iccs
*1, *6
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA = + 25°C, VCC = 5.5 V
*4: TA = + 85°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-04683 Rev.*C
Page 83 of 132
MB9B110T Series
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
TA = + 25°C,
Unit
mA
mA
mA
mA
mA
mA
Remarks
*1, *3
*1, *3
*1, *4
*1, *4
*1
name
Typ*2
Max*2
4
10
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
Main TIMER mode
Sub TIMER mode
STOP mode
-
1.1
-
55
5
TIMER mode
current
ICCT
VCC
50
5
1
When LVD is off
TA = + 85°C,
STOP mode
current
ICCH
-
50
*1
When LVD is off
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
Max
Low-voltage
detection circuit
(LVD) power
At operation
for interrupt
ICCLVD
VCC
4
7
μA
At not detect
supply current
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
12
14
mA
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
Max
At 1unit
operation
0.57
0.72
mA
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.06
1.1
35
1.96
4
μA
mA
μA
At 1unit
operation
AVRH=5.5 V
Reference power
supply current
ICCAVRH
At stop
0.06
Document Number: 002-04683 Rev.*C
Page 84 of 132
MB9B110T Series
12.3.2 Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Typ
Max
CMOS
[1]
-
Vcc × 0.8
-
Vcc + 0.3
V
hysteresis input
pin, MD0, MD1
"H" level input
voltage
VIHS
5 V tolerant
input pin
-
-
Vcc × 0.8
2.0
-
-
Vss + 5.5
Vcc + 0.3
V
V
(hysteresis
input)
TTL Schmitt
input pin
CMOS
[1]
-
Vss - 0.3
-
Vcc × 0.2
V
hysteresis input
pin, MD0, MD1
"L" level input
voltage
VILS
5 V tolerant
input pin
-
-
Vss - 0.3
Vss - 0.3
-
-
Vcc × 0.2
0.8
V
V
(hysteresis
input)
TTL Schmitt
input pin
Vcc ≥ 4.5 V,
IOH = - 4 mA
Vcc < 4.5 V,
IOH = - 2 mA
Vcc ≥ 4.5 V,
IOH = - 8 mA
Vcc < 4.5 V,
IOH = - 4 mA
Vcc ≥ 4.5 V,
IOH = - 12 mA
Vcc < 4.5 V,
IOH = - 8 mA
Vcc ≥ 4.5 V,
IOH = - 20.5 mA
Vcc < 4.5 V,
IOH = - 13.0 mA
[1]
4 mA type
8 mA type
12 mA type
Vcc - 0.5
Vcc - 0.5
Vcc - 0.5
Vcc - 0.4
-
-
-
-
Vcc
Vcc
Vcc
Vcc
V
V
V
V
[1]
"H" level
VOH
output voltage
P80, P81,
P82, P83
[2]
Document Number: 002-04683 Rev.*C
Page 85 of 132
MB9B110T Series
Value
Typ
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Vcc ≥ 4.5 V,
IOL = 4 mA
[1]
4 mA type
Vss
-
-
-
0.4
V
V
V
V
Vcc < 4.5 V,
IOL = 2 mA
Vcc ≥ 4.5 V,
IOL = 8 mA
[1]
8 mA type
Vss
Vss
0.4
0.4
Vcc < 4.5 V,
IOL = 4 mA
"L" level
VOL
output voltage
Vcc ≥ 4.5 V,
IOL = 12 mA
Vcc < 4.5 V,
IOL = 8 mA
12 mA
type
Vcc ≥ 4.5 V,
IOL = 18.5 mA
Vcc < 4.5 V,
IOL = 10.5 mA
P80, P81,
P82, P83
[2]
Vss
- 5
-
-
0.4
+ 5
Input leak
current
IIL
-
-
μA
kΩ
Vcc ≥ 4.5 V
25
30
50
80
100
200
Pull-up
resistance value
RPU
Pull-up pin
Vcc < 4.5 V
Other than
VCC,
VSS,
Input
capacitance
CIN
-
-
5
15
pF
AVCC,
AVSS,
AVRH
Document Number: 002-04683 Rev.*C
Page 86 of 132
MB9B110T Series
12.4
AC Characteristics
12.4.1 Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
4
48
Vcc ≥ 4.5 V
Vcc < 4.5 V
When crystal oscillator is
connected
MHz
4
4
20
48
Input frequency
FCH
Vcc ≥ 4.5 V
Vcc < 4.5 V
MHz
ns
When using external clock
When using external clock
4
20
X0,
X1
20.83
50
250
250
Vcc ≥ 4.5 V
Input clock cycle
tCYLH
Vcc < 4.5 V
PWH/tCYLH,
PWL/tCYLH
Input clock pulse
width
-
45
-
55
5
%
When using external clock
When using external clock
tCF,
tCR
Input clock rise time
and fall time
-
ns
FCM
FCC
FCP0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
144
144
72
MHz
MHz
MHz
MHz
MHz
Master clock
Base clock (HCLK/FCLK)
APB0 bus clock*2
Internal operating
clock[1] frequency
APB1 bus clock*2
APB2 bus clock*2
FCP1
FCP2
72
72
-
-
-
-
-
-
-
-
6.94
13.8
13.8
13.8
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
tCYCC
tCYCP0
tCYCP1
tCYCP2
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Internal operating
clock*1 cycle time
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL
MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this datasheet.
X0
Document Number: 002-04683 Rev.*C
Page 87 of 132
MB9B110T Series
12.4.2 Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
When crystal oscillator is
connected
-
-
-
-
32.768
-
kHz
kHz
μs
Input frequency
Input clock cycle
1/tCYLL
When using external
clock
32
10
-
-
100
X0A,
X1A
When using external
clock
tCYLL
-
31.25
PWH/tCYLL,
PWL/tCYLL
Input clock pulse
width
When using external
clock
45
-
55
%
X0A
12.4.3 Internal CR Oscillation Characteristics
High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
TA = + 25°C
Unit
MHz
μs
Remarks
Min
Typ
Max
3.96
3.84
4
4.04
When trimming*1
TA = 0°C to + 70°C
4
4.16
Clock frequency
FCRH
TA = - 40°C to + 85°C
TA = - 40°C to + 85°C
3.8
3
4
4
4.2
5
When not trimming
*2
Frequency stability
time
tCRWT
-
-
-
90
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
Clock frequency
FCRL
-
50
100
150
kHz
Document Number: 002-04683 Rev.*C
Page 88 of 132
MB9B110T Series
12.4.4 Operating Conditions of Main and USB PLL
Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Min Typ
Parameter
Symbol
Unit
Remarks
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
FPLLI
-
4
13
200
-
-
-
-
-
16
75
MHz
multiple
MHz
PLL macro oscillation clock frequency
FPLLO
FCLKPLL
300
144
Main PLL clock frequency*2
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
FPLLI
-
3.8
50
190
-
4
-
4.2
71
MHz
multiple
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
FCLKPLL
-
-
300
144
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed.
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
Document Number: 002-04683 Rev.*C
Page 89 of 132
MB9B110T Series
12.4.5 Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name Conditions
INITX
Unit
Remarks
Min
Max
Reset input time
tINITX
-
500
-
ns
12.4.6 Power-on Reset Timing
(Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
-
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
*1
Min
Max
Power supply shut down time
tOFF
-
50
-
ms
VCC
Power ramp rate
dV/dt
Vcc:0.2 V to 2.70 V
-
0.9
-
-
1000
0.76
mV/μs *2
Time until releasing Power-on reset
tPRT
0.46
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 5.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6 Low-Voltage Detection Characteristics”
Document Number: 002-04683 Rev.*C
Page 90 of 132
MB9B110T Series
12.4.7 External Bus Timing
External bus clock output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
50*2
32*3
Vcc ≥ 4.5 V
-
MHz
MHz
MCLKOUT*1
Output frequency
tCYCLE
Vcc < 4.5 V
-
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL
MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100 MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64 MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-04683 Rev.*C
Page 91 of 132
MB9B110T Series
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
MOEX
Vcc ≥ 4.5 V
Vcc < 4.5 V
tOEW
MOEX
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min pulse width
-9
+9
MCSX[7:0],
MAD[24:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ → Address
output delay time
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
-12
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MOEX ↑ →Address hold
0
time
MAD[24:0]
MCLK×m-9
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ →MOEX ↓ delay
time
MCLK×m-12
MOEX,
MCSX[7:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
MOEX ↑ →MCSX ↑ time
0
MCLK×m-9
MCSX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ →MDQM ↓
delay time
MDQM[1:0]
MCLK×m-12
20
38
MOEX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
Data set up → MOEX ↑
time
MADATA[15:0]
-
MOEX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MOEX ↑ →Data hold
tDH - OE
0
MCLK×n-3
0
-
-
time
MADATA[15:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
MWEXMin pulse width
tWEW
MWEX
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MWEX ↑ → Address
output delay time
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
MAD[24:0]
MCLK×n-9
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ → MWEX ↓
delay time
MCLK×n-12
MWEX,
MCSX[7:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
MWEX ↑ → MCSX ↑
0
delay time
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ → MDQM ↓
delay time
MDQM[1:0]
MCSX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCSX ↓ → Data output
time
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
MWEX,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MWEX ↑ →Data hold
tWEH - DX
0
time
MADATA[15:0]
Note:
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
−
Document Number: 002-04683 Rev.*C
Page 92 of 132
MB9B110T Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
MAD[24:0]
MOEX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15:0]
tCSL-DV
Document Number: 002-04683 Rev.*C
Page 93 of 132
MB9B110T Series
Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
9
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
Address delay time
tAV
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAD[24:0]
12
9
Vcc ≥ 4.5 V
Vcc < 4.5 V
tCSL
tCSH
tREL
tREH
tDS
1
1
1
1
12
9
MCLK,
MCSX delay time
MOEX delay time
MCSX[7:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
12
9
Vcc ≥ 4.5 V
Vcc < 4.5 V
12
9
MCLK,
MOEX
Vcc ≥ 4.5 V
Vcc < 4.5 V
12
19
37
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
Data set up →MCLK ↑
-
-
time
MADATA[15:0]
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK ↑ → Data hold
tDH
0
time
MADATA[15:0]
9
Vcc ≥ 4.5 V
Vcc < 4.5 V
tWEL
tWEH
tDQML
tDQMH
tOD
1
12
MCLK,
MWEX
MWEX delay time
9
Vcc ≥ 4.5 V
Vcc < 4.5 V
1
12
9
Vcc ≥ 4.5 V
Vcc < 4.5 V
1
12
MCLK,
MDQM[1:0] delay time
MDQM[1:0]
9
12
Vcc ≥ 4.5 V
Vcc < 4.5 V
1
MCLK+1
1
MCLK+18
MCLK+24
18
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK ↑ → Data output
time
MADATA[15:0]
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK ↑ → Data hold
tOD
time
MADATA[15:0]
24
Note:
When the external load capacitance = 30 pF.
−
Document Number: 002-04683 Rev.*C
Page 94 of 132
MB9B110T Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
MAD[24:0]
MOEX
tAV
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
MWEX
tWEL
tDS
tDH
MADATA[15:0]
RD
Invalid
WD
tODS
Document Number: 002-04683 Rev.*C
Page 95 of 132
MB9B110T Series
Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
10
Multiplexed
Vcc ≥ 4.5 V
Vcc < 4.5 V
tALE-CHMADV
0
ns
ns
address delay time
20
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
MCLK×n+10
MCLK×n+20
Multiplexed
Vcc ≥ 4.5 V
Vcc < 4.5 V
tCHMADH
address hold time
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04683 Rev.*C
Page 96 of 132
MB9B110T Series
Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
9
ns
ns
ns
ns
tCHAL
1
12
9
MCLK,
ALE
MALE delay time
tCHAH
1
1
12
Vcc ≥ 4.5 V
MCLK ↑ → Multiplexed
tCHMADV
tOD
ns
ns
Address delay time
MCLK,
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MADATA[15:0]
MCLK ↑ → Multiplexed
tCHMADX
1
tOD
Data output time
Note:
−
When the external load capacitance = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04683 Rev.*C
Page 97 of 132
MB9B110T Series
NAND Flash Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MNREX Min pulse width
tNREW
MNREX
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
38
-
-
MNREX,
MADATA[15:0]
MNREX,
Data setup → MNREX↑time
MNREX↑→ Data hold time
tDS – NRE
tDH – NRE
0
-
MADATA[15:0]
MNALE,
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MNALE↑→ MNWEX delay
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
time
MNWEX
MNALE,
MNALE↓→ MNWEX delay
time
MNWEX
MNCLE,
MNCLE↑→ MNWEX delay
time
MNWEX
MNCLE,
MNWEX↑→ MNCLE delay
0
time
MNWEX
MNWEX Min pulse width
MNWEX
MCLK×n-3
-
-9
+9
MNWEX,
MADATA[15:0]
MNWEX,
MNWEX↓→ Data output
tNWEL – DV
time
-12
+12
MCLK×m+9
MCLK×m+12
MNWEX↑→ Data hold time
tNWEH – DX
0
MADATA[15:0]
Note:
−
When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-04683 Rev.*C
Page 98 of 132
MB9B110T Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-04683 Rev.*C
Page 99 of 132
MB9B110T Series
External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Vcc ≥ 4.5 V
19
MCLK ↑ MRDY input
MCLK,
MRDY
tRDYI
-
ns
setup time
Vcc < 4.5 V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04683 Rev.*C
Page 100 of 132
MB9B110T Series
12.4.8 Base Timer Input Timing
Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tTIWH
Pin name
Conditions
Unit
Remarks
Min
Max
,
TIOAn/TIOBn
Input pulse width
-
2tCYCP
-
ns
tTIWL
(when using as CK, TIN)
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
TIOAn/TIOBn
Conditions
Unit
Remarks
Min
Max
tTRGH
,
Input pulse width
-
2tCYCP
-
ns
tTRGL
(when using as TGIN)
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 101 of 132
MB9B110T Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Vcc ≥ 4.5 V
Pin
name
-
Parameter
Symbol
Conditions
Unit
Min
-
Max
Min
Max
Baud rate
-
-
Mbps
ns
8
-
-
8
-
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVI
tIVSHI
tSHIXI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
-
-
-
-
SCKx,
SINx
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-04683 Rev.*C
Page 102 of 132
MB9B110T Series
tSCYC
VOH
SCK
SOT
SIN
VOL
VOL
tSLOVI
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-04683 Rev.*C
Page 103 of 132
MB9B110T Series
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Vcc ≥ 4.5 V
Pin
name
-
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Baud rate
-
-
Mbps
ns
-
8
-
8
-
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVI
tIVSLI
tSLIXI
- 30
+ 30
- 20
+ 20
ns
ns
ns
Master mode
50
0
-
-
30
0
-
-
SCKx,
SINx
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-04683 Rev.*C
Page 104 of 132
MB9B110T Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-04683 Rev.*C
Page 105 of 132
MB9B110T Series
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Vcc ≥ 4.5 V
Pin
name
-
Parameter
Symbol
Conditions
Unit
Min
-
Max
Min
Max
Baud rate
-
-
Mbps
ns
8
-
-
8
-
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SOT → SCK ↓ delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
ns
ns
ns
tIVSLI
50
0
-
-
-
30
0
-
-
-
Master mode
SCKx,
SINx
tSLIXI
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
tSOVLI
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-04683 Rev.*C
Page 106 of 132
MB9B110T Series
tSCYC
VOH
VOL
VOL
SCK
SOT
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-04683 Rev.*C
Page 107 of 132
MB9B110T Series
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Vcc ≥ 4.5 V
Pin
name
-
Parameter
Symbol
Conditions
Unit
Min
-
Max
Min
Max
Baud rate
-
-
Mbps
ns
8
-
-
8
-
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-04683 Rev.*C
Page 108 of 132
MB9B110T Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
tSLSH
tSHSL
tF
tCYCP + 10
-
ns
ns
ns
ns
tCYCP + 10
-
CL = 30 pF
-
-
5
5
SCK rise time
tR
tR
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
VIL
Document Number: 002-04683 Rev.*C
Page 109 of 132
MB9B110T Series
12.4.10 External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
ADTG
A/D converter trigger input
*1
-
-
-
ns
2tCYCP
FRCKx
ICxx
Free-run timer input clock
Input capture
*1
tINH,
tINL
DTTIxX
-
-
ns
ns
Wave form generator
2tCYCP
Input pulse width
Except Timer
mode,
2tCYCP + 100*1
INTxx,
NMIX
External interrupt
NMI
Stop mode
Timer mode,
Stop mode
500
-
ns
*1: tCYCP indicates the APB bus clock cycle time.About the APB bus number which the A/D converter, Multi-function Timer,
External interrupt are connected to, see "Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 110 of 132
MB9B110T Series
12.4.11 Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Unit
Parameter
Symbol
Conditions
Min
Max
AIN pin "H" width
AIN pin "L" width
tAHL
tALL
-
-
BIN pin "H" width
tBHL
-
BIN pin "L" width
tBLL
-
BIN rise time from AIN pin "H" level
AIN fall time from BIN pin "H" level
BIN fall time from AIN pin "L" level
AIN rise time from BIN pin "L" level
AIN rise time from BIN pin "H" level
BIN fall time from AIN pin "H" level
AIN fall time from BIN pin "L" level
BIN rise time from AIN pin "L" level
ZIN pin "H" width
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
tZHL
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
QCR:CGSC="0"
*1
-
ns
2tCYCP
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rise and fall time from
determined ZIN level
tZABE
tABEZ
QCR:CGSC="1"
QCR:CGSC="1"
Determined ZIN level from AIN/BIN
rise and fall time
*1: tCYCP indicates the APB bus clock cycle time.About the APB bus number which Quadrature Position/Revolution Counter is
connected to, see "Block Diagram" in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-04683 Rev.*C
Page 111 of 132
MB9B110T Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04683 Rev.*C
Page 112 of 132
MB9B110T Series
12.4.12 I2C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Standard-mode
Fast-mode
Min Max
Parameter
Symbol
FSCL
Conditions
Unit Remarks
Min
Max
SCL clock frequency
0
100
0
400
kHz
(Repeated) START condition hold
tHDSTA
4.0
-
0.6
-
μs
time SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
tLOW
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tHIGH
(Repeated) START setup time
SCL ↑ → SDA ↓
tSUSTA
CL = 30 pF,
4.7
-
0.6
-
μs
*1
R = (Vp/IOL
)
3.45*2
-
0.9*3
-
Data hold time SCL ↓ → SDA ↓ ↑
Data setup time SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tHDDAT
tSUDAT
0
0
μs
250
100
ns
tSUSTO
tBUF
4.0
4.7
-
-
0.6
1.3
-
-
μs
μs
Bus free time between "STOP
condition" and "START condition"
*4
*4
*4
*4
*4
*4
[5]
8 MHz ≤ tCYCP ≤ 40 Hz
40 MHz < tCYCP ≤ 60 Hz
60 MHz < tCYCP ≤ 72 Hz
-
-
-
-
-
-
ns
2 tCYCP
3 tCYCP
4 tCYCP
2 tCYCP
3 tCYCP
4 tCYCP
[5]
Noise filter
tSP
ns
[5]
ns
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see "Block Diagram" in
this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.To use Fast-mode, set the APB bus clock at 8
MHz or more.
*5: The number of steps of the noise filter can be changed with register settings.Change the number of the noise filter
steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-04683 Rev.*C
Page 113 of 132
MB9B110T Series
12.4.13 ETM Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
2
9
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
2
15
50
32
-
-
-
MHz
MHz
ns
TRACECLK frequency
1/ tTRACE
TRACECLK
20
TRACECLK
cycle time
tTRACE
31.25
-
ns
Note:
−
When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04683 Rev.*C
Page 114 of 132
MB9B110T Series
12.4.14 JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
TCK,
TMS, TDI
TCK,
TMS, TDI setup time
tJTAGS
15
-
ns
TMS, TDI hold time
tJTAGH
15
-
ns
ns
TMS, TDI
Vcc ≥ 4.5 V
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
Vcc < 4.5 V
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-04683 Rev.*C
Page 115 of 132
MB9B110T Series
12.5
12-bit A/D Converter
Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Unit
Remarks
name
Min
Typ
Max
Resolution
-
-
-
-
-
12
bit
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
-
-
-
-
-
± 4.5
± 2.5
± 15
LSB
LSB
mV
-
AVRH = 2.7 V to 5.5 V
VZT
ANxx
Full-scale transition
voltage
VFST
ANxx
-
-
AVRH ± 15
mV
1.0*1
1.2*1
*2
-
-
-
-
-
-
-
-
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
Conversion time
Sampling time
-
μs
Ts
-
-
ns
ns
*2
Compare clock cycle*3
Tcck
50
-
2000
State transition time to
operation permission
Tstt
CAIN
RAIN
-
-
-
-
-
-
-
-
-
1.0
μs
pF
kΩ
Analog input capacity
12.9
2
3.8
4
AVcc ≥ 4.5 V
Analog input resistance
Interchannel disparity
AVcc < 4.5 V
-
-
-
-
-
-
-
LSB
Analog port input leak
current
ANxx
5
μA
Analog input voltage
Reference voltage
-
-
ANxx
AVSS
2.7
-
-
AVRH
AVCC
V
V
AVRH
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz
sampling time: 300 ns
sampling time: 500 ns
compare time: 700 ns
compare time: 700 ns
AVcc < 4.5 V, HCLK=120 MHz
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL
MANUAL Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-04683 Rev.*C
Page 116 of 132
MB9B110T Series
Comparator
ANxx
Analog input pin
Rext
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistance of A/D = 2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN
:
Input capacity of A/D = 12.9 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-04683 Rev.*C
Page 117 of 132
MB9B110T Series
Definition of 12-bit A/D Converter Terms
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
Resolution:
Integral Nonlinearity:
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Deviation from the ideal value of the input voltage that is required to change the output
code by 1 LSB.
Differential Nonlinearity:
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
[LSB]
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
VNT
:
Document Number: 002-04683 Rev.*C
Page 118 of 132
MB9B110T Series
12.6
Low-Voltage Detection Characteristics
12.6.1
Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Detected voltage
Released voltage
VDL
VDH
-
-
2.25
2.45
2.65
V
V
When voltage drops
2.30
2.50
2.70
When voltage rises
12.6.2
Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.58
2.67
Typ
2.8
2.9
Max
3.02
3.13
Detected voltage
Released voltage
VDL
VDH
V
V
When voltage drops
When voltage rises
SVHI = 0000
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
LVD stabilization wait
time
*1
TLVDW
-
-
-
μs
4032 × tCYCP
*1: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04683 Rev.*C
Page 119 of 132
MB9B110T Series
12.7
Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Unit
Remarks
Typ*1
Max*1
Large Sector
Sector erase
0.7
3.7
s
Includes write time prior to internal erase
time
Small Sector
0.3
12
1.1
384
68
Half word (16-bit)
write time
μs
Not including system-level overhead time.
Includes write time prior to internal erase
Chip erase time
13.6
s
*1: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
12.7.2 Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
20*1
10*1
5*1
1,000
10,000
100,000
*1: At average + 85°C
Document Number: 002-04683 Rev.*C
Page 120 of 132
MB9B110T Series
12.8
Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Max*1
Typ
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
tCYCC
ns
40
80
μs
PLL TIMER mode
Ticnt
Low-speed CR TIMER mode
Sub TIMER mode
STOP mode
453
453
453
737
737
737
μs
μs
μs
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*1)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*1: External interrupt is set to detecting fall edge.
Document Number: 002-04683 Rev.*C
Page 121 of 132
MB9B110T Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*1)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode"
and "Operations of Standby Modes" in FM3 FAMILY PERIPHERAL MANUAL about the return factor from Low-Power
consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 FAMILY PERIPHERAL MANUAL".
Document Number: 002-04683 Rev.*C
Page 122 of 132
MB9B110T Series
12.8.2
Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Max*1
Typ
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
321
461
μs
321
461
μs
PLL TIMER mode
Trcnt
Low-speed CR TIMER mode
Sub TIMER mode
STOP mode
441
441
441
701
701
701
μs
μs
μs
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-04683 Rev.*C
Page 123 of 132
MB9B110T Series
Operation example of return from low power consumption mode (by internal resource reset*1)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
−
−
The return factor is different in each Low-Power consumption modes.See "CHAPTER 6: Low Power Consumption Mode" and
"Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.6 Power-on Reset Timing in 12.4 AC
Characteristics in Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset.
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04683 Rev.*C
Page 124 of 132
MB9B110T Series
13.
Ordering Information
On-chip
On-chip
SRAM
Part number
Flash
Package
Packing
memory
MB9BF116SPMC-GK7E1
MB9BF117SPMC-GK7E1
MB9BF118SPMC-GK7E1
MB9BF116TPMC-GK7E1
MB9BF117TPMC-GK7E1
MB9BF118TPMC-GK7E1
MB9BF116TBGL-GK7E1
MB9BF117TBGL-GK7E1
MB9BF118TBGL-GK7E1
512 Kbyte
768 Kbyte
1 Mbyte
64 Kbyte
96 Kbyte
128 Kbyte
64 Kbyte
96 Kbyte
128 Kbyte
64 Kbyte
96 Kbyte
128 Kbyte
Plastic LQFP 144-pin
(0.5 mm pitch), (LQS144)
512 Kbyte
768 Kbyte
1 Mbyte
Plastic LQFP 176-pin
(0.5 mm pitch), (LQP176)
Tray
512 Kbyte
768 Kbyte
1 Mbyte
Plastic PFBGA 192-pin
(0.8 mm pitch), (LBE192)
Document Number: 002-04683 Rev.*C
Page 125 of 132
MB9B110T Series
14.
Package Dimensions
Package Type
Package Code
LQFP 176
LQP176
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
7
4
3
6
176
45
45
176
1
44
44
1
e
2
A-B
5
7
D
3
0.10
A-B
C
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
A
SEATING
PLANE
A1
A'
0.25
b
L1
10
0.08
C
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17
0.09
0.15
0.27
0.20
0.22
c
D
26.00 BSC
24.00 BSC
0.50 BSC
26.00 BSC
24.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
002-15150 **
Document Number: 002-04683 Rev.*C
Page 126 of 132
MB9B110T Series
Package Type
Package Code
LQFP 144
LQS144
4
4
5
D
D
5
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
144
144
37
37
1
1
36
36
2
A-B
5
D
7
BOTTOM VIEW
e
3
0.10
C
0.20
C
A-B D
b
0.08
C
A-B
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
L
b
L1
10
A'
SECTION A-A'
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
D1
e
22.00 BSC
20.00 BSC
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
002-13015 *A
Document Number: 002-04683 Rev.*C
Page 127 of 132
MB9B110T Series
Package Type
Package Code
FBGA 192
LBE192
A
0.20
2X
C
14
13
12
11
10
9
7
8
7
6
5
4
3
2
1
P
N
M
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
PIN A1
CORNER
B
7
8
192xφ b
0.08
C A B
0.20
2X
C
6
TOP VIEW
BOTTOM VIEW
DETAIL A
C
0.10
C
SIDE VIEW
DETAIL A
NOTES
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
1.45
2. DIMENSIONS AND TOLERANCES METHODS PER ASME Y14.5-2009.
THIS OUTLINE CONFORMS TO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A
D
E
0.25
0.35
12.00 BSC
12.00 BSC
10.40 BSC
10.40 BSC
14
0.45
1
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
D
E
1
6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
1
MD
ME
n
7. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" =0.
14
192
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
b
eD
0.35
0.45
0.55
0.80 BSC
0.80 BSC
0.40 BSC
8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK.
METALLIZED MARK INDENTATION OR OTHER MEANS.
eE
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
SD / SE
PACKAGE OUTLINE, 192 BALL FBGA
12.00X12.00X1.45 MM LBE192 REV**
002-13493 **
Document Number: 002-04683 Rev.*C
Page 128 of 132
MB9B110T Series
15.
Major Changes
Spansion Publication Number: DS706-00016
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
9 to 11
Pin Assignment
Handling Devices
Block Diagram
Added the description of "Note".
Revised the description of "•C pin".
70, 71
Added the description of "•Base Timer".
Corrected the figure.
72
TIOA: input → input/output
TIOB: output → input
Electrical Characteristics
Added the "Smoothing capacitor (CS)".
Added the footnote.
Added "Internal operating clock frequency (FCM): Master
Clock".
82
87
12.2. Recommended Operating Conditions
12.4. AC Characteristics
12.4.1.Main Clock Input Characteristics
12.4.4.1 Operating Conditions of Main PLL
(In the case of using main clock for input of
PLL)
Added "Main PLL clock frequency (FCLKPLL)".
89
12.4.4.2 Operating Conditions of Main PLL
(In the case of using built-in high-speed CR
clock for the input clock of the main PLL)
12.5. 12-bit A/D Converter
12.5.1 Electrical Characteristics for the
A/D Converter
• Added the Symbol.
• Deleted the following Pin name.
"Sampling time"
"Compare clock cycle"
"State transition time to operation permission"
"Analog input capacity"
116
"Analog input resistance"
Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Revision 2.1
-
-
Company name and layout design change
Added the description of Maximum area size
Revision 3.0
Features
External Bus Interface
1
9, 10
Pin Assignment
I/O Circuit Type
Handling Devices
Added SWCLK and SWDIO and SWO
Added the description of I2C to the type of E, F, I,
58 to 64
69
Added about +B input
Added "7.2 Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your
mount board."
Handling Devices
7.3 Crystal oscillator circuit
69
Handling Devices
7.6 C Pin
70
72
73
Changed the description
Block Diagram
Modified the block diagram
Memory Map
10.1 Memory map(1)
Modified the area of "Extarnal Device Area"
Memory Map
10.2 Memory map(2)
74
Added the summary of Flash memory sector and the note
Document Number: 002-04683 Rev.*C
Page 129 of 132
MB9B110T Series
Page
Section
Change Results
Added the Clamp maximum current
Electrical Characteristics
12.1 Absolute Maximum Ratings
80, 81
Added the output current of P80, P81, P82, P83
Added about +B input
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Electrical Characteristics
12.2. Recommended Operation Conditions
82
Added the note about less than the minimum power
supply voltage
Changed the table format
Electrical Characteristics
12.3. DC Characteristics
12.3.1 Current rating
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current
83, 48
Electrical Characteristics
12.4. AC Characteristics
12.4.3 Built to in CR Oscillation Characteristics
88
90
91
Added Frequency stability time at Built to in high to speed CR
Electrical Characteristics
12.4. AC Characteristics
12.4.6 Power to on Reset Timing
Added Time until releasing Power to on reset
Changed the figure of timing
Electrical Characteristics
12.4. AC Characteristics
12.4.7 External Bus Timing
Modified Data output time
Modified from UART Timing to CSIO/UART Timing
Electrical Characteristics
12.4. AC Characteristics
12.4.9 CSIO/UART Timing
Changed from Internal shift clock operation to Master
106-109
mode
Changed from External shift clock operation to Slave
mode
Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full to scale
transition voltage
Electrical Characteristics
12.5. 12bit A/D Converter
116
Added Conversion time at AVcc < 4.5 V
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
Electrical Characteristics
12.8. Return Time from Low to Power
Consumption Mode
123 to
124
Added Return Time from Low to Power Consumption Mode
125
Ordering Information
Change to full part number
Note:
Please see “Document History” about later revised information.
−
Document Number: 002-04683 Rev.*C
Page 130 of 132
MB9B110T Series
Document History
Document Title: MB9B110T Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-04683
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
Migrated to Cypress and assigned document number 002-04683.
No change to document contents or format.
**
-
TOYO
02/10/2015
*A
5200957
TOYO
04/07/2016 Updated to Cypress template
Updated “12.4.6 Power-On Reset Timing”. Changed parameter from “Power Supply
rising time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some
comments (Page 90)
Added Notes for JTAG (Page 57), Changed “J-TAG” to” JTAG” in “4.2 List of Pin
Functions” (Page 37)
Updated Package code and dimensions as follows (Page 7-10, 82, 126-129)
FPT-144P-M08 -> LQS144, FPT-176P-M07 -> LQP176,
BGA-192P-M06 -> LBE192
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 117)
*B
YSKA
03/09/2017
5560212
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 103, 105, 107,
109)
Deleted MPNs below from “13. Ordering Information” (Page 126)
MB9BF116SPMC-GE1, MB9BF116TBGL-GE1, MB9BF116TPMC-GE1,
MB9BF117SPMC-GE1, MB9BF117TBGL-GE1, MB9BF117TPMC-GE1,
MB9BF118SPMC-GE1, MB9BF118TBGL-GE1, MB9BF118TPMC-GE1
Added MPNs below to “13. Ordering Information” (Page 126)
MB9BF116SPMC-GK7E1, MB9BF116TBGL-GK7E1, MB9BF116TPMC-GK7E1,
MB9BF117SPMC-GK7E1, MB9BF117TBGL-GK7E1, MB9BF117TPMC-GK7E1,
MB9BF118SPMC-GK7E1, MB9BF118TBGL-GK7E1, MB9BF118TPMC-GK7E1
*C
YSAT
07/11/2017
5797545
Adapted new Cypress logo
Document Number: 002-04683 Rev.*C
Page 131 of 132
MB9B110T Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Clocks & Buffers
Interface
Internet of Things
Memory
Technical Support
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other
countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of
the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software
provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in
binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s
patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use,
reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY
SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or
use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference
purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product.
Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations,
life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses
where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure
to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do
release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all
claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress
in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04683 Rev.*C
July 11, 2017
Page 132 of 132
相关型号：
MB9BF118TBGL
RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 144MHz, CMOS, PBGA192, 12 X 12 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, FBGA-192
FUJITSU
©2020 ICPDF网 联系我们和版权申明