MB96F612RBPMC-GTE1 [CYPRESS]
F2MC-16FX,16-bit Proprietary Microcontroller;
| 型号： | MB96F612RBPMC-GTE1 |
| 厂家： | 
CYPRESS |
| 描述： | F2MC-16FX,16-bit Proprietary Microcontroller 微控制器 |
| 文件： | 总63页 (文件大小：1234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB96610 Series
F2MC-16FX,16-bit Proprietary
Microcontroller
MB96610 series is based on Cypress advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy
migration of F2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to
the previous generation include significantly improved performance - even at the same operation frequency, reduced
power consumption and faster start-up time.For high processing speed at optimized power consumption an internal
PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator.
The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power
is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. Aflexible clock tree allows selecting
suitable operation frequencies for peripheral resources independent of the CPU speed.
Features
Technology
Low voltage detection function
0.18µm CMOS
Reset is generated when supply voltage falls below
programmable reference voltage
CPU
F2MC-16FX CPU
Code Security
Protects Flash Memory content from unintended read-out
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different
addressing modes, barrel shift, variety of pointers)
DMA
Automatic transfer function independent of CPU, can be
8-byte instruction queue
assigned freely to resources
Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit)
instructions available
Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
System clock
On-chip PLL clock multiplier (1 to 8, 1 when PLL stop)
4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator
depends on Q-factor)
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Up to 8MHz external clock for devices with fast clock input
feature
32.768kHz subsystem quartz clock
Bit rates up to 1Mbps
100kHz/2MHz internal RC clock for quick and safe startup,
32 message objects
clock stop detection function, watchdog
Each message object has its own identifier mask
Clock source selectable from mainclock oscillator, subclock
oscillator and on-chip RC oscillator, independently for CPU
and 2 clock domains of peripherals
Programmable FIFO mode (concatenation of message
objects)
Maskable interrupt
The subclock oscillator is enabled by the Boot ROM
program controlled by a configuration marker after a Power
or External reset
Disabled Automatic Retransmission mode for Time
Triggered CAN applications
Low Power Consumption - 13 operating modes (different
Programmable loop-back mode for self-test operation
Run, Sleep, Timer, Stop modes)
USART
On-chip voltage regulator
Full duplex USARTs (SCI/LIN)
Internal voltage regulator supports a wide MCU supply
Wide range of baud rate settings using a dedicated reload
voltage range (Min=2.7V), offering low power consumption
timer
Special synchronous options for adapting to different
synchronous serial protocols
Cypress Semiconductor Corporation
Document Number: 002-04709 Rev.*C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB96610 Series
LIN functionality working either as master or slave LIN
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral
clock as counter clock or of selected Reload timer
underflow as clock input
device
Extended support for LIN-Protocol to reduce interrupt load
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
A/D converter
SAR-type
8/10-bit resolution
Quadrature Position/Revolution Counter (QPRC)
Signals interrupt on conversion end, single conversion
mode, continuous conversion mode,
Up/down count mode, Phase difference count mode, Count
stop conversion mode, activation by software, external
mode with direction
trigger, reload timers and PPGs
16-bit position counter
Range Comparator Function
16-bit revolution counter
Two 16-bit compare registers with interrupt
Source Clock Timers
Detection edge of the three external event input pins AIN,
Three independent clock timers (23-bit RC clock timer, 23-
BIN and ZIN is configurable
bit Main clock timer, 17-bit Sub clock timer)
Real Time Clock
Hardware Watchdog Timer
Operational on main oscillation (4MHz), sub oscillation
Hardware watchdog timer is active after reset
(32kHz) or RC oscillation (100kHz/2MHz)
Window function of Watchdog Timer is used to select the
Capable to correct oscillation deviation of Sub clock or RC
lower window limit of the watchdog interval
oscillator clock (clock calibration)
Reload Timers
Read/write accessible second/minute/hour registers
Can signal interrupts every half
16-bit wide
second/second/minute/hour/day
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral
Internal clock divider and prescaler provide exact 1s clock
clock frequency
Event count function
External Interrupts
Free-Running Timers
Edge or Level sensitive
Interrupt mask bit per channel
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4)
Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28
Each available CAN channel RX has an external interrupt
for wake-up
of peripheral clock frequency
Selected USART channels SIN have an external interrupt
for wake-up
Input Capture Units
Non Maskable Interrupt
16-bit wide
Disabled after reset, can be enabled by Boot-ROM
Signals an interrupt upon external event
depending on ROM configuration block
Rising edge, Falling edge or Both (rising & falling) edges
Once enabled, can not be disabled other than by reset
High or Low level sensitive
sensitive
Output Compare Units
Pin shared with external interrupt 0
16-bit wide
I/O Ports
Signals an interrupt when a match with Free-running Timer
occurs
Most of the external pins can be used as general purpose
A pair of compare registers can be used to generate an
I/O
output signal
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
Programmable Pulse Generator
16-bit down counter, cycle and duty setting registers
Can be used as 2 ×8-bit PPG
One input level per GPIO-pin (either Automotive or CMOS
hysteresis)
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Bit-wise programmable pull-up resistor
Document Number: 002-04709 Rev.*C
Page 2 of 63
MB96610 Series
Built-in On Chip Debugger (OCD)
One-wire debug tool interface
Break function:
Flash Memory
Dual operation flash allowing reading of one Flash bank
while programming or erasing the other bank
Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory
Hardware break: 6 points (shared with code event)
Software break: 4096 points
Event function
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the automatic algorithm
Erase can be performed on each sector individually
Sector protection
Code event: 6 points (shared with hardware break)
Data event: 6 points
Event sequencer: 2 levels + reset
Execution time measurement function
Trace function: 42 branches
Security function
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase or write
Document Number: 002-04709 Rev.*C
Page 3 of 63
MB96610 Series
Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
Product Lineup.................................................................................................................................................... 6
Block Diagram..................................................................................................................................................... 7
Pin Assignment................................................................................................................................................... 8
Pin Description.................................................................................................................................................... 9
Pin Circuit Type................................................................................................................................................. 11
I/O Circuit Type.................................................................................................................................................. 13
Memory Map ...................................................................................................................................................... 18
RAMstart Addresses......................................................................................................................................... 19
User ROM Memory Map for Flash Devices ..................................................................................................... 20
10. Serial Programming Communication Interface .............................................................................................. 21
11. Interrupt Vector Table....................................................................................................................................... 22
12. Handling Precautions ....................................................................................................................................... 26
12.1 Precautions for Product Design........................................................................................................................ 26
12.2 Precautions for Package Mounting................................................................................................................... 27
12.3 Precautions for Use Environment..................................................................................................................... 29
13. Handling Devices .............................................................................................................................................. 30
13.1 Latch-up prevention.......................................................................................................................................... 30
13.2 Unused pins handling....................................................................................................................................... 30
13.3 External clock usage ........................................................................................................................................ 30
13.3.1 Single phase external clock for Main oscillator.................................................................................................. 30
13.3.2 Single phase external clock for Sub oscillator................................................................................................... 31
13.3.3 Opposite phase external clock .......................................................................................................................... 31
13.4 Notes on PLL clock mode operation................................................................................................................. 31
13.5 Power supply pins (Vcc/Vss)............................................................................................................................ 31
13.6 Crystal oscillator and ceramic resonator circuit ................................................................................................ 31
13.7 Turn on sequence of power supply to A/D converter and analog inputs........................................................... 32
13.8 Pin handling when not using the A/D converter................................................................................................ 32
13.9 Notes on Power-on........................................................................................................................................... 32
13.10 Stabilization of power supply voltage................................................................................................................ 32
13.11 Serial communication ....................................................................................................................................... 32
13.12 Mode Pin (MD) ................................................................................................................................................. 32
14. Electrical Characteristics ................................................................................................................................. 33
14.1 Absolute Maximum Ratings.............................................................................................................................. 33
14.2 Recommended Operating Conditions............................................................................................................... 35
14.3 DC Characteristics............................................................................................................................................ 36
14.3.1Current Rating................................................................................................................................................... 36
14.3.2 Pin Characteristics ............................................................................................................................................ 39
14.4 AC Characteristics............................................................................................................................................ 40
14.4.1 Main Clock Input Characteristics....................................................................................................................... 40
14.4.2 Sub Clock Input Characteristics ........................................................................................................................ 41
14.4.3 Built-in RC Oscillation Characteristics............................................................................................................... 42
14.4.4 Internal Clock Timing ........................................................................................................................................ 42
14.4.5 Operating Conditions of PLL............................................................................................................................. 43
14.4.6 Reset Input........................................................................................................................................................ 43
14.4.7 Power-on Reset Timing..................................................................................................................................... 44
14.4.8 USART Timing .................................................................................................................................................. 45
14.4.9 External Input Timing ........................................................................................................................................ 47
14.5 A/D Converter................................................................................................................................................... 48
14.5.1 Electrical Characteristics for the A/D Converter................................................................................................ 48
Document Number: 002-04709 Rev.*C
Page 4 of 63
MB96610 Series
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time.............................................................................. 49
14.5.3 Definition of A/D Converter Terms .................................................................................................................... 49
14.6 Low Voltage Detection Function Characteristics .............................................................................................. 52
14.7 Flash Memory Write/Erase Characteristics ...................................................................................................... 54
15. Example Characteristics................................................................................................................................... 55
16. Ordering Information ........................................................................................................................................ 58
17. Package Dimension .......................................................................................................................................... 59
18. Major Changes .................................................................................................................................................. 60
Document History...................................................................................................................................................... 62
Document Number: 002-04709 Rev.*C
Page 5 of 63
MB96610 Series
1. Product Lineup
Features
MB96610
Remark
Product Type
Flash Memory Product
Subclock
Subclock can be set by software
Dual Operation Flash Memory
32.5KB + 32KB
64.5KB + 32KB
128.5KB + 32KB
RAM
4KB
10KB
10KB
-
MB96F612R, MB96F612A
MB96F613R, MB96F613A
MB96F615R, MB96F615A
Product Options
R: MCU with CAN
A: MCU without CAN
LQFP-48
LQA048
2ch
Package
DMA
3ch
LIN-USART 2/7/8
LIN-USART 2
USART
with automatic LIN-Header
transmission/reception
Yes (only 1ch)
with 16 byte RX- and
TX-FIFO
No
AN 0/1/3/4/6 to 10/
8/10-bit A/D Converter
16ch
12/14/16/24/25/30/31
with Data Buffer
No
with Range Comparator
with Scan Disable
Yes
No
with ADC Pulse Detection
No
16-bit Reload Timer (RLT)
3ch
RLT 1/3/6
FRT 0 to 3
16-bit Free-Running Timer (FRT)
4ch
FRT 0 to 3 does not have external clock
input pin
7ch
ICU 0/1/4 to 6/9/10
16-bit Input Capture Unit (ICU)
(3 channels for LIN-USART)
(ICU 6/9/10 for LIN-USART)
OCU 0/1/4/6/7
5ch
16-bit Output Compare Unit (OCU)
(OCU 4 for FRT clear)
PPG 0/1/3/4/6/7/12/14
8/16-bit Programmable Pulse Generator (PPG)
with Timing point capture
with Start delay
8ch (16-bit) / 16ch (8-bit)
Yes
No
with Ramp
No
Quadrature Position/Revolution Counter
(QPRC)
2ch
QPRC 0/1
CAN 2
CAN Interface
1ch
32 Message Buffers
External Interrupts (INT)
Non-Maskable Interrupt (NMI)
Real Time Clock (RTC)
11ch
INT 0/2/3/4/7 to 13
1ch
1ch
35 (Dual clock mode)
I/O Ports
37 (Single clock mode)
Clock Calibration Unit (CAL)
Clock Output Function
1ch
2ch
Low voltage detection function can be
disabled by software
Low Voltage Detection Function
Yes
Yes
Yes
Yes
Hardware Watchdog Timer
On-chip RC-oscillator
On-chip Debugger
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the general I/O port according to your function use.
Document Number: 002-04709 Rev.*C
Page 6 of 63
MB96610 Series
2. Block Diagram
CKOT0_R, CKOT1, CKOT1_R
CKOTX1
X0, X1
X0A, X1A
RSTX
DEBUG I/F
OCD
NMI
MD
Clock &
Mode Controller
Interrupt
Controller
Flash
Memory A
16FX
CPU
16FX Core Bus (CLKB)
Voltage
Regulator
Peripheral
Bus Bridge
DMA
Controller
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
AVcc
AVss
Vcc
Vss
C
AVRH
AN0, AN1, AN3, AN4
AN6 to AN10
8/10-bit ADC
16ch
RX2
TX2
CAN Interface
1ch
AN12, AN14, AN16
AN24, AN25
AN30, AN31
ADTG_R
SIN2, SIN2_R, SIN7_R, SIN8_R
SOT2, SOT2_R, SOT7_R, SOT8_R
SCK2, SCK2_R, SCK7_R, SCK8_R
USART
3ch
16-bit
Reload Timer
1/3/6
TIN1
TOT1, TOT3
3ch
TTG0, TTG1, TTG4, TTG5
TTG12, TTG13
PPG0, PPG1, PPG3, PPG4
PPG6, PPG7, PPG12, PPG14
PPG0_B, PPG1_B, PPG3_B, PPG4_B
PPG6_B, PPG7_B, PPG12_B, PPG14_B
PPG
8ch (16-bit) /
16ch (8-bit)
I/O Timer 0
FRT 0
ICU 0/1
IN0, IN1
OUT0_R, OUT1_R
OCU 0/1
I/O Timer 1
FRT 1
Real Time
Clock
IN4, IN5
ICU 4/5/6
OCU 4/6/7
OUT6, OUT7
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
QPRC
2ch
I/O Timer 2
FRT 2
ICU 9
INT0, INT8 to INT13
INT2_R, INT4_R
External
Interrupt
11ch
I/O Timer 3
FRT 3
ICU 10
INT7_R, INT10_R
INT3_R1
Document Number: 002-04709 Rev.*C
Page 7 of 63
MB96610 Series
3. Pin Assignment
(Top view)
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
P01_0 / TIN1 / CKOT1 / OUT0_R
Vcc
C
23
22
21
20
19
18
17
16
15
14
13
P00_3 / INT11 / SCK8_R / PPG3_B*1
P00_5 / INT13 / SIN8_R / PPG14_B*1
P00_4 / INT12 / SOT8_R / PPG12_B
P00_2 / INT10 / SIN7_R*1
P00_1 / INT9 / SOT7_R / PPG1_B
P00_0 / INT8 / SCK7_R / PPG0_B*1
DEBUG I/F
P02_5 / BIN0 / IN1 / TTG1 / ADTG_R
P03_0 / AIN1 / IN4 / TTG4 / TTG12 / AN24
P03_1 / BIN1 / IN5 / TTG5 / TTG13 / AN25
P03_2 / INT10_R / RX2*1
P03_3 / TX2
LQFP - 48
P03_6 / ZIN1 / OUT6 / AN30
P03_7 / OUT7 / AN31
P17_0
P06_0 / AN0 / PPG0
MD
P06_1 / AN1 / PPG1
P04_1 / X1A*2
P04_0 / X0A*2
AVcc
1
2
3
4
5
6
7
8
9
10 11 12
(LQA048)
*1: CMOS input level only
*2: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
Document Number: 002-04709 Rev.*C
Page 8 of 63
MB96610 Series
4. Pin Description
Pin name
Feature
Description
ADTG_R
AINn
ADC
Relocated A/D converter trigger input pin
QPRC
ADC
Quadrature Position/Revolution Counter Unit n input pin
A/D converter channel n input pin
Analog circuits power supply pin
ANn
AVcc
Supply
ADC
AVRH
AVss
A/D converter high reference voltage input pin
Analog circuits power supply pin
Supply
QPRC
BINn
Quadrature Position/Revolution Counter Unit n input pin
Internally regulated power supply stabilization capacitor pin
Clock Output function n output pin
Relocated Clock Output function n output pin
Clock Output function n inverted output pin
On Chip Debugger input/output pin
Input Capture Unit n input pin
C
Voltage regulator
Clock Output function
Clock Output function
Clock Output function
OCD
CKOTn
CKOTn_R
CKOTXn
DEBUG I/F
INn
ICU
INTn
External Interrupt
External Interrupt
External Interrupt
Core
External Interrupt n input pin
INTn_R
INTn_R1
MD
Relocated External Interrupt n input pin
Relocated External Interrupt n input pin
Input pin for specifying the operating mode
Non-Maskable Interrupt input pin
NMI
External Interrupt
OCU
OUTn
OUTn_R
Pnn_m
PPGn
PPGn_B
RSTX
RXn
Output Compare Unit n waveform output pin
Relocated Output Compare Unit n waveform output pin
General purpose I/O pin
OCU
GPIO
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
Programmable Pulse Generator n output pin (16bit/8bit)
Reset input pin
PPG
Core
CAN
CAN interface n RX input pin
SCKn
SCKn_R
SINn
USART
USART n serial clock input/output pin
Relocated USART n serial clock input/output pin
USART n serial data input pin
USART
USART
SINn_R
SOTn
SOTn_R
TINn
USART
Relocated USART n serial data input pin
USART n serial data output pin
USART
USART
Relocated USART n serial data output pin
Reload Timer n event input pin
Reload Timer
Reload Timer
PPG
TOTn
TTGn
TXn
Reload Timer n output pin
Programmable Pulse Generator n trigger input pin
CAN interface n TX output pin
CAN
Supply
Power supply pin
Vcc
Supply
Power supply pin
Vss
X0
Clock
Oscillator input pin
X0A
Clock
Subclock Oscillator input pin
X1
Clock
Oscillator output pin
X1A
Clock
Subclock Oscillator output pin
Document Number: 002-04709 Rev.*C
Page 9 of 63
MB96610 Series
Pin name
Feature
Description
Quadrature Position/Revolution Counter Unit n input pin
ZINn
QPRC
Document Number: 002-04709 Rev.*C
Page 10 of 63
MB96610 Series
5. Pin Circuit Type
Pin no.
1
I/O circuit type*
Pin name
AVss
Supply
G
K
2
AVRH
3
P06_3 / AN3 / PPG3
P06_4 / AN4 / PPG4
4
K
5
K
P06_6 / AN6 / PPG6
6
K
P06_7 / AN7 / PPG7
7
I
P05_0 / AN8 / SIN2 / INT3_R1
P05_1 / AN9 / SOT2
8
K
9
I
P05_2 / AN10 / SCK2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
K
P05_4 / AN12 / TOT3 / INT2_R
P05_6 / AN14 / INT4_R
P07_0 / AN16 / INT0 / NMI
P04_0 / X0A
K
K
B
B
P04_1 / X1A
C
H
O
M
H
M
H
M
M
H
H
H
M
H
M
H
H
H
MD
P17_0
DEBUG I/F
P00_0 / INT8 / SCK7_R / PPG0_B
P00_1 / INT9 / SOT7_R / PPG1_B
P00_2 / INT10 / SIN7_R
P00_4 / INT12 / SOT8_R / PPG12_B
P00_5 / INT13 / SIN8_R / PPG14_B
P00_3 / INT11 / SCK8_R / PPG3_B
P01_0 / TIN1 / CKOT1 / OUT0_R
P01_1 / TOT1 / CKOTX1 / OUT1_R
P01_4 / PPG4_B
P01_5 / SIN2_R / INT7_R
P01_6 / SOT2_R / PPG6_B
P01_7 / SCK2_R / PPG7_B
P02_0 / PPG12 / CKOT1_R
P02_2 / ZIN0 / PPG14 / CKOT0_R
P02_4 / AIN0 / IN0 / TTG0
Document Number: 002-04709 Rev.*C
Page 11 of 63
MB96610 Series
Pin no.
33
I/O circuit type*
Pin name
RSTX
X1
C
34
A
35
A
X0
36
Supply
Vss
37
Supply
Vcc
38
F
C
39
H
P02_5 / BIN0 / IN1 / TTG1 / ADTG_R
P03_0 / AIN1 / IN4 / TTG4 / TTG12 / AN24
P03_1 / BIN1 / IN5 / TTG5 / TTG13 / AN25
P03_2 / INT10_R / RX2
P03_3 / TX2
40
K
41
K
42
M
43
H
44
K
P03_6 / ZIN1 / OUT6 / AN30
P03_7 / OUT7 / AN31
45
K
K
46
P06_0 / AN0 / PPG0
47
K
P06_1 / AN1 / PPG1
48
Supply
AVcc
*: See I/O Circuit Type” for details on the I/O circuit types.
Document Number: 002-04709 Rev.*C
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MB96610 Series
6. I/O Circuit Type
Type
Circuit
Remarks
A
High-speed oscillation circuit:
X1
Programmable between
oscillation mode (external crystal
or resonator connected to X0/X1
pins) and Fast external Clock
Input (FCI) mode (external clock
connected to X0 pin)
R
Feedback resistor = approx.
0
1
1.0MΩ
X out
The amplitude: 1.8V±0.15V
to operate by the internal supply
voltage
FCI
X0
FCI or Osc disable
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MB96610 Series
Type
Circuit
Remarks
B
Low-speed oscillation circuit shared
with GPIO functionality:
Pull-up control
Pout
Feedback resistor = approx.
5.0MΩ
P-ch
P-ch
N-ch
GPIO functionality selectable
(CMOS level output (IOL = 4mA,
IOH = -4mA), Automotive input with
input shutdown function and
programmable pull-up resistor)
Nout
Standby
control
for input
shutdown
R
Automotive input
X1A
R
X out
0
1
FCI
X0A
FCI or Osc disable
Pull-up control
P-ch
P-ch
N-ch
Pout
Nout
Standby
control
for input
shutdown
R
Automotive input
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Page 14 of 63
MB96610 Series
Type
Circuit
Remarks
C
CMOS hysteresis input pin
F
Power supply input protection circuit
P-ch
N-ch
G
A/D converter ref+ (AVRH) power
supply input pin with protection
circuit
P-ch
N-ch
Without protection circuit against
VCC for pins AVRH
H
CMOS level output
(IOL = 4mA, IOH = -4mA)
Pull-up control
Pout
Automotive input with input
shutdown function
Programmable pull-up resistor
P-ch
P-ch
N-ch
Nout
R
Standby control
for input shutdown
Automotive input
Document Number: 002-04709 Rev.*C
Page 15 of 63
MB96610 Series
Type
Circuit
Remarks
I
CMOS level output
(IOL = 4mA, IOH = -4mA)
Pull-up control
Pout
CMOS hysteresis input with input
shutdown function
Programmable pull-up resistor
Analog input
P-ch
P-ch
N-ch
Nout
R
Hysteresis input
Standby control
for input shutdown
Analog input
K
CMOS level output
Pull-up control
Pout
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
P-ch
P-ch
Programmable pull-up resistor
Analog input
N-ch
Nout
R
Automotive input
Standby control
for input shutdown
Analog input
M
CMOS level output
(IOL = 4mA, IOH = -4mA)
Pull-up control
Pout
CMOS hysteresis input with input
shutdown function
Programmable pull-up resistor
P-ch
P-ch
N-ch
Nout
R
Hysteresis input
Standby control
for input shutdown
Document Number: 002-04709 Rev.*C
Page 16 of 63
MB96610 Series
Type
Circuit
Remarks
Open-drain I/O
O
Output 25mA, Vcc = 2.7V
TTL input
N-ch
Nout
R
Standby control
for input shutdown
TTL input
Document Number: 002-04709 Rev.*C
Page 17 of 63
MB96610 Series
7. Memory Map
FF:FFFFH
USER ROM*1
Reserved
DE:0000H
DD:FFFFH
10:0000H
0F:C000H
Boot-ROM
Peripheral
0E:9000H
Reserved
01:0000H
00:8000H
ROM/RAM
MIRROR
Internal RAM
bank0
RAMSTART0*2
Reserved
00:0C00H
Peripheral
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
GPR*3
DMA
Reserved
Peripheral
*1: For details about USER ROM area, see “
User ROM Memory Map for Flash Devices” on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04709 Rev.*C
Page 18 of 63
MB96610 Series
8. RAMstart Addresses
Bank 0
Devices
RAMSTART0
RAM size
MB96F612
4KB
00:7200H
00:5A00H
MB96F613, MB96F615
10KB
Document Number: 002-04709 Rev.*C
Page 19 of 63
MB96610 Series
9. User ROM Memory Map for Flash Devices
MB96F612
MB96F613
MB96F615
CPU mode
address
FF:FFFFH
FF:8000H
FF:7FFFH
FF:0000H
FE:FFFFH
Flash memory
mode address
3F:FFFFH
Flash size
32.5KB + 32KB
Flash size
64.5KB + 32KB
Flash size
128.5KB + 32KB
SA39 - 32KB
3F:8000H
SA39 - 64KB
SA39 - 64KB
SA38 - 64KB
3F:7FFFH
3F:0000H
Bank A of Flash A
3E:FFFFH
FE:0000H
FD:FFFFH
3E:0000H
Reserved
Reserved
Reserved
DF:A000H
DF:9FFFH
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
DE:0000H
1F:9FFFH
1F:8000H
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA4 - 8KB
SA3 - 8KB
SA2 - 8KB
SA1 - 8KB
SAS - 512B*
Reserved
SA4 - 8KB
SA3 - 8KB
SA2 - 8KB
SA1 - 8KB
SAS - 512B*
Reserved
SA4 - 8KB
SA3 - 8KB
SA2 - 8KB
SA1 - 8KB
SAS - 512B*
Reserved
Bank B of Flash A
Bank A of Flash A
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
SAS can not be used for E2PROM emulation.
Document Number: 002-04709 Rev.*C
Page 20 of 63
MB96610 Series
10.Serial Programming Communication Interface
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96610
Pin Number
USART Number
Normal Function
SIN2
7
8
USART2
SOT2
9
SCK2
20
19
18
22
21
23
SIN7_R
SOT7_R
SCK7_R
SIN8_R
SOT8_R
SCK8_R
USART7
USART8
Document Number: 002-04709 Rev.*C
Page 21 of 63
MB96610 Series
11.Interrupt Vector Table
Index in
ICR to
Vector
Offset in
Cleared by
DMA
Vector name
CALLV0
Description
number
vector table
program
0
1
2
3
4
5
6
7
8
9
3FCH
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
-
CALLV instruction
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
370H
36CH
368H
364H
360H
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
INT9
-
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
CALLV instruction
Reset vector
-
-
-
-
-
-
-
-
INT9 instruction
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
EXCEPTION
NMI
-
Undefined instruction execution
Non-Maskable Interrupt
Delayed Interrupt
RC Clock Timer
-
DLY
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
RC_TIMER
MC_TIMER
SC_TIMER
LVDI
Main Clock Timer
Sub Clock Timer
Low Voltage Detector
External Interrupt 0
Reserved
EXTINT0
-
Yes
-
EXTINT2
EXTINT3
EXTINT4
-
Yes
Yes
Yes
-
External Interrupt 2
External Interrupt 3
External Interrupt 4
Reserved
-
-
Reserved
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
CAN2
No
-
CAN Controller 2
Reserved
-
-
-
Reserved
PPG0
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
PPG1
Document Number: 002-04709 Rev.*C
Page 22 of 63
MB96610 Series
Index in
ICR to
Vector
Offset in
Cleared by
DMA
Vector name
Description
number
vector table
program
40
35CH
-
-
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Reserved
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
2BCH
PPG3
Yes
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Reserved
PPG4
Yes
-
-
PPG6
Yes
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Reserved
PPG7
Yes
-
-
-
-
Reserved
-
-
Reserved
-
-
Reserved
PPG12
Yes
Programmable Pulse Generator 12
Reserved
-
-
PPG14
Yes
Programmable Pulse Generator 14
Reserved
-
-
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
RLT1
Yes
-
Reload Timer 1
Reserved
-
RLT3
Yes
-
Reload Timer 3
Reserved
-
-
-
Reserved
RLT6
Yes
Yes
Yes
-
Reload Timer 6
Input Capture Unit 0
Input Capture Unit 1
Reserved
ICU0
ICU1
-
-
-
Reserved
ICU4
Yes
Yes
Yes
-
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Reserved
ICU5
ICU6
-
-
-
Reserved
ICU9
Yes
Yes
-
Input Capture Unit 9
Input Capture Unit 10
Reserved
ICU10
-
OCU0
Yes
Yes
-
Output Compare Unit 0
Output Compare Unit 1
Reserved
OCU1
-
-
-
Reserved
Document Number: 002-04709 Rev.*C
Page 23 of 63
MB96610 Series
Index in
ICR to
Vector
Offset in
Cleared by
DMA
Vector name
OCU4
Description
number
vector table
program
81
2B8H
Yes
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Output Compare Unit 4
82
2B4H
2B0H
2ACH
2A8H
2A4H
2A0H
29CH
298H
294H
290H
28CH
288H
284H
280H
27CH
278H
274H
270H
26CH
268H
264H
260H
25CH
258H
254H
250H
24CH
248H
244H
240H
23CH
238H
234H
230H
22CH
228H
224H
220H
21CH
218H
-
-
Reserved
83
OCU6
Yes
Output Compare Unit 6
Output Compare Unit 7
Reserved
84
OCU7
Yes
85
-
-
86
-
-
Reserved
87
-
-
Reserved
88
-
-
Reserved
89
FRT0
Yes
Free-Running Timer 0
Free-Running Timer 1
Free-Running Timer 2
Free-Running Timer 3
Real Time Clock
Clock Calibration Unit
Reserved
90
FRT1
Yes
91
FRT2
Yes
92
FRT3
Yes
93
RTC0
No
94
CAL0
No
95
-
-
96
-
-
Reserved
97
-
-
Reserved
98
ADC0
Yes
A/D Converter 0
Reserved
99
-
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
-
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
LINR2
Yes
LIN USART 2 RX
LIN USART 2 TX
Reserved
LINT2
Yes
-
-
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Reserved
LINR7
Yes
Yes
Yes
Yes
-
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
Reserved
LINT7
LINR8
LINT8
-
-
-
-
Reserved
-
Reserved
Document Number: 002-04709 Rev.*C
Page 24 of 63
MB96610 Series
Index in
ICR to
Vector
Offset in
Cleared by
DMA
Vector name
Description
number
vector table
program
122
214H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
122
Reserved
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
210H
20CH
208H
204H
200H
1FCH
1F8H
1F4H
1F0H
1ECH
1E8H
1E4H
1E0H
1DCH
1D8H
1D4H
1D0H
1CCH
1C8H
1C4H
1C0H
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FLASHA
Yes
Flash memory A interrupt
Reserved
-
-
-
-
Reserved
-
-
Reserved
QPRC0
Yes
Quad Position/Revolution counter 0
Quad Position/Revolution counter 1
A/D Converter 0 - Range Comparator
Reserved
QPRC1
Yes
ADCRC0
No
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Document Number: 002-04709 Rev.*C
Page 25 of 63
MB96610 Series
12.Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
12.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and
in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design
stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such
conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
Document Number: 002-04709 Rev.*C
Page 26 of 63
MB96610 Series
CAUTION:
The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from
high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
12.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Document Number: 002-04709 Rev.*C
Page 27 of 63
MB96610 Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION:
When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be
reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styro foam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-04709 Rev.*C
Page 28 of 63
MB96610 Series
12.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated,
consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use
devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
5. Smoke, Flame
CAUTION:
Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke
or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04709 Rev.*C
Page 29 of 63
MB96610 Series
13.Handling Devices
Special care is required for the following when handling the device:
Latch-up prevention
Unused pins handling
External clock usage
Notes on PLL clock mode operation
Power supply pins (Vcc/Vss)
Crystal oscillator and ceramic resonator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on Power-on
Stabilization of power supply voltage
Serial communication
Mode Pin (MD)
13.1 Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
13.2 Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more
than 2k.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
13.3 External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See
Document Number: 002-04709 Rev.*C
Page 30 of 63
MB96610 Series
AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:
13.3.1 Single phase external clock for Main oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
X0
X1
13.3.2 Single phase external clock for Sub oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and X0A/P04_0 pin must
be driven. X1A/P04_1 pin can be configured as GPIO.
13.3.3 Opposite phase external clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
X0
X1
13.4 Notes on PLL clock mode operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
13.5 Power supply pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc and
Vss pins as close as possible to Vcc and Vss pins.
13.6 Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially
when using low-Q resonators at higher frequencies.
Document Number: 002-04709 Rev.*C
Page 31 of 63
MB96610 Series
13.7 Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning the digital power supply
(VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must
not exceed AVCC Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital
power supplies simultaneously on or off is acceptable)
13.8 Pin handling when not using the A/D converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC AVSS = AVRH =
VSS
.
13.9 Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower
than 50s from 0.2V to 2.7V.
13.10Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction may
occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be
stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within
10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation
for power supply switching.
13.11Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13.12Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection.
Document Number: 002-04709 Rev.*C
Page 32 of 63
MB96610 Series
14.Electrical Characteristics
14.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
VCC
Condition
Unit
Remarks
Min
Max
Power supply voltage[1]
-
-
VSS - 0.3
VSS + 6.0
V
Analog power supply
voltage[1]
[2]
AVCC
VSS - 0.3
VSS - 0.3
VSS + 6.0
V
V
VCC = AVCC
Analog reference
voltage[1]
AVCC ≥ AVRH,
AVRH ≥ AVSS
AVRH
-
VSS + 6.0
Input voltage[1]
Output voltage[1]
VI
-
-
VSS - 0.3
VSS - 0.3
VSS + 6.0
VSS + 6.0
V
V
VI ≤ VCC + 0.3V[3]
VO ≤ VCC + 0.3V[3]
VO
Maximum Clamp
Current
Applicable to general
purpose I/O pins [4]
ICLAMP
Σ|ICLAMP
IOL
-
-
-
-
-
-
-
-
-
-
-4.0
+4.0
13
15
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total Maximum Clamp
Current
Applicable to general
purpose I/O pins [4]
|
-
-
-
-
-
-
-
-
"L" level maximum
output current
"L" level average output
current
IOLAV
ΣIOL
ΣIOLAV
IOH
"L" level maximum
overall output current
32
16
-15
-4
"L" level average
overall output current
"H" level maximum
output current
"H" level average
output current
IOHAV
"H" level maximum
overall output current
-32
ΣIOH
"H" level average
overall output current
Power consumption[5]
-
-16
mA
mW
°C
ΣIOHAV
PD
TA= +125°C
-
284[6]
+125[7]
+150
Operating ambient
temperature
TA
-
-
-40
-55
Storage temperature
TSTG
°C
[1]: This parameter is based on VSS = AVSS = 0V.
[2]: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog
inputs does not exceed AVCC when the power is switched on.
[3]: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output
voltages of standard ports depend on VCC
.
[4]:
Applicable to all general purpose I/O pins (Pnn_m).
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Document Number: 002-04709 Rev.*C
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MB96610 Series
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided
from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply
voltage may not be sufficient to operate the Power reset.
The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current
(4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to
maximum 6.0V.
Sample recommended circuits:
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
[5]: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal
conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL IOL + VOH IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation
mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC
.
[6]: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
[7]: Write/erase to a large sector in flash memory is warranted with TA ≤ + 105°C.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04709 Rev.*C
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MB96610 Series
14.2 Recommended Operating Conditions
(VSS = AVSS = 0V)
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
2.7
5.5
V
Power supply voltage
VCC, AVCC
2.0
-
5.5
V
Maintains RAM data in stop mode
1.0µF (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Please use the ceramic capacitor or the
capacitor of the frequency response of this
level. The smoothing capacitor at VCC must use
the one of a capacity value that is larger than
CS.
Smoothing capacitor
at C pin
CS
0.5
1.0 to 3.9
4.7
µF
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04709 Rev.*C
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MB96610 Series
14.3 DC Characteristics
14.3.1 Current Rating
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
-
25
-
mA
TA = +25°C
PLL Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32MHz
ICCPLL
-
-
-
-
-
34
35
-
mA
mA
mA
TA = +105°C
TA = +125°C
TA = +25°C
Flash 0 wait
(CLKRC and CLKSC stopped)
3.5
Main Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 4MHz
ICCMAIN
Flash 0 wait
-
-
-
-
7.5
8.5
mA
mA
TA = +105°C
TA = +125°C
(CLKPLL, CLKSC and CLKRC
stopped)
-
1.7
-
mA
TA = +25°C
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
2MHz
Power supply
current in Run
modes[1]
ICCRCH
Vcc
Flash 0 wait
-
-
-
-
-
5.5
6.5
-
mA
mA
mA
TA = +105°C
TA = +125°C
TA = +25°C
(CLKMC, CLKPLL and CLKSC
stopped)
0.15
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
100kHz
ICCRCL
Flash 0 wait
-
-
3.2
mA
TA = +105°C
(CLKMC, CLKPLL and CLKSC
stopped)
-
-
-
4.2
-
mA
mA
TA = +125°C
TA = +25°C
0.1
Sub Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32kHz
ICCSUB
Flash 0 wait
-
-
-
-
3
4
mA
mA
TA = +105°C
TA = +125°C
(CLKMC, CLKPLL and CLKRC
stopped)
Document Number: 002-04709 Rev.*C
Page 36 of 63
MB96610 Series
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
-
6.5
-
mA
TA = +25°C
PLL Sleep mode with
ICCSPLL
CLKS1/2 = CLKP1/2 = 32MHz
(CLKRC and CLKSC stopped)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13
14
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
-
0.9
Main Sleep mode with
CLKS1/2 = CLKP1/2 = 4MHz,
SMCR:LPMSS = 0
ICCSMAIN
ICCSRCH
ICCSRCL
ICCSSUB
-
4
(CLKPLL, CLKRC and CLKSC
stopped)
-
5
0.5
-
RC Sleep mode with CLKS1/2 =
CLKP1/2 = CLKRC = 2MHz,
Power supply
current in Sleep
modes[1]
Vcc
SMCR:LPMSS = 0
-
3.5
4.5
-
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.06
RC Sleep mode with CLKS1/2 =
CLKP1/2 = CLKRC = 100kHz
-
2.7
3.7
-
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.04
Sub Sleep mode with
CLKS1/2 = CLKP1/2 = 32kHz,
-
-
2.5
3.5
(CLKMC, CLKPLL and CLKRC
stopped)
Document Number: 002-04709 Rev.*C
Page 37 of 63
MB96610 Series
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
µA
Remarks
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
TA = +25°C
TA = +105°C
TA = +125°C
name
Min
Max
-
1800
2245
PLL Timer mode with CLKPLL =
32MHz (CLKRC and CLKSC
stopped)
ICCTPLL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3165
3975
325
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-
Main Timer mode with
CLKMC = 4MHz,
285
ICCTMAIN
ICCTRCH
ICCTRCL
ICCTSUB
-
1085
1930
210
SMCR:LPMSS = 0
(CLKPLL, CLKRC and CLKSC
stopped)
-
160
RC Timer mode with
CLKRC = 2MHz,
Power supply
current in
Vcc
-
-
1025
1840
75
Timer modes[2]
SMCR:LPMSS = 0 (CLKPLL,
CLKMC and CLKSC stopped)
35
-
RC Timer mode with
855
CLKRC = 100kHz (CLKPLL,
CLKMC and CLKSC stopped)
-
1640
65
25
-
Sub Timer mode with
830
CLKSC = 32kHz (CLKMC,
CLKPLL and CLKRC stopped)
-
1620
-
-
-
20
-
55
µA
µA
µA
TA = +25°C
TA = +105°C
TA = +125°C
Power supply
current in Stop
mode[3]
ICCH
-
-
825
-
1615
Flash Power
Down current
ICCFLASHPD
-
-
36
5
70
-
µA
µA
Power supply
current
Vcc
TA = +25°C
for active Low
ICCLVD
Low voltage detector enabled
Voltage
-
-
12.5
µA
TA = +125°C
detector[4]
-
-
12.5
-
-
mA
mA
TA = +25°C
Flash Write/
Erase current[5]
ICCFLASH
-
20
TA = +125°C
[1]: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further
details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power supply current in Run mode does
not include Flash Write / Erase current.
[2]: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. The current for "On Chip Debugger" part is not included.
[3]: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
[4]: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
[5]: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
Document Number: 002-04709 Rev.*C
Page 38 of 63
MB96610 Series
14.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
-
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
-
-
VCC×0.7
VCC+ 0.3
V
V
CMOS Hysteresis input
Port inputs
Pnn_m
VIH
AUTOMOTIVE Hysteresis
input
VCC×0.8
VD×0.8
VCC×0.8
-
-
-
VCC+ 0.3
External clock in
VIHX0S
X0
VD
V
VD=1.8V±0.15V
"Fast Clock Input
mode"
"H" level input
voltage
External clock in
VIHX0AS
X0A
VCC+ 0.3
V
"Oscillation mode"
VIHR
VIHM
VIHD
RSTX
-
-
-
-
VCC×0.8
VCC- 0.3
2.0
-
-
-
-
VCC+ 0.3
VCC+ 0.3
VCC+ 0.3
VCC×0.3
V
V
V
V
CMOS Hysteresis input
CMOS Hysteresis input
TTL Input
MD
DEBUG I/F
VSS- 0.3
CMOS Hysteresis input
Port inputs
Pnn_m
VIL
AUTOMOTIVE Hysteresis
input
-
VSS- 0.3
-
-
-
VCC×0.5
VD×0.2
VCC×0.2
V
V
V
External clock in
"Fast Clock Input
mode"
VILX0S
X0
VSS
VD=1.8V±0.15V
"L" level input
voltage
External clock in
"Oscillation mode"
-
VILX0AS
X0A
VSS- 0.3
VILR
VILM
VILD
RSTX
VSS- 0.3
VSS- 0.3
VSS- 0.3
-
-
-
VCC×0.2
VSS+ 0.3
0.8
V
V
V
CMOS Hysteresis input
CMOS Hysteresis input
TTL Input
MD
-
DEBUG I/F
-
4.5V ≤ VCC ≤ 5.5V
IOH = -4mA
"H" level
VOH4
4mA type
4mA type
VCC- 0.5
-
-
VCC
V
V
output voltage
2.7V ≤ VCC < 4.5V
IOH = -1.5mA
4.5V ≤ VCC ≤ 5.5V
IOL = +4mA
2.7V ≤ VCC < 4.5V
IOL = +1.7mA
VCC = 2.7V
VOL4
-
0.4
"L" level
output voltage
VOLD
DEBUG I/F
Pnn_m
0
-
-
0.25
+ 1
V
IOL = +25mA
VSS < VI < VCC
Input leak
current
IIL
- 1
µA
AVSS < VI <AVCC
,
AVRH
Pull-up
resistance
RPU
Pnn_m
VCC = 5.0V ±10%
25
-
50
5
100
15
kΩ
value
Other than
C, Vcc,
Vss, AVcc,
AVss,
Input
capacitance
CIN
-
pF
AVRH
Document Number: 002-04709 Rev.*C
Page 39 of 63
MB96610 Series
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Pin
Parameter
Symbol
Unit
MHz
Remarks
name
Min
Max
When using a crystal oscillator,
PLL off
4
-
-
8
When using an opposite phase
external clock, PLL off
When using a crystal oscillator or
opposite phase external clock,
PLL on
-
8
8
MHz
MHz
Input frequency
fC
X0, X1
4
-
-
When using a single phase
external clock in “Fast Clock Input
mode”, PLL off
-
8
8
MHz
MHz
Input frequency
Input clock cycle
fFCI
X0
When using a single phase
external clock in “Fast Clock Input
mode”, PLL on
4
-
tCYLH
-
-
125
55
-
-
-
-
ns
ns
Input clock pulse width PWH, PWL
Document Number: 002-04709 Rev.*C
Page 40 of 63
MB96610 Series
14.4.2 Sub Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
kHz
Remarks
name
Min
Max
When using an
oscillation circuit
When using an
opposite phase
external clock
When using a
single phase
-
-
-
-
32.768
-
X0A,
X1A
-
100
kHz
Input frequency
Input clock cycle
fCL
X0A
-
-
-
-
-
-
50
-
kHz
µs
external clock
tCYLL
-
-
-
10
30
Input clock pulse
width
PWH/tCYLL
,
70
%
PWL/tCYLL
Document Number: 002-04709 Rev.*C
Page 41 of 63
MB96610 Series
14.4.3 Built-in RC Oscillation Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Parameter
Symbol
Unit
kHz
Remarks
Min
Typ
Max
200
When using slow frequency of RC
oscillator
50
100
Clock frequency
fRC
When using fast frequency of RC
oscillator
1
2
4
MHz
When using slow frequency of RC
oscillator (16 RC clock cycles)
When using fast frequency of RC
oscillator
80
160
320
s
RC clock stabilization time
tRCSTAB
64
128
256
s
(256 RC clock cycles)
14.4.4 Internal Clock Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Unit
Parameter
Symbol
Min
Max
Internal System clock frequency
fCLKS1, fCLKS2
-
54
MHz
(CLKS1 and CLKS2)
Internal CPU clock frequency (CLKB), Internal peripheral
fCLKB, fCLKP1
-
-
32
32
MHz
MHz
clock frequency (CLKP1)
Internal peripheral clock frequency (CLKP2)
fCLKP2
Document Number: 002-04709 Rev.*C
Page 42 of 63
MB96610 Series
14.4.5 Operating Conditions of PLL
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
1
Max
4
PLL oscillation stabilization wait time
PLL input clock frequency
tLOCK
-
-
-
ms
For CLKMC = 4MHz
fPLLI
4
8
MHz
MHz
Permitted VCO output
frequency of PLL (CLKVCO)
PLL oscillation clock frequency
fCLKVCO
56
108
For CLKMC (PLL input
clock) ≥ 4MHz
PLL phase jitter
tPSKEW
-5
-
+5
ns
14.4.6 Reset Input
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter Symbol Pin name
Reset input time
Value
Unit
Min
Max
10
-
-
µs
µs
tRSTL
RSTX
Rejection of reset input time
1
tRSTL
RSTX
0.2VCC
0.2VCC
Document Number: 002-04709 Rev.*C
Page 43 of 63
MB96610 Series
14.4.7 Power-on Reset Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Parameter
Symbol
Pin name
Unit
Min
Max
Power on rise time
Power off time
tR
Vcc
Vcc
0.05
1
-
-
30
-
ms
ms
tOFF
Document Number: 002-04709 Rev.*C
Page 44 of 63
MB96610 Series
14.4.8 USART Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF)
4.5V VCC <5.5V
2.7V VCC <4.5V
Uni
t
Parameter
Symbol
Pin name
Conditions
Min
Max
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCKn
ns
ns
4tCLKP1
-
4tCLKP1
-
SCKn,
SOTn
SCK ↓ →SOT delay time
- 20
+ 20
- 30
+ 30
SCKn,
SOTn
N×tCLKP1
20*
–
N×tCLKP1
30*
–
Internal
shift clock
mode
SOT → SCK ↑ delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tOVSHI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
SCKn,
SINn
tCLKP1
+ 55
tCLKP1+ 45
0
SCKn,
SINn
0
tCLKP1
+ 10
SCKn
SCKn
tCLKP1+ 10
tCLKP1+ 10
-
tCLKP1
+ 10
2tCLKP1
+ 45
2tCLKP1
+ 55
SCKn,
SOTn
-
External
shift clock
mode
tCLKP1/2
+ 10
SCKn,
SINn
tCLKP1/2+ 10
tCLKP1+ 10
-
-
-
-
tCLKP1
+ 10
SCKn,
SINn
SCK fall time
SCK rise time
tF
SCKn
SCKn
ns
ns
-
-
20
20
-
-
20
20
tR
Notes:
− AC characteristic in CLK synchronized mode
− CL is he load capacity value of pins when testing.
− Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
These parameters are shown in “MB96600 series HARDWARE MANUAL”.
− tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKn and SOTn_R is not guaranteed.
*: Parameter N depends on tSCYC and can be calculated as follows:
If tSCYC = 2 ×k ×tCLKP1, then N = k, where k is an integer > 2
If tSCYC = (2 ×k + 1) ×tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC
N
2
3
4 ×tCLKP1
5 ×tCLKP1, 6 ×tCLKP1
7 ×tCLKP1, 8 ×tCLKP1
4
Document Number: 002-04709 Rev.*C
Page 45 of 63
MB96610 Series
tSCYC
VOH
SCK
VOL
VOL
tOVSHI
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Internal shift clock mode
tSHSL
tSLSH
SCK
VIH
VIH
tR
VIH
VIL
tSLOVE
VIL
tF
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
External shift clock mode
Document Number: 002-04709 Rev.*C
Page 46 of 63
MB96610 Series
14.4.9 External Input Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Parameter
Symbol
Pin name
Unit
Remarks
Min
Max
Pnn_m
General Purpose I/O
ADTG_R
A/D Converter trigger input
TINn
TTGn
INn
Reload Timer
PPG trigger input
Input Capture
2tCLKP1 +200
(tCLKP1=1/fCLKP1)*
-
ns
Input pulse
width
tINH, tINL
Quadrature Position/Revolution
Counter
AINn, BINn, ZINn
INTn, INTn_R,
INTn_R1
External Interrupt
200
-
ns
NMI
Non-Maskable Interrupt
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
tINH
tINL
External input timing
VIH
VIH
VIL
VIL
Document Number: 002-04709 Rev.*C
Page 47 of 63
MB96610 Series
14.5 A/D Converter
14.5.1 Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Parameter
Resolution
Symbol
Pin name
Unit
bit
Remarks
Min
Typ
Max
-
-
-
-
-
-
10
Total error
-
-
-
- 3.0
- 2.5
- 1.9
+ 3.0
+ 2.5
+ 1.9
LSB
LSB
LSB
Nonlinearity error
-
-
-
-
Differential
Nonlinearity error
Zero transition
voltage
AVSS+
0.5LSB
VOT
ANn
Typ - 20
Typ - 20
Typ + 20
Typ + 20
mV
mV
Full scale transition
voltage
AVRH-
1.5LSB
VFST
ANn
-
1.0
2.2
0.5
1.2
-
-
5.0
8.0
-
µs
µs
µs
µs
mA
4.5V ≤ ΑVCC ≤ 5.5V
Compare time*
Sampling time*
-
-
2.7V ≤ ΑVCC <4.5V
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC <4.5V
A/D Converter active
-
-
-
-
-
IA
2.0
3.1
Power supply current
AVCC
A/D Converter not
operated
IAH
-
-
-
-
3.3
810
1.0
µA
µA
µA
Reference power
supply current
IR
520
-
A/D Converter active
AVRH
(between AVRH and
A/D Converter not
operated
IRH
AVSS
)
Analog input capacity CVIN
ANn
ANn
-
-
-
-
-
-
15.6
2050
3600
pF
Ω
4.5V ≤ AVCC ≤ 5.5V
2.7V ≤ AVCC < 4.5V
Analog impedance
RVIN
Ω
Analog port input
current (during
conversion)
AVSS <VAIN <AVCC
AVRH
,
IAIN
ANn
- 0.3
-
+ 0.3
Ω
Analog input voltage
VAIN
-
ANn
AVSS
-
-
AVRH
AVCC
V
V
Reference voltage
range
AVRH
AVCC- 0.1
Variation between
channels
-
ANn
-
-
4.0
LSB
*: Time for each channel.
Document Number: 002-04709 Rev.*C
Page 48 of 63
MB96610 Series
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold
capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends
on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The
following replacement model can be used for the calculation:
MCU
Analog
input
RVIN
Rext
Source
Comparator
Cext
CVIN
Sampling switch
(During sampling:ON)
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62 ×(Rext ×Cext + (Rext + RVIN) ×CVIN
)
Do not select a sampling time below the absolute minimum permitted value.
(0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V)
If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin.
A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL
(static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and
comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.
The accuracy gets worse as |AVRH - AVSS| becomes smaller.
14.5.3 Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Nonlinearity error : Deviation of the actual conversion characteristics from a straight line that connects the zero transition point
(0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111).
Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by
1LSB.
Total error
: Difference between the actual value and the theoretical value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Zero transition voltage: Input voltage which results in the minimum conversion value.
Full scale transition voltage: Input voltage which results in the maximum conversion value.
Document Number: 002-04709 Rev.*C
Page 49 of 63
MB96610 Series
VNT - {1LSB ×(N - 1) + VOT
}
Nonlinearity error of digital output N =
[LSB]
- 1 [LSB]
1LSB
V(N + 1) T - VNT
1LSB
Differential nonlinearity error of digital output N =
VFST - VOT
1LSB =
1022
N
: A/D converter digital output value.
VO : Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0x3FE to 0x3FF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04709 Rev.*C
Page 50 of 63
MB96610 Series
AVRH - AVSS
1024
1LSB (Ideal value) =
[V]
VNT - {1LSB × (N - 1) + 0.5LSB}
Total error of digital output N =
1LSB
N
: A/D converter digital output value.
VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVSS + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
Document Number: 002-04709 Rev.*C
Page 51 of 63
MB96610 Series
14.6 Low Voltage Detection Function Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Parameter
Symbol
VDL0
Conditions
Unit
Max
Min
CILCR:LVL = 0000B
CILCR:LVL = 0001B
CILCR:LVL = 0010B
CILCR:LVL = 0011B
CILCR:LVL = 0100B
CILCR:LVL = 0111B
CILCR:LVL = 1001B
2.70
2.79
2.98
3.26
3.45
3.73
3.91
2.90
3.10
3.21
3.42
3.74
3.95
4.27
4.49
V
V
V
V
V
V
V
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
3.00
3.20
3.50
3.70
4.00
4.20
Detected voltage[1]
Power supply voltage change
rate[2]
dV/dt
VHYS
-
- 0.004
-
+ 0.004
V/µs
CILCR:LVHYS=0
CILCR:LVHYS=1
-
-
50
mV
mV
Hysteresis width
80
100
120
Stabilization time
TLVDSTAB
td
-
-
-
-
-
-
75
30
µs
µs
Detection delay time
[1]: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low
voltage detection will occur or stop after the power supply voltage passes the detection range.
[2]: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power supply
voltage within the limits of the change ration of power supply voltage.
Voltage
Vcc
dV
Detected Voltage
dt
VDLX max
VDLX min
Time
Document Number: 002-04709 Rev.*C
Page 52 of 63
MB96610 Series
RCR:LVDE
Low voltage detection
function disable
Stabilization time
TLVDSTAB
···Low voltage detection
function enable
Low voltage detection
function enable···
Document Number: 002-04709 Rev.*C
Page 53 of 63
MB96610 Series
14.7 Flash Memory Write/Erase Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Value
Typ
Parameter
Large Sector
Conditions
Unit
Remarks
Min
Max
7.5
TA ≤ + 105°C
-
1.6
s
s
s
Includes write time prior to
internal erase.
Sector erase time
Small Sector
Security Sector
Large Sector
Small Sector
-
-
-
-
-
0.4
0.31
25
2.1
-
1.65
400
400
TA ≤ + 105°C
µs
µs
Word (16-bit) write
time
Not including system-level
overheadtime.
-
25
Includes write time prior to
internal erase.
Chip erase time
TA ≤ + 105°C
-
5.11
25.05
s
Note:
While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low
voltage detection function.
To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to
+0.004V/s) after the external power falls below the detection voltage (VDLX)*1.
Write/Erase cycles and data hold time
Write/Erase cycles
Data hold time
(year)
(cycle)
1,000
20 [2]
10 [2]
5 [2]
10,000
100,000
[1]:See "14.6 Low Voltage Detection Function Characteristics".
[2]:This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into
normalized value at + 85˚c).
Document Number: 002-04709 Rev.*C
Page 54 of 63
MB96610 Series
15.Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
MB96F615
Run Mode
(VCC = 5.5V)
100.00
PLL clock (32MHz)
10.00
Main osc. (4MHz)
1.00
RC clock (2MHz)
RC clock (100kHz)
0.10
Sub osc. (32kHz)
0.01
-50
0
50
100
150
TA [ºC]
Sleep Mode
(VCC = 5.5V)
100.000
10.000
1.000
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
0.100
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04709 Rev.*C
Page 55 of 63
MB96610 Series
MB96F615
10.000
1.000
Timer Mode
(VCC = 5.5V)
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
0.100
RC clock (100kHz)
Sub osc. (32kHz)
0.010
0.001
-50
0
50
100
150
TA [ºC]
Stop Mode
(VCC = 5.5V)
1.000
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04709 Rev.*C
Page 56 of 63
MB96610 Series
Used setting
Selected Source
Clock
Mode
Clock/Regulator and FLASH Settings
Run mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
Main osc.
RC clock fast
RC clock slow
Sub osc.
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Sleep mode
Regulator in High Power Mode, (CLKB is stopped in this mode)
Main osc.
RC clock fast
RC clock slow
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode, (CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode, (CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode, (CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode, (CLKB is stopped in this mode)
CLKMC = 4MHz, CLKPLL = 32MHz
Timer mode
PLL
(System clocks are stopped in this mode) Regulator in High Power Mode,
FLASH in Power-down / reset mode
Main osc.
CLKMC = 4MHz
(System clocks are stopped in this mode) Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock fast
RC clock slow
Sub osc.
CLKMC = 2MHz
(System clocks are stopped in this mode) Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 100kHz
(System clocks are stopped in this mode) Regulator in Low Power Mode,
FLASH in Power-down / reset mode
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode, FLASH in Power-down / reset mode
(All clocks are stopped in this mode)
Stop mode
stopped
Regulator in Low Power Mode, FLASH in Power-down / reset mode
Document Number: 002-04709 Rev.*C
Page 57 of 63
MB96610 Series
16.Ordering Information
MCU with CAN controller
Part number
Flash memory
Package*
MB96F612RBPMC-GSE1
MB96F612RBPMC-GS-UJE1
MB96F612RBPMC-GSE2
MB96F612RBPMC-GS-UJE2
MB96F612RBPMC-GTE1
MB96F613RBPMC-GSE1
MB96F613RBPMC-GS-UJE1
MB96F613RBPMC-GSE2
MB96F613RBPMC-GS-UJE2
MB96F613RBPMC-GTE1
MB96F615RBPMC-GSE1
MB96F615RBPMC-GS-UJE1
MB96F615RBPMC-GSE2
MB96F615RBPMC-GS-UJE2
MB96F615RBPMC-GTE1
Flash A (64.5KB)
48-pin plastic LQFP (LQA048)
Flash A (96.5KB)
Flash A (160.5KB)
48-pin plastic LQFP (LQA048)
48-pin plastic LQFP (LQA048)
*: For details about package, see "Package Dimension".
MCU without CAN controller
Part number
Flash memory
Package*
MB96F612ABPMC-GSE1
MB96F612ABPMC-GS-UJE1
MB96F612ABPMC-GSE2
MB96F612ABPMC-GS-UJE2
MB96F612ABPMC-GTE1
MB96F613ABPMC-GSE1
MB96F613ABPMC-GS-UJE1
MB96F613ABPMC-GSE2
MB96F613ABPMC-GS-UJE2
MB96F613ABPMC-GTE1
MB96F615ABPMC-GSE1
MB96F615ABPMC-GS-UJE1
MB96F615ABPMC-GSE2
MB96F615ABPMC-GTE1
Flash A
(64.5KB)
48-pin plastic LQFP (LQA048)
Flash A
(96.5KB)
48-pin plastic LQFP (LQA048)
48-pin plastic LQFP (LQA048)
Flash A
(160.5KB)
*: For details about package, see "Package Dimension".
Document Number: 002-04709 Rev.*C
Page 58 of 63
MB96610 Series
17.Package Dimension
LQA048, 48 Lead Plastic Low Profile Quad Flat Package
Package Type
Package Code
LQFP 48pin
LQA048
4
5
D
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
7
e
0.10
C
D
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
θ
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0°
0.75
0.70
L1
θ
0.50
8°
002-13731 **
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
Document Number: 002-04709 Rev.*C
Page 59 of 63
MB96610 Series
18.Major Changes
Spansion Publication Number: MB96610_DS704-00007
Page
Section
Change Results
Revision 3.0
FEATURES
Changed the description of “External Interrupts”
Interrupt mask and pending bit per channel
Interrupt mask bit per channel
4
23 to 26
HANDLING PRECAUTIONS
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Added a section
Changed the Conditions for ICCSRCH
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz,
CLKS1/2 = CLKP1/2 = CLKRC = 2MHz,
Changed the Conditions for ICCSRCL
(1) Current Rating
34
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz
CLKS1/2 = CLKP1/2 = CLKRC = 100kHz
Changed the Conditions for ICCTPLL
PLL Timer mode with CLKP1 = 32MHz
PLL Timer mode with CLKPLL = 32MHz
Changed the Value of “Power supply current in Timer modes”
ICCTPLL
Typ: 2480μA → 1800μA (TA = +25°C)
Max: 2710μA → 2245μA (TA = +25°C)
Max: 3985μA → 3165μA (TA = +105°C)
Max: 4830μA → 3975μA (TA = +125°C)
Changed the Conditions for ICCTRCL
35
RC Timer mode with CLKRC = 100kHz,
SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped)
RC Timer mode with CLKRC = 100kHz
(CLKPLL, CLKMC and CLKSC stopped)
Changed the annotation *2
Power supply for "On Chip Debugger" part is not included.
Power supply current in Run mode does not include
Flash Write / Erase current.
36
The current for "On Chip Debugger" part is not included.
5. A/D Converter
Deleted the unit “[Min]” from approximation formula of Sampling
47
52
(2) Accuracy and Setting of the A/D Converter
Sampling Time
time
7. Flash Memory Write/Erase Characteristics
Changed the condition
(VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V,
TA = - 40°C to + 125°C)
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to +
125°C)
Document Number: 002-04709 Rev.*C
Page 60 of 63
MB96610 Series
Page
Section
Change Results
ELECTRICAL CHARACTERISTICS
Changed the Note
7. Flash Memory Write/Erase Characteristics While the Flash memory is written or erased, shutdown of the
external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while
writing, be sure to turn the power off by using an external
voltage detector.
52
While the Flash memory is written or erased, shutdown of the
external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while writing
or erasing, be sure to turn the power off by using a low voltage
detection function.
ORDERING INFORMATION
Deleted the Part number
MCU with CAN controller
MB96F612RBPMC-GTE2
MB96F613RBPMC-GTE2
MB96F615RBPMC-GTE2
MCU without CAN controller
MB96F612ABPMC-GTE2
MB96F613ABPMC-GTE2
MB96F615ABPMC-GTE2
56
Revision 3.1
-
-
Company name and layout design change
Rev.*B
1. Product Lineup
3. Pin Assignment
Package description modified to JEDEC description.
6, 8, 58,
59
16. Ordering Information
17. Package Dimension
FPT-48P-M26 → LQA048
Added the following part number.
MB96F612RBPMC-GS-UJE1,
MB96F612RBPMC-GS-UJE2,
MB96F613RBPMC-GS-UJE1,
MB96F613RBPMC-GS-UJE2,
MB96F615RBPMC-GS-UJE1,
MB96F615RBPMC-GS-UJE2,
MB96F612ABPMC-GS-UJE1,
MB96F612ABPMC-GS-UJE2
MB96F613ABPMC-GS-UJE1,
MB96F613ABPMC-GS-UJE2
MB96F615ABPMC-GS-UJE1,
MB96F615ABPMC-GS-UJE2
58
16. Ordering Information
Rev.*C
58
16. Ordering Information
Deleted the Part number
MCU without CAN controller
MB96F615ABPMC-GS-UJE2
Document Number: 002-04709 Rev.*C
Page 61 of 63
MB96610 Series
Document History
Document Title: MB96610 Series, F2MC, 16FX, 16-bit Proprietary Microcontroller
Document Number: 002-04709
Orig. of Submission
Revision ECN
Description of Change
Migrated to Cypress and assigned document number 002-04709.
Change
KSUN
KSUN
KUME
Date
**
01/31/2014
No change to document contents or format.
*A
*B
5146534
5735123
02/29/2016 Updated to Cypress template
Updated the Ordering Information and the Package Dimension
05/15/2017
07/11/2017
For details, please see 18. Major Changes.
Updated the Ordering Information
*C
5809040
MIYH
For details, please see 18. Major Changes.
Document Number: 002-04709 Rev.*C
Page 62 of 63
MB96610 Series
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© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the
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Document Number: 002-04709 Rev.*C
Revised July 11, 2017
Page 63 of 63
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