MB90F351TAPMC1_技术文档

MB90350 Series

F²MC-16LX 16-bit Microcontroller

The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive and industrial appli-

cations. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible

message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35μm CMOS technology,

Cypress now offers on-chip Flash-ROM program memory up to 128 Kbytes.

The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms

of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,

the clock monitor function can monitor main clock and sub clock independently.

As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit

freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.

Features

Clock

Increased processing speed

■ Built-in PLL clock frequency multiplication circuit

■ 4-byte instruction queue

■ Selection of machine clocks (PLL clocks) is allowed among

frequencydivisionbytwoonoscillationclock,andmultiplication

of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,

4 MHz to 24 MHz).

Powerful interrupt function

■ Powerful 8-level, 34-condition interrupt feature

■ Up to 8 channels external interrupts are supported.

■ Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock

divided by two) is allowed. (devices without S-suffix only)

Automatic data transfer function independent of CPU

■ Extended intelligent I/O service function (EI²OS) : up to 16

channels

■ Minimum execution time of instruction : 42 ns (when operating

with 4-MHz oscillation clock, and 6-time multiplied PLL clock).

■ DMA: up to 16 channels

■ Built-in clock modulation circuit

Low power consumption (standby) mode

16 Mbytes CPU memory space

■ Sleep mode (a mode that halts CPU operating clock)

■ 24-bit internal addressing

■ Main timer mode (a timebase timer mode switched from the

main clock mode)

Clock monitor function (MB90x356x and MB90x357x

only)

■ PLLtimer mode (a timebase timer mode switched from the PLL

clock mode)

■ Main clock or sub clock is monitored independently.

■ Internal CR oscillation clock (100 kHz typical) can be used as

sub clock.

■ Watch mode (a mode that operates sub clock and watch timer

only)

Instruction system best suited to controller

■ Wide choice of data types (bit, byte, word, and long word)

■ Wide choice of addressing modes (23 types)

■ Stop mode (a mode that stops oscillation clock and sub clock)

■ CPU intermittent operation mode

Process

■ Enhanced multiply-divide instructions with sign and RETI

instructions

■ CMOS technology

I/O port

■ Enhanced high-precision computing with 32-bit accumulator

■ General-purpose input/output port (CMOS output)

❐ 49 ports (devices without S-suffix : devices that correspond

to sub clock)

Instruction system compatible with high-level

language (C language) and multitask

❐ 51 ports (devices with S-suffix : devices that do not corre-

spond to sub clock)

■ Employing system stack pointer

■ Enhanced various pointer indirect instructions

■ Barrel shift instructions

Cypress Semiconductor Corporation

Document Number: 002-07872 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 31, 2017

MB90350 Series

Sub clock pin (X0A, X1A)

8/10-bit A/D converter: 15 channels

■ Yes (using the external oscillation) : devices without S-suffix

■ Resolution is selectable between 8-bit and 10-bit.

■ Activation by external trigger input is allowed.

■ No (using the sub clock mode at internal CR oscillation) :

devices with S-suffix

■ Conversion time: 3 μs (at 24-MHz machine clock, including

sampling time)

Timer

Program patch function

■ Timebase timer, watch timer, watchdog timer: 1 channel

■ 8/16-bit PPG timer: 8-bit × 10 channels or 16-bit × 6 channels

■ 16-bit reload timer: 4 channels

■ Address matching detection for 6 address pointers.

Capable of changing input voltage level for port

■ 16- bit input/output timer

■ Automotive/CMOS-Schmitt (initial level is Automotive in single

❐ 16-bit freerun timer : 2 channels (FRT0: ICU0/1, FRT1: ICU

chip mode)

4/5/6/7, OCU 4/5/6/7)

■ TTL level (corresponds to external bus pins only, initial level of

these pins is TTL in external bus mode)

❐ 16- bit input capture: (ICU): 6 channels

❐ 16-bit output compare: (OCU): 4 channels

Low voltage/CPU operation detection reset (devices

with T-suffix)

FULL-CAN interface 1 channel

■ Compliant with Ver2.0 part A and Ver2.0 part B CAN specifica-

tions

■ Detects low voltage (4.0 V  0.3 V) and resets automatically

■ Resets automatically when program is runaway and counter is

not cleared within interval time (approx. 262 ms : external 4

MHz)

■ Flexible message buffering (mailbox and FIFO buffering can

be mixed)

■ CAN wake-up function

Dual operation flash memory (only flash memory

devices with A-suffix)

UART (LIN/SCI): 2 channels

■ Equipped with full-duplex double buffer

■ Erase/write and read can be executed in the different bank

(Upper Bank/Lower Bank) at the same time.

■ Clock-asynchronous or clock-synchronous serial transmission

is available.

Models that support  125 °C

■ Devices without A-suffix (excluding evaluation device)

: The maximum operating frequency is 16 MHz

^{(at T}_A 125 °C) .

■ Devices with A-suffix (excluding evaluation device)

: The maximum operating frequency is 24 MHz

^{(at T}_A 125 °C) .

2

I C interface: 1 channel

■ Up to 400 Kbit/s transfer rate

DTP/External interrupt: 8 channels, CAN wakeup: 1

channel

■ Module for activation of extended intelligent I/O service

(EI²OS), DMA, and generation of external interrupt by external

input.

Flash security function

■ Protects the content of Flash memory (MB90F352x and

MB90F357x only)

Delay interrupt generator module

■ Generates interrupt request for task switching.

External bus interface

■ 4 Mbytes external memory space

Document Number: 002-07872 Rev. *A

Page 2 of 83

MB90350 Series

Contents

Product Lineup 1 .............................................................4

Product Lineup 2 .............................................................6

Product Lineup 3 .............................................................8

Product Lineup 4 ...........................................................10

Packages and Product Correspondence .....................12

Pin Assignments ............................................................13

Pin Description ...............................................................14

I/O Circuit Type ...............................................................18

Handling Devices ............................................................22

Preventing latch-up ...................................................22

Handling unused pins ................................................22

Using external clock ..................................................23

Precautions for when not using a sub clock signal ....23

Notes on during operation of PLL clock mode ..........23

Power supply pins (VCC/VSS) .................................23

Pull-up/down resistors ...............................................23

Crystal Oscillator Circuit ............................................23

Turning-on Sequence of Power Supply to

(External-bus mode) ..................................................24

Notes on using CAN Function ...................................24

Flash security Function .............................................25

^{Correspondence with TA} 105 °C or more ...........25

Low voltage/CPU operation reset circuit ...................25

Internal CR oscillation circuit .....................................26

Block Diagrams ..............................................................27

Memory Map ....................................................................31

I/O Map ............................................................................32

CAN Controllers ..............................................................40

Interrupt Factors, Interrupt Vectors,

Interrupt Control Register ..............................................46

Electrical Characteristics ...............................................48

Absolute Maximum Ratings .......................................48

Recommended Operating Conditions .......................50

DC Characteristics ....................................................51

AC Characteristics .....................................................56

A/D Converter ............................................................71

Definition of A/D Converter Terms ...........................74

Flash Memory Program/Erase Characteristics ..........76

Ordering Information .....................................................77

Package Dimensions ......................................................79

Major Changes ................................................................81

Document History ...........................................................82

Sales, Solutions, and Legal Information ......................83

A/D Converter and Analog Inputs ..............................24

Connection of Unused Pins of A/D Converter if

A/D Converter is not used .........................................24

Notes on Energization ...............................................24

Stabilization of power supply voltage ........................24

Initialization ................................................................24

Port 0 to port 3 output during Power-on

Document Number: 002-07872 Rev. *A

Page 3 of 83

MB90350 Series

1. Product Lineup 1

Part Number

MB90F351,

MB90F352

MB90F351S,

MB90F352S

MB90F351A,

MB90F352A

MB90F351TA, MB90F351AS,

MB90F352TA MB90F352AS

MB90F351TAS,

MB90F352TAS

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

System clock

Flash memory

64Kbytes :MB90F351(S)

128Kbytes :MB90F352(S)

Dual operation flash memory

64Kbytes :MB90F351A(S), MB90F351TA(S)

128Kbytes :MB90F352A(S), MB90F352TA(S)

ROM

RAM

4 Kbytes

Emulator-specific power

supply*

—

Sub clock pin

(X0A, X1A)

(Max 100 kHz)

Yes

No

Yes

No

Clock monitor

function

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter/Flash programming

4.5 V to 5.5 V : at using external bus

Operating

voltage range

Operating

temperature range

40 °C to 105 °C (125 °C up to

40 °C to 125 °C

16 MHz machine clock)

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit Reload Timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

(Continued)

Document Number: 002-07872 Rev. *A

Page 4 of 83

MB90350 Series

(Continued)

Part Number

MB90F351,

MB90F352

MB90F351S,

MB90F352S

MB90F351A,

MB90F352A

MB90F351TA, MB90F351AS,

MB90F352TA MB90F352AS

MB90F351TAS,

MB90F352TAS

Parameter

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

8/16-bit

Programmable Pulse

Generator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

^{8-bit prescaler} 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc  4 MHz

^(fsys Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

—

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

I/O Ports

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Flash Memory

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F352x only)

Corresponding EVA

name

MB90V340A-

102

MB90V340A-

101

MB90V340A-102

MB90V340A-101

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-07872 Rev. *A

Page 5 of 83

MB90350 Series

2. Product Lineup 2

Part Number

MB90351A,

MB90352A

MB90351TA,

MB90352TA

MB90351AS, MB90351TAS,

MB90352AS MB90352TAS

MB90V340A-

101

MB90V340A-

102

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

System clock

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

MASK ROM

64Kbytes :MB90351A(S), MB90351TA(S)

128Kbytes :MB90352A(S), MB90352TA(S)

ROM

RAM

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific power

supply*

—

Sub clock pin

(X0A, X1A)

(Max 100 kHz)

Yes

No

Yes

Clock monitor

function

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

^{5 V} 10%

Operating

temperature range

40 °C to 125 °C

—

Package

LQFP-64

2 channels

PGA-299

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit Reload Timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

I/O Timer 0 corresponds to ICU

0/1/2/3, OCU 0/1/2/3.

I/O Timer 1 corresponds to ICU

4/5/6/7, OCU 4/5/6/7.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

8 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

8 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

(Continued)

Page 6 of 83

Document Number: 002-07872 Rev. *A

MB90350 Series

(Continued)

Part Number

MB90351A,

MB90352A

MB90351TA,

MB90352TA

MB90351AS, MB90351TAS,

MB90352AS MB90352TAS

MB90V340A-

101

MB90V340A-

102

Parameter

8 channels (16-bit)/

16 channels (8-bit)

8-bit reload counters × 16

8-bit reload registers for

L pulse width × 16

8-bit reload registers for

H pulse width × 16

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

8/16-bit

Programmable Pulse

Generator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

^{8-bit prescaler} 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc  4 MHz

^(fsys Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

3 channels

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

—

2 channels

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

I/O Ports

Flash Memory

—

Corresponding EVA

name

MB90V340A-102

MB90V340A-101

—

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-07872 Rev. *A

Page 7 of 83

MB90350 Series

3. Product Lineup 3

Part Number

MB90F356A,

MB90F357A

MB90F356TA,

MB90F357TA

MB90F356AS,

MB90F357AS

MB90F356TAS,

MB90F357TAS

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

System clock

Dual operation flash memory

64Kbytes :MB90F356A(S), MB90F356TA(S)

128Kbytes :MB90F357A(S), MB90F357TA(S)

ROM

RAM

4 Kbytes

—

Emulator-specific power

supply*

No

Sub clock pin

(X0A, X1A)

Yes

(internal CR oscillation can be used as

sub clock)

Clock monitor

function

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

3.5 V to 5.5 V : at using A/D converter/Flash programming

3.5 V to 5.5 V : at using external bus

Operating

voltage range

Operating

temperature range

40 °C to 125 °C

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit Reload Timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

(Continued)

Document Number: 002-07872 Rev. *A

Page 8 of 83

MB90350 Series

(Continued)

Part Number

MB90F356A,

MB90F357A

MB90F356TA,

MB90F357TA

MB90F356AS,

MB90F357AS

MB90F356TAS,

MB90F357TAS

Parameter

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

8/16-bit

Programmable Pulse

Generator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

^{8-bit prescaler} 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc  4 MHz

^(fsys Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

—

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

I/O Ports

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Flash Memory

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F357x only)

Corresponding EVA

name

MB90V340A-104

MB90V340A-103

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-07872 Rev. *A

Page 9 of 83

MB90350 Series

4. Product Lineup 4

Part Number

MB90356A,

MB90357A

MB90356TA,

MB90357TA

MB90356AS, MB90356TAS,

MB90357AS MB90357TAS

MB90V340A-

103

MB90V340A-

104

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

System clock

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

MASK ROM

64Kbytes :MB90356A(S), MB90356TA(S)

128Kbytes :MB90357A(S), MB90357TA(S)

ROM

RAM

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific power

supply*

—

No

(internal CR

Sub clock pin

(X0A, X1A)

Yes

(internal CR oscillation can be

used as sub clock)

oscillation can

be used as sub

Yes

clock)

Clock monitor

function

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

^{5 V} 10%

Operating

temperature range

40 °C to 125 °C

—

Package

LQFP-64

PGA-299

2 channels

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit Reload Timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

I/O Timer 0 corresponds to ICU

0/1/2/3, OCU 0/1/2/3.

I/O Timer 1 corresponds to ICU

4/5/6/7, OCU 4/5/6/7.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

8 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

(Continued)

Document Number: 002-07872 Rev. *A

Page 10 of 83

MB90350 Series

(Continued)

Part Number

MB90356A,

MB90357A

MB90356TA,

MB90357TA

MB90356AS, MB90356TAS,

MB90357AS MB90357TAS

MB90V340A-

103

MB90V340A-

104

Parameter

6 channels

8 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

8 channels (16-bit)/16 channels

(8-bit)

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 16

8-bit reload counters × 12

8-bit reload registers for

8-bit reload registers for L pulse width × 12

L pulse width × 16

8-bit reload registers for H pulse width × 12

8/16-bit

8-bit reload registers for

Programmable Pulse

Generator

H pulse width × 16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

^{8-bit prescaler} 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc  4 MHz

^(fsys Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

3 channels

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

—

2 channels

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

I/O Ports

Flash Memory

—

Corresponding EVA

name

MB90V340A-104

MB90V340A-103

—

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-07872 Rev. *A

Page 11 of 83

MB90350 Series

5. Packages and Product Correspondence

MB90F351A (S) , MB90F351TA (S)

MB90F352A (S) , MB90F352TA (S)

MB90F356A (S) , MB90F356TA (S)

MB90F357A (S) , MB90F357TA (S)

MB90351A (S) , MB90351TA (S)

MB90352A (S) , MB90352TA (S)

MB90356A (S) , MB90356TA (S)

MB90357A (S) , MB90357TA (S)

MB90V340A

-101

MB90F351

MB90F351S

MB90F352

MB90F352S

Package

-102

-103

-104

PGA-299C-A01

×

FPT-64P-M23

(12 mm , 0.65 mm pitch)

×

FPT-64P-M24

(10 mm , 0.50 mm pitch)

*

* : This device is under development.

: Yes, × : No

Note : Refer to “Package Dimensions” for detail of each package.

Document Number: 002-07872 Rev. *A

Page 12 of 83

MB90350 Series

6. Pin Assignments

■ MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),

MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),

MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),

(TOP VIEW)

(LQFP-64P)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P10/AD08/TIN1

Vcc

C

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

P07/AD07/INT15

P25/A21/IN1/ADTG

P44/SDA0/FRCK0

P45/SCL0/FRCK1

P30/ALE/IN4

P31/RD/IN5

P06/AD06/INT14

P05/AD05/INT13

P04/AD04/INT12

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

MD0

P32/WRL/WR/INT10R

P33/WRH

P34/HRQ/OUT4

P35/HAK/OUT5

P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0

MD1

MD2

P41/X1A*

P40/X0A*

P61/AN1

Vss

AVcc

P43/IN7/TX1

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FPT-64P-M23, FPT-64P-M24)

* : Devices without S-suffix

Devices with S-suffix

: X0A, X1A

: P40, P41

Document Number: 002-07872 Rev. *A

Page 13 of 83

MB90350 Series

7. Pin Description

Pin No.

Circuit

type

Pin name

Function

LQFP64*

46

47

45

X1

X0

Oscillation output pin

A

E

Oscillation input pin

RST

Reset input pin

P62 to P67

AN2 to AN7

General purpose I/O ports

Analog input pins for A/D converter

3 to 8

I

PPG4 (5) , 6 (7) , 8

(9) , A (B) , C (D) , E

(F)

Output pins for PPGs

P50

AN8

General purpose I/O port

9

O

I

Analog input pin for A/D converter

Serial data input pin for UART2

General purpose I/O port

SIN2

P51

10

11

12

AN9

Analog input pin for A/D converter

Serial data output pin for UART2

General purpose I/O port

SOT2

P52

AN10

SCK2

P53

I

Analog input pin for A/D converter

Serial clock I/O pin for UART2

General purpose I/O port

AN11

TIN3

I

Analog input pin for A/D converter

Event input pin for reload timer3

General purpose I/O port

P54

13

AN12

TOT3

P55, P56

AN13, AN14

P42

I

Analog input pin for A/D converter

Output pin for reload timer3

General purpose I/O ports

14, 15

Analog input pins for A/D converter

General purpose I/O port

IN6

Data sample input pin for input capture ICU6

RX input pin for CAN1

16

17

F

RX1

INT9R

P43

External interrupt request input pin for INT9

General purpose I/O port

IN7

Data sample input pin for input capture ICU7

TX output pin for CAN1

TX1

General purpose I/O ports

(devices with S-suffix and MB90V340A-101/103)

P40, P41

X0A, X1A

P00 to P07

F

B

19, 20

X0A : Oscillation input pins for sub clock

X1A : Oscillation output pins for sub clock

(devices without S-suffix and MB90V340A-102/104)

General purpose I/O ports. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

24 to 31

G

Input/output pins of external address data bus lower 8 bits. This function is enabled

when the external bus is enabled.

AD00 to AD07

INT8 to INT15

External interrupt request input pins for INT8 to INT15

(Continued)

Document Number: 002-07872 Rev. *A

Page 14 of 83

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

P10

32

33

G

Input/output pin for external bus address data bus bit 8.

This function is enabled when external bus is enabled.

AD08

TIN1

P11

Event input pin for reload timer1

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 9. This function is enabled when

external bus is enabled.

AD09

TOT1

P12

Output pin for reload timer1

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 10. This function is enabled when

external bus is enabled.

AD10

34

N

SIN3

Serial data input pin for UART3

INT11R

External interrupt request input pin for INT11

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

P13

35

36

G

Input/output pin for external bus address data bus bit 11.

This function is enabled when external bus is enabled.

AD11

SOT3

P14

Serial data output pin for UART3

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 12.

This function is enabled when external bus is enabled.

AD12

SCK3

P15

Clock input/output pin for UART3

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

37

38

39

N

G

Input/output pin for external bus address data bus bit 13.

This function is enabled when external bus is enabled.

AD13

P16

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 14.

This function is enabled when external bus is enabled.

AD14

P17

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 15.

This function is enabled when external bus is enabled.

AD15

General purpose I/O ports. The register can be set to select whether to use a pull-up

resistor. In external bus mode, the pins are enabled as a general purpose I/O port when

the corresponding bit in the external address output control register (HACR) is 1.

P20 to P23

A16 to A19

Output pins for A16 to A19 of the external address data bus.

When the corresponding bit in the external address output control register (HACR) is 0,

the pins are enabled as high address output pins A16 to A19.

40 to 43

G

PPG9 (8) ,

PPGB (A) ,

PPGD (C) ,

PPGF (E)

Output pins for PPGs

(Continued)

Document Number: 002-07872 Rev. *A

Page 15 of 83

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output control

register (HACR) is 1.

P24

44

G

Output pin for A20 of the external address data bus. When the corresponding bit in the

external address output control register (HACR) is 0, the pin is

enabled as high address output pin A20.

A20

IN0

Data sample input pin for input capture ICU0

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output control

register (HACR) is 1.

P25

Output pin for A21 of the external address data bus. When the corresponding bit in the

external address output control register (HACR) is 0, the pin is enabled as high address

output pin A21.

51

G

A21

IN1

ADTG

P44

Data sample input pin for input capture ICU1

Trigger input pin for A/D converter

General purpose I/O port

52

53

SDA0

FRCK0

P45

H

Serial data I/O pin for I²C 0

Input pin for the 16-bit I/O Timer 0

General purpose I/O port

Serial clock I/O pin for I²C 0

SCL0

FRCK1

Input pin for the 16-bit I/O Timer 1

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

P30

54

55

G

ALE

IN4

Address latch enable output pin. This function is enabled when external bus is enabled.

Data sample input pin for input capture ICU4

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

P31

Read strobe output pin for data bus. This function is enabled when external bus is

enabled.

RD

IN5

Data sample input pin for input capture ICU5

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode or with the WR/WRL pin

output disabled.

P32

Write strobe output pin for the data bus. This function is enabled when both the external

bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits

of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit

access.

56

57

G

WR/WRL

INT10R

P33

External interrupt request input pin for INT10

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode, in

external bus 8-bit mode or with the WRH pin output disabled.

Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when

the external bus is enabled, when the external bus 16-bit mode is selected, and when

the WRH output pin is enabled.

WRH

(Continued)

Document Number: 002-07872 Rev. *A

Page 16 of 83

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode or with the hold function

disabled.

P34

58

59

60

G

Hold request input pin. This function is enabled when both the external bus and the hold

function are enabled.

HRQ

OUT4

Waveform output pin for output compare OCU4

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode or with the hold function

disabled.

P35

Hold acknowledge output pin. This function is enabled when both the

external bus and the hold function are enabled.

HAK

OUT5

Waveform output pin for output compare OCU5

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode or with the external ready

function disabled.

P36

Ready input pin. This function is enabled when both the external bus and the external

ready function are enabled.

RDY

OUT6

Waveform output pin for output compare OCU6

General purpose I/O port. The register can be set to select whether to use a pull-up

resistor. This function is enabled either in single-chip mode or with the CLK output

disabled.

P37

61

G

I

CLK output pin. This function is enabled when both the external bus and CLK output are

enabled.

CLK

OUT7

P60, P61

AN0, AN1

AV_CC

Waveform output pin for output compare OCU7

General purpose I/O ports

62, 63

Analog input pins for A/D converter

64

2

K

L

V_CCpower input pin for analog circuits

Reference voltage input for the A/D converter. This power supply must be turned on or

AVRH

off while a voltage higher than or equal to AVRH is applied to AV_CC

V_SSpower input pin for analog circuits

Input pins for specifying the operating mode

Input pin for specifying the operating mode

Power (3.5 V to 5.5 V) input pin

.

1

AV_SS

MD1, MD0

MD2

K

C

22, 23

21

D

49

V_CC

—

18, 48

V_SS

Power (0 V) input pins

This is the power supply stabilization capacitor pin. It should be connected to a higher

than or equal to 0.1 μF ceramic capacitor.

50

C

K

* : FPT-64P-M23, FPT-64P-M24

Document Number: 002-07872 Rev. *A

Page 17 of 83

MB90350 Series

8. I/O Circuit Type

Type

Circuit

Remarks

Oscillation circuit

X1

Xout

• High-speed oscillation feedback

resistor = approx. 1 M

A

X0

Standby control signal

Xout

X1A

X0A

Oscillation circuit

• Low-speed oscillation feedback

resistor = approx. 10 M

B

Standby control signal

CMOS

Mask ROM device:

R

• CMOS hysteresis input pin

C

hysteresis

Flash memory device:

• CMOS input pin

inputs

Mask ROM device:

CMOS

hysteresis

inputs

• CMOS hysteresis input pin

• Pull-down resistor value: approx. 50 k

D

Pull-down

resistor

Flash memory device:

• CMOS input pin

• No Pull-down

CMOS hysteresis input pin

• Pull-up resistor value: approx. 50 k

Pull-up

resistor

E

R

CMOS

hysteresis

inputs

(Continued)

Document Number: 002-07872 Rev. *A

Page 18 of 83

MB90350 Series

Type

Circuit

P-ch

Remarks

^•(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

Pout

Nout

• CMOS hysteresis inputs (With the standby-time

input shutdown function)

N-ch

• Automotive input (With the standby-time input

shutdown function)

R

F

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

^•(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

Pull-up control

Pout

Pull-up

resistor

• CMOS hysteresis inputs (With the standby-time

input shutdown function)

P-ch

N-ch

• Automotive input (With the standby-time input

shutdown function)

• TTL input (With the standby-time input shut-

down function)

Nout

• Programmable pull-up resistor:

approx. 50 k

R

G

CMOS

hysteresis inputs

Automotive inputs

TTL input

Standby control for

input shutdown

^•(^CI_O^M_L^O=^S3^lem^vA^el, ^oI_O^u_H^tp^ut3 mA)

P-ch

N-ch

Pout

Nout

• CMOS hysteresis inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time input

shutdown function)

H

R

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

(Continued)

Document Number: 002-07872 Rev. *A

Page 19 of 83

MB90350 Series

Type

Circuit

Pout

Remarks

• CMOS level output

P-ch

N-ch

(I_OL= 4 mA, I_OH= 4 mA)

• CMOS hysteresis inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time input

shutdown function)

Nout

• A/D analog input

R

I

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

• Power supply input protection circuit

P-ch

N-ch

K

• A/D converter reference voltage power supply

input pin, with the protection circuit

• Flash memory devices do not have a

protection circuit against V_CCfor pin

AVRH.

ANE

AVR

P-ch

N-ch

L

ANE

(Continued)

Document Number: 002-07872 Rev. *A

Page 20 of 83

MB90350 Series

(Continued)

Type

Circuit

Remarks

^•(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

pull-up control

pull-up

resistor

• CMOS inputs (With the standby-time

input shutdown function)

Pout

Nout

• Automotive input (With the standby-time input

shutdown function)

• TTL input (With the standby-time input shut-

down function)

• Programmable pull-up resistor:

approx. 50 k

R

N

CMOS inputs

Automotive inputs

TTL input

Standby control for

input shutdown

^•(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

P-ch

N-ch

Pout

Nout

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time input

shutdown function)

• A/D analog input

R

O

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Analog input

Document Number: 002-07872 Rev. *A

Page 21 of 83

MB90350 Series

9. Handling Devices

Special care is required for the following when handling the device :

■ Preventing latch-up

■ Treatment of unused pins

■ Using external clock

■ Precautions for when not using a sub clock signal

■ Notes on during operation of PLL clock mode

■ Power supply pins (V_CC/V_SS

)

■ Pull-up/down resistors

■ Crystal Oscillator Circuit

■ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

■ Connection of Unused Pins of A/D Converter

■ Notes on Energization

■ Stabilization of power supply voltage

■ Initialization

■ Port0 to port3 output during Power-on (External-bus mode)

■ Notes on using CAN Function

■ Flash security Function

■ Correspondence with T_A  105 °C or more

■ Low voltage/CPU operation detection reset circuit

■ Internal CR oscillation circuit

9.1 Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

■ A voltage higher than V_CCor lower than V_SSis applied to an input or output pin.

■ A voltage higher than the rated voltage is applied between V_CCpin and V_SSpin.

■ The AV_CCpower supply is applied before the V_CCvoltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

In using the devices, take sufficient care to avoid exceeding maximum ratings.

For the same reason, also be careful not to let the analog power-supply voltage (AV_CC, AVRH) exceed the digital power-supply voltage.

9.2 Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they

must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ.

Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.

Document Number: 002-07872 Rev. *A

Page 22 of 83

MB90350 Series

9.3 Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90350 Series

X0

X1

Open

9.4 Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.

9.5 Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even when there is no

external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.

9.6 Power supply pins (V /V

)

CC SS

■ If there are multiple V_CCand V_SSpins, from the point of view of device design, pins to be of the same potential are connected inside

of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard

for total output current, be sure to connect the V_CCand V_SSpins to the power supply and ground externally.

Connect V_CCand V_SSpins to the device from the current supply source at a low impedance.

■ As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between V_CCand V_SSpins

in the vicinity of V_CCand V_SSpins of the device.

Vcc

Vss

Vcc

Vss

Vcc

MB90350

Series

Vcc

Vss

Vcc

Vss

9.7 Pull-up/down resistors

The MB90350 series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external compo-

nents where needed.

9.8 Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest

distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of

oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the

operation.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

Document Number: 002-07872 Rev. *A

Page 23 of 83

MB90350 Series

9.9 Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on theA/D converter power supply (AV_CC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power

supply (V_CC) .

Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage

does not exceed AVRH or AV_CC(turning on/off the analog and digital power supplies simultaneously is acceptable).

9.10 Connection of Unused Pins of A/D Converter if A/D Converter is not used

Connect unused pins of A/D converter to AV_CC V_CC, AV_SS AVRH  V_SS

.

9.11 Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

50 μs or more (0.2 V to 2.7 V) .

9.12 Stabilization of power supply voltage

Asudden change in the power supply voltage may cause the device to malfunction even within the specified V_CCpower supply voltage

operating range. Therefore, the V_CCpower supply voltage should be stabilized.

For reference, the power supply voltage should be controlled so that V_CCripple variations (peak-to-peak value) at commercial

frequencies (50 Hz to 60 Hz) fall below 10% of the standard V_CCpower supply voltage and the coefficient of fluctuation does not

exceed 0.1 V/ms at instantaneous power switching.

9.13 Initialization

In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power

again.

9.14 Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable.

1/2 VCC

V

CC

Port0 to Port3

Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z

might be unstable.

9.15 Notes on using CAN Function

To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).

If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers.

Note : Please refer to section “22.15 CAN Direct Mode Register” in Hardware Manual of MB90350 series for detail of CAN direct mode

register.

Document Number: 002-07872 Rev. *A

Page 24 of 83

MB90350 Series

9.16 Flash security Function

The security byte is located in the area of the flash memory.

If protection code 01_His written in the security byte, the flash memory is in the protected state by security.

Therefore please do not write 01_Hin this address if you do not use the security function.

Please refer to following table for the address of the security byte.

Flash memory size

Address for security bit

MB90F352(S)

MB90F352A(S)

MB90F352TA(S)

MB90F357A(S)

MB90F357TA(S)

Embedded 1 Mbit Flash Memory

FE0001_H

9.17 Correspondence with T  105 °C or more

A

If used exceeding T_A 105 °C, please contact sales representatives for reliability limitations.

9.18 Low voltage/CPU operation reset circuit

The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below

a given voltage level. When a low voltage condition is detected, an internal reset signal is generated.

The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset

signal if not cleared within a given time after startup.

9.18.1 Low voltage detection reset circuit

Detection voltage

^{4.0 V} 0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC: LVRF) is set to “1” and an internal reset signal is output.

Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates

an internal reset and releases stop mode.

During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal

reset, the reset output from the low voltage detection reset circuit is suppressed.

9.18.2 CPU operation detection reset circuit

The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a

power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been

cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated

from the CPU operation detection circuit has a width of 5 machine cycles.

Interval time

2²⁰/F_C(approx. 262 ms*)

* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.

During recovery from standby mode, the detection period is the maximum interval plus 20 μs.

This circuit does not operate in modes where CPU operation is stopped.

The CPU operation detection reset circuit counter is cleared under any of the following conditions.

■ “0” writing to CL bit of LVRC register

■ Internal reset

■ Main oscillation clock stop

■ Transit to sleep mode

■ Transit to timebase timer mode and watch mode

Document Number: 002-07872 Rev. *A

Page 25 of 83

MB90350 Series

9.19 Internal CR oscillation circuit

Value

Typ

100

—

Parameter

Symbol

Unit

Min

50

Max

Oscillation frequency

f_RC

200

100

kHz

Oscillation stabilization wait time

tstab

—

μs

Document Number: 002-07872 Rev. *A

Page 26 of 83

MB90350 Series

10. Block Diagrams

■ MB90V340A-101/102

X0

X0A*

Clock

controller

RST

X1

16LX CPU

X1A*

RAM

30 Kbytes

I/O Timer 0

FRCK0

Input

Capture

8 channels

IN7 to IN0

Output

Compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

5 channels

I/O Timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

Controller

3 channels

UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

Reload Timer

4 channels

AVCC

TIN3 to TIN0

10-bit

A/D

Converter

24 channels

AVSS

TOT3 to TOT0

AN23 to AN0

AVRH

AD15 to AD00

A21 to A16

ALE

AVRL

ADTG

10-bit

D/A

Converter

2 channels

RD

External

Bus

Interface

WRL

DA00,DA01

WRH

HRQ

HAK

8/16-bit

PPG

16 channels

PPGF to PPG0

RDY

CLK

I²C interface

2 channels

SDA0,SDA1

SCL0,SCL1

INT7 to INT0

INT15 to INT8

External

Interrupt

(INT11R to INT9R)

DMAC

Clock

CKOT

Monitor

* : MB90V340A-102 only

Document Number: 002-07872 Rev. *A

Page 27 of 83

MB90350 Series

■ MB90V340A-103/104

X0

X0A *

RST

X1

X1A*

Clock

controller/Monit

or

F²MC-16LX

Core

FRCK0

I/O Timer 0

CR oscillation

circuit

Input

Capture

8 channels

IN7 to IN0

RAM

30 Kbytes

Output

Compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

5 channels

I/O Timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

Controller

3 channels

UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

Reload

Timer

AVCC

AVSS

AN23 to AN0

AVRH

AVRL

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

Converter

24 channels

4 channels

AD15 to AD00

A23 to A16

ALE

ADTG

10-bit

D/A

Converter

2 channels

RD

WRL

WRH

External

Bus

Interface

DA01, DA00

HRQ

HAK

RDY

CLK

8/16-bit

PPG

16 channels

PPGF to PPG0

I²C interface

2 channels

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/External

Interrupt

DMA

Clock

Monitor

CKOT

* : MB90V340A-104 only

Document Number: 002-07872 Rev. *A

Page 28 of 83

MB90350 Series

■ MB90F352 (S) , MB90F351 (S) , MB90F352A (S) , MB90F352TA (S) , MB90F351A (S) , MB90F351TA (S) , MB90352A (S) ,

MB90352TA (S) , MB90351A (S) , MB90351TA (S)

X0

X0A *¹

Clock

RST

controller

16LX CPU

X1

X1A*¹

Low voltage/

CPU operation

detection

I/O Timer 0

FRCK0

reset*²

Input

Capture

6 channels

RAM

4 Kbytes

IN7 to IN4,

IN1, IN0

ROM/Flash

128 K/64

Kbytes

Output

Compare

4 channels

OUT7 to OUT4

FRCK1

Prescaler

2 channels

I/O Timer 1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

CAN

Controller

1 channel

UART

2 channels

RX1

TX1

16-bit

Reload Timer

4 channels

AVCC

TIN3, TIN1

AVSS

8/10-bit

A/D

Converter

15 channels

TOT3, TOT1

AN14 to AN0

AVRH

AD15 to AD00

A21 to A16

ALE

ADTG

RD

External

Bus

WRL

Interface

WRH

8/16-bit

PPG

PPGF to PPG8

PPG6, PPG4

HRQ

10/6 channels

HAK

RDY

CLK

I²C interface

1 channel

SDA0

SCL0

External

Interrupt

INT15 to INT8

(INT11R to INT9R)

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

Document Number: 002-07872 Rev. *A

Page 29 of 83

MB90350 Series

■ MB90F357A (S) , MB90F357TA (S) , MB90F356A (S) , MB90F356TA (S) , MB90357A (S) , MB90357TA (S) , MB90356A (S) ,

MB90356TA (S)

X0

Clock

controller/

monitor

X0A*¹

RST

16LX CPU

X1

X1A*¹

CR

oscillation

circuit

I/O Timer 0

FRCK0

Input

Capture

6 channels

Low voltage detector*²

CPU operation

detector*²

IN7 to IN4,

IN1, IN0

Output

Compare

4 channels

OUT7 to OUT4

FRCK1

RAM

4 Kbytes

I/O Timer 1

ROM/Flash

128 K/64 K

bytes

CAN

Controller

1 channel

RX1

TX1

Prescaler

2 channels

16-bit

Reload Timer

4 channels

TIN3, TIN1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

UART

2 channels

TOT3, TOT1

AVCC

AD15 to AD00

A21 to A16

ALE

AVSS

8/10-bit

A/D

Converter

15 channels

AN14 to AN0

RD

External

Bus

Interface

AVRH

ADTG

WRL

WRH

HRQ

HAK

8/16-bit

PPG

10/6 channels

PPGF to PPG8

PPG6, PPG4

RDY

CLK

SDA0

SCL0

I²C interface

1 channel

External

Interrupt

INT15 to INT8

(INT11R to INT9R)

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

Document Number: 002-07872 Rev. *A

Page 30 of 83

MB90350 Series

11. Memory Map

MB90352A (S)

MB90352TA (S)

MB90357A (S)

MB90357TA (S)

MB90F352A (S)

MB90F352TA (S)

MB90F357A (S)

MB90F357TA (S)

MB90F352 (S)

MB90351A (S)

MB90351TA (S)

MB90356A (S)

MB90356TA (S)

MB90F351A (S)

MB90F351TA (S)

MB90F356A (S)

MB90F356TA (S)

MB90F351 (S)

MB90V340A-101

MB90V340A-102

MB90V340A-103

MB90V340A-104

FFFFFFH

FF0000H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

FF0000H

FEFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FDFFFFH

External access

area

External access

area

FC0000H

FBFFFFH

FB0000H

FAFFFFH

C00100H

00FFFFH

C00100H

00FFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

ROM (image of

FF bank)

ROM (image of

FF bank)

F80000H

00FFFFH

008000H

007FFFH

008000H

007FFFH

ROM (image of

FF bank)

Peripheral

008000H

007FFFH

007900H

Peripheral

007900H

0078FFH

RAM 30 Kbytes

001100H

0010FFH

000100H

RAM 4 Kbytes

External access area

Peripheral

RAM 4 Kbytes

External access area

Peripheral

000100H

0000EFH

000000H

0000EFH

000000H

0000EFH

000000H

Peripheral

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.

Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer

declaration.

For example, an attempt to access 00C000_Haccesses the value at FFC000_Hin ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000_Hand FFFFFF_His visible in bank 00, while the image between FF0000_Hand FF7FFF_His visible

only in bank FF.

Document Number: 002-07872 Rev. *A

Page 31 of 83

MB90350 Series

12. I/O Map

Address

Register

Port 0 Data Register

Port 1 Data Register

Abbreviation Access

Resource name

Initial value

XXXXXXXX_B

00_H

01_H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

02_H

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

03_H

04_H

05_H

06_H

07_Hto 0A_H

0B_H

Reserved

Port 5 Analog Input Enable Register

Port 6 Analog Input Enable Register

ADER5

ADER6

R/W

Port 5, A/D

Port 6, A/D

11111111_B

0C_H

0D_H

Reserved

0E_H

Input Level Select Register 0

Input Level Select Register 1

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

ILSR0

ILSR1

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

R/W

Ports

00000000_B

XX000000_B

00000000_B

XX000000_B

X0000000_B

00000000_B

0F_H

10_H

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

11_H

12_H

13_H

14_H

15_H

16_H

17_Hto 19_H

1A_H

Reserved

DDRA

Reserved

SIN input Level Setting Register

W

UART2, UART3

X00XXXXX_B

1B_H

1C_H

Port 0 Pull-up Control Register

Port 1 Pull-up Control Register

Port 2 Pull-up Control Register

Port 3 Pull-up Control Register

PUCR0

PUCR1

PUCR2

PUCR3

R/W

Port 0

Port 1

Port 2

Port 3

00000000_B

1D_H

1E_H

1F_H

20_Hto 37_H

38_H

Reserved

PPG 4 Operation Mode Control Register

PPG 5 Operation Mode Control Register

PPG 4/5 Count Clock Select Register

PPGC4

PPGC5

PPG45

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bit Programmable

Pulse Generator 4/5

39_H

3A_H

Address Match

Detection 1

3B_H

Address Detect Control Register 1

PACSR1

R/W

00000000_B

3C_H

3D_H

3E_H

3F_H

40_H

41_H

42_H

43_H

PPG 6 Operation Mode Control Register

PPG 7 Operation Mode Control Register

PPG 6/7 Count Clock Select Register

PPGC6

PPGC7

PPG67

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bit Programmable

Pulse Generator 6/7

Reserved

PPG 8 Operation Mode Control Register

PPG 9 Operation Mode Control Register

PPG 8/9 Count Clock Select Register

PPGC8

PPGC9

PPG89

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bit Programmable

Pulse Generator 8/9

Reserved

(Continued)

Document Number: 002-07872 Rev. *A

Page 32 of 83

MB90350 Series

Address

44_H

Register

Abbreviation Access

Resource name

Initial value

0X000XX1_B

0X000001_B

000000X0_B

PPG A Operation Mode Control Register

PPG B Operation Mode Control Register

PPG A/B Count Clock Select Register

PPGCA

PPGCB

PPGAB

W, R/W

R/W

16-bit Programmable

Pulse Generator A/B

45_H

46_H

47_H

Reserved

48_H

PPG C Operation Mode Control Register

PPG D Operation Mode Control Register

PPG C/D Count Clock Select Register

PPGCC

PPGCD

W,R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bit Programmable

Pulse Generator C/D

49_H

4A_H

4B_H

4C_H

4D_H

4E_H

4F_H

Reserved

PPG E Operation Mode Control Register

PPG F Operation Mode Control Register

PPG E/F Count Clock Select Register

PPGCE

PPGCF

PPGEF

W,R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bit Programmable

Pulse Generator E/F

Reserved

50_H

Input Capture Control Status Register 0/1

Input Capture Edge Register 0/1

ICS01

ICE01

R/W

00000000_B

Input Capture 0/1

51_H

R/W, R

XXX0X0XX_B

52_H, 53_H

54_H

Reserved

Input Capture Control Status Register 4/5

Input Capture Edge Register 4/5

ICS45

ICE45

ICS67

ICE67

R/W

R

00000000_B

XXXXXXXX_B

00000000_B

XXX000XX_B

Input Capture 4/5

Input Capture 6/7

55_H

56_H

Input Capture Control Status Register 6/7

Input Capture Edge Register 6/7

R/W

R/W, R

57_H

58_Hto 5B_H

5C_H

5D_H

5E_H

5F_H

Reserved

Output Compare Control Status Register 4

Output Compare Control Status Register 5

Output Compare Control Status Register 6

Output Compare Control Status Register 7

Timer Control Status Register 0

Timer Control Status Register 1

Timer Control Status Register 2

Timer Control Status Register 3

A/D Control Status Register 0

A/D Control Status Register 1

A/D Data Register 0

OCS4

OCS5

R/W

R

0000XX00_B

0XX00000_B

0000XX00_B

0XX00000_B

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

000XXXX0_B

0000000X_B

00000000_B

XXXXXX00_B

00000000_B

Output Compare 4/5

Output Compare 6/7

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

OCS6

OCS7

60_H

TMCSR0

TMCSR1

TMCSR2

TMCSR3

ADCS0

ADCS1

ADCR0

ADCR1

ADSR0

ADSR1

61_H

62_H

63_H

64_H

65_H

66_H

67_H

68_H

69_H

6A_H

6B_H

6C_H

6D_H

A/D Converter

A/D Data Register 1

R

ADC Setting Register 0

R/W

ADC Setting Register 1

Low Voltage/CPU

Operation Detection

Reset

Low Voltage/CPU Operation Detection Reset

Control Register

6E_H

LVRC

R/W, W

00111000_B

(Continued)

Document Number: 002-07872 Rev. *A

Page 33 of 83

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

ROM Mirror

Initial value

6F_H

ROM Mirror Function Select Register

ROMM

W

XXXXXXX1_B

70_Hto 7F_H

Reserved

80_Hto 8F_HReserved for CAN Interface 1. Refer to “CAN Controllers”

90_Hto 9A_H

Reserved

DMA Descriptor Channel Specification

Register

9B_H

DCSR

R/W

00000000_B

DMA

9C_H

9D_H

DMA Status Register L

DMA Status Register H

DSRL

DSRH

R/W

00000000_B

Address Match

Detection 0

9E_H

9F_H

A0_H

Address Detect Control Register 0

PACSR0

DIRR

R/W

00000000_B

XXXXXXX0_B

00011000_B

Delayed Interrupt/Release Register

Delayed Interrupt

Low-power Consumption Mode Control

Register

Low Power Consumption

Control Circuit

LPMCR

W,R/W

Low Power Consumption

Control Circuit

A1_H

Clock Selection Register

CKSCR

R,R/W

11111100_B

A2_H, A3_H

A4_H

Reserved

DMA Stop Status Register

Automatic Ready Function Selection Register

External Address Output Control Register

Bus Control Signal Selection Register

Watchdog Control Register

DSSR

ARSR

HACR

ECSR

WDTC

TBTC

WTC

R/W

W

DMA

00000000_B

0011XX00_B

00000000_B

0000000X_B

XXXXX111_B

1XX00100_B

1X001000_B

A5_H

External Memory

Access

A6_H

W

A7_H

W

A8_H

R,W

W,R/W

R,R/W

Watchdog Timer

Timebase timer

Watch Timer

A9_H

Timebase Timer Control Register

Watch Timer Control Register

AA_H

AB_H

AC_H

AD_H

Reserved

DMA Enable Register L

DMA Enable Register H

DERL

DERH

R/W

00000000_B

DMA

Flash Control Status Register

(Flash Devices only. Otherwise reserved)

AE_H

AF_H

FMCS

R,R/W

Flash Memory

000X0000_B

Reserved

(Continued)

Document Number: 002-07872 Rev. *A

Page 34 of 83

MB90350 Series

Address

B0_H

Register

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

Abbreviation Access

Resource name

Initial value

00000111_B

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Reserved

ENIR1

EIRR1

ELVR1

EISSR

PSCCR

BAPL

W,R/W

B1_H

B2_H

B3_H

B4_H

B5_H

B6_H

B7_H

Interrupt Control

B8_H

B9_H

BA_H

BB_H

BC_H

BD_H

BE_H

BF_H

C0_Hto C9_H

CA_H

CB_H

CC_H

CD_H

CE_H

CF_H

D0_H

D1_H

D2_H

D3_H

D4_H

D5_H

D6_H

D7_H

D8_H

D9_H

DA_H

DB_H

External Interrupt Enable Register 1

External Interrupt Source Register 1

External Interrupt Level Register 1

External Interrupt Source Select Register

PLL/Sub clock Control register

DMA Buffer Address Pointer L

DMA Buffer Address Pointer M

DMA Buffer Address Pointer H

DMA Control Register

R/W

W

00000000_B

XXXXXXXX_B

00000000_B

XXXX0000_B

XXXXXXXX_B

00000000_B

00001000_B

External Interrupt 1

PLL

R/W

W,R/W

R/W

R,R/W

BAPM

BAPH

DMACS

IOAL

DMA

I/O Register Address Pointer L

I/O Register Address Pointer H

Data Counter L

IOAH

DCTL

Data Counter H

DCTH

SMR2

SCR2

Serial Mode Register 2

Serial Control Register 2

Reception/Transmission Data Register 2

Serial Status Register 2

RDR2/TDR2

SSR2

UART2

R,W,

R/W

DC_H

Extended Communication Control Register 2

ECCR2

000000XX_B

DD_H

DE_H

Extended Status/Control Register 2

Baud Rate Generator Register 20

Baud Rate Generator Register 21

ESCR2

BGR20

BGR21

Reserved

R/W

00000100_B

00000000_B

DF_H

E0_Hto EF_H

(Continued)

Document Number: 002-07872 Rev. *A

Page 35 of 83

MB90350 Series

Address

Register

Abbreviation Access

Resource name

Initial value

F0_Hto FF_H

External area

7900_Hto

7907_H

Reserved

7908_H

7909_H

790A_H

790B_H

790C_H

790D_H

790E_H

790F_H

7910_H

7911_H

7912_H

7913_H

7914_H

7915_H

7916_H

7917_H

7918_H

7919_H

791A_H

791B_H

791C_H

791D_H

791E_H

791F_H

7920_H

7921_H

7922_H

7923_H

Reload Register L4

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

R/W

R

XXXXXXXX_B

16-bit Programmable

Pulse

Reload Register H4

Reload Register L5

Reload Register H5

Reload Register L6

Reload Register H6

Reload Register L7

Reload Register H7

Reload Register L8

Reload Register H8

Reload Register L9

Reload Register H9

Reload Register LA

Reload Register HA

Reload Register LB

Reload Register HB

Reload Register LC

Reload Register HC

Reload Register LD

Reload Register HD

Reload Register LE

Reload Register HE

Reload Register LF

Reload Register HF

Input Capture Register 0

Input Capture Register 1

Generator 4/5

16-bit Programmable

Pulse

Generator 6/7

16-bit Programmable

Pulse

Generator 8/9

16-bit Programmable

Pulse

Generator A/B

16-bit Programmable

Pulse

Generator C/D

16-bit Programmable

Pulse

Generator E/F

R

Input Capture 0/1

Input Capture 4/5

R

7924_Hto

7927_H

Reserved

7928_H

7929_H

792A_H

792B_H

Input Capture Register 4

Input Capture Register 5

IPCP4

IPCP5

R

XXXXXXXX_B

(Continued)

Document Number: 002-07872 Rev. *A

Page 36 of 83

MB90350 Series

Address

792C_H

792D_H

792E_H

792F_H

Register

Input Capture Register 6

Abbreviation Access

Resource name

Initial value

XXXXXXXX_B

IPCP6

IPCP7

R

Input Capture Register 6

Input Capture Register 7

Input Capture 6/7

7930_Hto

7937_H

Reserved

7938_H

7939_H

793A_H

793B_H

793C_H

793D_H

793E_H

793F_H

7940_H

7941_H

7942_H

7943_H

7944_H

7945_H

7946_H

7947_H

7948_H

7949_H

794A_H

794B_H

794C_H

794D_H

794E_H

794F_H

7950_H

7951_H

7952_H

7953_H

Output Compare Register 4

Output Compare Register 5

Output Compare Register 6

Output Compare Register 7

Timer Data Register 0

OCCP4

OCCP5

OCCP6

OCCP7

TCDT0

TCCSL0

TCCSH0

TCDT1

TCCSL1

TCCSH1

R/W

W, R/W

R/W

R,R/W

XXXXXXXX_B

00000000_B

Output Compare 4/5

Output Compare 6/7

I/O Timer 0

Timer Data Register 0

00000000_B

Timer Control Status Register 0

Timer Data Register 1

00000000_B

0XXXXXXX_B

00000000_B

Timer Data Register 1

00000000_B

I/O Timer 1

Timer Control Status Register 1

00000000_B

0XXXXXXX_B

XXXXXXXX_B

00000000_B

TMR0/TMRL

R0

Timer Register 0/Reload Register 0

Timer Register 1/Reload Register 1

Timer Register 2/Reload Register 2

Timer Register 3/Reload Register 3

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

TMR1/TMRL

R1

TMR2/TMRL

R2

TMR3/TMRL

R3

Serial Mode Register 3

SMR3

SCR3

Serial Control Register 3

00000000_B

Reception/Transmission Data Register 3

Serial Status Register 3

RDR3/TDR3

SSR3

00000000_B

00001000_B

UART3

R,W,

R/W

7954_H

Extended Communication Control Register 3

ECCR3

000000XX_B

7955_H

7956_H

7957_H

Extended Status/Control Register 3

Baud Rate Generator Register 30

Baud Rate Generator Register 31

ESCR3

BGR30

BGR31

R/W

00000100_B

00000000_B

7958_H,

7959_H

Reserved

(Continued)

Document Number: 002-07872 Rev. *A

Page 37 of 83

MB90350 Series

Address

Register

Abbreviation Access

Resource name

Initial value

7960_H

Clock Monitor Function Control Register

CSVCR

Reserved

CDMR

Reserved

R, R/W

Clock Monitor

00011100_B

7961_Hto

796D_H

796E_H

796F_H

7970_H

7971_H

7972_H

7973_H

7974_H

7975_H

7976_H

7977_H

7978_H

CAN Direct Mode Register

R/W

CAN Clock Sync

XXXXXXX0_B

I²C Bus Status Register 0

I²C Bus Control Register 0

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

R

W,R/W

R/W

00000000_B

11111111_B

00111111_B

00000000_B

01111111_B

00000000_B

I²C 10-bit Slave Address Register 0

I²C Interface 0

I²C 10-bit Slave Address Mask Register 0

I²C 7-bit Slave Address Register 0

I²C 7-bit Slave Address Mask Register 0

I²C data register 0

ISMK0

IDAR0

7979_H,

797A_H

Reserved

ICCR0

Reserved

797B_H

I²C Clock Control Register 0

R/W

I²C Interface 0

00011111_B

797C_Hto

79A1_H

79A2_H

79A3_H

79A4_H

Flash Write Control Register 0

Flash Write Control Register 1

Sector Change Setting Register

FWR0

FWR1

SSR0

R/W

00000000_B

00XXXXX0_B

Dual Operation

Flash

79A5_Hto

79C1_H

Reserved

79C2_H

Setting Prohibited

Reserved

79C3_Hto

79DF_H

79E0_H

79E1_H

79E2_H

79E3_H

79E4_H

79E5_H

79E6_H

79E7_H

79E8_H

Detect Address Setting Register 0

Detect Address Setting Register 1

Detect Address Setting Register 2

PADR0

PADR1

PADR2

R/W

XXXXXXXX_B

R/W

Address Match

Detection 0

79E9_Hto

79EF_H

Reserved

(Continued)

Document Number: 002-07872 Rev. *A

Page 38 of 83

MB90350 Series

(Continued)

Address

79F0_H

79F1_H

79F2_H

79F3_H

79F4_H

79F5_H

79F6_H

79F7_H

79F8_H

Register

Abbreviation Access

Resource name

Initial value

XXXXXXXX_B

Detect Address Setting Register 3

Detect Address Setting Register 4

Detect Address Setting Register 5

PADR3

PADR4

PADR5

R/W

Address Match

Detection 1

79F9_Hto

7BFF_H

Reserved

7C00_Hto

7CFF_H

Reserved for CAN Interface 1. Refer to “CAN Controllers”

Reserved

7D00_Hto

7DFF_H

7E00_Hto

7FFF_H

Notes :

■ Initial value of “X” represents unknown value.

■ Any write access to reserved addresses in I/O map should not be performed.Aread access to reserved addresses results reading “X”.

Document Number: 002-07872 Rev. *A

Page 39 of 83

MB90350 Series

13. CAN Controllers

The CAN controller has the following features :

■ Conforms to CAN Specification Version 2.0 Part A and B

❐ Supports transmission/reception in standard frame and extended frame formats

■ Supports transmitting of data frames by receiving remote frames

■ 16 transmitting/receiving message buffers

❐ 29-bit ID and 8-byte data

❐ Multi-level message buffer configuration

■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance

mask

❐ Two acceptance mask registers in either standard frame format or extended frame formats

■ Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)

List of Control Registers

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN1

000080_H

000081_H

000082_H

000083_H

000084_H

000085_H

000086_H

000087_H

000088_H

000089_H

00008A_H

00008B_H

00008C_H

00008D_H

00008E_H

00008F_H

007D00_H

007D01_H

007D02_H

007D03_H

007D04_H

007D05_H

007D06_H

007D07_H

007D08_H

007D09_H

007D0A_H

007D0B_H

00000000_B

Message buffer enable register

Transmit request register

Transmit cancel register

00000000_B

Transmission complete register

Receive complete register

Remote request receiving register

Receive overrun register

R/W

00000000_B

RCR

00000000_B

RRTRR

ROVRR

RIER

00000000_B

Reception interrupt

enable register

00000000_B

R/W, W

R/W, R

0XXXX0X1_B

00XXX000_B

Control status register

Last event indicator register

Receive/transmit error counter

Bit timing register

CSR

000X0000_B

XXXXXXXX_B

LEIR

R/W

R

00000000_B

RTEC

11111111_B

X1111111_B

BTR

R/W

XXXXXXXX_B

IDE register

IDER

00000000_B

Transmit RTR register

TRTRR

(Continued)

Document Number: 002-07872 Rev. *A

Page 40 of 83

MB90350 Series

(Continued)

Address

Register

Abbreviation

RFWTR

Access

R/W

Initial Value

CAN1

007D0C_H

007D0D_H

007D0E_H

007D0F_H

007D10_H

007D11_H

007D12_H

007D13_H

007D14_H

007D15_H

007D16_H

007D17_H

007D18_H

007D19_H

007D1A_H

007D1B_H

Remote frame receive waiting

register

XXXXXXXX_B

Transmit interrupt

enable register

00000000_B

TIER

R/W

XXXXXXXX_B

Acceptance mask

select register

AMSR

AMR0

AMR1

R/W

XXXXXXXX_B

Acceptance mask register 0

Acceptance mask register 1

XXXXXXXX_B

Document Number: 002-07872 Rev. *A

Page 41 of 83

MB90350 Series

List of Message Buffers (ID Registers)

Abbreviation

Address

CAN1

Register

Access

Initial Value

007C00_H

to

007C1F_H

XXXXXXXX_B

to

XXXXXXXX_B

General-purpose RAM

ID register 0

—

R/W

007C20_H

007C21_H

007C22_H

007C23_H

007C24_H

007C25_H

007C26_H

007C27_H

007C28_H

007C29_H

007C2A_H

007C2B_H

007C2C_H

007C2D_H

007C2E_H

007C2F_H

007C30_H

007C31_H

007C32_H

007C33_H

007C34_H

007C35_H

007C36_H

007C37_H

007C38_H

007C39_H

007C3A_H

007C3B_H

007C3C_H

007C3D_H

007C3E_H

007C3F_H

007C40_H

007C41_H

007C42_H

007C43_H

XXXXXXXX_B

IDR0

R/W

XXXXXXXX_B

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

ID register 8

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

IDR8

XXXXXXXX_B

(Continued)

Document Number: 002-07872 Rev. *A

Page 42 of 83

MB90350 Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007C44_H

007C45_H

007C46_H

007C47_H

007C48_H

007C49_H

007C4A_H

007C4B_H

007C4C_H

007C4D_H

007C4E_H

007C4F_H

007C50_H

007C51_H

007C52_H

007C53_H

007C54_H

007C55_H

007C56_H

007C57_H

007C58_H

007C59_H

007C5A_H

007C5B_H

007C5C_H

007C5D_H

007C5E_H

007C5F_H

XXXXXXXX_B

ID register 9

IDR9

R/W

XXXXXXXX_B

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

XXXXXXXX_B

Document Number: 002-07872 Rev. *A

Page 43 of 83

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX_B

007C60_H

007C61_H

007C62_H

007C63_H

007C64_H

007C65_H

007C66_H

007C67_H

007C68_H

007C69_H

007C6A_H

007C6B_H

007C6C_H

007C6D_H

007C6E_H

007C6F_H

007C70_H

007C71_H

007C72_H

007C73_H

007C74_H

007C75_H

007C76_H

007C77_H

007C78_H

007C79_H

007C7A_H

007C7B_H

007C7C_H

007C7D_H

007C7E_H

007C7F_H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

007C80_H

to

007C87_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 0

(8 bytes)

DTR0

R/W

(Continued)

Document Number: 002-07872 Rev. *A

Page 44 of 83

MB90350 Series

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C88_H

to

007C8F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 1

(8 bytes)

DTR1

R/W

007C90_H

to

007C97_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 2

(8 bytes)

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

DTR14

DTR15

R/W

007C98_H

to

007C9F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 3

(8 bytes)

007CA0_H

to

007CA7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 4

(8 bytes)

007CA8_H

to

007CAF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 5

(8 bytes)

007CB0_H

to

007CB7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 6

(8 bytes)

007CB8_H

to

007CBF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 7

(8 bytes)

007CC0_H

to

007CC7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 8

(8 bytes)

007CC8_H

to

007CCF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 9

(8 bytes)

007CD0_H

to

007CD7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 10

(8 bytes)

007CD8_H

to

007CDF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 11

(8 bytes)

007CE0_H

to

007CE7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 12

(8 bytes)

007CE8_H

to

007CEF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 13

(8 bytes)

007CF0_H

to

007CF7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 14

(8 bytes)

007CF8_H

to

007CFF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 15

(8 bytes)

Document Number: 002-07872 Rev. *A

Page 45 of 83

MB90350 Series

14. Interrupt Factors, Interrupt Vectors, Interrupt Control Register

EI²OS

Interrupt control

register

Interrupt vector

DMA ch

number

Interrupt cause

corre-

sponding

Number

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

#39

#40

#41

#42

Address

FFFFDC_H

FFFFD8_H

FFFFD4_H

FFFFD0_H

FFFFCC_H

FFFFC8_H

FFFFC4_H

FFFFC0_H

FFFFBC_H

FFFFB8_H

FFFFB4_H

FFFFB0_H

FFFFAC_H

FFFFA8_H

FFFFA4_H

FFFFA0_H

FFFF9C_H

FFFF98_H

FFFF94_H

FFFF90_H

FFFF8C_H

FFFF88_H

FFFF84_H

FFFF80_H

FFFF7C_H

FFFF78_H

FFFF74_H

FFFF70_H

FFFF6C_H

FFFF68_H

FFFF64_H

FFFF60_H

FFFF5C_H

FFFF58_H

FFFF54_H

Number

Address

Reset

N

—

0

—

INT9 instruction

Exception

N

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B0_H

0000B1_H

0000B2_H

0000B3_H

0000B4_H

0000B5_H

0000B6_H

0000B7_H

0000B8_H

0000B9_H

0000BA_H

0000BB_H

0000BC_H

0000BD_H

0000BE_H

0000BF_H

Reserved

N

CAN 1 RX / Input Capture 6

CAN 1 TX/NS / Input Capture 7

I²C

Y1

N

Reserved

N

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

PPG 4/5

Y1

N

1

2

—

3

PPG 6/7

N

PPG 8/9/C/D

N

PPG A/B/E/F

N

Timebase Timer

External Interrupt 8 to 11

Watch Timer

N

Y1

N

—

4

External Interrupt 12 to 15

A/D Converter

Y1

N

5

I/O Timer 0 / I/O Timer 1

Input Capture 4/5

Output Compare 4/5

Input Capture 0/1

Output Compare 6/7

Reserved

—

6

Y1

N

7

8

9

10

11

12

13

14

15

—

Reserved

N

UART 3 RX

Y2

Y1

Y2

Y1

N

UART 3 TX

UART 2 RX

UART 2 TX

Flash Memory

Delayed interrupt

N

Y1 : Usable

Y2 : Usable, with EI²OS stop function

N

: Unusable

Document Number: 002-07872 Rev. *A

Page 46 of 83

MB90350 Series

Notes :

■ The peripheral resources sharing the ICR register have the same interrupt level.

■ When two peripheral resources share the ICR register, only one can use EI²OSat a time.

■ When either of the two peripheral resources sharing the ICR register specifies EI²OS, the other one cannot use interrupts.

Document Number: 002-07872 Rev. *A

Page 47 of 83

MB90350 Series

15. Electrical Characteristics

15.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V_CC

AV_CC

AVRH

V_I

V_SS 0.3 V_SS 6.0

V

2

Power supply voltage*¹

V

V_CC AV_CC

*

V

AV_CC≥ AVRH*²

Input voltage*¹

Output voltage*¹

V

*3

*5

*4

V_O

V

Maximum Clamp Current

I_CLAMP

|I_CLAMP

I_OL

4.0

—

4.0

40

mA

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

|

—

15

I_OLAV

I_OL

I_OLAV

I_OH

—

4

—

100

50

—

15

4

100

50

I_OHAV

I_OH

I_OHAV

—

MB90F351(S), MB90F352(S)

105 °C < T_A≤ 125 °C,

Normal operation : maximum

frequency 16 MHz

—

240

mW

Power consumption

P_D

MB90F351(S), MB90F352(S)

40 °C < T_A≤ 105 °C,

Normal operation : maximum

frequency 24 MHz

320

—

320

mW Device other than above

°C

40

55

105

125

150

Operating temperature

Storage temperature

T_A

°C

*6

T_STG

(Continued)

Document Number: 002-07872 Rev. *A

Page 48 of 83

MB90350 Series

(Continued)

*1: This parameter is based on V_SS AV_SS 0 V

*2: Set AV_CCand V_CCto the same voltage. Make sure that AV_CCdoes not exceed V_CCand that the voltage at the analog inputs

does not exceed AV_CCwhen the power is switched on.

*3: V_Iand V_Oshould not exceed V_CC 0.3 V. V should not exceed the specified ratings. However if the maximum current to/from

I

an input is limited by some means with external components, the I

rating supersedes the V rating.

I

CLAMP

*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67

*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,

P50 to P56 (for evaluation device : P50 to P55) , P60 to P67

• Use within recommended operating conditions.

• Use at DC voltage (current)

^{• The}B signal should always be applied a limiting resistance placed between the B signal and the microcontroller.

^{• The value of the limiting resistance should be set so that when the}B signal is applied the input current to the microcontroller

pin does not exceed rated values, either instantaneously or for prolonged periods.

^{• Note that when the microcontroller drive current is low, such as in the power saving modes, the}B input potential may pass

through the protective diode and increase the potential at the V_CCpin, and this may affect other devices.

^{• Note that if a}B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided

from the pins, so that incomplete operation may result.

• Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting power supply

voltage may not be sufficient to operate the power-on reset.

^{• Care must be taken not to leave the}B input pin open.

• Sample recommended circuits:

■ Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

N-ch

B input (0 V to 16 V)

R

^{*6 : If used exceeding T}_A 105 °C, be sure to contact sales for reliability limitations.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in

excess of absolute maximum ratings. Do not exceed these ratings.

Document Number: 002-07872 Rev. *A

Page 49 of 83

MB90350 Series

15.2 Recommended Operating Conditions

(V_SS AV_SS 0 V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Under normal operation

Min

Max

4.0

5.0

5.5

V

Under normal operation, when not using the A/D

converter and not Flash programming.

3.5

5.0

5.5

V_CC

,

Power supply voltage

AV_CC

4.5

3.0

5.0

—

5.5

V

When External bus is used.

Maintains RAM data in stop mode

Use a ceramic capacitor or capacitor of better AC

μF characteristics. Bypass capacitor at the V_CCpin

Smooth capacitor

C_S

T_A

0.1

—

1.0

should be greater than this capacitor.

40

—

105

125

°C MB90F352(S) f_CP≤ 24MHz

Operating temperature

*, MB90F352(S) f_CP≤ 16MHz,

Devices with A-suffix

°C

^{* : If used exceeding T}_A 105 °C, be sure to contact sales for reliability limitations.

■ C Pin Connection Diagram

C

CS

Operation guaranteed range

24

16

MB90F351(S),

MB90F352(S)

Device other

than above

− 40

+105

+125

Operation temperature TA (°C)

WARNING:

The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their representatives beforehand.

Document Number: 002-07872 Rev. *A

Page 50 of 83

MB90350 Series

15.3 DC Characteristics

(MB90F352(S)/MB90F351(S): T_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter Symbol

Condition

Unit

Remarks

Min

Typ

Max

Pin inputs if CMOS

hysteresis input levels are

selected (except P12, P15,

P44, P45, P50)

V_IHS

—

0.8 V_CC

—

V_CC 0.3

V

Pin inputs if

AUTOMOTIVE input

levels are selected

V_IHA

—

0.8 V_CC

—

V_CC 0.3

V

Input H

voltage

(At V_CC

^{5 V} 10%)

Pin inputs if TTL input levels

are selected

V_IHT

V_IHS

—

2.0

—

V_CC 0.3

V



P12, P15, P50 inputs if CMOS

input levels are selected

0.7 V_CC

P44, P45 inputs if CMOS

hysteresis input levels are

selected

V_IHI

—

0.7 V_CC

—

V_CC 0.3

V

RST input pin (CMOS

hysteresis)

V_IHR

V_IHM

—

0.8 V_CC

—

V_CC 0.3

V

V_CC 0.3

MD input pin

Pin inputs if CMOS

hysteresis input levels are

selected (except P12, P15,

P44, P45, P50)

V_ILS

—

V_SS 0.3

—

0.2 V_CC

V

Pin inputs if

AUTOMOTIVE input

levels are selected

V_ILA

0.5 V_CC

Input L

voltage

(At V_CC

^{5 V} 10%)

Pin inputs if TTL

input levels are selected

V_ILT

V_ILS

—

V_SS 0.3

—

0.8

V



P12, P15, P50 inputs if CMOS

input levels are selected

0.3 V_CC

P44, P45 inputs if CMOS

hysteresis input levels are

selected

V_ILI

—

V_SS 0.3

—

0.3 V_CC

V

RST input pin (CMOS

hysteresis)

V_ILR

V_ILM

V_OH

—

V_SS 0.3

V_CC 0.5

—

0.2 V_CC

V_SS 0.3

—

V

MD input pin

Output H

voltage

Normal

outputs

V_CC 4.5 V,

I_OH 4.0 mA

Output H

voltage

I²C current V_CC 4.5 V,

V_OHI

V_CC 0.5

—

V

outputs

I_OH 3.0 mA

(Continued)

Document Number: 002-07872 Rev. *A

Page 51 of 83

MB90350 Series

(MB90F352(S)/MB90F351(S): T_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Output L

Symbol

Normal

outputs

I²C current

outputs

Condition

Unit

Remarks

Min

Typ

Max

V_CC 4.5 V,

V_OL

V_OLI

I_IL

—

0.4

V

voltage

I_OL 4.0 mA

Output L

voltage

V_CC 4.5 V,

—

0.4

1

I_OL 3.0 mA

Input leak

current

V_CC 5.5 V,

—

 1

µA

V

_SS<V_I<V_CC

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P37,

RST

Pull-up

resistance

R_UP

—

25

50

100

kΩ

Pull-down

resistance

Except Flash

memory devices

R_DOWN

MD2

25

—

50

48

100

60

kΩ

V_CC 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

mA

V_CC 5.0 V,

Flash memory

devices

I_CC

Internal frequency : 24 MHz,

At writing FLASH memory.

—

53

58

25

65

70

35

mA

V_CC 5.0 V,

Flash memory

devices

Internal frequency : 24 MHz,

At erasing FLASH memory.

V_CC 5.0 V,

I_CCS

Internal frequency : 24 MHz,

At Sleep mode.

Devices

mA without

“T”-suffix

—

0.3

0.4

0.8

1.0

V_CC 5.0 V,

I_CTS

Internal frequency : 2 MHz,

At Main Timer mode

Power supply

current

V_CC

Devices

mA

with “T”-suffix

V_CC 5.0 V,

I_CTSPLL

Internal frequency : 24 MHz,

At PLL Timer mode,

—

4

7

mA

6

^{external frequency} 4 MHz

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub clock operation

T_A= 25C

I_CCL

—

70

140

μA

(Continued)

Document Number: 002-07872 Rev. *A

Page 52 of 83

MB90350 Series

(MB90F352(S)/MB90F351(S): T_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

V_CC= 5.0 V,

Unit

Remarks

Min

Typ

Max

Internal frequency: 8 kHz,

During operating clock

monitor function,

MB90F356A

MB90F357A

MB90356A

MB90357A

—

100

200

µA

At sub clock operation

T_A= 25C

V_CC= 5.0 V,

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

Internal CR oscillation/

4 division,

At sub clock operation

T_A= 25C

—

100

120

200

240

µA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub clock operation

T_A= 25C

I_CCL

Power supply

current

V

_CC= 5.0 V,

V_CC

Internal frequency: 8 kHz,

During operating clock

monitor function,

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

—

150

300

µA

At sub clock operation

T_A= 25C

V_CC= 5.0 V,

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

Internal CR oscillation/

4 division,

At sub clock operation

T_A= 25C

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub sleep

I_CCLS

—

20

50

μA

T_A= 25C

(Continued)

Document Number: 002-07872 Rev. *A

Page 53 of 83

MB90350 Series

(MB90F352(S)/MB90F351(S): T_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

V_CC= 5.0 V,

Unit

Remarks

Min

Typ

Max

Internal frequency: 8 kHz,

During operating clock monitor

function,

MB90F356A

MB90F357A

MB90356A

MB90357A

—

60

200

μA

At sub sleep

T_A= 25C

V

_CC= 5.0 V,

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

Internal CR oscillation/

4 division,

At sub sleep

T_A= 25C

—

60

70

200

150

μA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub sleep

I_CCLS

T_A= 25C

Power supply

current

V

_CC= 5.0 V,

V_CC

Internal frequency: 8 kHz,

During operating clock

monitor function,

At sub sleep

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

—

110

300

μA

T_A= 25C

V_CC= 5.0 V,

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

Internal CR oscillation/

4 division,

At sub sleep

T_A= 25C

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At watch mode

I_CCT

—

10

35

μA

T_A= 25C

(Continued)

Document Number: 002-07872 Rev. *A

Page 54 of 83

MB90350 Series

(Continued)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

V_CC= 5.0 V,

Unit

Remarks

Min

Typ

Max

Internal frequency: 8 kHz,

During operating clock monitor

function,

MB90F356A

MB90F357A

MB90356A

MB90357A

—

25

150

μA

At watch mode

T_A= 25C

V

_CC= 5.0 V,

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

Internal CR oscillation/

4 division,

At watch mode

T_A= 25C

—

25

60

150

140

μA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

V_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At watch mode

I_CCT

Power supply

current

T_A= 25C

V_CC

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock monitor

function,

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

—

80

250

μA

At watch mode

T_A= 25C

V_CC= 5.0 V,

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

Internal CR oscillation/

4 division,

At watch mode

T_A= 25C

—

80

7

250

25

Devices

μA without

V_CC 5.0 V,

At Stop mode,

T_A 25C

“T”-suffix

I_CCH

Devices

with “T”-suffix

—

60

5

130

15

μA

Other than C, AV_CC, AV_SS

AVRH, V_CC, V_SS

,

Input capacity

C_IN

—

pF

,

Document Number: 002-07872 Rev. *A

Page 55 of 83

MB90350 Series

15.4 AC Characteristics

15.4.1 Clock Timing

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

1/2 (at PLL stop)

Min

Typ

Max

3

—

16

MHz

When using an oscillation circuit

1 multiplied PLL

When using an oscillation circuit

4

—

16

12

8

2 multiplied PLL

When using an oscillation circuit

X0, X1

3 multiplied PLL

When using an oscillation circuit

4

4 multiplied PLL

When using an oscillation circuit

4

6

6 multiplied PLL

When using an oscillation circuit

—

3

4

f_C

Clock frequency

1/2 (at PLL stop),

When using an external clock

24

12

8

1 multiplied PLL

When using an external clock

4

2 multiplied PLL

When using an external clock

4

X0

3 multiplied PLL

When using an external clock

4

4 multiplied PLL

When using an external clock

4

6

6 multiplied PLL

When using an external clock

—

4

f^CL

X0A, X1A

X0, X1

X0

—

62.5

41.67

10

32.768

—

100

333

—

kHz

ns

When using an oscillation circuit

When using an external clock

t_CYL

Clock cycle time

—

ns

t^CYLL

X0A, X1A

X0

30.5

—

s

ns

P_WH, P_WL

10

—

Input clock pulse width

Duty ratio is about 30% to 70%.

When using an external clock

P

_WHL, P_WLL

X0A

5

15.2

—

s

Input clock rise and fall

time

t

_CR, t_CF

X0

—

5

ns

(Continued)

Document Number: 002-07872 Rev. *A

Page 56 of 83

MB90350 Series

(Continued)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

MB90F352/(S), MB90F351/(S)

When using main clock

(T_A≤ 105 °C)

MB90F352/(S), MB90F351/(S)

When using main clock

(T_A≤ 125 °C)

24

1.5

—

MHz

Internal operating clock

frequency

(machine clock)

f_CP

f_CPL

t_CP

—

16

Device other than above,

When using main clock

1.5

—

24

50

8.192

kHz When using sub clock

MB90F352/(S), MB90F351/(S)

When using main clock

(T_A≤ 105 °C)

MB90F352/(S), MB90F351/(S)

41.67

62.5

—

666

ns

Internal operating clock

cycle time

(machine clock)

When using main clock

(T_A≤ 125 °C)

Device other than above,

When using main clock

41.67

20

—

666

—

ns

t_CPL

122.1

s

When using sub clock

■ Clock Timing

t

CYL

0.8 VCC

X0

0.2 VCC

P

WH

PWL

t

CF

tCR

t

CYLL

0.8 VCC

0.2 VCC

X0A

P

WHL

PWLL

t

CF

tCR

Document Number: 002-07872 Rev. *A

Page 57 of 83

MB90350 Series

■ PLL guaranteed operation range

Guaranteed operation range

Guaranteed PLL operation range (CS2=1)

5.5

4.5

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range (CS2=0)

1.5

4

8

20

24

Internal clock f_CP(MHz)

Guaranteed operation range of MB90350 series

CS2(bit0 of PSCCR register) = 0

Guaranteed oscillation frequency range

4 multiplied 3 multiplied 2 multiplied

(CS=11) (CS=10) (CS=01)

1 multiplied

(CS=00)

20

16

12

8

×1/2

(PLL off)

4.0

1.5

3

4

8

12

20

24

16

External clock f_C(MHz) *¹

CS2(bit0 of PSCCR register) = 1

Guaranteed oscillation frequency range

6 multiplied 4 multiplied

(CS=10) (CS=01)

2 multiplied

(CS=00)

24

16

12

8

×1/2

(PLL off)

4.0

1.5

3

4

8

12

24

16

External clock f_C(MHz) *²

*1 : Guaranteed 1 multiplied PLL operation range is 4.0 MHz to 20 MHz.

*2 : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.

External clock frequency and internal operation clock frequency

Document Number: 002-07872 Rev. *A

Page 58 of 83

MB90350 Series

15.4.2 Reset Standby Input

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

500

—

ns

Under normal operation

In Stop mode, Sub Clock

mode, Sub Sleep mode and

Watch mode

Oscillation time of oscillator*

—

μs

Reset input time

t_RSTL

RST

 100 μs

In Main timer mode and PLL

timer mode

100

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators, the oscillation time

is between hundreds of μs to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation:

tRSTL

RST

0.2 VCC

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100 μs

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

Document Number: 002-07872 Rev. *A

Page 59 of 83

MB90350 Series

15.4.3 Power On Reset

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t_R

V_CC

ms

—

t_OFF

—

Due to repetitive operation

tR

2.7 V

VCC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you start up smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

VCC

We recommend the slope for

a rise of 50 mV/ms maximum.

3 V

Holds RAM data

VSS

15.4.4 Clock Output Timing

^(T_A 40 °C to 105 °C, V_CC 5.0 V  10%, V_SS 0.0 V, f_CP≤ 24 MHz)

Value

Min

Parameter

Cycle time

CLK ↑ → CLK ↓

Symbol

CLK

Condition

Unit

Remarks

Max

—

62.5

41.67

20

ns

f_CP 16 MHz

f_CP 24 MHz

f_CP 16 MHz

f_CP 24 MHz

t_CYC

—

t_CHCL

13

—

tCYC

tCHCL

2.4 V

CLK

0.8 V

Document Number: 002-07872 Rev. *A

Page 60 of 83

MB90350 Series

15.4.5 Bus Timing (Read)

(T_A= –40C to +105C, V_CC= 5.0 V  10 %, V_SS= 0.0 V, f_CP≤ 24 MHz)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

ALE pulse width

t_LHLL

ALE

t_CP/2  10

—

ns

ALE, A21 to

A16, AD15 to

AD00

Valid address → ALE  time

ALE  → Address valid time

Valid address → RD  time

t_AVLL

t

_CP/2  20

_CP/2  15

t_CP 15

—

ns

ALE, AD15 to

AD00

t_LLAX

t

A21 toA16,

t_AVRLAD15 to AD00,

RD

A21 to A16,

t_AVDV

Valid address → Valid data input

RD pulse width

5 t_CP/2  60

ns

AD15 to AD00

t_RLRHRD

(n*+3/2) t_CP 20

—

RD, AD15 to

RD  → Valid data input

t_RLDV

AD00

—

(n*+3/2) t_CP 50 ns

RD, AD15 to

RD  → Data hold time

t_RHDX

AD00

0

—

ns

RD  → ALE  time

t_RHLHRD, ALE

t_CP/2  15

t_CP/2  10

—

ns

RD  → Address valid time

t_RHAXRD, A21 to A16

A21 to A16,

t_AVCHAD15 to AD00,

CLK

Valid address → CLK  time

t_CP/2  16

—

ns

RD  → CLK  time

ALE  → RD  time

t_RLCHRD, CLK

t_CP/2  15

—

ns

t_LLRL

ALE, RD

* : n: number of ready cycles

Document Number: 002-07872 Rev. *A

Page 61 of 83

MB90350 Series

For 1 cycle of auto-ready

tRLCH

tAVCH

2.4 V

CLK

tLLAX

tAVLL

tLHLL

tRHLH

2.4 V

0.8 V

2.4 V

ALE

RD

tAVRL

tRLRH

2.4 V

0.8 V

tLLRL

tRHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tRLDV

tRHDX

tAVDV

2.4 V

0.8 V

V_IH

2.4 V

0.8 V

V_IH

V_IL

AD15 to AD00

Address

Read data

V_IL

Document Number: 002-07872 Rev. *A

Page 62 of 83

MB90350 Series

15.4.6 Bus Timing (Write)

(T_A= –40C to +105C, V_CC= 5.0 V  10 %, V_SS= 0.0 V, f_CP≤ 24 MHz)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

—

A21 to A16, AD15

to AD00, WR

Valid address → WR  time

WR pulse width

t_AVWL

^t_CP15

ns

t_WLWHWR

AD15 to AD00,

(n*+3/2)t_CP 20

—

Valid data output → WR  time

t_DVWH

—

WR

—

AD15 to AD00,

WR

WR  → Data hold time

t_WHDX

15

—

ns

WR  → Address valid time

WR  → ALE  time

t_WHAXA21 to A16, WR

t_WHLHWR, ALE

t_CP/2  10

t_CP/2  15

—

ns

WR  → CLK  time

t_WLCHWR, CLK

* : n: Number of ready cycles

For 1 cycle of auto-ready

tWLCH

2.4 V

CLK

tWHLH

2.4 V

ALE

tAVWL

tWLWH

2.4 V

WR (WRL, WRH)

0.8 V

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tDVWH

tWHDX

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

0.8 V

Document Number: 002-07872 Rev. *A

Page 63 of 83

MB90350 Series

15.4.7 Ready Input Timing

(T_A= –40C to +105C, V_CC= 5.0 V  10 %, V_SS= 0.0 V, f_CP≤ 24 MHz)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

45

32

0

Max

—

ns

f_CP 16 MHz

f_CP 24 MHz

RDY set-up time

RDY hold time

t_RYHS

t_RYHH

RDY

—

Note : If the RDY set-up time is insufficient, use the auto-ready function.

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

RDY

V_IH

(When WAIT is not used.)

RDY

(When WAIT is used.)

V_IL

Document Number: 002-07872 Rev. *A

Page 64 of 83

MB90350 Series

15.4.8 Hold Timing

(T_A= –40C to +105C, V_CC= 5.0 V  10 %, V_SS= 0.0 V, f_CP≤ 24 MHz)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

30

Max

t_CP

Pin floating → HAK  time

t_XHAL

HAK

ns

—

HAK  time → Pin valid time t_HAHV

t_CP

2 t_CP

Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.

2.4 V

HAK

0.8 V

tHAHV

tXHAL

Hi-Z

2.4 V

0.8 V

2.4 V

0.8 V

Each pin

Document Number: 002-07872 Rev. *A

Page 65 of 83

MB90350 Series

15.4.9 UART 2/3

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

^{(Device other than above: T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t_SCYC

t_SLOV

SCK2, SCK3

8 t_CP

*

—

ns

SCK2, SCK3,

SOT2, SOT3

SCK ↓ → SOT delay time

80

100

60

80

—

Internal shift clock

CL

^mo^de8^o0^up^tpF^u^{t p}1ⁱⁿT^sT^aL^re

SCK2, SCK3,

SIN2, SIN3

Valid SIN → SCK ↑

t_IVSH

ns

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

t_SHIX

t_SHSL

t_SLSH

—

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK2, SCK3

4 t_CP

—

ns

SCK2, SCK3,

SOT2, SOT3

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t_SLOV

t_IVSH

t_SHIX

External shift clock

—

60

150

—

ns

CL

^mo^de8^o0^up^tpF^u^{t p}1ⁱⁿT^sT^aL^re

SCK2, SCK3,

SIN2, SIN3

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

—

* : Refer to “ (1) Clock timing” rating for t_CP(internal operating clock cycle time).

Notes :

■ AC characteristic in CLK synchronized mode.

■ C_Lis load capacity value of pins when testing.

■ Internal Shift Clock Mode

tSCYC

2.4 V

SCK

SOT

0.8 V

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

V_IH

V_IL

V_IH

V_IL

SIN

Document Number: 002-07872 Rev. *A

Page 66 of 83

MB90350 Series

■ External Shift Clock Mode

tSLSH

tSHSL

V_IH

SCK

V_IL

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

V_IH

V_IL

V_IH

V_IL

15.4.10 Trigger Input Timing

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

(MB90F352(S)/MB90F351(S): T_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

(Device other than above: T  40 °C to 125 °C, V_CC 5.0 V  10%, f ≤ 24 MHz, V_SS AV_SS 0 V)

A

CP

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

INT8 to INT15,

INT9R to INT11R,

ADTG

t_TRGH

t_TRGL

Input pulse width

—

5 t_CP

—

ns

V_IH

INT8 to INT15,

INT9R to INT11R,

ADTG

V_IL

tTRGH

tTRGL

Document Number: 002-07872 Rev. *A

Page 67 of 83

MB90350 Series

15.4.11 Timer Related Resource Input Timing

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

(Device other than above: T  40 °C to 125 °C, V_CC 5.0 V  10%, f ≤ 24 MHz, V_SS AV_SS 0 V)

A

CP

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

t_TIWH

t_TIWL

TIN1, TIN3,

IN0, IN1,

IN4 to IN7

Input pulse width

—

4 t_CP

—

ns

V_IH

TIN1, TIN3,

IN0, IN1,

V_IL

IN4 to IN7

tTIWH

tTIWL

15.4.12 Timer Related Resource Output Timing

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

(MB90F352(S)/MB90F351(S): T_A 40 °C to 125 °C, V_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

(Device other than above: T  40 °C to 125 °C, V_CC 5.0 V  10%, f ≤ 24 MHz, V_SS AV_SS 0 V)

A

CP

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

TOT1, TOT3,

PPG4, PPG6,

PPG8 to PPGF

CLK  → T_OUTchange time

t_TO

—

30

—

ns

2.4 V

CLK

2.4 V

0.8 V

TOT1, TOT3,

PPG4, PPG6

PPG8 to PPGF

tTO

Document Number: 002-07872 Rev. *A

Page 68 of 83

MB90350 Series

15.4.13 I²C Timing

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 105 °C, V_CC AV_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, V_CC AV_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

(Device other than above: T  40 °C to 125 °C, V_CC AV_CC 5.0 V  10%, f ≤ 24 MHz, V_SS AV_SS 0 V)

A

CP

Standard-mode

Fast-mode*⁴

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f_SCL

0

100

0

400

kHz

Hold time for (repeated) START condition

SDA↓→SCL↓

t_HDSTA

4.0

—

0.6

—

μs

“L” width of the SCL clock

“H” width of the SCL clock

t_LOW

t_HIGH

4.7

4.0

—

1.3

0.6

—

μs

Set-up time for a repeated START condition

SCL↑→SDA↓

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

t_BUS

4.7

0

—

3.45*²

—

0.6

0

—

0.9*³

—

μs

ns

μs

R  1.7 kΩ,

^C 50 pF*¹

Data hold time

SCL↓→SDA↓↑

Data set-up time

SDA↓↑→SCL↑

250*⁵

4.0

100*⁵

0.6

Set-up time for STOP condition

SCL↑→SDA↑

—

Bus free time between STOP condition and START

condition

4.7

—

1.3

—

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t_HDDAThas only to be met if the device does not stretch the “L” width (t_LOW) of the SCL signal.

*3 : A Fast-mode I²C -bus device can be used in a Standard-mode I²C-bus system, but the requirement

t_SUDAT≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

*5 : Refer to “Note of SDA, SCL set-up time”.

■ Note of SDA, SCL set-up time

SDA

Input data set-up time

SCL

6 tcp

Document Number: 002-07872 Rev. *A

Page 69 of 83

MB90350 Series

Note : Theratingoftheinputdataset-uptimeinthedeviceconnectedtothebuscannotbesatisfieddependingontheloadcapacitance

or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied.

■ Timing definition

SDA

tBUF

tHDSTA

tSUDAT

tLOW

SCL

tHDSTA

tSUSTA

tHIGH

tSUSTO

tHDDAT

fSCL

Document Number: 002-07872 Rev. *A

Page 70 of 83

MB90350 Series

15.5 A/D Converter

(MB90F352(S)/MB90F351(S): T_A 40 °C to 105 °C, 3.0 V ≤ AVRH, V_CC AV_CC 5.0 V  10%, f_CP≤ 24 MHz, V_SS AV_SS 0 V)

^{(MB90F352(S)/MB90F351(S): T}_A 40 °C to 125 °C, 3.0 V ≤ AVRH, V_CC AV_CC 5.0 V  10%, f_CP≤ 16 MHz, V_SS AV_SS 0 V)

(

Device other than above: T_A



40 °C to



125 °C

,

3.0 V ≤ AVRH, V_CC AV_CC 5.0 V



10%

,

f

≤ 24 MHz, V_SS AV_SS 0 V

)

CP

Value

Parameter

Resolution

Symbol

Unit

Remarks

Min

—

Typ

—

Max

—

10

bit

Total error

—

3.0

2.5

LSB

Nonlinearity error

—

Differential

nonlinearity error

—

1.9

LSB

V

Zero reading

voltage

AV_SS

1.5 LSB



AV_SS

0.5 LSB



AV_SS

2.5 LSB



V_OT

V_FST

AN0 to AN14

Full scale reading

voltage

^AVRH

AVRH 

AVRH 

V

3.5 LSB

1.5 LSB

0.5 LSB

1.0

2.0

0.5

1.2

4.5 V ≤ AV_CC≤ 5.5 V

4.0 V ≤ AV_CC< 4.5 V

4.5 V ≤ AV_CC≤ 5.5 V

4.0 V ≤ AV_CC< 4.5 V

Compare time

Sampling time

—

16,500

¥

s

Analog port input

current

I_AIN

V_AIN

—

AN0 to AN14

AVRH

0.3

AV_SS

—

+0.3

AVRH

AV_CC

A

V

Analog input

voltage range

Reference

voltage range

AV_SS 2.7

V

I_A

AV_CC

—

3.5

—

7.5

5

mA

Power supply

current

I_AH

μA

*

I_R

I_RH

—

AVRH

—

600

—

900

5

μA

Reference

voltage supply

current

Offset between

input channels

AN0 to AN14

—

4

LSB

* : If A/D converter is not operating, a current when CPU is stopped is applicable (V_CC AV_CC AVRH  5.0 V) .

Document Number: 002-07872 Rev. *A

Page 71 of 83

MB90350 Series

Notes on A/D Converter Section

■ About the external impedance of the analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage

charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external

impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external

impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a

capacitor of about 0.1 μF to the analog input pin.

· Analog input equivalence circuit

R

Analog input

Comparator

C

ON at sampling

MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S),

MB90F356A(S), MB90F357A(S), MB90F356TA(S), MB90F357TA(S),

R

C

4.5 V AV_CC5.5 V 2.0 kΩ (Max) 16.0 pF (Max)

4.0 V AV_CC4.5 V 8.2 kΩ (Max) 16.0 pF (Max)

MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),

MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S),

R

C

4.5 V AV_CC5.5 V 2.0 kΩ (Max) 14.4 pF (Max)

4.0 V AV_CC4.5 V 8.2 kΩ (Max) 14.4 pF (Max)

Note : The value is reference value.

Document Number: 002-07872 Rev. *A

Page 72 of 83

MB90350 Series

■ Flash memory device

· Relation between External impedance and minimum sampling time

(MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S), MB90F356A(S),

MB90F357A(S), MB90F356TA(S), MB90F357TA(S))

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20 kΩ]

4.5 V AV_CC5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V AV_CC4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

■ MASK ROM device

· Relation between External impedance and minimum sampling time

(MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),

MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S))

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20kΩ]

4.5 V AV_CC5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V AV_CC4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

■ About the error

^{Values of relative errors grow larger, as |AVRH} AV_SS| becomes smaller.

Document Number: 002-07872 Rev. *A

Page 73 of 83

MB90350 Series

15.6 Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale

transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics.

Non linearity error

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Difference between an actual value and a theoretical value. A total error includes zero transition error,

full-scale transition error, and linear error.

Total error

:

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actual measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V

_NT {1 LSB × (N  1)  0.5 LSB}

[LSB]

Total error of digital output “N” 

1 LSB

AVRH  AV

SS

1 LSB  (Ideal value)

[V]

1024

N : A/D converter digital output value

V_OT(Ideal value)  AV_SS 0.5 LSB [V]

V_FST(Ideal value)  AVRH  1.5 LSB [V]

V_NT: A voltage at which digital output transits from (N  1) to N.

(Continued)

Document Number: 002-07872 Rev. *A

Page 74 of 83

MB90350 Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FFH

Actual conversion

characteristics

3FEH

3FDH

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT}

V^FST(actual

measurement

value)

N

V^NT(actual

measurement value)

004H

003H

002H

001H

V ^(N+ 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V^OT(actual measurement value)

Analog input

AVSS

AVRH

AVSS

AVRH

Analog input

V

_NT {1 LSB × (N  1)  V

}

OT

[LSB]

Non linearity error of digital output N 

1 LSB

V ( )  V

N+1 T

1 LSB

NT

Differential linearity error of digital output N 

1 LSB [LSB]

[V]

V

_FST V

OT

1 LSB 

1022

N : A/D converter digital output value

V_OT: Voltage at which digital output transits from “000_H” to “001_H.”

V_FST: Voltage at which digital output transits from “3FE_H” to “3FF_H.”

Document Number: 002-07872 Rev. *A

Page 75 of 83

MB90350 Series

15.7 Flash Memory Program/Erase Characteristics

Flash Memory

Value

Typ

Parameter

Sector erase time

Conditions

Unit

Remarks

Min

Max

Excludes programming prior to

erasure

—

1

9

15

s

^T_A 25 °C

V_CC 5.0 V

Excludes programming prior to

erasure

Chip erase time

—

Word (16-bit width)

programming time

Except for the overhead time of

the system level

—

10,000

20

16

—

3,600

—

μs

Program/Erase cycle

—

cycle

year

Flash Memory Data

Retention Time

Average

^T_A 85 °C

—

*

* : This value comes from the technology qualification.

^{(Using Arrhenius equation to translate high temperature measurements into normalized value at}85 °C)

Dual Operation Flash Memory

Value

Parameter

Sector erase time

Conditions

Unit

Remarks

Min

Typ

Max

Excludes programming prior to

erasure

—

0.2

0.5

s

(4 Kbytes sector)

Sector erase time

(16 Kbytes sector)

Excludes programming prior to

erasure

—

0.5

4.6

7.5

—

^T_A 25 °C

V_CC 5.0 V

Excludes programming prior to

erasure

Chip erase time

Word (16-bit width)

programming time

Except for the overhead time of

the system level

—

10,000

20

64

—

3,600

—

μs

Program/Erase cycle

—

cycle

year

Flash Memory Data

Retention Time

Average

^T_A 85 °C

—

*

* : This value comes from the technology qualification.

^{(Using Arrhenius equation to translate high temperature measurements into normalized value at}85 °C)

Document Number: 002-07872 Rev. *A

Page 76 of 83

MB90350 Series

16. Ordering Information

Part number

MB90F351PMC

Package

Remarks

Flash memory products

64-pin plastic LQFP

FPT-64P-M23

12mm, 0.65mm pitch

(64 Kbytes)

MB90F351SPMC

MB90F352PMC

Flash memory products

(128 Kbytes)

MB90F352SPMC

MB90F351APMC

MB90F351ASPMC

MB90F351TAPMC

MB90F351TASPMC

MB90F356APMC

MB90F356ASPMC

MB90F356TAPMC

MB90F356TASPMC

MB90F352APMC

MB90F352ASPMC

MB90F352TAPMC

MB90F352TASPMC

MB90F357APMC

MB90F357ASPMC

MB90F357TAPMC

MB90F357TASPMC

MB90351APMC

64-pin plastic LQFP

FPT-64P-M23

12mm, 0.65mm pitch

Dual operation

Flash memory products

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M23

12mm, 0.65mm pitch

Dual operation

Flash memory products

(128 Kbytes)

MB90351ASPMC

MB90351TAPMC

MB90351TASPMC

MB90356APMC

64-pin plastic LQFP

FPT-64P-M23

12mm, 0.65mm pitch

MASK ROM products

(64 Kbytes)

MB90356ASPMC

MB90356TAPMC

MB90356TASPMC

MB90352APMC

MB90352ASPMC

MB90352TAPMC

MB90352TASPMC

MB90357APMC

64-pin plastic LQFP

FPT-64P-M23

12mm, 0.65mm pitch

MASK ROM products

(128 Kbytes)

MB90357ASPMC

MB90357TAPMC

MB90357TASPMC

(Continued)

Document Number: 002-07872 Rev. *A

Page 77 of 83

MB90350 Series

(Continued)

Part number

Package

Remarks

MB90F351APMC1

MB90F351ASPMC1

MB90F351TAPMC1

MB90F351TASPMC1

MB90F356APMC1

MB90F356ASPMC1

MB90F356TAPMC1

MB90F356TASPMC1

MB90F352APMC1

MB90F352ASPMC1

MB90F352TAPMC1

MB90F352TASPMC1

MB90F357APMC1

MB90F357ASPMC1

MB90F357TAPMC1

MB90F357TASPMC1

MB90351APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

Dual operation

Flash memory products*

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

Dual operation

Flash memory products*

(128 Kbytes)

MB90351ASPMC1

MB90351TAPMC1

MB90351TASPMC1

MB90356APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

MASK ROM products*

(64 Kbytes)

MB90356ASPMC1

MB90356TAPMC1

MB90356TASPMC1

MB90352APMC1

MB90352ASPMC1

MB90352TAPMC1

MB90352TASPMC1

MB90357APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

MASK ROM products*

(128 Kbytes)

MB90357ASPMC1

MB90357TAPMC1

MB90357TASPMC1

MB90V340A-101

MB90V340A-102

299-pin ceramic PGA

PGA-299C-A01

Device for evaluation

MB90V340A-103

MB90V340A-104

* : These devices are under development.

Document Number: 002-07872 Rev. *A

Page 78 of 83

MB90350 Series

17. Package Dimensions

64-pin plastic LQFP

Lead pitch

0.65 mm

12.0 × 12.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.47 g

Code

(Reference)

P-LQFP64-12×12-0.65

(FPT-64P-M23)

64-pin plastic LQFP

(FPT-64P-M23)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.006 .002)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ^+0.20

–

0.10

(Mounting height)

.059 ^+.008

–.004

0.25(.010)

INDEX

0~8°

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4

(Continued)

Document Number: 002-07872 Rev. *A

Page 79 of 83

MB90350 Series

(Continued)

64-pin plastic LQFP

Lead pitch

0.50 mm

Package width ×

package length

10.0 mm × 10.0 mm

Lead shape

Gullwing

Plastic mold

Sealing method

Code

(Reference)

P-LFQFP64-10×10-0.50

(FPT-64P-M24)

64-pin plastic LQFP

(FPT-64P-M24)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00 0.20(.472 .008)SQ

Details of "A" part

*10.00 0.10(.394 .004)SQ

0.145 0.055

(.006 .002)

48

33

0.15(.006)

MAX

49

32

0.40(.016)

MAX

0.08(.003)

Details of "B" part

1.50 ^+0.20

11.00(.433)

NOM.

–

0.10

.004

(Mounting height)

.059 ^+.008

–

0.25(.010)

INDEX

0~8°

"A"

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"B"

1

16

LEAD No.

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3

Document Number: 002-07872 Rev. *A

Page 80 of 83

MB90350 Series

18. Major Changes

Spansion Publication Number: DS07-13737-6E

Page

Section

Change Results

Deleted the following package.

FPT-64P-M09

—

Changed the correspondence package for MB90F351, MB90F351S,

MB90F352 and MB90F352S.

FPT-64P-M09 → FPT-64P-M23

5. Packages and Product Correspon-

dence

13

26

Corrected a typo in number 10.

“is used”→ “is not used”

9. Handling Devices

15. Electrical Characteristics

15.4. AC Characteristics

15.4.4. Clock Output Timing

Changed the Minimum value of cycle time.

41.76 → 41.67

64

75

15.5. A/D Converter

Changed the notation of “Zero reading voltage” and “Full scale reading voltage”.

Changed the part numbers and the package.

MB90F351PFM → MB90F351PMC

MB90F351SPFM → MB90F351SPMC

MB90F352PFM → MB90F352PMC

MB90F352SPFM → MB90F352SPMC

FPT-64P-M09 → FPT-64P-M23

81

16. Ordering Information

NOTE: Please see “Document History” about later revised information.

Document Number: 002-07872 Rev. *A

Page 81 of 83

MB90350 Series

Document History

Document Title: MB90350 Series F²MC-16LX 16-bit Microcontroller

Document Number: 002-07872

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

Migrated to Cypress and assigned document number 002-07872.

No change to document contents or format.

**

—

AKFU

09/29/2003

*A

5755299

05/31/2017 Updated to Cypress format.

Document Number: 002-07872 Rev. *A

Page 82 of 83

MB90350 Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-07872 Rev. *A

Revised May 31, 2017

Page 83 of 83


型号：	MB90F351TAPMC1
厂家：	CYPRESS
描述：	F2MC-16LX 16-bit Microcontroller 微控制器
文件：	总83页 (文件大小：1275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F351TAPMC1 [CYPRESS]

相关型号：

MB90F351TASPMC

MB90F351TASPMC1

MB90F351TE

MB90F351TEPMC

MB90F351TEPMC

MB90F351TEPMC

MB90F351TEPMC1

MB90F351TEPMC1

MB90F351TEPMC1

MB90F351TES

MB90F351TESPMC

MB90F351TESPMC1