FM24V05-GTR [CYPRESS]
512Kb Serial 3V F-RAM Memory; 512KB串行3V F-RAM存储器
| 型号： | FM24V05-GTR |
| 厂家： | 
CYPRESS |
| 描述： | 512Kb Serial 3V F-RAM Memory |
| 文件： | 总17页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FM24V05
512Kb Serial 3V F-RAM Memory
Features
Device ID
Device ID reads out Manufacturer ID & Part ID
512K bit Ferroelectric Nonvolatile RAM
Organized as 65,536 x 8 bits
High Endurance 100 Trillion (1014) Read/Writes
10 year Data Retention
Low Voltage, Low Power Operation
Low Voltage Operation 2.0V – 3.6V
Active Current < 150 A (typ. @ 100KHz)
90 A Standby Current (typ.)
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
5 A Sleep Mode Current (typ.)
Fast Two-wire Serial Interface
Up to 3.4 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC Package
a hardware drop-in replacement. The devices are
available in industry standard 8-pin SOIC package
using a familiar two-wire (I2C) protocol. Both
devices incorporate a read-only Device ID that allows
the host to determine the manufacturer, product
density, and product revision. The devices are
guaranteed over an industrial temperature range of -
40°C to +85°C.
Description
The FM24V05 is a 512Kbit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Pin Configuration
The FM24V05 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, F-RAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
1
2
3
4
8
7
6
5
VDD
WP
A0
A1
A2
SCL
SDA
VSS
Pin Name
A0-A2
SDA
SCL
WP
Function
These capabilities make the FM24V05 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Supply Voltage
Ground
VDD
VSS
The FM24V05 provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s
internal qualification testing and has reached production status.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 001-84462 Rev. *B
Revised May 29, 2013
FM24V05 - 512Kb I2C FRAM
Address
Latch
8K x 64
FRAM Array
Counter
8
SDA
Serial to Parallel
Converter
Data Latch
8
SCL
WP
Control Logic
Device ID and
Serial Number
A0-A2
Figure 1. FM24V05 Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A2
Input
Device Select Address 0-2: These pins are used to select one of up to 8 devices of
the same type on the same two-wire bus. To select the device, the address value on
the two pins must match the corresponding bits contained in the slave address. The
address pins are pulled down internally.
SDA
I/O
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is
open-drain and is intended to be wire-OR‟d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. An external pull-up resistor is
required.
SCL
WP
Input
Input
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of
the part on the falling edge, and into the device on the rising edge. The SCL input
also incorporates a Schmitt trigger input for noise immunity.
Write Protect: When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
VDD
VSS
Supply
Supply
Supply Voltage
Ground
Document Number: 001-84462 Rev. *B
Page 2 of 17
FM24V05 - 512Kb I2C FRAM
Overview
Two-wire Interface
The FM24V05 is a family of serial F-RAM memory
devices. The memory array is logically organized as a
65,536 x 8 bit memory array and is accessed using an
industry standard two-wire (I2C) interface. Functional
operation of the F-RAM is similar to serial
EEPROM. The major difference between the
FM24V05 and serial EEPROM is F-RAM‟s superior
write performance.
The FM24V05 employs a bi-directional two-wire bus
protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24V05 in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24V05 always is a slave device.
Memory Architecture
When accessing the FM24V05, the user addresses
65,536 locations each with 8 data bits. These data bits
are shifted serially. The 65,536 addresses are
accessed using the two-wire protocol, which includes
a slave address (to distinguish other non-memory
devices) and a 2-byte address. All 16 address bits are
used by the decoder for accessing the memory.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications section.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
VDD
Rmin = 1.1 Kohm
Rmax = tR/Cbus
Microcontroller
Users expect several obvious system benefits from
the FM24V05 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
SDA SCL
FM24V05
SDA
FM24V05
A0 A1 A2
SCL
A0 A1 A2
Figure 2. Typical System Configuration
Note that it is the user‟s responsibility to ensure that
VDD is within datasheet tolerances to prevent
incorrect operation.
Document Number: 001-84462 Rev. *B
Page 3 of 17
FM24V05 - 512Kb I2C FRAM
SCL
SDA
7
6
0
Stop
Start
Data bits
(Transmitter)
Data bit Acknowledge
(Transmitter) (Receiver)
(Master) (Master)
Figure 3. Data Transfer Protocol
Stop Condition
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24V05 will
continue to place data onto the bus as long as the
receiver sends acknowledges (and clocks). When a
read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24V05 to attempt to drive the bus
on the next clock while the master is sending a new
command such as stop.
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24V05 should end
with a stop condition. If an operation is in progress
when a stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24V05 for a new operation.
Slave Address
The first byte that the FM24V05 expects after a start
condition is the slave address. As shown in Figure 4,
the slave address contains the device type or slave
ID, the device select address bits, a page address bit,
and a bit that specifies if the transaction is a read or a
write.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.
Bits 7-4 are the device type (slave ID) and should be
set to 1010b for the FM24V05. These bits allow other
function types to reside on the 2-wire bus within an
identical address range. Bits 3-1 are the device select
address bits. They must match the corresponding
value on the external address pins to select the
device. Up to eight FM24V05 devices can reside on
the same two-wire bus by assigning a different
address to each. Bit 0 is the read/write bit. R/W=1
indicates a read operation and R/W=0 indicates a
write operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
High Speed Mode (HS-mode)
The FM24V05 supports a 3.4MHz high speed mode.
A master code (0000 1XXXb) must be issued to place
the device into high speed mode. Communication
between master and slave will then be enabled for
speeds up to 3.4MHz. A stop condition will exit HS-
mode. Single- and multiple-byte reads and writes are
supported. See Figures 10 and 11 for HS-mode
timings.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Document Number: 001-84462 Rev. *B
Page 4 of 17
FM24V05 - 512Kb I2C FRAM
Memory Operation
The FM24V05 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24V05 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Device Select
Slave ID
A1
2
A0
1
1
7
0
6
1
0
4
A2
3
R/W
0
5
Figure 4. Slave Address
Write Operation
Addressing Overview
All writes begin with a slave address, then a memory
address. The bus master indicates a write operation
by setting the LSB of the slave address (R/W bit) to a
„0‟. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from FFFFh to 0000h.
After the FM24V05 (as receiver) acknowledges the
slave address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The complete 16-bit address is
latched internally. Each access causes the latched
address value to be incremented automatically. The
current address is the value that is held in the latch --
either a newly written value or the address following
the last access. The current address will be held for as
long as power remains or until a new value is written.
Reads always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
Unlike other nonvolatile memory technologies, there
is no effective write delay with F-RAM. Since the
read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge polling,
a technique used with EEPROMs to determine if a
write is complete is unnecessary and will always
return a ready condition.
After transmission of each data byte, just prior to the
acknowledge, the FM24V05 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (FFFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Internally, an actual memory write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8th data bit. The FM24V05 uses no page
buffering.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24V05 can begin. For a read operation the
FM24V05 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24V05 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24V05 will end the read operation. For a write
operation, the FM24V05 will accept 8 data bits from
the master then send an acknowledge. All data
transfer occurs MSB (most significant bit) first.
The memory array can be write-protected using the
WP pin. This feature is available only on FM24V05
devices. Setting the WP pin to a high condition (VDD
)
will write-protect all addresses. The FM24V05 will
not acknowledge data bytes that are written to
protected addresses. In addition, the address counter
will not increment if writes are attempted to these
addresses. Setting WP to a low state (VSS) will
deactivate this feature. WP is pulled down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
Document Number: 001-84462 Rev. *B
Page 5 of 17
FM24V05 - 512Kb I2C FRAM
Stop
Start
S
Address & Data
Address MSB
By Master
Slave Address
0
A
A
Address LSB
A
Data Byte
A
P
By FM24V05
Acknowledge
Figure 5. Single Byte Write
Start
Stop
P
Address & Data
Address MSB
By Master
S
Slave Address
0
A
A
Address LSB
A
Data Byte
A
Data Byte
A
By FM24V05
Acknowledge
Figure 6. Multiple Byte Write
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the FM24V05
attempts to read out additional data onto the bus. The
four valid methods are:
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24V05 uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
Current Address & Sequential Read
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
As mentioned above the FM24V05 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
4. The bus master issues a start in the 9th clock
cycle.
If the internal address reaches FFFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
To perform a current address read, the bus master
supplies a slave address with the LSB set to a „1‟.
This indicates that a read operation is requested.
After receiving the complete slave address, the
FM24V05 will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24V05 acknowledges the address, the bus master
issues a start condition. This simultaneously aborts
Each time the bus master acknowledges a byte,
this indicates that the FM24V05 should read out
the next sequential byte.
Document Number: 001-84462 Rev. *B
Page 6 of 17
FM24V05 - 512Kb I2C FRAM
operation is now a current address read.
the write operation and allows the read command to
be issued with the slave address LSB set to a „1‟. The
No
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
Data
1
P
By FM24V05
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1
P
By FM24V05
Acknowledge
Data
Figure 8. Sequential Read
Start
No
Address
Acknowledge
Start
Address
By Master
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
S
Slave Address
1
A
Data Byte
Data
1 P
By FM24V05
Figure 9. Selective (Random) Read
Start
Start &
Enter HS-mode
No
Acknowledge
HS-mode command
Address
By Master
Stop &
Exit HS-mode
S
1
S
Slave Address
1
A
Data Byte
Data
1
P
0
0
0
0
1
X
X
X
By FM24V05
No
Acknowledge
Acknowledge
Figure 10. HS-mode Current Address Read
Start
Stop &
Exit HS-mode
Start &
Enter HS-mode
Address & Data
HS-mode command
By Master
S
1
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
Data Byte
A P
0
0
0
0
1
X
X
X
By FM24V05
No
Acknowledge
Figure 11. HS-mode Byte Write
Document Number: 001-84462 Rev. *B
Page 7 of 17
FM24V05 - 512Kb I2C FRAM
5. The master sends Reserved Slave ID 0x86
6. The FM24V05 sends an ACK.
7. The master sends STOP to ensure the device
enters sleep mode.
Sleep Mode
A
low power mode called Sleep Mode is
implemented on both FM24V05 devices. The device
will enter this low power state when the Sleep
command 86h is clocked-in. Sleep Mode entry can be
entered as follows:
Once in sleep mode, the device draws IZZ current, but
the device continues to monitor the I2C pins. Once
the master sends a Slave Address that the FM24V05
identifies, it will “wakeup” and be ready for normal
operation within tREC (400 s max.). As an alternative
method of determining when the device is ready, the
master can send read or write commands and look for
an ACK. While the device is waking up, it will
NACK the master until it is ready.
1. The master sends a START command.
2. The master sends Reserved Slave ID 0xF8
3. The master sends the I2C-bus slave address of
the slave device it needs to identify. The last
bit is a „Don‟t care‟ value (R/W bit). Only one
device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Start
Address
Address
Stop
P
Start
S
By Master
S
Rsvd Slave ID (F8)
A
Slave Address
A
Rsvd Slave ID (86)
A
X
By FM24V05
Acknowledge
Figure 12. Sleep Mode Entry
Document Number: 001-84462 Rev. *B
Page 8 of 17
FM24V05 - 512Kb I2C FRAM
5. The master sends Reserved Slave ID 0xF9
6. The Device ID Read can be done, starting
with the 12 manufacturer bits, followed by
the 9 part identification bits, and then the 3
die revision bits.
7. The master ends the Device ID read
sequence by NACKing the last byte, thus
resetting the slave device state machine and
allowing the master to send the STOP
command.
Device ID
The FM24V05 devices incorporate a means of
identifying the device by providing three bytes of
data, which are manufacturer, product ID, and die
revision. The Device ID is read-only. It can be
accessed as follows:
1. The master sends a START command.
2. The master sends Reserved Slave ID 0xF8
3. The master sends the I2C-bus slave address
of the slave device it needs to identify. The
last bit is a „Don‟t care‟ value (R/W bit).
Only one device must acknowledge this byte
(the one that has the I2C-bus slave address).
4. The master sends a Re-START command.
Note: The reading of the Device ID can be stopped
anytime by sending a NACK command.
Start
No
Acknowledge
Acknowledge
Address
A
Address
Start
S
By Master
Stop
S
Rsvd Slave ID (F8)
Slave Address
A
Rsvd Slave ID (F9)
A
Data Byte
A
Data Byte
Data
A
Data Byte
1
P
By FM24V05
Acknowledge
Figure 13. Read Device ID
Manufacturer ID
Product ID
Die Rev.
11 10
9
8
7
6
5
4
3
0
2
1
1
0
0
0
8
7
6
5
4
3
2
1
0
2
1
0
Ramtron
Density
Variation
0
0
0
0
0
0
0
0
0
0
1
1
N
0
0
0
0
0
0
0
Figure 14. Manufacturer and Product ID
Density: 01h=128Kb, 02h=256Kb, 03h=512Kb, 04=1Mb
Variation: Product ID bit 4 = S/N, Product ID bit 0 = reserved
The 3-byte hex code for an FM24V05 will be:
0x00 0x43 0x00
Document Number: 001-84462 Rev. *B
Page 9 of 17
FM24V05 - 512Kb I2C FRAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
VDD
VIN
Description
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
Ratings
-1.0V to +4.5V
-1.0V to +4.5V
and VIN < VDD+1.0V *
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
-55 C to +125 C
260 C
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
2.5kV
1.25kV
200V
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
Notes
VDD
IDD
Main Power Supply
2.0
3.3
3.6
V
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 1 MHz
@ SCL = 3.4 MHz
1
175
400
1000
A
A
A
A
A
A
A
V
V
V
V
ISB
IZZ
ILI
ILO
VIL
VIH
VOL1
VOL2
RIN
Standby Current
Sleep Mode Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
90
5
150
8
±1
2
2
3
3
±1
-0.3
0.7 VDD
0.3 VDD
VDD + 0.3
0.4
Input High Voltage
Output Low Voltage (IOL = 2 mA, VDD ≥ 2.7V)
Output Low Voltage (IOL = 150 A)
Address Input Resistance (WP, A2-A0)
For VIN = VIL (max)
0.2
50
1
4
K
M
For VIN = VIH (min)
Notes
1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4. The input pull-down circuit is stronger (50K ) when the input voltage is below VIL and weak (1M ) when the input voltage
is above VIH.
Document Number: 001-84462 Rev. *B
Page 10 of 17
FM24V05 - 512Kb I2C FRAM
AC Parameters (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified)
F/S-mode
HS-mode
(CL<500pF)
(CL<100pF)
Symbol Parameter
Min
Max
Min
Max
Units Notes
fSCL
tLOW
tHIGH
tAA
SCL Clock Frequency
Clock Low Period
Clock High Period
SCL Low to SDA Data Out Valid
0
500
260
1.0
0
160
60
3.4
MHz
ns
ns
1
450
130
ns
tBUF
Bus Free Before New Transmission
Start Condition Hold Time
Start Condition Setup for Repeated Start
Data In Hold
Data In Setup
Input Rise Time
Input Fall Time
Stop Condition Setup
Data Output Hold (from SCL @ VIL)
Noise Suppression Time Constant on SCL, SDA
0.5
260
260
0
0.3
160
160
0
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
50
10
3
2
2
120
120
80
80
260
0
160
0
tSP
50
5
Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations.
1. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL
(max).
2. This parameter is periodically sampled and not 100% tested.
3. In HS-mode and VDD < 2.7V, the tSU:DAT (min.) spec is 15ns.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
Min
Max
Units Notes
CI/O
CIN
Input/Output Capacitance (SDA)
Input Capacitance
-
-
8
6
pF
pF
1
1
Notes
1. This parameter is periodically sampled and not 100% tested.
Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V)
Symbol Parameter
Min
Max
Units Notes
tVR
tVF
tPU
tPD
tREC
VDD Rise Time
VDD Fall Time
Power Up (VDD min) to First Access (Start condition)
Last Access (Stop condition) to Power Down (VDD min)
Recovery Time from Sleep Mode
50
100
250
0
-
-
-
s/V
s/V
s
s
s
1,2
1,2
-
-
400
Notes
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on VDD waveform.
Power Cycle Timing
tVR
tVF
VDD min.
VDD
tPD
tPU
Access Allowed
Document Number: 001-84462 Rev. *B
Page 11 of 17
FM24V05 - 512Kb I2C FRAM
Equivalent AC Test Load Circuit
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
3.6V
1.8 Kohm
Output
Diagram Notes
All start and stop timing parameters apply to both read and write cycles.
Clock specifications are identical for read and write cycles. Write
timing parameters apply to slave address, word address, and write data
bits. Functional relationships are illustrated in the relevant datasheet
sections. These diagrams illustrate the timing parameters only.
100 pF
Read Bus Timing
tHIGH
tR
tSP
tF
tSP
tLOW
`
SCL
1/fSCL
tSU:SDA
tHD:DAT
tSU:DAT
tBUF
SDA
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Data Retention (TA = -40 C to +85 C)
Parameter
Data Retention
Min
10
Max
-
Units
Years
Notes
Document Number: 001-84462 Rev. *B
Page 12 of 17
FM24V05 - 512Kb I2C FRAM
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
Recommended PCB Footprint
7.70
3.70
3.90 ±0.10 6.00 ±0.20
2.00
1.27
0.65
Pin 1
0.25
0.50
4.90 ±0.10
1.35
1.75
0.19
0.25
45
0.10 mm
1.27
0.10
0.25
0 - 8
0.40
1.27
0.33
0.51
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXXXX = part number, P = package type
R = rev code, LLLLL = lot code, Z = Package code
RIC = Ramtron Int‟l Corp, YY = year, WW = work week
XXXXXXX-P
R LLLLLZ
RICYYWW
= Pb-free
Example:
FM24V05, “Green”/RoHS SOIC
Rev. A, Lot 67989, SOIC
Year 2013, Work Week 07
Pb-free
FM24V05-G
A 67989S
RIC1307
Document Number: 001-84462 Rev. *B
Page 13 of 17
FM24V05 - 512Kb I2C FRAM
Revision History
Revision
1.0
Date
Summary
Initial Release
Added tape and reel ordering information.
Changed to Pre-Production status. Updated ESD ratings. Changed part
marking scheme. Expanded CRC check description.
Removed S/N option.
8/22/2008
2/2/2009
5/25/2010
1.1
2.0
2.1
3.0
11/22/2011
1/30/2012
Changed to Production status.
Ordering Information
Part Number
Features
Operating
Voltage
Package
FM24V05-G
FM24V05-GTR
Device ID
Device ID
2.0-3.6V
2.0-3.6V
8-pin “Green”/RoHS SOIC
8-pin “Green”/RoHS SOIC,
Tape & Reel
Document Number: 001-84462 Rev. *B
Page 14 of 17
FM24V05 - 512Kb I2C FRAM
Appendix A - Errata for FM24V05
Errata Number
001
Date
January 12, 2011 (Updated Jan. 2012)
FM24V05
Product
The FM24V05 devices have a problem with the sleep mode function. Some devices will not exit sleep at
Vdd voltages within the specified operating range. Worst case is at high VDD (3.6V). The failing voltage
will be lower at cold temperatures. This does not affect operation if the sleep function is not used.
There is an effective screen that is implemented at final test. A temporary part number has been assigned
for customers who use sleep mode. Customers who require sleep mode should order the FM24V05-G.
The part will be marked with a triangle to the right of the part mark. An example of the mark is as
follows:
No Sleep Mode Screen
FM24V05-G
A9646447
Sleep Mode Screen
FM24V05-G
A9646447
XXXXXXX-PT
RLLLLLLLL
RIC YYWW
RIC1011
RIC1011
This errata will remain in effect until the sleep function is fixed.
UPDATE: Ramtron has implemented a screen such that all devices comply with the datasheet
specifications without exception over all operating temperature and voltage conditions. Therefore the
above errata no longer applies. The starting date code for errata-free devices is 1204. (YY=12, WW=04)
Document Number: 001-84462 Rev. *B
Page 15 of 17
FM24V05 - 512Kb I2C FRAM
Document History
Document Title: FM24V05 512Kb Serial 3V F-RAM Memory
Document Number: 001-84462
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3902204
3985098
GVCH
GVCH
02/25/2013
05/09/2013
New Spec
*A
Removed FM24VN05 part number related information
Updated SOIC package marking scheme
Added Appendix A - Errata for FM24V05
*B
4014247
GVCH
05/29/2013
Document Number: 001-84462 Rev. *B
Page 16 of 17
FM24V05 - 512Kb I2C FRAM
Sales, Solutions, and Legal Information
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trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress
Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor
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Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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Document Number: 001-84462 Rev. *B
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