CYWB0226ABSX-FDXI [CYPRESS]
West Bridge®: Astoria⢠USB and Mass Storage Peripheral Controller; 西Bridge® ： Astoriaâ ?? ¢ USB和海量存储外设控制器
| 型号： | CYWB0226ABSX-FDXI |
| 厂家： | 
CYPRESS |
| 描述： | West Bridge®: Astoria⢠USB and Mass Storage Peripheral Controller |
| 文件： | 总78页 (文件大小：1534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYWB022XX Family
West Bridge®: Astoria™ USB and Mass
Storage Peripheral Controller
West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller
❐ SPI (slave mode) interface
❐ Direct memory access (DMA) slave support
Features
■ Multimedia device support
❐ Up to two SD, SDIO, MMC, MMC+, and CE-ATA devices
■ FlexBoot
❐ Processor can boot from the processor interface port
■ Ultra low power, 1.8-V core operation
■ Low power modes
®
■ Supports Microsoft Media Transfer Protocol (MTP) with
optimized data throughput
■ Simultaneous Link to Independent Multimedia (SLIM®)
architecture, enabling simultaneous and independent data
paths between the processor and USB, and between the USB
and mass storage
■ Small footprint:
❐ 3.91 × 3.91 × 0.55 mm 81-ball WLCSP (SP and Lite SP)
❐ 6 × 6 × 1.0 mm 100-ball VFBGA
❐ 10 × 10 × 1.20 mm 121-ball FBGA
■ Supports I2C boot and processor boot
■ High-speed USB at 480 Mbps
❐ USB 2.0 compliant
❐ Integrated USB switch
❐ Integrated USB 2.0 transceiver, smart serial interface engine
❐ 16 programmable endpoints
■ Selectable clock input frequencies
❐ 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
Applications
■ GPIF (General Programmable Interface)
❐ Allows direct connection to most parallel interface
❐ Programmable waveform descriptors and configuration
registers to define waveforms
❐ Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
■ Cellular phones
■ Portable media players
■ Personal digital assistants
■ Portable navigation devices
■ Digital cameras
■ Flexible processor interface that supports:
❐ Multiplexing and nonmultiplexing address and data interface
❐ SRAM interface
■ POS terminals
❐ Pseudo cellular random access memory (CRAM) interface
■ Portable video recorders
■ Data cards and wireless dongles
(Antioch interface)
❐ Pseudo NAND flash interface
Logic Block Diagram
West BridgeTM AstoriaTM
Control
Registers
uC
Access Control
P
U
SLIMTM
SD/SDIO/
MMC+/ CE- N-XpressTM
ATA Block Engine
Cypress
Configurable Storage
Interface
S
Cypress Semiconductor Corporation
Document Number: 001-13805 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 6, 2012
CYWB022XX Family
Contents
Functional Overview ........................................................3
Turbo-MTP Support .....................................................3
SLIM Architecture ........................................................3
8051 Microprocessor ...................................................3
Configuration and Status Registers .............................3
Processor Interface (P-Port) ........................................3
FlexBoot ......................................................................3
USB Interface (U-Port) ................................................3
Mass Storage Support (S-Port) ...................................4
Clocking .......................................................................5
Power Domains ...........................................................6
Power Modes ..............................................................7
Packages and Interface Options .....................................8
Pin Assignments ..............................................................9
Absolute Maximum Ratings ..........................................32
Operating Conditions .....................................................32
DC Characteristics .........................................................33
AC Timing Parameters ...................................................35
P Port Interface .........................................................35
S Port Interface AC Timing Parameters ....................68
Reset and Standby Timing Parameters ....................69
Ordering Information ......................................................71
Ordering Code Definitions .........................................71
Package Diagram ............................................................72
Acronyms ........................................................................75
Document Conventions .................................................75
Units of Measure .......................................................75
Document History Page .................................................76
Sales, Solutions, and Legal Information ......................78
Worldwide Sales and Design Support .......................78
Products ....................................................................78
PSoC Solutions .........................................................78
Document Number: 001-13805 Rev. *M
Page 2 of 78
CYWB022XX Family
P-Port of the WLCSP package only supports PNAND and SPI
interface.
Functional Overview
Turbo-MTP Support
The memory address is decoded to access any of the multiple
endpoint buffers inside Astoria. These endpoints serve as buffers
for data between each pair of ports, for example, between the
processor port and the USB port. The processor writes and reads
into these buffers through the memory interface.
Turbo-MTP is an implementation of Microsoft’s MTP enabled by
West Bridge. In the current generation of MTP-enabled mobile
phones, all protocol packets needs to be handled by the main
processor. West Bridge Turbo-MTP switches these packet types
and sends only control packets to the processor, while data
payloads are written directly to mass storage, thereby bringing
the high performance of West Bridge to MTP. For more
information refer to the application note Optimizing Performance
using West Bridge® Controllers with Turbo-MTP.
Access to these buffers is controlled by either using a DMA
protocol or using an interrupt to the main processor. These two
modes are configurable by the external processor. The 81-ball
WLCSP package only supports interrupt.
As a DMA slave, Astoria generates a DMA request signal to
signify to the main processor that a specific buffer is ready to be
read from or written to. The external processor monitors this
signal and polls Astoria for the specific buffers ready for read or
write. It then performs the appropriate read or write operations
on the buffer through the processor interface. This way, the
external processor only deals with the buffers to access a
multitude of storage devices connected to Astoria.
SLIM Architecture
The SLIM architecture enables three different interfaces (P-port,
S-port, and U-port) to connect to one another independently.
With this architecture, connecting a device using Astoria to a PC
through USB does not disturb any of the functions of the device.
The device can still access mass storage at the same time as the
PC synchronizes with the main processor.
In the interrupt mode, Astoria communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Astoria for the specific
buffers ready for read or write and it performs the appropriate
read or write operations through the processor interface.
The SLIM architecture enables new usage models in which a PC
can access a mass storage device independent of the main
processor or enumerate access to both the mass storage and
the main processor at the same time.
In a handset, this typically enables using the phone as a thumb
drive, downloading media files to the phone while still having full
functionality available on the phone, or using the same phone as
a modem to connect the PC to the web.
FlexBoot
FlexBoot is an optional feature that Astoria emulates a NAND
Flash device. In this optional feature, the P-Port is configured as
pseudo NAND interface. The processor can download its boot
image through the P-Port.
8051 Microprocessor
When P-Port is configured to pseudo NAND interface, it supports
two operation modes:
The 8051 microprocessor embedded in Astoria does basic
transaction management for all the transactions between P-Port,
S-Port, and U-Port. The 8051 does not reside in the data path; it
manages the path. The data path is optimized for performance.
The 8051 executes firmware that supports SD, SDIO, MMC+,
and CE-ATA devices at the S-Port.
■ Logic NAND Access (LNA) mode
■ Non-Logic NAND Access (non-LNA) mode
LNA refers to the mode of operation where Astoria emulates a
NAND flash device. This mode is designed for systems that
require booting of the system processor from a NAND Flash
device. In this type of application, the system processor can
communicate to Astoria using common NAND commands to
boot from a NAND Flash connected to Astoria’s S-port. In this
mode of operation, Astoria mimics a real NAND device and
allows the system processor to use its internal boot-ROM to boot
from Astoria, as it boots from a NAND Flash.
Configuration and Status Registers
The West Bridge Astoria device includes configuration and
status registers that are accessible as memory mapped registers
through the processor interface. The configuration registers
allow the system to specify certain Astoria behaviors. For
example, it is able to mask certain status registers from raising
an interrupt. The status registers convey various status such as
the addresses of buffers for read operations.
In the non-LNA mode of operation, the system processor
interfaces with Astoria using standard NAND interface, but does
not use standard NAND commands. In this mode, Astoria
responds to a subset of NAND commands. The system
processor uses a set of APIs provided by Cypress to
communicate through its NAND controller to Astoria. For details,
refer to the application note “Interfacing To West Bridge™
Astoria’s™ Pseudo-NAND Processor Port“.
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface also can be configured to a
pseudo NAND interface to support the processor’s NAND
interface. In addition, this interface can be configured to support
SPI slave. Asynchronous accesses can reach a bandwidth of up
to 66.7 MBps. Synchronous accesses can be performed at
33 MHz across 16 bits for up to 66.7 MBps bandwidth. The
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Astoria can
operate in both full speed and high speed USB modes. The USB
interface consists of the USB transceiver and can be accessed
by both the P-Port and the S-Port.
Document Number: 001-13805 Rev. *M
Page 3 of 78
CYWB022XX Family
The Astoria USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Dual SD/SDIO/MMC/CE-ATA Interface Mode
The dual SD/SDIO/MMC/MMC+/CE-ATA interface mode
configures the S-Port for up to two
SD/SDIO/MMC/MMC+/CE-ATA port as shown in Figure 3. Each
SD/SDIO/MMC/MMC+/CE-ATA port is independent and
supports different SD, SDIO, MMC, MMC+, or CE-ATA devices.
Astoria also has an integrated USB switch (see Figure 1) that
allows interfacing to an external full speed USB PHY.
Figure 1. U-Port With Switch and Control Block
SWD+
Figure 3. Dual SD/SDIO/MMC/CE-ATA Interface Mode
UVALID
USBALLO
SWD-
D+
D-
USB Switch
and Control
Block
USB 2.0
XCVR
USB Port
(U Port)
Astoria
S Port
SD
SDIO
MMC
SD
SDIO
MMC
Mass Storage Support (S-Port)
OR
OR
OR
OR
OR
OR
OR
OR
MMC+
CE-ATA
MMC+
CE-ATA
The S-Port is configurable in five different interface modes:
■ Simultaneously supporting an SD/SDIO/MMC+/CE-ATA port
and an GPIF
■ Supporting two SD/SDIO/MMC+/CE-ATA ports
■ Supporting SD/SDIO/MMC+/CE-ATA port and GPIO
■ Supporting GPIF and GPIO
SD/SDIO/MMC/CE-ATA and GPIO Interface
■ Supporting GPIO
The SD/SDIO/MMC/MMC+/CE-ATA and GPIO interface mode
configures the S-Port to support SD/SDIO/MMC/MMC+/CE-ATA
device and GPIOs as shown in Figure 4. Each GPIO is
configured as either input or output independently. The
processor accesses those GPIO through the P-Port driver’s API.
These configurations are controlled by the 8051 firmware.
S-Port Configuration Modes
The S Port is configurable in six different interface modes:
Figure 4. SD/SDIO/MMC/CE-ATA and GPIO Interface Mode
■ GPIF and SD/SDIO/MMC/CE-ATA interface mode
■ Dual SD/SDIO/MMC/CE-ATA interface mode
■ SD/SDIO/MMC/CE-ATA and GPIO interlace mode
■ GPIF and GPIO interface mode
Astoria
S Port
SD
SDIO
■ GPIO interface mode
GPIF and SD/SDIO/MMC/CE-ATA Interface Mode
MMC
OR
MMC+
CE-ATA
GPIO
This mode configures the S-Port into GPIF and
SD/SDIO/MMC/MMC+/CE-ATA ports as shown in Figure 2. The
SD/SDIO/MMC/MMC+/CE-ATA port supports either SD, SDIO,
MMC, MMC+, or CE-ATA device.
OR
OR
OR
Figure 2. GPIF and SD/SDIO/MMC/CE-ATA Interface Mode
Document Number: 001-13805 Rev. *M
Page 4 of 78
CYWB022XX Family
GPIF and GPIO Interface
■ SD Specifications – Part E1 SDIO Specification, Version 1.10,
August 18, 2004
The GPIF and GPIO interface mode configure the S-Port to
support GPIF and GPIO as shown in Figure 5. Each GPIO is
configured as either input or output independently. The
processor accesses those GPIO through the P-Port driver’s API.
■ CE-ATA Specification – CE-ATA Digital Protocol, CE-ATA
Committee, Version 1.1, September, 2005
West Bridge Astoria provides support for 1-bit and 4-bit SD;
SDIO cards; 1-bit, 4-bit, and 8-bit MMC; MMC+ cards; and
CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA,
this block supports one card for one physical bus interface.
Figure 5. GPIF and GPIO Interface Mode
Astoria supports SD commands including the multisector
program command that are handled by the API.
GPIO Port (S-Port)
The GPIO in S-Port is configurable as either input or output
direction independently. The processor accesses the GPIO
through the P-Port driver’s API.
Clocking
Astoria allows connection of a crystal between the XTALIN and
XTALOUT pins or an external clock at the XTALIN pin. The
81-ball WLCSP package only supports the external clock. The
power supply level at the crystal supply XVDDQ determines
whether a crystal or a clock is provided. If XVDDQ is detected to
be 1.8 V, Astoria assumes that a clock input is provided. For a
crystal to be connected, XVDDQ must be 3.3 V.
GPIO Interface Mode
The GPIO interface mode configures the S-Port to all GPIO as
shown in Figure 6. Each GPIO is configured as either input or
output independently. The processor accesses those GPIO
through the P-Port driver’s API.
Note Clock inputs at 3.3 V level are not supported.
Astoria’s 100-ball VFBGA package supports external crystal and
clock inputs at 19.2, 24, and 26 MHz frequencies. At 48 MHz,
only clock inputs are supported. The 81-ball SPWLCSP only
supports 19.2 and 26 MHz external clock input. The 81-ball Lite
SP WLCSP only supports 26 MHz external clock or crystal input.
The crystal or clock frequency selection is shown in Table 1 on
page 6, Table 2 on page 6, and Table 3 on page 6.
Figure 6. GPIO Interface Mode
Astoria
S Port
The XTALIN frequency is independent of the clock and data rate
of the 8051 microprocessor or any of the device interfaces
(including P-Port and S-Port). The internal PLL applies the
proper clock multiply option depending on the input frequency.
For applications that use an external clock source to drive
XTALIN, the XTALOUT pin must be left floating. The external
clock source must also stop high or low and not toggle, to
achieve the lowest possible current consumption. The
requirements for an external clock source are shown in Table 4
on page 6.
GPIO
Astoria has an on-chip oscillator circuit that uses an external
19.2, 24, and 26 MHz (±150 ppm) crystal with the following
characteristics:
SD/SDIO/MMC+/CE-ATA Port (S-Port)
When Astoria is configured with firmware to support SD, SDIO,
MMC+, and CE-ATA, this interface supports:
■ Parallel resonant
■ Fundamental mode
■ 1 mW drive level
■ The Multimedia Card System Specification, MMCA Technical
Committee, Version 4.1
■ SD Memory Card Specification – Part 1, Physical Layer
Specification, SD Group, Version 1.10, October 15, 2004
■ 12 pF (5% tolerance) load capacitors
■ 150 ppm
■ SD Memory Card Specification – Part 1, Physical Layer
Specification, SD Group, Version 2.0, May 9, 2006
Document Number: 001-13805 Rev. *M
Page 5 of 78
CYWB022XX Family
Figure 7. Crystal Configuration
Table 1. 100-ball FVBGA Clock Selection
Astoria
XTALSLC[1] XTALSLC[0]
Freq
Crystal/Clock
Crystal/Clock
Crystal/Clock
Clock
XTALIN
0
0
1
1
0
1
0
1
19.2 MHz
24 MHz
48 MHz
26 MHz
XTAL
XTALOUT
PLL
Crystal/Clock
12pf
12pf
Table 2. 81-ball SP WLCSP Clock Selection
* 12 pF capacitor values assumes a trace capacitance of 3 pF per
side on a four layer FR4 PCA
XTALSLC
Freq
Crystal/Clock
Clock
0
1
19.2 MHz
26 MHz
Clock
Table 3. 81-ball Lite SP WLCSP Clock Supports 26 MHz
XTALSLC
Freq
Crystal/Clock
NA
26 MHz Clock or Crystal
Table 4. External Clock Requirements
Specification
Unit
Parameter
Description
Min
–
Max
20
Vn (AVDDQ)
PN_100
PN_1k
Supply voltage noise at frequencies < 50 MHz
Input phase noise at 100 Hz
Input phase noise at 1 kHz offset
Input phase noise at 10 kHz offset
Input phase noise at 100 kHz offset
Input phase noise at 1 MHz offset
Duty cycle
mV p-p
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
–
–75
–104
–120
–128
–130
70
–
PN_10k
PN_100k
PN_1M
–
–
–
30
–
Maximum frequency deviation
Overshoot
150
3
ppm
–
%
Undershoot
–
–3
%
■ VDD is the supply voltage for the logic core. The nominal supply
voltage level is 1.8 V. This supplies the core logic circuits. The
same supply must also be used for AVDDQ
Power Domains
Astoria has multiple power domains that serve different purposes
within the chip.
■ AVDDQ is the 1.8 V supply for PLL and USB serializer analog
components. The same supply must also be used for VDD. The
maximum permitted noise on AVDDQ is 20 mV p-p
■ VDDQ refers to a group of four independent supply domains
for the digital I/Os. The nominal voltage level on these supplies
are 1.8 V, 2.5 V, or 3.3 V. The three separate I/O power domains
are:
■ XVDDQ is the clock I/O supply; 3.3 V for XTAL or 1.8 V for an
external clock
❐ PVDDQ – P-Port Processor interface I/O
❐ SNVDDQ – S-Port GPIF interface I/O
❐ SSVDDQ – S-Port SD interface I/O
❐ GVDDQ – Other miscellaneous I/O
Noise guideline for all supplies except AVDDQ is a maximum of
100 mV p-p. All I/O supplies of Astoria must be ON when a
system is active even if Astoria is not in use. The core VDD can
also be deactivated at any time to preserve power if there is a
minimum impedance of 1 k between the VDD pin and ground.
All I/Os tristate when the core is disabled.
■ UVDDQ is the 3.3-V nominal supply for the USB I/O and some
analog circuits. It also supplies power to the USB transceiver
■ VDD33 supply is required for the power sequence control
circuits. For more details, see Pin Assignments on page 9.
Document Number: 001-13805 Rev. *M
Page 6 of 78
CYWB022XX Family
Figure 8. Astoria Power Supply Domains
This mode is entered through the deassertion of the WAKEUP
input pin or through internal register settings. To leave this mode,
assert the WAKEUP, CE#, and RESET#; change state of
GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, and SD2_D3.
VDD
UVDDQ
D+
D-
*VDDQ
In this mode all configuration register settings and program RAM
contents are preserved. However, data in the buffers or other
parts of the data path, if any, is not guaranteed in values.
Therefore, the external processor must ensure that the required
data is read before placing Astoria in the standby mode.
I/O
D-CORE
USB-IO
In the standby mode:
■ The program counter is reset on waking up from standby mode
■ All outputs are tristated and I/O is placed in input only
configuration. Values of I/Os in standby mode are listed in the
pin assignments table
Power Supply Sequence
The power supplies are independently sequenced without
damaging the part. All power supplies must be up and stable
before the device operates. If the supplies are not stable, the
remaining domains are in low power (standby) state.
■ Core power supply must be retained
■ Hard Reset can be performed by asserting the RESET# input,
and Astoria is initialized
Power Modes
■ PLL is disabled
In addition to the normal operating mode, Astoria contains
several low power states when normal operation is not required.
■ USB switches the SWD+/SWD– to D+/D–
Core Power Down Mode
Normal Mode
The core power supply VDD is powered down in this state.
Because AVDDQ is tied to the same supply as VDD, it is also
powered down. The endpoint buffers, configuration registers,
and program RAM do not maintain state. All VDDQ power
supplies (except AVDDQ) must be ON and not power down in
this mode. VDD33 must also remain ON. It has an option that the
UVDDQ can be powered down or stay ON while VDD is powered
down when SWD+/SWD– are not connected. The UVDDQ
cannot be powered down when SWD+/SWD– is connected, or
Normal mode is the mode in which Astoria is fully functional. In
this mode, data transfer functions described in this document are
performed.
Suspend Mode
This mode is entered internally by 8051 (the external processor
only initiates entry into this mode through Mailbox commands).
This mode is exited by the D+ bus going low, GPIO[0] going to a
pre-determined state or by asserting CE# LOW.
VDD is active. When UVDDQ is powered down, D+/D– cannot be
driven by an external device.
In Astoria’s suspend mode:
In the WLCSP package, AVDDQ is internally tied to XVDDQ.
Due to this, the clock input at XTALIN must be brought to a
steady low level prior to entry into Core Power Down Mode. In
the WLCSP package, VDD33 is tied to UVDDQ internally.
UVDDQ must be ON during the core power down mode
■ The clocks are shut off
■ All I/Os maintain their previous state
■ Core power supply must be retained
■ The states of the configuration registers, endpoint buffers, and
the program RAM are maintained. All transactions must be
complete before Astoria enters suspend mode (state of
outstanding transactions are not preserved)
The core power down mode has two power down options:
■ Core only power down – VDD power down
■ Core and USB power down – VDD and UVDDQ are both
powered down. In this option, SWD+/SWD– are not connected
and cannot be driven by an external device
■ The firmware resumes its operation from where it was
suspended because the program counter is not reset
In these power down options, the endpoint buffers, configuration
registers, or the program RAM do not maintain state. It is
necessary to reload the firmware on exiting from this mode. All
VDDQ power supplies must be ON and not powered down in this
mode.
■ Only inputs that are sensed are RESET#, GPIO[0]/SD_CD,
GPIO[1]/SD2_CD, SD_D3, SD2_D3, D+, and CE#. The last
three are wake up sources (each can be individually enabled
or disabled)
■ Hard Reset can be performed by asserting the RESET# input,
and Astoria is initialized
In the 82-ball WLCSP package, in the core power down mode,
the USB switches the SWD+/SWD– to D+/D–.
Standby Mode
Standby mode is a low-power state. This is the lowest power
mode of Astoria while still maintaining external supply levels.
Document Number: 001-13805 Rev. *M
Page 7 of 78
CYWB022XX Family
Packages and Interface Options
Astoria provides one 100-ball VFBGA, one 100-ball BGA, one 121-ball FBGA and two types of 81-ball WLCSP packages. The two
WLCSP packages are SP WLCSP and Lite SP WLCSP. These two packages have different interface options as listed in Table 5. The
100-ball VFBGA/BGA package pin list is listed in Table 6 on page 9, the 81-ball SP CSP package is listed in Table 10 on page 21,
and the 81-ball Lite SP CSP package in Table 11 on page 24.
Table 5. Interface Options for 100-ball VFBGA, 81-ball SP, and 81-ball Lite SP
P-Port
S-Port
SD2 GPIF GPIO
Clock
Package
PNAN
Ext
CLK
Freq.
(MHz)
PCRAM SRAM ADM
I2C
SPI
SD1
Crystal
D
100-ball BGA /
VFBGA
19.2,
24, 26,
48
121-ball FBGA
19.2,
24, 26,
48
81-ball SP
WLCSP
19.2,
26
81-ball Lite SP
WLCSP
26
Document Number: 001-13805 Rev. *M
Page 8 of 78
CYWB022XX Family
Pin Assignments
Table 6. Astoria 100-ball VFBGA Package Pin Assignments
Power
Pin Description
Domain
Pin Name
Ball #
PCRAM
Non-Multiplexing
I/O Address / Data I/O
bus Multiplexing
(ADM)
SRAM
I/O
PNAND
I/O
SPI
I/O
J2
CLK (pull low in
Asyn mode)
I
I
I
CLK (pull low in
Async mode)
I
I
I
Ext pull low
CE#
I
I
I
Ext pull low
CE#
I
I
I
SCK
SS#
I
I
I
Clock
PVDDQ
VGND
G1
H3
CE#
CE#
CE# or SPI Slave
Select
A7
Ext pull up
A7
A7 > 1:SBD
A7 > 0:LBD
Ext pull up
Addr. Bus 7
2
H2
H1
J3
A6
A5
A4
A3
I
I
I
I
SDA
I
I
I
I
A6
A5
A4
A3
I
I
I
I
SDA
SCL
WP#
I/O SDA
I/O SCL
I/O A6 or I C data
2
SCL
I/O A5 or I C clock
Ext pull up
I
I
Ext pull up
I
I
A4 or PNAND WP
A3
J1
A3 = 0 (Ext pull
low)
A3 = 0 (Ext pull
low)
A3 = 1 (Ext pull up)
K3
A2
I
A2 = 1 (Ext pull up)
I
A2
I
A2 = 0 (Ext pull
low)
I
A2 = 0 (Ext pull
low)
I
A2
K2
K1
G2
G3
F1
F2
F3
E1
E2
E3
D1
D2
D3
C1
C2
C3
B1
B2
A1
B3
A2
A3
A4
B4
A1
I
I
Ext pull up
Ext pull up
I
I
A1
A0
I
I
RB#
CLE
O
I
Ext pull up
Ext pull up
I
I
A1 or PNAND R/B#
A0 or PNAND CLE
D15, AD15, or I/O15
D14, AD14, or I/O14
D13, AD13, or I/O13
D12, AD12, or I/O12
D11, AD11, or I/O11
D10, AD10, or I/O10
D9, AD9, or I/O9
D8, AD8, or I/O8
D7, AD7, or I/O7
D6, AD6, or I/O6
D5, AD5, or I/O5
D4, AD4, or I/O4
D3, AD3, or I/O3
D2, AD2, or I/O2
SPI SDO, AD1or D1
SPI SDI, AD0, or D0
Address Valid
A0
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
ADV#
OE#
I/O AD[15]
I/O AD[14]
I/O AD[13]
I/O AD[12]
I/O AD[11]
I/O AD[10]
I/O AD[9]
I/O AD[8]
I/O AD[7]
I/O AD[6]
I/O AD[5]
I/O AD[4]
I/O AD[3]
I/O AD[2]
I/O AD[1]
I/O AD[0]
I/O DQ[15]
I/O DQ[14]
I/O DQ[13]
I/O DQ[12]
I/O DQ[11]
I/O DQ[10]
I/O DQ[9]
I/O DQ[8]
I/O DQ[7]
I/O DQ[6]
I/O DQ[5]
I/O DQ[4]
I/O DQ[3]
I/O DQ[2]
I/O DQ[1]
I/O DQ[0]
I
I/O I/O[15]
I/O I/O[14]
I/O I/O[13]
I/O I/O[12]
I/O I/O[11]
I/O I/O[10]
I/O I/O[9]
I/O I/O[8]
I/O I/O[7]
I/O I/O[6]
I/O I/O[5]
I/O I/O[4]
I/O I/O[3]
I/O I/O[2]
I/O I/O[1]
I/O I/O[0]
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O SDO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I/O SDI
I
I
ADV#
OE#
I
I
ALE
I
I
Ext pull up
Ext pull up
Ext pull up
SINT#
I
I
I
OE#
RE#
I
Output Enable
WE#
I
WE#
WE#
I
WE#
INT#
DRQ#
DACK#
I
I
WE#
INT#
O
O
I
INT#
O
O
I
INT#
O
O
I
O
O
I
O
O
I
INT Request
GVDDQ
VGND
DRQ#
DACK#
DRQ#
DACK#
DRQ#
DACK#
N/C
DMA Request
Ext pull up
DMA
Acknowledgement
A5
A6
A7
C6
D+
I/O/Z USB D+
UVDDQ
UVSSQ
D–
I/O/Z USB D–
SWD+
SWD–
I/O/Z USB Switch DP
I/O/Z USB Switch DM
Document Number: 001-13805 Rev. *M
Page 9 of 78
CYWB022XX Family
Table 6. Astoria 100-ball VFBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
Double SDIO
Configuration
SDIO & GPIO
Configuration
GPIO
Configuration
GPIF
Configuration
GPIF & GPIO
Configuration
Ball #
I/O
I/O
I/O
I/O
I/O
G9
SD_D[7]
I/O SD_D[7]
I/O SD_D[6]
I/O SD_D[5]
I/O SD_D[4]
I/O SD_D[3]
I/O SD_D[2]
I/O SD_D[1]
I/O SD_D[0]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O GPIF_DATA[15]
I/O GPIF_DATA[14]
I/O GPIF_DATA[13]
I/O GPIF_DATA[12]
I/O GPIF_DATA[11]
I/O GPIF_DATA[10]
I/O GPIF_DATA[9]
I/O GPIF_DATA[8]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O SD Data or GPIO or
GPIF Data
SSVDDQ
VGND
G10 SD_D[6]
F9 SD_D[5]
F10 SD_D[4]
E9 SD_D[3]
E10 SD_D[2]
D9 SD_D[1]
D10 SD_D[0]
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
F8
G8
H8
SD_CLK
SD_CMD
SD_POW
O
SD_CLK
O
PC[7] (GPIO)
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
N/C
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
PC[5] (GPIO)
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O SD Power or GPIO
SD Write Protect
I/O SD_CMD
SD_POW
I/O PC[3] (GPIO)
PC[6] (GPIO)
H10 SD_WP
I
SD_WP
I
N/C
K7
K8
J8
SD2_D[7]
SD2_D[6]
SD2_D[5]
SD2_D[4]
SD2_D[3]
SD2_D[2]
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O GPIF_DATA[7]
I/O GPIF_DATA[7]
I/O SD2 Data or GPIO or SNVDDQ
GPIF Data
VGND
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K9
J9
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
H9
I/O SD2 Data or GPIO or
GPIF Data
K10 SD2_D[1]
J10 SD2_D[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K6
J6
J5
K4
H6
J7
J4
K5
SD2_CLK
SD2_CMD
SD2_POW
N/C
O
PA[6] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O SD2 Clock or GPIO
I/O SD2 CMD or GPIO
I/O SD2 Power or GPIO
I/O PA[7] (GPIO)
O
O
O
PC[0] (GPIO)
N/C
O
O
N/C
N/C
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF Control Signal
GPIF Control Signal
N/C
N/C
PA[5] (GPIO)
N/C
I/O PA[5] (GPIO)
I/O PA[5] (GPIO)
N/C
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O GPIO
I
N/C
I
I
O
O
GPIF Ready Signal
SD2_WP
O
PC[2] (GPIO)
I/O SD Write Protect or
GPIO
B10 RESETOUT
O
RESETOUT
O
RESETOUT
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT /
GPIF_RDY[1]
O
Reset Out
GVDDQ
VGND
C9
D8
SD2_CD
I/O PC-5 (GPIO[1])
I
I/O PC-5 (GPIO[1])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O GPIO or SD2 CD
I/O GPIO or SD CD
PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])
SD_CD SD_CD
I
I
C10 RESET#
C7 WAKEUP
I
I
RESET
Wake Up Signal
Document Number: 001-13805 Rev. *M
Page 10 of 78
CYWB022XX Family
Table 6. Astoria 100-ball VFBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
C5
C4
E8
C8
D7
A8
B8
XTALSLC[1]
XTALSLC[0]
TEST[2]
I
I
Clock Select 1
Clock Select 0
Test Cfg 2
GVDDQ
VGND
TEST[1]
Test Cfg 1
TEST[0]
Test Cfg 0
XTALIN
I
Crystal/Clock IN
Crystal Out
XVDDQ
VGND
XTALOUT
O
D4, PVDDQ
H4
Power Processor I/F VDD
H5
B5
H7
D6
B9
B7
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
Power GPIF VDD
Power USB VDD
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Crystal VDD
Power Core VDD
D5, VDD
G4,
G5,
G6,
G7,
F7
A10 VDD33
Power Independent 3.3 V
Power USB GND
B6
A9
UVSSQ
AVSSQ
Power Analog GND
Power Core GND
E4, VGND
E5,
E6,
E7,
F4,
F5,
F6
Document Number: 001-13805 Rev. *M
Page 11 of 78
CYWB022XX Family
Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments
Power
Pin Description
Domain
Pin Name
Ball #
PCRAM Non
Multiplexing
I/O Addr/Data bus I/O
Multiplexing
SRAM
I/O
PNAND
I/O
SPI
I/O
(ADM)
J2
CLK (pull-low in
Asyn mode)
I
I
I
CLK (pull-low in
Async mode)
I
I
I
Ext pull-low
CE#
I
I
I
Ext pull-low
CE#
I
I
I
SCK
SS#
I
I
I
Clock
PVDDQ
VGND
G1
H3
CE#
CE#
CE# or SPI Slave
Select
A7
Ext pull-up
A7
A7 > 1:SBD
A7 > 0: LBD
Ext pull-up
Addr. Bus 7
2
H2
H1
J3
A6
A5
A4
A3
I
I
I
I
SDA
I
I
I
I
A6
A5
A4
A3
I
I
I
I
SDA
SCL
WP#
I/O SDA
I/O SCL
I/O A6 or I C data
2
SCL
I/O A5 or I C clock
Ext pull-up
I
I
Ext pull-up
I
I
A4 or PNAND WP
A3
J1
A3 = 0 (Ext
pull-low)
A3 = 0 (Ext
pull-low)
A3 = 1 (Ext pull-up)
K3
A2
I
A2 = 1 (Ext pull-up)
I
A2
I
A2 = 0 (Ext
pull-low)
I
A2 = 0 (Ext
pull-low)
I
A2
K2
K1
G2
G3
F1
F2
F3
E1
E2
E3
D1
D2
D3
C1
C2
C3
B1
B2
A1
B3
A2
A3
A4
B4
A1
I
I
Ext pull-up
Ext pull-up
I
I
A1
A0
I
I
RB#
CLE
O
I
Ext pull-up
Ext pull-up
I
I
A1 or PNAND R/B#
A0 or PNAND CLE
D15, AD15, or I/O15
D14, AD14, or I/O14
D13, AD13, or I/O13
D12, AD12, or I/O12
D11, AD11, or I/O11
D10, AD10, or I/O10
D9, AD9, or I/O9
D8, AD8, or I/O8
D7, AD7, or I/O7
D6, AD6, or I/O6
D5, AD5, or I/O5
D4, AD4, or I/O4
D3, AD3, or I/O3
D2, AD2, or I/O2
SPI SDO, AD1or D1
SPI SDI, AD0, or D0
Address Valid
A0
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
ADV#
OE#
I/O AD[15]
I/O AD[14]
I/O AD[13]
I/O AD[12]
I/O AD[11]
I/O AD[10]
I/O AD[9]
I/O AD[8]
I/O AD[7]
I/O AD[6]
I/O AD[5]
I/O AD[4]
I/O AD[3]
I/O AD[2]
I/O AD[1]
I/O AD[0]
I/O DQ[15]
I/O DQ[14]
I/O DQ[13]
I/O DQ[12]
I/O DQ[11]
I/O DQ[10]
I/O DQ[9]
I/O DQ[8]
I/O DQ[7]
I/O DQ[6]
I/O DQ[5]
I/O DQ[4]
I/O DQ[3]
I/O DQ[2]
I/O DQ[1]
I/O DQ[0]
I
I/O I/O[15]
I/O I/O[14]
I/O I/O[13]
I/O I/O[12]
I/O I/O[11]
I/O I/O[10]
I/O I/O[9]
I/O I/O[8]
I/O I/O[7]
I/O I/O[6]
I/O I/O[5]
I/O I/O[4]
I/O I/O[3]
I/O I/O[2]
I/O I/O[1]
I/O I/O[0]
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O SDO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I/O SDI
I
I
ADV#
OE#
I
I
ALE
I
I
Ext pull-up
Ext pull-up
Ext pull-up
SINT#
I
I
I
OE#
RE#
I
Output Enable
WE#
I
WE#
WE#
I
WE#
INT#
DRQ#
DACK#
I
I
WE#
INT#
O
O
I
INT#
O
O
I
INT#
O
O
I
O
O
I
O
O
I
INT Request
GVDDQ
VGND
DRQ#
DACK#
DRQ#
DACK#
DRQ#
DACK#
N/C
DMA Request
Ext pull-up
DMA
Acknowledgement
A5
A6
A7
C6
D+
I/O/Z USB D+
UVDDQ
UVSSQ
D–
I/O/Z USB D–
SWD+
SWD–
I/O/Z USB Switch DP
I/O/Z USB Switch DM
Document Number: 001-13805 Rev. *M
Page 12 of 78
CYWB022XX Family
Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
Double SDIO
Configuration
SDIO & GPIO
Configuration
GPIO
Configuration
GPIF
Configuration
GPIF & GPIO
Configuration
Ball #
I/O
I/O
I/O
I/O
I/O
G9
SD_D[7]
I/O SD_D[7]
I/O SD_D[6]
I/O SD_D[5]
I/O SD_D[4]
I/O SD_D[3]
I/O SD_D[2]
I/O SD_D[1]
I/O SD_D[0]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O GPIF_DATA[15]
I/O GPIF_DATA[14]
I/O GPIF_DATA[13]
I/O GPIF_DATA[12]
I/O GPIF_DATA[11]
I/O GPIF_DATA[10]
I/O GPIF_DATA[9]
I/O GPIF_DATA[8]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O SD Data or GPIO or
GPIF Data
SSVDDQ
VGND
G10 SD_D[6]
F9 SD_D[5]
F10 SD_D[4]
E9 SD_D[3]
E10 SD_D[2]
D9 SD_D[1]
D10 SD_D[0]
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
F8
G8
H8
SD_CLK
SD_CMD
SD_POW
O
SD_CLK
O
PC[7] (GPIO)
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
PC[5] (GPIO)
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O SD Power or GPIO
SD Write Protect
I/O SD_CMD
SD_POW
I/O PC[3] (GPIO)
PC[6] (GPIO)
H10 SD_WP
I
SD_WP
I
N/C
I
N/C
K7
K8
J8
SD2_D[7]
SD2_D[6]
SD2_D[5]
SD2_D[4]
SD2_D[3]
SD2_D[2]
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O GPIF_DATA[7]
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O GPIF_DATA[7]
I/O SD2 Data or GPIO or SNVDDQ
GPIF Data
VGND
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K9
J9
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
H9
I/O SD2 Data or GPIO or
GPIF Data
K10 SD2_D[1]
J10 SD2_D[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K6
J6
J5
K4
H6
J7
J4
K5
SD2_CLK
SD2_CMD
SD2_POW
N/C
O
PA[6] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA [7] (GPIO)
I/O PC[0] (GPIO)
I/O SD2 Clock or GPIO
I/O SD2 CMD or GPIO
I/O SD2 Power or GPIO
I/O PA[7] (GPIO)
O
O
O
PC[0] (GPIO)
N/C
O
O
N/C
N/C
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF Control Signal
GPIF Control Signal
N/C
N/C
PA[5] (GPIO)
N/C
I/O PA[5] (GPIO)
I/O PA[5] (GPIO)
N/C
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O GPIO
I
N/C
I
I
O
O
GPIF Ready Signal
SD2_WP
O
PC[2] (GPIO)
I/O SD Write Protect or
GPIO
B10 RESETOUT
O
RESETOUT
O
RESETOUT
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT
GVDDQ
VGND
C9
D8
SD2_CD
I/O PC-5 (GPIO[1])
I
I/O PC-5 (GPIO[1])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O GPIO or SD2 CD
I/O GPIO or SD CD
PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])
SD_CD SD_CD
I
I
C10 RESET#
C7 WAKEUP
I
I
RESET
Wake Up Signal
Document Number: 001-13805 Rev. *M
Page 13 of 78
CYWB022XX Family
Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
C5
C4
E8
C8
D7
A8
B8
XTALSLC[1]
XTALSLC[0]
TEST[2]
I
I
Clock Select 1
Clock Select 0
Test Cfg 2
GVDDQ
VGND
TEST[1]
Test Cfg 1
TEST[0]
Test Cfg 0
XTALIN
I
Crystal / Clock IN
Crystal Out
XVDDQ
VGND
XTALOUT
O
D4
H4
PVDDQ
Power Processor I/F VDD
H5
B5
H7
D6
B9
B7
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
Power GPIF VDD
Power USB VDD
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Crystal VDD
Power Core VDD
D5, VDD
G4,
G5,
G6,
G7,
F7
A10 VDD33
Power Independent 3.3 V
Power USB GND
B6
A9
UVSSQ
AVSSQ
Power Analog GND
Power Core GND
E4, VGND
E5,
E6,
E7,
F4,
F5,
F6
Document Number: 001-13805 Rev. *M
Page 14 of 78
CYWB022XX Family
Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments
Power
Pin Description
Domain
Pin Name
Ball #
PCRAM Non
Multiplexing
I/O Addr/Data bus I/O
Multiplexing
SRAM
I/O
PNAND
I/O
SPI
I/O
(ADM)
J2
CLK (pull-low in
Asyn mode)
I
I
I
CLK (pull-low in
Async mode)
I
I
I
Ext pull-low
CE#
I
I
I
Ext pull-low
CE#
I
I
I
SCK
SS#
I
I
I
Clock
PVDDQ
VGND
G1
H3
CE#
CE#
CE# or SPI Slave
Select
A7
Ext pull-up
A7
A7 > 1:SBD
A7 > 0: LBD
Ext pull-up
Addr. Bus 7
2
H2
H1
J3
A6
A5
A4
A3
I
I
I
I
SDA
I
I
I
I
A6
A5
A4
A3
I
I
I
I
SDA
SCL
WP#
I/O SDA
I/O SCL
I/O A6 or I C data
2
SCL
I/O A5 or I C clock
Ext pull-up
I
I
Ext pull-up
I
I
A4 or PNAND WP
A3
J1
A3 = 0 (Ext
pull-low)
A3 = 0 (Ext
pull-low)
A3 = 1 (Ext pull-up)
K3
A2
I
A2 = 1 (Ext pull-up)
I
A2
I
A2 = 0 (Ext
pull-low)
I
A2 = 0 (Ext
pull-low)
I
A2
K2
K1
G2
G3
F1
F2
F3
E1
E2
E3
D1
D2
D3
C1
C2
C3
B1
B2
A1
B3
A2
A3
A4
B4
A1
I
I
Ext pull-up
Ext pull-up
I
I
A1
A0
I
I
RB#
CLE
O
I
Ext pull-up
Ext pull-up
I
I
A1 or PNAND R/B#
A0 or PNAND CLE
D15, AD15, or I/O15
D14, AD14, or I/O14
D13, AD13, or I/O13
D12, AD12, or I/O12
D11, AD11, or I/O11
D10, AD10, or I/O10
D9, AD9, or I/O9
D8, AD8, or I/O8
D7, AD7, or I/O7
D6, AD6, or I/O6
D5, AD5, or I/O5
D4, AD4, or I/O4
D3, AD3, or I/O3
D2, AD2, or I/O2
SPI SDO, AD1or D1
SPI SDI, AD0, or D0
Address Valid
A0
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
ADV#
OE#
I/O AD[15]
I/O AD[14]
I/O AD[13]
I/O AD[12]
I/O AD[11]
I/O AD[10]
I/O AD[9]
I/O AD[8]
I/O AD[7]
I/O AD[6]
I/O AD[5]
I/O AD[4]
I/O AD[3]
I/O AD[2]
I/O AD[1]
I/O AD[0]
I/O DQ[15]
I/O DQ[14]
I/O DQ[13]
I/O DQ[12]
I/O DQ[11]
I/O DQ[10]
I/O DQ[9]
I/O DQ[8]
I/O DQ[7]
I/O DQ[6]
I/O DQ[5]
I/O DQ[4]
I/O DQ[3]
I/O DQ[2]
I/O DQ[1]
I/O DQ[0]
I
I/O I/O[15]
I/O I/O[14]
I/O I/O[13]
I/O I/O[12]
I/O I/O[11]
I/O I/O[10]
I/O I/O[9]
I/O I/O[8]
I/O I/O[7]
I/O I/O[6]
I/O I/O[5]
I/O I/O[4]
I/O I/O[3]
I/O I/O[2]
I/O I/O[1]
I/O I/O[0]
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O Ext pull-up
I/O SDO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I/O SDI
I
I
ADV#
OE#
I
I
ALE
I
I
Ext pull-up
Ext pull-up
Ext pull-up
SINT#
I
I
I
OE#
RE#
I
Output Enable
WE#
I
WE#
WE#
I
WE#
INT#
DRQ#
DACK#
I
I
WE#
INT#
O
O
I
INT#
O
O
I
INT#
O
O
I
O
O
I
O
O
I
INT Request
GVDDQ
VGND
DRQ#
DACK#
DRQ#
DACK#
DRQ#
DACK#
N/C
DMA Request
Ext pull-up
DMA
Acknowledgement
Document Number: 001-13805 Rev. *M
Page 15 of 78
CYWB022XX Family
Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
Double SDIO
Configuration
SDIO & GPIO
Configuration
GPIO
Configuration
GPIF
Configuration
GPIF & GPIO
Configuration
I/O
I/O
I/O
I/O
I/O
G9
SD_D[7]
I/O SD_D[7]
I/O SD_D[6]
I/O SD_D[5]
I/O SD_D[4]
I/O SD_D[3]
I/O SD_D[2]
I/O SD_D[1]
I/O SD_D[0]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O GPIF_DATA[15]
I/O GPIF_DATA[14]
I/O GPIF_DATA[13]
I/O GPIF_DATA[12]
I/O GPIF_DATA[11]
I/O GPIF_DATA[10]
I/O GPIF_DATA[9]
I/O GPIF_DATA[8]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O SD Data or GPIO or
GPIF Data
SSVDDQ
VGND
G10 SD_D[6]
F9 SD_D[5]
F10 SD_D[4]
E9 SD_D[3]
E10 SD_D[2]
D9 SD_D[1]
D10 SD_D[0]
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
F8
G8
H8
SD_CLK
SD_CMD
SD_POW
O
SD_CLK
O
PC[7] (GPIO)
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
N/C
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
PC[5] (GPIO)
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O SD Power or GPIO
SD Write Protect
I/O SD_CMD
SD_POW
I/O PC[3] (GPIO)
PC[6] (GPIO)
H10 SD_WP
I
SD_WP
I
N/C
K7
K8
J8
SD2_D[7]
SD2_D[6]
SD2_D[5]
SD2_D[4]
SD2_D[3]
SD2_D[2]
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O GPIF_DATA[7]
I/O GPIF_DATA[7]
I/O SD2 Data or GPIO or SNVDDQ
GPIF Data
VGND
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K9
J9
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
H9
I/O SD2 Data or GPIO or
GPIF Data
K10 SD2_D[1]
J10 SD2_D[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K6
J6
J5
K4
H6
J7
J4
K5
SD2_CLK
SD2_CMD
SD2_POW
N/C
O
PA[6] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O SD2 Clock or GPIO
I/O SD2 CMD or GPIO
I/O SD2 Power or GPIO
I/O PA[7] (GPIO)
O
O
O
PC[0] (GPIO)
N/C
O
O
N/C
N/C
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF Control Signal
GPIF Control Signal
N/C
N/C
PA[5] (GPIO)
N/C
I/O PA[5] (GPIO)
I/O PA[5] (GPIO)
N/C
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O GPIO
I
N/C
I
I
O
O
GPIF Ready Signal
SD2_WP
O
PC[2] (GPIO)
I/O SD Write Protect or
GPIO
B10 RESETOUT
O
RESETOUT
O
RESETOUT
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT /
GPIF_RDY[1]
O
Reset Out
GVDDQ
VGND
C9
D8
SD2_CD
I/O PC-5 (GPIO[1])
I
I/O PC-5 (GPIO[1])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O GPIO or SD2 CD
I/O GPIO or SD CD
PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])
SD_CD SD_CD
I
I
C10 RESET#
C7 WAKEUP
I
I
RESET
Wake Up Signal
Document Number: 001-13805 Rev. *M
Page 16 of 78
CYWB022XX Family
Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
C5
C4
E8
C8
D7
A8
B8
XTALSLC[1]
XTALSLC[0]
TEST[2]
I
I
Clock Select 1
Clock Select 0
Test Cfg 2
GVDDQ
VGND
TEST[1]
Test Cfg 1
TEST[0]
Test Cfg 0
XTALIN
I
Crystal / Clock IN
Crystal Out
XVDDQ
VGND
XTALOUT
O
D4
H4
PVDDQ
Power Processor I/F VDD
H5
B5
H7
D6
B9
B7
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
Power GPIF VDD
Power USB VDD
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Crystal VDD
Power Core VDD
D5, VDD
G4,
G5,
G6,
G7,
F7
A10 VDD33
Power Independent 3.3 V
Power USB GND
B6
A9
UVSSQ
AVSSQ
Power Analog GND
Power Core GND
E4, VGND
E5,
E6,
E7,
F4,
F5,
F6
Document Number: 001-13805 Rev. *M
Page 17 of 78
CYWB022XX Family
Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments
Power
Pin Description
Domain
Pin Name
Ball #
J2
Pull Direction
I/O
P/D
P/U
P/U
P/U
P/U
P/D
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
N/C
N/C
P/U
I
I
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
No Connect
No Connect
Pull-up
PVDDQ
VGND
G1
H3
J3
I
I
J1
I
K3
K2
K1
G2
G3
F1
F2
F3
E1
E2
E3
D1
D2
D3
C1
C2
C3
B1
B2
A1
B3
A2
A3
A4
B4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
O
O
I
GVDDQ
VGND
Interface Pins
I/O Pin Description
2
H2
H1
SDA
SCL
I/O I C data
PVDDQ
VGND
2
I/O I C clock
A5
A6
A7
C6
D+
I/O/Z USB D+
UVDDQ
UVSSQ
D–
I/O/Z USB D–
SWD+
SWD–
I/O/Z USB Switch DP
I/O/Z USB Switch DM
Document Number: 001-13805 Rev. *M
Page 18 of 78
CYWB022XX Family
Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
Double SDIO
Configuration
SDIO & GPIO
Configuration
GPIO
Configuration
GPIF
Configuration
GPIF & GPIO
Configuration
I/O
I/O
I/O
I/O
I/O
G9
SD_D[7]
I/O SD_D[7]
I/O SD_D[6]
I/O SD_D[5]
I/O SD_D[4]
I/O SD_D[3]
I/O SD_D[2]
I/O SD_D[1]
I/O SD_D[0]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O GPIF_DATA[15]
I/O GPIF_DATA[14]
I/O GPIF_DATA[13]
I/O GPIF_DATA[12]
I/O GPIF_DATA[11]
I/O GPIF_DATA[10]
I/O GPIF_DATA[9]
I/O GPIF_DATA[8]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O SD Data or GPIO or
GPIF Data
SSVDDQ
VGND
G10 SD_D[6]
F9 SD_D[5]
F10 SD_D[4]
E9 SD_D[3]
E10 SD_D[2]
D9 SD_D[1]
D10 SD_D[0]
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
F8
G8
H8
SD_CLK
SD_CMD
SD_POW
O
SD_CLK
O
PC[7] (GPIO)
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
N/C
I/O PC[7] (GPIO)
I/O PC[3] (GPIO)
I/O PC[6] (GPIO)
PC[5] (GPIO)
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O SD Power or GPIO
SD Write Protect
I/O SD_CMD
SD_POW
I/O PC[3] (GPIO)
PC[6] (GPIO)
H10 SD_WP
I
SD_WP
I
N/C
K7
K8
J8
SD2_D[7]
SD2_D[6]
SD2_D[5]
SD2_D[4]
SD2_D[3]
SD2_D[2]
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O GPIF_DATA[7]
I/O GPIF_DATA[7]
I/O SD2 Data or GPIO or SNVDDQ
GPIF Data
VGND
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O GPIF_DATA[6]
I/O GPIF_DATA[5]
I/O GPIF_DATA[4]
I/O GPIF_DATA[3]
I/O GPIF_DATA[2]
I/O GPIF_DATA[1]
I/O GPIF_DATA[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K9
J9
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
H9
I/O SD2 Data or GPIO or
GPIF Data
K10 SD2_D[1]
J10 SD2_D[0]
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
K6
J6
J5
K4
H6
J7
J4
K5
SD2_CLK
SD2_CMD
SD2_POW
N/C
O
PA[6] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O SD2 Clock or GPIO
I/O SD2 CMD or GPIO
I/O SD2 Power or GPIO
I/O PA[7] (GPIO)
O
O
O
PC[0] (GPIO)
N/C
O
O
N/C
N/C
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF Control Signal
GPIF Control Signal
N/C
N/C
PA[5] (GPIO)
N/C
I/O PA[5] (GPIO)
I/O PA[5] (GPIO)
N/C
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O PA[5] (GPIO)
GPIF_RDY[0]
I/O PC[2] (GPIO)
I/O GPIO
I
N/C
I
I
O
O
GPIF Ready Signal
SD2_WP
O
PC[2] (GPIO)
I/O SD Write Protect or
GPIO
B10 RESETOUT
O
RESETOUT
O
RESETOUT
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT /
GPIF_RDY[1]
O
Reset Out
GVDDQ
VGND
C9
D8
SD2_CD
I/O PC-5 (GPIO[1])
I
I/O PC-5 (GPIO[1])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O GPIO or SD2 CD
I/O GPIO or SD CD
PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])
SD_CD SD_CD
I
I
C10 RESET#
C7 WAKEUP
I
I
RESET
Wake Up Signal
Document Number: 001-13805 Rev. *M
Page 19 of 78
CYWB022XX Family
Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
C5
C4
E8
C8
D7
A8
B8
XTALSLC[1]
XTALSLC[0]
TEST[2]
I
I
Clock Select 1
Clock Select 0
Test Cfg 2
GVDDQ
VGND
TEST[1]
Test Cfg 1
TEST[0]
Test Cfg 0
XTALIN
I
Crystal/Clock IN
Crystal Out
XVDDQ
VGND
XTALOUT
O
D4
H4
PVDDQ
Power Processor I/F VDD
H5
B5
H7
D6
B9
B7
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
Power NAND VDD
Power USB VDD
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Crystal VDD
Power Core VDD
D5, VDD
G4,
G5,
G6,
G7,
F7
A10 VDD33
Power Independent 3.3 V
Power USB GND
B6
A9
UVSSQ
AVSSQ
Power Analog GND
Power Core GND
E4, VGND
E5,
E6,
E7,
F4,
F5,
F6
Document Number: 001-13805 Rev. *M
Page 20 of 78
CYWB022XX Family
Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments
Power
Pin Description
Domain
Pin Name
Ball #
H9
PNAND
I/O
SPI
I/O
Ext pull low
CE#
I
I
SCK
SS#
I
I
Clock
PVDDQ
VGND
F9
CE# or SPI Slave
Select
E7
H8
J9
SDA
I/O SDA
I/O SCL
I/O I2C data
I/O I2C clock
SCL
WP#
I
I
Ext pull up
A[3]=0; (Ext pull up)
I
I
PNAND WP
A[3]
G8
E6
G9
F8
D9
D8
C9
B9
C8
C7
B8
A8
B7
B6
A7
C1
A[3]=0; (Ext pull low)
A[2]=0; (Ext pull low)
RB#
I
A[2]=0; (Ext pull low)
Ext pull up
I
A[2]
O
I
I
PNAND R/B#
PNAND CLE
IO7
CLE
Ext pull up
I
I/O[7]
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O Ext pull up
I/O SDO
I
I/O[6]
I
IO6
I/O[5]
I
IO5
I/O[4]
I
IO4
I/O[3]
I
IO3
I/O[2]
I
IO2
I/O[1]
O
I
IO1 or SPI SDO
IO0 or SPI SDI
Address Valid
Output Enable
WE#
I/O[0]
I/O SDI
ALE
I
I
Ext pull up
Ext pull up
Ext pull up
SINT#
I
RE#
I
WE#
I
I
INT#
O
O
INT Request
GVDDQ
VGND
A4
A5
C4
C5
D+
I/O/Z USB D+
UVDDQ
UVSSQ
D–
I/O/Z USB D–
SWD+
SWD–
I/O/Z USB Switch D+
I/O/Z USB Switch D–
Document Number: 001-13805 Rev. *M
Page 21 of 78
CYWB022XX Family
Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
Double SDIO
Configuration
SDIO & GPIO
Configuration
GPIO
Configuration
GPIF
Configuration
GPIF & GPIO
Configuration
Ball #
I/O
I/O
I/O
I/O
I/O
H2
SD_D[7]
SD_D[6]
SD_D[5]
SD_D[4]
SD_D[3]
SD_D[2]
SD_D[1]
SD_D[0]
I/O SD_D[7]
I/O SD_D[6]
I/O SD_D[5]
I/O SD_D[4]
I/O SD_D[3]
I/O SD_D[2]
I/O SD_D[1]
I/O SD_D[0]
I/O PD[7] (GPIO)
I/O PD[6] (GPIO)
I/O PD[5] (GPIO)
I/O PD[4] (GPIO)
I/O PD[3] (GPIO)
I/O PD[2] (GPIO)
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O GPIF_DATA [15] I/O PD[7] (GPIO)
I/O GPIF_DATA [14] I/O PD[6] (GPIO)
I/O GPIF_DATA [13] I/O PD[5] (GPIO)
I/O GPIF_DATA [12] I/O PD[4] (GPIO)
I/O SD Data or GPIO or
GPIF Data
SSVDDQ
VGND
H1
G3
G2
F2
F3
E3
E2
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
I/O GPIF_DATA [11]
I/O PD[3] (GPIO)
I/O SD Data or GPIO or
GPIF Data
I/O GPIF_DATA [10] I/O PD[2] (GPIO)
I/O SD Data or GPIO or
GPIF Data
I/O GPIF_DATA [9]
I/O GPIF_DATA [8]
I/O PD[1] (GPIO)
I/O PD[0] (GPIO)
I/O SD Data or GPIO or
GPIF Data
I/O SD Data or GPIO or
GPIF Data
G1
F4
J1
SD_CLK
SD_CMD
SD_POW
SD_WP
O
SD_CLK
PC-7 (GPIO)
I/O PC-7 (GPIO)
I/O PC-3 (GPIO)
I/O PC-6 (GPIO)
I/O PC-7 (GPIO)
I/O PC-3 (GPIO)
I/O PC-6 (GPIO)
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O SD Power or GPIO
I/O SD Write Protect
I/O SD_CMD
I/O PC-3 (GPIO)
O
I
SD_POW
SD_W
O
I
PC-6 (GPIO)
N/C
E1
H5
I
N/C
I
PC-5 (GPIO)
SD2_D[7]
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O PB[7] (GPIO)
I/O PB[6] (GPIO)
I/O PB[5] (GPIO)
I/O PB[4] (GPIO)
I/O PB[3] (GPIO)
I/O PB[2] (GPIO)
I/O PB[1] (GPIO)
I/O PB[0] (GPIO)
I/O GPIF_DATA [7]
I/O GPIF_DATA [6]
I/O GPIF_DATA [5]
I/O GPIF_DATA [4]
I/O GPIF_DATA [3]
I/O GPIF_DATA [2]
I/O GPIF_DATA [1]
I/O GPIF_DATA [0]
I/O GPIF_DATA [7]
I/O GPIF_DATA [6]
I/O GPIF_DATA [5]
I/O GPIF_DATA [4]
I/O GPIF_DATA [3]
I/O GPIF_DATA [2]
I/O GPIF_DATA [1]
I/O GPIF_DATA [0]
I/O SD2 Data or GPIO or SNVDDQ
GPIF Data
VGND
J4
SD2_D[6]
SD2_D[5]
SD2_D[4]
SD2_D[3]
SD2_D[2]
SD2_D[1]
SD2_D[0]
I/O SD2 Data or GPIO or
GPIF Data
G5
H4
J3
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
G4
H3
J2
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
I/O SD2 Data or GPIO or
GPIF Data
F7
H6
G7
J8
SD2_CLK
SD2_CMD
SD2_POW
N/C
O
PA[6] (GPIO)
I/O PA[6] (GPIO)
I/O PA[7] (GPIO)
I/O PC[0] (GPIO)
I/O PA-6 (GPIO)
I/O PA-7 (GPIO)
I/O PC-0 (GPIO)
I/O PA-6 (GPIO)
I/O PA-7 (GPIO)
I/O PC-0 (GPIO)
I/O SD2 Clock or GPIO
I/O SD2 CMD or GPIO
I/O SD2 Power or GPIO
I/O PA[7] (GPIO)
O
O
O
PC[0] (GPIO)
N/C
O
O
N/C
N/C
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF_CTL[1]
GPIF_CTL[0]
O
O
GPIF Control Signal
GPIF Control Signal
J5
N/C
N/C
G6
H7
J7
PA-5 (GPIO)
N/C
I/O PA-5 (GPIO)
I/O PA-5 (GPIO)
N/C
I/O PC-2 (GPIO)
I/O PA-5 (GPIO)
GPIF_RDY[0]
I/O PC-2 (GPIO)
I/O PA-5 (GPIO)
GPIF_RDY[0]
I/O PC-2 (GPIO)
I/O GPIO
I
N/C
I
I
O
O
GPIF Ready Signal
SD2_WP
O
PC-2 (GPIO)
I/O SD Write Protect or
GPIO
C2
D2
D1
RESETOUT
O
RESETOUT
O
RESETOUT
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT /
GPIF_RDY[1]
O
RESETOUT or GPIF
GVDDQ
VGND
PC-5 (GPIO[1]) or I/O PC-5 (GPIO[1])
SD2_CD
I/O PC-5 (GPIO[1])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O PC-5 (GPIO[1])
I/O PC-4 (GPIO[0])
I/O GPIO or SD2 CD
I/O GPIO or SD CD
PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])
SD_CD
I
SD_CD
I
C3
D4
RESET#
WAKEUP
I
I
RESET
Wake Up Signal
Document Number: 001-13805 Rev. *M
Page 22 of 78
CYWB022XX Family
Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments (continued)
Power
Pin Description
Domain
Pin Name
A1
B1
C6
B4
A2
XTALSLC
TEST[2]
TEST[1]
TEST[0]
XTALIN
I
I
I
I
I
Clock Select
Test Cfg 2
GVDDQ
VGND
Test Cfg 1
Test Cfg 0
Crystal / Clock IN
XVDDQ
VGND
A9, PVDDQ
E8
Power Processor I/F VDD
J6
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
Power GPIF VDD
Power USB VDD
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Core VDD
B5
F1
D3
B3
A6, VDD
D6,
E5,
F6
A3
B2
UVSSQ
AVSSQ
Power USB GND
Power Analog GND
Power Core GND
D5, VGND
D7,
E4,
E9,
F5
Document Number: 001-13805 Rev. *M
Page 23 of 78
CYWB022XX Family
Table 11. Astoria 81-ball Lite SP WLCSP Package Pin Assignments
Pin Name
Power
Domain
Pin Description
Ball #
SRAM Interface
ADM (Address/Data Multi-
plexing)
I/O
PNAND
I/O
G9
H5
CE#
A7
I
I
CE#
I
I
CE#
I
I
CE#
A7
PVDDQ
VGND
External Pull Up
A7 > 1:SBD
A7 > 0: LBD
J8
H6
H7
J9
A6
I
I
I
I
I
I
I
SDA
I/O SDA
I/O SCL
I/O A7 or SDA
I/O A6 or SCL
A5
SCL
A4
External Pull Up
External Pull Low
External Pull Up
External Pull Up
External Pull Up
I
I
I
I
I
WP#
I
I
I
I
I
A4 or WP#
A3
A3
External Pull Low
External Pull Low
R/B#
H8
H9
G8
G6
F9
F8
F7
E9
E8
D9
D7
D8
C9
D6
B9
C8
C7
B8
A8
B7
B6
A7
C1
D4
D3
A4
A5
C4
C5
A2
A2
A1
A1 or R/B#
A0 or CLE
A0
CLE
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
I/O AD[15]
I/O AD[14]
I/O AD[13]
I/O AD[12]
I/O AD[11]
I/O AD[10]
I/O AD[9]
I/O AD[8
I/O I/O[15]
I/O I/O[14]
I/O I/O[13]
I/O I/O[12]
I/O I/O[11]
I/O I/O[10]
I/O I/O[9]
I/O I/O[8]
I/O I/O[7]
I/O I/O[6]
I/O I/O[5]
I/O I/O[4]
I/O I/O[3]
I/O I/O[2]
I/O I/O[1]
I/O I/O[0]
I/O D15, AD15, or IO15
I/O D14, AD14, or IO14
I/O D13, AD13, or IO13
I/O D12, AD12, or IO12
I/O D11, AD11, or IO11
I/O D10, AD10, or IO10
I/O D9, AD9, or IO9
I/O D8, AD8, or IO8
I/O D7, AD7, or IO7
I/O D6, AD6, or IO6
I/O D5, AD5, or IO5
I/O D4, AD4, or IO4
I/O D3, AD3, or IO3
I/O D2, AD2, or IO2
I/O D1, AD1, or IO1
I/O D0I, AD0, or IO0
I/O AD[7]
I/O AD[6]
I/O AD[5]
I/O AD[4]
I/O AD[3]
I/O AD[2]
I/O AD[1]
I/O AD[0]
I
I
ADV#
OE#
I
I
ALE
I
I
Address Valid
Output Enable
WE#
OE#
RE#
WE#
INT#
DRQ#
DACK#
D+
I
WE#
I
WE#
INT#
DRQ#
DACK#
I
O
O
I
INT#
O
O
I
O
O
I
INT Request
DMA Request
DMA ACK
GVDDQ
VGND
DRQ#
DACK#
I/O/Z USB D+
UVDDQ
UVSSQ
D–
I/O/Z USB D–
SWD+
SWD–
I/O/Z USB Switch DP
I/O/Z USB Switch DM
Document Number: 001-13805 Rev. *M
Page 24 of 78
CYWB022XX Family
Table 11. Astoria 81-ball Lite SP WLCSP Package Pin Assignments (continued)
S-Port Interface
I/O
F3
H1
G2
E3
F2
F1
E2
E1
G1
J1
J5
J4
H4
J3
H3
G4
J2
H2
J7
J6
SD_D[7]
I/O SD Data or GPIO
I/O SD Data or GPIO
I/O SD Data or PIO
I/O SD Data or GPIO
I/O SD Data or GPIO
I/O SD Data or GPIO
I/O SD Data or GPIO
I/O SD Data or GPIO
I/O SD Clock or GPIO
I/O SD CMD or GPIO
I/O GPIOI
SSVDDQ
VGND
SD_D[6]
SD_D[5]
SD_D[4]
SD_D[3]
SD_D[2]
SD_D[1]
SD_D[0]
SD_CLK
SD_CMD
PB[7] (GPIO)
PB[6] (GPIO)
PB[5] (GPIO)
PB[4] (GPIO)
PB[3] (GPIO)
PB[2] (GPIO)
PB[1] (GPIO)
PB[0] (GPIO)
GPIF_RDY
GPIF_CTL
I/O GPIOI
I/O GPIOI
I/O GPIOI
I/O GPIOI
I/O GPIOI
I/O GPIOI
I/O GPIOI
O
I
Test Mode
Test Mode (Ext
Pull-High)
D1
C2
E5
C3
D5
B1
A2
A1
SD_CD
I
I
SD CD
GVDDQ
VGND
RESET#
WAKEUP
TEST[2]
TEST[1]
TEST[0]
XTALIN
RESET
I
Wake Up Signal
Test Cfg 2
Test Cfg 1
Test Cfg 0
Clock IN
I
GVDDQ
VGND
I
I
I
XVDDQ
VGND
XTALOUT
O
Clock OUT
A9, F6 PVDDQ
Power Processor I/F VDD
Power USBVDD
B5
E4
D2
B3
B4
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
Power SDIO VDD
Power Misc I/O VDD
Power Analog VDD
Power Crystal VDD
Power Core VDD
E7,A6, VDD
C6, F5
A3
B2
UVSSQ
AVSSQ
Power USB GND
Power Analog GND
Power Core GND
G7,E6, VGND
G5,F4,
G3
Document Number: 001-13805 Rev. *M
Page 25 of 78
CYWB022XX Family
Figure 9. Astoria 100-ball VFBGA Ball Map - Top View
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
ADV#
WE#
INT#
DRQ#
D+
D‐
SWD+
XTALIN
AVSSQ
VDD33
A
B
C
D
E
F
DQ[1]
DQ[4]
DQ[7]
DQ[0]
DQ[3]
DQ[6]
OE#
DACK#
UVDDQ
UVSSQ
SWD‐
XVDDQ
WAKEUP
TEST[0]
VGND
VDD
XTALOUT
TEST[1]
AVDDQ
GPIO[1]
RESETOUT
RESET#
DQ[2]
DQ[5]
DQ[8]
XTALSLC[0] XTALSLC[1]
PVDDQ
VGND
VDD
VGND
VGND
VDD
GVDDQ
VGND
VGND
VDD
GPIO[0]
TEST[2]
SD_D[1]
SD_D[0]
SD_D[2]
DQ[10] DQ[9]
SD_D[3]
DQ[13] DQ[12] DQ[11]
VGND
SD_CLK
SD_CMD
SD_POW
SD_D[5]
SD_D[4]
SD_D[6]
G
H
J
CE#
A[5]
A[3]
DQ[15] DQ[14]
VDD
VDD
SD_D[7]
G
H
J
A[6]
CLK
A[7]
A[4]
PVDDQ
GPIF_RDY[0]
SNVDDQ GPIF_CTL[0]
SSVDDQ
PA[5]
GPIF_DATA[2]
SD_WP
PC[0]
PA[7]
GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0]
K
A[0]
1
A[1]
2
A[2]
3
GPIF_CTL[1]
4
PC[2]
5
PA[6]
6
GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1]
10
K
7
8
9
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDDQ/AVDDQ
VGND/AVSSQ
PVDDQ
SNVDDQ
XVDDQ
VDD33
Document Number: 001-13805 Rev. *M
Page 26 of 78
CYWB022XX Family
Figure 10. Ball map_CYWB0216 - Top View
Top View
1
2
3
4
5
6
7
8
9
10
11
P/U
N/C
N/C
D+
D-
SWD+
XTALIN
AVSSQ
VDD33
A
B
C
D
E
F
P/U
A
B
C
D
E
F
N/C
P/U
P/U
P/U
P/U
P/U
P/U
SCL
P/U
P/U
N/C
1
P/U
P/U
P/U
P/U
P/U
P/U
SDA
P/D
P/U
N/C
2
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/U
P/D
N/C
3
P/U
XTA LSLC[0]
PVDDQ
VGND
UVDDQ
XTA LSLC[1]
VDD
UVSSQ
SWD-
XVDDQ
WAKEUP
TEST[0]
VGND
XTALOUT
TEST[1]
AVDDQ
GPIO[1]
RESETOUT
RESET#
SD_D[0]
SD_D[2]
SD_D[4]
SD_D[6]
SD_WP
N/C
N/C
GVDDQ
VGND
VGND
VDD
GPIO[0]
SD_D[1]
N/C
VGND
VGND
VDD
TEST[2]
SD_D[3]
N/C
N/C
VGND
VDD
SD_CLK
SD_CMD
SD_POW
SD_D[5]
VDD
VDD
SD_D[7]
N/C
N/C
N/C
N/C
N/C
11
G
H
J
G
H
J
PVDDQ
GPIF_RDY [0]
GPIF_CTL [1]
N/C
SNVDDQ
PC [0]
GPIF_CTL [0]
PA [7]
PA [6]
N/C
SSVDDQ
PA [5]
GPIF_DATA[2]
GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0]
PC [2]
GPIF_DATA[7] GPIF_DATA[6]
GPIF_DATA[1]
K
L
GPIF_DATA[4]
K
L
N/C
N/C
N/C
N/C
N/C
4
5
6
7
8
9
10
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDDQ/AVDDQ
VGNDAVSSQ
PVDDQ
SNVDDQ
XVDDQ
VDD33
P/U
P/D
N/C
Document Number: 001-13805 Rev. *M
Page 27 of 78
CYWB022XX Family
Figure 11. Ball map_CYWB0220 - Top View
Top View
1
2
3
4
DRQ#
5
N/C
6
N/C
7
8
9
AVSSQ
AVDDQ
GPIO[1]
10
11
ADV#
DQ[1]
DQ[4]
DQ[7]
DQ[10]
DQ[13]
CE#
INT#
OE#
N/C
XTALIN
XTALOUT
TEST[1]
GPIO[0]
TEST[2]
SD_CLK
SD_CMD
SD_POW
VDD33
A
B
C
D
E
F
A
B
C
D
E
F
N/C
N/C
N/C
N/C
WE#
DQ[0]
DQ[3]
DQ[6]
DQ[9]
DQ[12]
DQ[15]
A[6]
DACK#
XTALSLC[0]
PVDDQ
VGND
UVDDQ
XTALSLC[1]
VDD
UVSSQ
N/C
XVDDQ
WAKEUP
TEST[0]
VGND
VDD
RESETOUT
RESET#
SD_D[0]
SD_D[2]
SD_D[4]
SD_D[6]
SD_WP
DQ[2]
DQ[5]
DQ[8]
DQ[11]
DQ[14]
A[7]
GVDDQ
VGND
VGND
VDD
SD_D[1]
SD_D[3]
SD_D[5]
SD_D[7]
GPIF_DATA[2]
VGND
VGND
VDD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
11
VGND
VDD
VDD
G
H
J
G
H
J
A[5]
PVDDQ
GPIF_RDY[0]
GPIF_CTL[1]
N/C
SNVDDQ
PC [0]
PC [2]
N/C
GPIF_CTL[0]
PA [7]
PA [6]
N/C
SSVDDQ
PA[5]
A[3]
CLK
A[4]
GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0]
A[0]
A[1]
A[2]
GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1]
K
L
K
L
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDDQ/AVDDQ
VGNDAVSSQ
PVDDQ
SNVDDQ
XVDDQ
VDD33
N/C
Document Number: 001-13805 Rev. *M
Page 28 of 78
CYWB022XX Family
Figure 12. Ball map_CYWB0224 - Top View
Top View
1
2
3
4
DRQ#
5
D+
6
D-
7
8
9
10
11
ADV#
DQ[1]
DQ[4]
DQ[7]
DQ[10]
DQ[13]
CE#
INT#
OE#
SWD+
XVDDQ
WAKEUP
TEST[0]
VGND
VDD
XTALIN
XTALOUT
TEST[1]
GPIO[0]
TEST[2]
SD_CLK
SD_CMD
SD_POW
AVSSQ
AVDDQ
GPIO[1]
VDD33
A
B
C
D
E
F
A
B
C
D
E
F
N/C
N/C
N/C
N/C
WE#
DQ[0]
DQ[3]
DQ[6]
DQ[9]
DQ[12]
DQ[15]
A[6]
DACK#
XTALSLC[0]
PVDDQ
VGND
UVDDQ
XTALSLC[1]
VDD
UVSSQ
SWD-
GVDDQ
VGND
VGND
VDD
RESETOUT
RESET#
SD_D[0]
SD_D[2]
SD_D[4]
SD_D[6]
SD_WP
DQ[2]
DQ[5]
DQ[8]
DQ[11]
DQ[14]
A[7]
SD_D[1]
SD_D[3]
SD_D[5]
SD_D[7]
GPIF_DATA[2]
VGND
VGND
VDD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
11
VGND
VDD
VDD
G
H
J
G
H
J
A[5]
PVDDQ
GPIF_RDY[0]
GPIF_CTL[1]
N/C
SNVDDQ
PC[0]
GPIF_CTL [0]
PA[7]
SSVDDQ
PA[5]
A[3]
CLK
A[4]
GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0]
A[0]
A[1]
A[2]
PC[2]
PA[6]
GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1]
K
L
K
L
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10
POWER DOM AIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDDQ/AVDDQ
VGNDAVSSQ
PVDDQ
SNVDDQ
XVDDQ
VDD33
N/C
Document Number: 001-13805 Rev. *M
Page 29 of 78
CYWB022XX Family
Figure 13. Astoria 81-ball SP WLCSP Ball Map - Top View
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
XTALSLC
XTALIN
UVSSQ
D+
D‐
VDD
WE#
IO[0]
PVDDQ
A
B
C
D
E
F
TEST[2]
INT#
AVSSQ
RESETOUT
GPIO[1]
SD_D[0]
SD_D[3]
SD_D[4]
SD_D[7]
AVDDQ
RESET#
GVDDQ
SD_D[1]
SD_D[2]
SD_D[5]
TEST[0]
SWD+
UVDDQ
SWD‐
VGND
VDD
RE#
TEST[1]
VDD
ALE
IO[2]
IO[1]
IO[3]
IO[6]
PVDDQ
CLE
IO[4]
IO[5]
GPIO[0]
SD_WP
SSVDDQ
SD_CLK
SD_D[6]
WAKEUP
VGND
VGND
SDA
IO[7]
A[2]
VGND
CE#
SD_CMD
VGND
VDD
PA[6]
G
H
J
GPIF_DATA[2] GPIF_DATA[5]
PA[5]
PA[7]
PC[0]
A[3]
R/B#
G
H
J
GPIF_DATA[1] GPIF_DATA[4] GPIF_DATA[7]
GPIF_RDY[0]
SCL
Pull‐Low
POW
1
GPIF_DATA[0] GPIF_DATA[3] GPIF_DATA[6] GPIF_CTL [0] SNVDDQ
PC [2]
7
GPIF_CTL [1]
8
WP#
9
2
3
4
5
6
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDDQ/AVDDQ
VGND/AVSSQ
PVDDQ
SNVDDQ
XVDDQ
Document Number: 001-13805 Rev. *M
Page 30 of 78
CYWB022XX Family
Figure 14. Astoria 81-ball Lite SP WLCSP Ball Map - Top View
1
2
3
4
5
6
7
8
9
XTALOUT
XTALIN
UVSSQ
D+
D-
VDD
WE#
DQ[0] PVDDQ
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
TEST[0]
INT#
AVSSQ
RESET#
GVDDQ
SD_D[1]
SD_D[3]
SD_D[5]
AVDDQ
TEST[2]
DACK#
SD_D[4]
SD_D[7]
VGND
XVDDQ
SWD+
UVDDQ
SWD-
OE#
VDD
ADV#
DQ[2]
DQ[8]
VDD
DQ[1]
DQ[3]
DQ[7]
DQ[4]
DQ[6]
DQ[9]
GPIO[0]
SD_D[0]
SD_D[2]
SD_CLK
DRQ#
TEST[1]
WAKEUP
VDD
DQ[5]
VGND
PVDDQ
DQ[15]
A[5]
SSVDDQ
VGND
DQ[10] DQ[11]
DQ[13] DQ[14]
DQ[12]
VGND
A[4]
PB[2] (GPIO)
VGND
A[7]
A[0]
A[2]
A [6]
CE#
A[1]
A [3]
SD_D[6] PB[0] (GPIO) PB[3] (GPIO) PB[5] (GPIO)
SD_CMD PB[1] (GPIO) PB[4] (GPIO) PB[6] (GPIO) PB[7] (GPIO) GPIF_RDY GPIF_CTL
1
2
3
4
5
6
7
8
9
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDD/AVDDQ
VGND/AVSSQ
PVDDQ
XVDDQ
Document Number: 001-13805 Rev. *M
Page 31 of 78
CYWB022XX Family
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
TA (ambient temperature under bias)
Industrial .................................................... –40 °C to +85 °C
Storage temperature ................................ –65 °C to +150 °C
VDD, AVDDQ supply voltage ..........................1.7 V to 1.9 V
UVDDQ supply voltage ....................................3.0 V to 3.6 V
Ambient temperature with
power supplied (Industrial) ........................ –40 °C to +85 °C
PVDDQ, GVDDQ, SNVDDQ, SSVDDQ
Supply voltage to ground potential
supply voltage ..................................................1.7 V to 3.6 V
VDD, AVDDQ ..............................................–0.5 V to +2.0 V
XVDDQ (Crystal I/O) supply voltage ...............3.0 V to 3.6 V
XVDDQ (Ext. Clock I/O) supply voltage ..........1.7 V to 1.9 V
GVDDQ, PVDDQ, SSVDDQ, SNVDDQ,
UVDDQ, and VDD33 and XVDDQ ..............–0.5 V to +4.0 V
DC input voltage to any input pin
(Depends on I/O supply voltage.
Inputs are not overvoltage tolerant.) ..............1.89 V to 3.6 V
DC voltage applied to
outputs in High Z state .................... –0.5 V to VDDQ + 0.5 V
Static discharge voltage
(ESD) from JESD22-A114 ......................................> 2000 V
Latch up current .....................................................> 200 mA
Maximum output short circuit current
for all I/O configurations. (Vout = 0 V) [1] ................. –100 mA
Note
1. Do not test more than one output at a time. Duration of the short circuit must not exceed one second. Tested initially and after any design or process changes that
may affect these parameters
Document Number: 001-13805 Rev. *M
Page 32 of 78
CYWB022XX Family
DC Characteristics
Table 12. DC Specifications for All Voltage Supplies (Except USB Switch)
Parameter
VDD
Description
Core voltage supply
Analog voltage supply
Crystal voltage supply
Clock voltage supply
Processor interface I/O
Conditions
Min
1.7
1.7
3.0
1.7
1.7
Typ
1.8
1.8
3.3
1.8
Max
1.9
1.9
3.6
1.9
3.6
Unit
V
AVDDQ
XVDDQ
XVDDQ
PVDDQ[4]
V
V
V
1.8, 2.5,
3.3
V
GVDDQ[4]
Miscellaneous I/O voltage supply
1.7
1.7
1.7
1.8, 2.5,
3.3
3.6
3.6
3.6
V
V
V
SNVDDQ[3, 4] S-Port GPIF voltage supply
1.8, 2.5,
3.3
SSVDDQ[3, 4] S-Port SD I/O voltage supply
1.8, 2.5,
3.3
UVDDQ[6]
VDD33
USB voltage supply
3.0
3.0
3.3
3.3
–
3.6
3.6
V
V
V
Power sequence control supply
Input HIGH voltage 1
[5]
VIH1
All ports except USB,
0.625 × VCC
VCC + 0.3
2.0 V < VCC < 3.6 V
[5]
VIH2
Input HIGH voltage 2
All ports except USB,
1.7 V < VCC < 2.0 V
VCC – 0.4
–
VCC + 0.3
VIL
Input LOW voltage
–0.3
–
–
–
–
–
–
0.25 × VCC
V
V
VOH
VOL
IIX
Output HIGH voltage
Output LOW voltage
Input leakage current
Output leakage current
IOH(MAX) = –0.1 mA
0.9 × VCC
IOL(MIN) = 0.1 mA
0.1 × VCC
V
All I/O signals held at VDDQ
All I/O signals held at VDDQ
–1
–1
–
1
1
A
A
mA
IOZ
ICC Core
Operating current of core voltage VFBGA package
supply (VDD) and analog voltage outputs tri-stated
110
supply (AVDDQ)
WLCSP package
outputs tri-stated
–
–
–
–
115
5
mA
mA
ICC Crystal
Operating current of crystal
voltage supply (XVDDQ)[8]
VFBGA package
XTALOUT floating
WLCSP package
–
–
N/A
25
ICC USB
ISB1
Operating current of USB voltage Operating and terminated for high speed
supply (UVDDQ)[8]
mode
Total standby current of Astoria 1. *VDDQ = 3.3 V nominal
–
mA
25 C
85 C
–
–
300[2]
–
–
A
A
when device is in suspend mode
(3.0–3.6 V)
3000
(For 100-ball
VFBGA and
81-ball SP
WLCSP-
2. Outputs and Bidirs high or
floating[7]
3. XTALOUT floating
4. D+ floating, D–grounded
5. Device in suspend mode
Packages)
Notes
2. Isb1 typical value is not a maximum specification but a typical value. Isb1 maximum current value specified for 85°C.
3. The SSVDDQ I/O voltage can be dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the
lower minimum voltage limit. SSVDDQ and SNVDDQ levels for SD modes: 2.0 V3.6 V, MMC modes: 1.7 V3.6 V.
4. Interfaces with a voltage range are adjustable with respect to the I/O voltage and supports multiple I/O voltages.
5.
V
= pertinent VDDQ value.
CC
6. When U-Port is in a disabled state, UVDDQ can go down to 2.4 V, provided UVDDQ is still the highest supply voltage level.
7. The Outputs and Bidirs that are forced low in standby mode can increase I/O supply standby current beyond specified value.
8. Active Current Conditions:
-UVDDQ: USB transmitting 50% of the time, receiving 50% of the time.
-PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active current depends on I/O activity, bus load and supply level.
-XVDDQ: Assume highest frequency clock (48 MHz) or crystal (26 MHz).
Document Number: 001-13805 Rev. *M
Page 33 of 78
CYWB022XX Family
Table 12. DC Specifications for All Voltage Supplies (Except USB Switch) (continued)
Parameter Description Conditions
ISB1 Total standby current of Astoria 6. *VDDQ = 3.3 V nominal
Min
TBD
TBD
Typ
TBD
TBD
Max
TBD
TBD
Unit
A
A
25 C
85 C
when device is in suspend mode
(3.0–3.6 V)
(For 81-ball Lite
SP WLCSP)
7. Outputs and Bidirs high or
floating[7]
8. XTALOUT floating
9. D+ floating, D– grounded
10.Device in suspend mode
ISB2
Total standby current of Astoria
when device is in standby mode
1. *VDDQ = 3.3 V Nominal
(3.0–3.6 V)
25 C
–
–
52
A
2. Outputs and Bidirs High or
Floating[7]
3. XTALOUT Floating
4. D+ Floating, D– Grounded
85 C
–
–
–
–
–
–
450
28
A
A
A
ISB3
Total standby current of Astoria
when device is in core
power-down mode
1. Outputs and Bidirs High or 25 C
Floating[7]
85 C
139
2. XTALOUT Floating
3. D+ Floating, D– Grounded
4. Core Powered Down
Table 13. USB Switch DC Specifications
Parameter Description
VIH Input voltage HIGH
Conditions
Min
1.6
–
Typ
–
Max
–
Unit
V
VIL
Input voltage LOW
On resistance
–
0.8
10
–
V
RON
4.5
1M
–
7
ROFF
Off resistance
–
CDP/DM_ON
D+/D– on capacitance (with
Full-Speed switch On)
–
25
pF
CDP/DM_OFF
D+/D– off capacitance
–
–
20
pF
Table 14. Capacitance
Parameter
Description
Conditions
Typ
Max
Unit
CIN
Input pin capacitance, except
D+/D–
TA = 25 °C, f = 1 MHz, VCC = VCCIO
–
9
pF
Input pin capacitance, D+/D–
Output pin capacitance
–
–
15
10
pF
pF
COUT
Document Number: 001-13805 Rev. *M
Page 34 of 78
CYWB022XX Family
AC Timing Parameters
P Port Interface
PCRAM Non Multiplexing Asynchronous Mode
Table 15. Asynchronous Mode Timing Parameters
Parameter
Description
Min
Max
Unit
Read Timing Parameters
Interface bandwidth (MBPS)
–
–
66.7
30
–
MBps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOH
Data output hold from address change
Chip enable to data valid
ADV# to data valid access time
Address valid to ADV# HIGH
ADV# HIGH to address hold
CE# low setup time to ADV# HIGH
ADV# HIGH time
3
tEA
–
30
30
–
tAADV
tAVS
tAVH
tCVS
tVPH
tVP
–
5
2[10]
–
5
–
15[9]
7.5
–
–
ADV# pulse width LOW
OE# LOW to data valid
OE# LOW to Low Z
–
tOE
22.5
–
tOLZ
tOHZ
tLZ
3
OE# HIGH to High Z
0
22.5
–
CE# LOW to Low Z
3
tHZ
CE# HIGH to High Z
–
22.5
Write Timing Parameters
tCW
tAW
CE# LOW to write end
30
30
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to write end
Address setup to write start
ADV# setup to write start
WE# pulse width
tAS
–
tADVS
tWP
0
–
22
10
10
5
–
tWPH
tCPH
tAVS
tAVH
tCVS
tVPH
tVP
WE# HIGH time
–
CE# HIGH time
–
Address valid to ADV# HIGH
ADV# HIGH to address hold
CE# LOW setup time to ADV# HIGH
ADV# HIGH time
–
2[10]
–
5
–
15[9]
7.5
30
18
0
–
ADV# pulse width LOW
ADV# LOW to end of write
Data setup to write end
Data hold from write end
Write to DQ High Z output
End of write to Low Z output
–
tVS
–
tDW
tDH
–
–
tWHZ
tOW
–
22.5
–
3
Notes
9. In applications where access cycle time is at least 60 ns, t
can be relaxed to 12 ns.
VPH
10. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t
spec. can be relaxed to 0 ns.
AVH
Document Number: 001-13805 Rev. *M
Page 35 of 78
CYWB022XX Family
Figure 15. Non Multiplexing Asynchronous Pseudo CRAM Mode Single Read Time Parameters
Valid Address
A
ADV#
CE#
tAA
tAVH
tOH
tVPH
tAVS
tVP
tHZ
tAADV
tCVS
tEA
tLZ
tOE
OE#
tOHZ
R/W#
DQ
tOLZ
High-Z
Valid Output
Figure 16. Non Multiplexing Asynchronous Pseudo CRAM mode Back to Back Read Timing Parameters
Valid Address
Valid Address
A
tAA
tVPH
tAVS
tAVH
ADV#
CE#
tHZ
tVP
tAADV
tEA
OE#
tOHZ
WE#
DQ
High-Z
Valid Output
Valid Output
tLZ
Document Number: 001-13805 Rev. *M
Page 36 of 78
CYWB022XX Family
Figure 17. Non Multiplexing Asynchronous Pseudo CRAM Mode Back to Back Write Timing Parameters
Valid Address
Valid Address
A
tAVS
tVP
tAVH
tVPH
ADV#
CE#
tCPH
tVS
tCW
OE#
WE#
tAW
tWPH
tWP
tOW
tAS
tADVS
tDH
tDW
High-Z
Valid Input
Valid Input
DQ_IN
tWHZ
tLZ
DQ_OUT
Figure 18. Non Multiplexing Asynchronous Pseudo CRAM Mode Read to Write Timing Parameters
Valid Address
Valid Address
tAVS
tVP
Valid Address
A
tAA
tAVH
tVPH
tAVS
tVPH
tAVH
ADV#
CE#
tVP
tVS
tAADV
tEA
tOE
OE#
WE#
tOHZ
tAW
tWP
tOW
tDH
tDW
tAS
High-Z
Valid Input
Valid Input
DQ_IN
tOLZ
tWHZ
High-Z
DQ_OUT
Valid Output
tLZ
Document Number: 001-13805 Rev. *M
Page 37 of 78
CYWB022XX Family
Figure 19. Non Multiplexing Asynchronous Pseudo CRAM Mode Write to Read Timing Parameters
Valid Address
tAVS
Valid Address
A
tAA
tAVH
tAVS
tAVH
tVP
ADV#
CE#
tVP
tVS
tAADV
tOE
OE#
WE#
tAW
tWP
tDH
tDW
tAS
Valid Input
DQ_IN
tOLZ
tWHZ
DQ_OUT
Valid Output
Address Data Multiplexing Asynchronous Mode
Table 16. Address Data Multiplexing Asynchronous Mode Timing Parameters
Parameter
Description
Min
Max
Unit
Read Timing Parameters
Interface bandwidth
–
–
50
30
30
30
–
MBps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tEA
Chip enable access time
ADV# to data valid access time
Address valid to ADV# HIGH
ADV# HIGH to address hold
–
tAADV
tAVS
tAVH
tCVS
tVPH
tVP
–
5
2
–
CE# LOW setup time to ADV# HIGH
ADV# HIGH time
5
–
15
7.5
0
–
ADV# pulse width LOW
ADV# HIGH to OE# LOW
OE# LOW to data valid
OE# LOW to Low Z
–
tAVDOE
tOE
–
–
22.5
–
tOLZ
tOHZ
tLZ
3
OE# HIGH to High Z
–
22.5
–
CE# LOW to Low Z
3
tHZ
CE# HIGH to High Z
–
22.5
Write Timing Parameters
tCW
CE# LOW to write end
30
–
ns
Document Number: 001-13805 Rev. *M
Page 38 of 78
CYWB022XX Family
Table 16. Address Data Multiplexing Asynchronous Mode Timing Parameters (continued)
Parameter Description
tAW
Min
30
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to write end
ADV# HIGH to write start
WE# pulse width
tAVDWE
tWP
–
22
5
–
tAVS
tAVH
tCVS
tVPH
tVP
Address valid to ADV# HIGH
ADV# HIGH to address hold
–
2
–
CE# LOW setup time to ADV# HIGH
ADV# HIGH time
5
–
15
7.5
30
18
0
–
ADV# pulse width LOW
ADV# LOW to end of write
Data setup to write end
Data hold from write end
–
tVS
–
tDS
–
tDH
–
Figure 20. Address Data Multiplexing Asynchronous Single Read Timing Parameters
tAA
tAVH
tAVS
A<7:0>/
High-Z
High-Z
Valid Address
Valid Data
DQ<15:0>
tVPH
tAADV
tVP
ADV#
CE#
tHZ
tCVS
tLZ
tEA
tAVDOE tOLZ
tOHZ
tOE
OE#
WE#
Logic High
Document Number: 001-13805 Rev. *M
Page 39 of 78
CYWB022XX Family
Figure 21. Address Data Multiplexing Asynchronous Single Write Timing Parameters
tAW
tAVH
tDH
tAVS
tDS
A<7:0>/
High-Z
Valid Address
Valid Input
DQ<15:0>
tVPH
tVS
tVP
ADV#
CE#
tCVS
tCW
tAVDWE
tWP
WE#
Non Multiplexing Synchronous Mode Timing Parameters
Table 17. Non Multiplexing Synchronous Mode Timing Parameters
Parameter Description
FREQ
Min
Max
33
–
Unit
MHz
ns
Interface clock frequency
Clock period
–
tCLK
30
12
12
0
tCLKH
tCLKL
tWH
Clock HIGH time
Clock LOW time
–
ns
–
ns
Address hold time (write to the register) for the first time that processor configures
the P-Port from non-ADM asynchronous mode to non-ADM synchronous mode
–
ns
tS
CE#/WE#/ADDR/DQ setup time
CE#/WE#/ADDR/DQ hold time
Clock to valid data
7.5
1.5
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tCO
18
–
tOH
Clock to data hold time
OE# LOW to data Low Z
OE# HIGH to data High Z
OE# LOW to data valid
Clock to data High Z
2
tOLZ
tOHZ
tOE
3
–
–
22.5
22.5
18
–
–
tCKHZ
tCKLZ
–
Clock to data Low Z
3
Document Number: 001-13805 Rev. *M
Page 40 of 78
CYWB022XX Family
Figure 22. Non Multiplexing Synchronous Pseudo CRAM Mode Write Timing Parameters
tCLKH
tCLKL
tCLK
CLK
CE#
tH
tS
A[7:0]
An+1
An+2
An
tWH
An+3
WE#
OE#
DQ[15:0]
(input)
Dn+1
Dn+2
Dn
Dn+3
High-Z
DQ[15:0]
(output)
Note:
- Assumes previous cycle had CE# deselected
- OE# is don’t care during write operations
Figure 23. Non Multiplexing Synchronous Pseudo CRAM Mode Read Timing Parameters
tCLKH
tCLKL
tCLK
CLK
CE#
tS
tH
A[7:0]
An+1
An+2
An+4
An
An+3
WE#
OE#
High-Z
High-Z
DQ[15:0]
(input)
tOHZ
tOH
Dn
tOLZ
tOE
tCO
DQ[15:0]
(output)
Dn+1
tCKLZ
Note:
- Assumes previous cycle had CE# deselected
Document Number: 001-13805 Rev. *M
Page 41 of 78
CYWB022XX Family
Figure 24. Non Multiplexing Synchronous Mode Read (OE# Fixed LOW) Timing Parameters
CLK
CE#
tS
tH
A[7:0]
Ax+1
Ax+2
Ax
WE#
OE#
tCKHZ
Dx+1
tOH
Dx-1
tCO
DQ[15:0]
(output)
Dx-2
Dx
Dx
Note:
- Assumes previous several cycles were Read
Figure 25. Non Multiplexing Synchronous Mode Read to Write (OE# Controlled) Timing Parameters
tCLKH
tCLKL
tCLK
CLK
CE#
tS
tH
A[7:0]
Ax+1
An
Dn
An+2
Ax
An+1
Dn+1
WE#
OE#
tS
tH
High-Z
DQ[15:0]
(input)
Dn+2
tOH
Dx-1
tCO
tOHZ
DQ[15:0]
(output)
Dx-2
Dx
Note:
- Assumes previous several cycles were Read
- (Ax) and (Ax+1) cycles are turnaround . (Ax+1) operation does not cross pipeline .
Document Number: 001-13805 Rev. *M
Page 42 of 78
CYWB022XX Family
Figure 26. Non Multiplexing Synchronous Mode Read to Write (OE# Fixed LOW) Timing Parameters
tCLKH
tCLKL
tCLK
CLK
CE#
tH
tS
A[7:0]
Ax+1
Ax+2
Ax
An
An+1
WE#
OE#
tH
Dn
tS
High-Z
DQ[15:0]
(input)
Dn+1
tCO
tOH
Dx-1
DQ[15:0]
(output)
Dx
Dx-2
tCO
Note:
- Assumes previous several cycles were Read
- In this scenario, OE# is held LOW
- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.
- No operation is performed during the Ax+2 cycle (true turnaround operation)
Figure 27. Non Multiplexing Synchronous Mode Write to Read Timing Parameters
tCLKH
tCLKL
tCLK
CLK
CE#
tH
tS
A[7:0]
An+1
An+2
An
tWH
An+3
WE#
OE#
DQ[15:0]
(input)
Dn+1
Dn+2
Dn
Dn+3
High-Z
DQ[15:0]
(output)
Note:
- Assumes previous cycle had CE# deselected
- OE# is don’t care during write operations
Document Number: 001-13805 Rev. *M
Page 43 of 78
CYWB022XX Family
Address Data Multiplexing Synchronous Mode
Table 18. Address Data Multiplexing Synchronous Mode Parameters
Parameter
FREQ
Description
Min
–
Max
33
–
Unit
MHz
ns
Interface clock frequency
tAVH
Address hold time (write to the register) for the first time that processor configures
the P-Port from ADM asynchronous mode to ADM synchronous mode
2
tCLK
tCLKH
tCLKL
tS
Clock period
30
12
12
7.5
1.5
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High time
Clock Low time
–
CE#/WE#/DQ setup time
CE#/WE#/DQ hold time
Clock to valid data
–
tH
–
tCO
18
–
tOH
Clock to data hold time
ADV# HIGH to OE# LOW
ADV# HIGH to WE# LOW
CE# HIGH to data High Z
OE# HIGH to data High Z
OE# LOW to data Low Z
OE# LOW to data Valid
2
tAVDOE
tAVDWE
tHZ
0
–
0
–
–
22.5
22.5
–
tOHZ
tOLZ
tOE
–
3
–
22.5
Figure 28. Address Data Multiplexing Synchronous Burst Read Timing Parameters
(Burst of 4 with Latency=2, WE#=HIGH)
tCLKH tCLKL
CLK
tCLK
tCO
tOH
tS
tH
A<7:0>/
DQ<15:0>
Valid
Address
tAVH *
D0
D1
D2
D3
tS tH
ADV#
CE#
tHZ
tS
tAVDOE tOLZ
tOE
tOHZ
OE#
WE#
Logic High
* tAVH is the ADM address hold time (write to the register) for the first time that Processor configure
the P-Port Astoria from ADM Async mode to ADM Sync mode
Document Number: 001-13805 Rev. *M
Page 44 of 78
CYWB022XX Family
Figure 29. Address Data Multiplexing Synchronous Burst Write Timing Parameters
(Burst of 4 with Latency=2, OE# is Ignored)
tCLKH tCLKL
CLK
tCLK
tDS tDH
tDH
tS
tH
A<7:0>/
DQ<15:0>
Valid
Address
tAVH *
D0
D1
D2
D3
tS tH
ADV#
CE#
tS
tS
tAVDWE
WE#
* tAVH is the ADM address hold time (write to the register) for the first time that Processor configure
the P-Port Astoria from ADM Async mode to ADM Sync mode
Table 19. Asynchronous SRAM Mode Timing Parameters
Parameter Description
Min
Max
Unit
Interface bandwidth (MBPS)
Read Timing Parameters
–
66.7
MBPS
tRC
tAA
Read cycle time
Address to data valid
30
–
–
30
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOH
tEA
Data output hold from address change
Chip enable to data valid
OE# LOW to data valid
OE# LOW to Low Z
3
–
30
22.5
–
tOE
tOLZ
tOHZ
tLZ
–
3
OE# HIGH to High Z
0
22.5
–
CE# LOW to Low Z
3
tHZ
CE# HIGH to High Z
–
22.5
Write Timing Parameters
tWC
tCW
tAW
tAS
Write cycle time
30
30
30
0
–
–
–
–
ns
ns
ns
ns
CE# LOW to write end
Address valid to WE# end
Address setup to WE# or CE# start
Document Number: 001-13805 Rev. *M
Page 45 of 78
CYWB022XX Family
Table 19. Asynchronous SRAM Mode Timing Parameters (continued)
Parameter
tAH
Description
Min
Max
Unit
Address hold time from WE# or CE# end for PCRAM to SRAM changes (Astoria is
default in the PCRAM mode after RESET. This timing is the requirement for the first
time to access the P-Port Interface Configuration Register to change the Astoria to
PSRAM mode)
2
–
ns
Address hold time from WE# or CE# end for PSRAM mode
WE# pulse width
0
22
10
10
18
0
–
–
tWP
ns
ns
ns
ns
ns
ns
ns
ns
tWPH
tCPH
tDS
WE# HIGH time
–
CE# HIGH time
–
Data setup to write end
Data hold from write end
Write to DQ High Z output
End of write to Low Z output
DRQ# pulse width
–
tDH
–
tWHZ
tOW
tDPW
–
22.5
–
3
110
–
Non Multiplexing Asynchronous SRAM Mode
Figure 30. Non Multiplexing Asynchronous SRAM Read Timing Parameters
Endpoint Read – Address Transition Controlled Timing (OE# is asserted )
tRC
ADDRESS
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
DATA OUT
OE# Controlled Timing
ADDRESS
tRC
CE#
OE#
tEA
tHZ
tOHZ
tOE
tOLZ
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZ
DATA OUT
DATA VALID
Document Number: 001-13805 Rev. *M
Page 46 of 78
CYWB022XX Family
Figure 31. Non Multiplexing Asynchronous SRAM Write Timing (WE# and CE# Controlled)
Write Cycle 1 WE# Controlled, OE# High During Write
tWC
ADDRESS
tCW
CE#
tAW
tWP
tAH
tDH
WE#
tAS
tWPH
OE#
tDS
VALID DATA
DATA I/O
VALID DATA
tWHZ
Write Cycle 2 CE# Controlled, OE# High During Write
tWC
ADDRESS
tAS
tCW
tCPH
CE#
WE#
tAW
tAH
tDH
tWP
OE#
tDS
VALID DATA
DATA I/O
VALID DATA
tWHZ
Document Number: 001-13805 Rev. *M
Page 47 of 78
CYWB022XX Family
Figure 32. Non Multiplexing Asynchronous SRAM Write Timing (WE# Controlled, OE# LOW)
Write Cycle 3 WE# Controlled. OE# Low
tWC
tCW
CE#
tAW
tAH
tAS
tWP
WE#
tDS
tDH
DATA I/O
VALID DATA
tOW
tWHZ
Pseudo NAND (PNAND) Mode
Table 20. PNAND Mode Parameters
Parameter
Description
Min
100
100
450
5
Max
–
Unit
ns
Non LNA Mode Register Write
Non LNA Mode EP Write
LNA Mode
tADL
Address to data loading time
–
ns
–
ns
tALH
tALS
tAR
ALE hold time
–
ns
ALE setup time
ALE to RE# delay
15
–
ns
10
–
ns
MCU/S-Port NAND
dependent
tBERS
Block erase time
tCEA
tCH
CE# access time
CE# hold time
–
5
35
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHZ
tCLH
tCLR
tCLS
tCS
CE# HIGH to O/P HI-Z
CLE hold time
–
40
–
5
CLE to RE# time
CLE setup time
CE# setup time
Data hold time
10
15
20
5
–
–
–
tDH
–
tDS
Data setup time
Data output hold time
15
15
–
tOH
–
Document Number: 001-13805 Rev. *M
Page 48 of 78
CYWB022XX Family
Table 20. PNAND Mode Parameters (continued)
Parameter
Description
Min
Depends on
MCU/S-Port/NAND
Max
Unit
Program time for LNA mode
tPROG
ns
Program time for register write in non LNA mode
Program time for EP write in non LNA mode
130
130
130
130
ns
ns
ns
ns
–
–
–
–
Busy duration during Non LNA register read using page read
Busy duration during non LNA EP read using page read
tR
Depends on
MCU/S-Port/NAND
Busy duration during LNA page read (SBD/SLD)
ns
ns
Read cycle time (VFBGA Package)
Read cycle time (WLCSP package)
RE# for register access time
RE# for EP access time
RE# HIGH hold time
30
33
–
–
–
tRC
30
30
–
ns
ns
ns
ns
ns
ns
ns
tREA
–
tREH
tRHW
tRHZ
tRP
10
40
–
RE# HIGH to WE LOW
RE# HIGH to output High Z
RE# pulse width
–
40
–
15
20
tRR
Ready to RE LOW
–
Depends on
MCU/S-Port/NAND
tRST
tWB
Device reset time
ns
ns
WE# HIGH to busy
–
30
33
10
30
450
15
100
–
Write cycle time (VFBGA package)
Write Cycle Time (WLCSP package)
WE# HIGH hold time
tWC
tWH
tWHR
tWP
ns
–
–
ns
ns
ns
ns
WE# HIGH to RE LOW in non LNA mode
WE# HIGH to RE LOW in LNA mode
WE# pulse width
–
–
–
Figure 33. PNAND Mode Command Latch Cycle
CLE
tCLS
tCS
tCLH
tCH
CE#
WE#
ALE
tWP
tALH
tDH
tALS
tDS
Command
I/Ox
Document Number: 001-13805 Rev. *M
Page 49 of 78
CYWB022XX Family
Figure 34. PNAND Mode Address Latch Cycle
tCLS
tCS
CLE
CE#
WE#
tWC
tWC
tWC
tWC
tWP
tWP
tWP
tALS
tWP
tWH
tWH
tWH
tWH
tALS
tALS
tALS
tALH
tALS
ALE
I/Ox
tALH
tALH
tDH
tALH
tALH
tDS
tDS
tDS
tDS tDH
Row.Add2
tDH
tDS tDH
tDH
Col.Add1
Row.Add3
Col.Add2
Row.Add1
Figure 35. PNAND Mode Input Data Latch Cycle
tCLH
tCH
CLE
CE#
tWC
ALE
WE#
tALS
tWP
tWP
tWP
tWH
tDS tDH
DIN0
tDS tDH
DIN1
tDS tDH
DIN final
I/Ox
Document Number: 001-13805 Rev. *M
Page 50 of 78
CYWB022XX Family
Figure 36. PNAND Mode Serial Access Cycle After Read
tCEA
tCHZ
tOH
CE#
RE#
tREH
tREA
tREA
tREA
tRHZ
tOH
tRHZ
I/Ox
Dout
tRC
Dout
Dout
tRR
R/B #
Figure 37. PNAND Mode Status Read Cycle
tCLR
CLE
tCLH
tCLS
tCS
CE#
tWP
tCHZ
tOH
WE#
RE#
I/Ox
tCEA
tWHR
tRHZ
tDS
tDH
tIR
tREA
tOH
70h
Status Output
Document Number: 001-13805 Rev. *M
Page 51 of 78
CYWB022XX Family
Figure 38. PNAND LBD Read Operation
tCLR
CLE
CE#
WE#
tWC
tWB
tAR
tRR
ALE
RE#
tR
tRP
tRHZ
tRC
Column Address
00h Col Add1 Col Add2
Row Address
Row
Add1
Row
Add2
Row
Add3
Dout
N+1
I/Ox
Dout N
Dout M
30h
Busy
R/B#
Table 21. Page-Read Command Sequence for Large-Block Devices
Cycle type
CMD0
IO bus
Comments
00h
Page-read command - 1st cycle
CA0
EP_Offset[7:0]/
REG_Addr[7:0]
REG_Sel field determines how the two column address cycles are interpreted
EP_Offset[11:10] = REG_Sel = 2`b11 ‡ Register
EP_Offset[11:10] = REG_Sel = 2`b0x, 2`b10 ‡EP buffer offset
EP_Offset[11:0] = EP buffer offset
CA1
RA0
{4’b0000, EP_Offset[11:8]}
Row address byte 0
First row-address cycle
RA0[4:0] = default EPA – Endpoint address
RA1
Row address byte 1
Row address byte 2
Row address byte 3
30h
The number row-address bytes present in Page-read command depend on
RA_COUNT configuration parameter setting. LNA row addresses are interpreted by
firmware;
RA2
RA3
CMD1
Data[0-2111]
Page-read command - 2nd cycle
Data
Data is returned by Astoria delay tR beyond the second command.
Document Number: 001-13805 Rev. *M
Page 52 of 78
CYWB022XX Family
Figure 39. PNAND LBD Read Operation
7
0
REG_Sel[1:0]
EP_Offset[7:0]/
REG_Addr[7:0]
CA0
CA1
Reserved
EP_Offset[11:8]
RA0 (default
EPA position)
EPA[4:0]
RA1
RA2
RA3
Figure 40. PNAND SBD Read Operation
CLE
CE#
WE#
tWC
tWB
tAR
ALE
RE#
tR
tRP
tRR
tRHZ
tRC
Column
Address
Row Address
Row
Add2
Row
Add3
Row
Add1
Dout
N+1
00h, 01h,
or *50h
I/Ox
Dout N
Dout M
Col Add1
Busy
R/B#
* For the Command 50h, A[3:0] in Col Add1 are
valid address and A [7:4] are Don’t care
Document Number: 001-13805 Rev. *M
Page 53 of 78
CYWB022XX Family
Table 22. Page-Read Command Sequence for Small-Block Devices
Cycle type
CMD0
IO bus
Comments
00h/01h/50h
Sets base-address within page as 0, 256, or 512, for read operation.
CA0
EP_Offset[7:0]/
REG_Addr[7:0]
EP_Offset[7:0] = EP buffer offset for non-register accesses.
REG_Addr[7:0] specifies register address when EPA[4:0] field = 5`b10000.
RA0
Row address byte 0 First row-address cycle
RA0[4:0] = default EPA – Endpoint address
EPA may be specified in any other row-address byte.
RA1
Row address byte 1 The number row-address bytes present in Page-read command depend on
RA_COUNT configuration parameter setting. LNA row addresses are interpreted by
RA2
Row address byte 2
Row address byte 3
Data
firmware;
RA3
Data[0-527]
Data is returned by Astoria delay tR beyond the second command.
Figure 41. Small Block Device Mode Address Cycles
7
0
EP_Offset[7:0]/
REG_Addr[6:0]
CA0
RA0 - default
EPA position
EPA[4:0]
RA1
RA2
RA3
Document Number: 001-13805 Rev. *M
Page 54 of 78
CYWB022XX Family
Figure 42. PNAND Mode LBD Random Data Operation (CASDO)
CLE
CE#
tCLR
WE#
ALE
tRHW
tWHR
tWB
tAR
tRP
tREA
tR
tRC
RE#
I/Ox
tRR
Row
Add1
Row
Add2
Row
Add3
Dout
N+1
Dout
M+1
00h Col Add1 Col Add2
Column Address
30h
05h
Dout M
Dout N
Col Add1 Col Add2 E0h
Column Address
Row Address
Busy
R/B#
Figure 43. PNAND Mode Register Read Using CASDO in 8-Bit Mode
CLE
tCLR
CE#
tCH
WE#
tWHR
ALE
tREA
RE#
Col
Add1
Column Address
Col
Add2
I/Ox
05h
E0h
DOUT1
*DOUT2
R/B#
* This timing diagram shows the 8-bit register read. For 16-bit
register read, DOUT2 is not available
Document Number: 001-13805 Rev. *M
Page 55 of 78
CYWB022XX Family
Figure 44. PNAND Mode LBD Read Operation (With CE# Don’t Care)
CLE
CE#
WE#
tWB
ALE
RE#
tR
Col
Col
Row Row Row
Dout
N+1
Dout
M
I/Ox
30h
Dout N
00h
Add1 Add2 Add1 Add2 Add3
Column Address
Row Address
Busy
R/B#
tCEA
CE#
RE#
I/Ox
tREA
Dout
Document Number: 001-13805 Rev. *M
Page 56 of 78
CYWB022XX Family
Figure 45. PNAND Mode SBD Read Operation (With CE# Don’t Care)
CLE
CE#
WE#
tWB
ALE
RE#
tR
Col
Row Row Row
Dout
N+1
Dout
M
I/Ox
Dout N
00h
Add1 Add1 Add2 Add3
Column
Address
Row Address
Busy
R/B#
tCEA
CE#
tREA
RE#
I/Ox
Dout
Document Number: 001-13805 Rev. *M
Page 57 of 78
CYWB022XX Family
Figure 46. PNAND Mode LBD Page Program Operation
CLE
CE#
tWC
WE#
ALE
tWB
tADL
tWHR
tPROG
RE#
I/Ox
Col Col Row Row Row
Add1 Add2 Add1 Add2 Add3
Din
N
10
h
Din
M
80h
70h
I/O0
Column
1 up to m Byte Program
Serial Input Command
Serial Data Input
Command
Read Status
Command
Row Address
Address
R/B#
M = 2112byte in 8-bit interface
M = 1056 in 16-bit interface
I/O0=0 Successful Program
I/O0=1 Error in Program
Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle
Document Number: 001-13805 Rev. *M
Page 58 of 78
CYWB022XX Family
Figure 47. PNAND Mode SBD Page Program Operation
CLE
CE#
tWC
WE#
ALE
tPROG
tADL
tWB
RE#
I/Ox
Column
Address
Col
Row Row
Add1 Add2 Add3
Row Address
Din
N
Din
M
Row
10h
70h
I/O0
80h
Add1
1 up to m Byte
Serial Input
Program
Command
Read Status
Command
Serial Data
Input
Command
R/B#
M = 528 byte in 8-bit interface
M = 264 byte in 16-bit interface
I/O0=0 Successful Program
I/O0=1 Error in Program
Document Number: 001-13805 Rev. *M
Page 59 of 78
CYWB022XX Family
Figure 48. PNAND Mode LBD Page Program Operation with Random Data Input (CASDI)
CLE
CE#
tWC
WE#
ALE
tADL
tWB tPROG
tWHR
RE#
I/Ox
Col
Row Row
Add1 Add2
Col
Row
Add3
Col
Col
Din
N
Din
M
Din
J
Din
K
85h
80h
70h
I/O0
10h
Program
Add2
Add1
Add1 Add2
Column
Address
Serial Data Input
Command
Row Address
Read Status
Command
Serial
Input
Serial
Input
Column
Address
Command
R/B#
Random Data
Input Command
*Random Programming (CASDI) to endpoint is only supported during logical NAND emulation (LNA mode) of LBD device.
Partial page programming is not supported
Figure 49. PNAND Mode Register Write Using CASDI in 8-Bit Mode
CLE
CE#
tWC
WE#
tADL
ALE
RE#
Col
Add1 Add2
Col
85h
DIN1 *DIN2
I/Ox
Serial
Input
Random Data
Input Command
R/B#
* This timing diagram shows the 8-bit register write. For 16-bit
register write, DIN2 should not be available
Document Number: 001-13805 Rev. *M
Page 60 of 78
CYWB022XX Family
Figure 50. PNAND Mode LBD Page Program Operation (With CE# Don’t Care)
CLE
CE#
tWC
WE#
ALE
tADL
tWB tPROG
tWHR
RE#
I/Ox
1 up to M Byte
Serial Input
Col Col Row Row Row
Add2 Add1 Add3
Din
Din
M
10h
80h
70h
I/O0
Add1
Column
Address
Add2
Row Address
N
Program
Command
Serial Data Input
Command
Read Status
Command
M = 2112 byte in 8-bit interface
M = 1056 byte in 16-bit interface
Note: tADL is the time from WE rising edge of final
address cycle to the WE rising edge of first data cycle
I/O0=0 Successful Program
I/O0=1 Error in Program
R/B#
tCH
tCS
CE#
tWP
WE#
Document Number: 001-13805 Rev. *M
Page 61 of 78
CYWB022XX Family
Figure 51. PNAND Mode SBD Page Program Operation (With CE# Don’t Care)
CLE
CE#
tWC
WE#
ALE
tPROG
tADL
tWB
RE#
I/Ox
Column
Address
Col
Row Row
Add1 Add2 Add3
Row Address
Din
N
Din
M
Row
10h
70h
I/O0
80h
Add1
Program
Command
1 up to m Byte
Serial Input
Read Status
Command
Serial Data
Input
Command
M = 528 byte in 8-bit interface
M = 264 byte in 16-bit interface
R/B#
I/O0=0 Successful Program
I/O0=1 Error in Program
tCH
tCS
CE#
WE#
tWP
Document Number: 001-13805 Rev. *M
Page 62 of 78
CYWB022XX Family
Figure 52. PNAND Mode Block Erase Operation
CLE
CE#
tWC
WE#
ALE
tBERS
tWB
RE#
Row
Add1
Row
Add2
Row
Add3
I/Ox
D0h
60h
70h
I/O0
Row Address
R/B#
Busy
Read Status I/O0=0 Successful Erase
Command I/O0=1 Error in Erase
Auto Block Erase
Setup Command
Erase Command
Figure 53. PNAND Mode Multi-Blocks (up to 4) Erase
CLE
CE#
WE#
ALE
RE#
I/Ox
tWC
tWB
tBERS
2nd and 3rd
Block Erase
1st Block Erase
4th Block Erase
Row
Add1
Row
Add3
Row
Add1
Row
Row
Add2
Row
Add2
D0h
D0h
60h
60h
70h
I/O 0
Add3
Row Address
Row Address
R/B#
Busy
Read Status I/O0=0 Successful Erase
Auto Block Erase
Setup Command
Erase Command Auto Block Erase
Setup Command
Erase Command
Command
I/O0=1 Error in Erase
Note: The multi-block erase can support up to 4 blocks erase
Document Number: 001-13805 Rev. *M
Page 63 of 78
CYWB022XX Family
Figure 54. PNAND Mode Read ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tREA
00h
I/Ox
Byte 0
Byte 1
90h
Byte 2
Can up to six bytes
Byte 0 – Byte 5 are the values of registers of PNAD_RD_ID0 to PNAND_RD_ID5.
Byte 3
Byte 4
Byte 5
Read ID Command
Address 1cycle
Figure 55. PNAND Mode Read ID2 Operation
CLE
CE#
WE#
tAR
ALE
RE#
tREA
I/Ox
00h
Read ID Command Address 1cycle
Ext_ID
91h
Document Number: 001-13805 Rev. *M
Page 64 of 78
CYWB022XX Family
Figure 56. PNAND Mode Reset Operation
CLE
CE#
tWB
WE#
R/B #
I/Ox
tRST
FFh
SPI and PI2C Interface
Table 23. SPI Mode Parameters
Parameter
Description
Min
Max
Units
f
t
t
t
t
t
t
t
t
t
Operating frequency
Cycle time
0
38.5
19.23
19.23
17.33
17.33
–
26
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
OP
CYC
Lead
Lag
SCKH
SCKL
SU
Enable lead time
Enable lag time
–
–
Clock high time
–
Clock low time
Data setup time (inputs)
Data hold time (inputs)
7
7
–
H
Data valid time, after enable edge
Data hold time, after enable edge
–
18
–
V
0
HO
Document Number: 001-13805 Rev. *M
Page 65 of 78
CYWB022XX Family
Figure 57. SPI Timing Diagram
SS#
SCK
tCYC
tLag
tSCKL
tSCKH
tLead
(MSB) BIT-7 OUT
(LSB) BIT-7 OUT
Note
MISO
MOSI
BIT-6 OUT
BIT-6 IN
tSU
tH
tV
tHO
tHO
(MSB)
BIT-7 IN
(LSB)
BIT-0 IN
Note: Not defined but normal MSB of character just received
Table 24. PI2C Interface Standard Mode Parameters
Parameter Description
Min
0
Max
82
–
Units
kHz
µs
F
Operating frequency
tBUF
Bus free time (between stop and start conditions)
4.7
4.0
tHD:STA
Hold time after (Repeated) start condition. After this period the first clock is
generated
–
µs
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Repeated start condition setup time
Stop condition setup time
Data hold time
4.7
4.0
0
–
–
–
–
µs
µs
ns
ns
ms
µs
µs
ms
ns
ns
Data setup time
250
Detect clock low timeout
Clock low period
NA
4.7
4.0
–
–
tHIGH
Clock high period
tLOW:SEXT
Cumulative clock low extend time (slave device)
Rise time
NA
t
–
–
1000
300
r
f
t
Fall time
Document Number: 001-13805 Rev. *M
Page 66 of 78
CYWB022XX Family
Table 25. PI2C Interface Fast Mode Parameters
Parameter
Description
Min
0
Max
312
–
Units
kHz
µs
F
Operating frequency
tBUF
tHD:STA
Bus free time (between stop and start condition)
1.3
0.6
Hold time after (Repeated) start condition. After this period the first clock is
generated
–
µs
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
–
–
µs
µs
ns
ns
ms
µs
µs
ms
ns
ns
0.9
–
Data setup time
100
Detect clock low timeout
Clock low period
NA
NA
1.3
0.6
–
–
tHIGH
Clock high period
tLOW:SEXT
Cumulative clock low extend time (slave device)
Rise time
t
–
–
300
300
r
f
t
Fall time
Figure 58. PI2C Timing Diagram
tf
70%
50%
30%
SDA
tBUF
tHIGH
tr
tSU;DAT
70%
50%
tLOW
50%
SCL
30%
tHD;STA
tHD;DAT
tSU;STA
tHD;STA
tSU;STO
S
Sr
P
S
Other P-Port Timings
In Sync mode, this holdoff time is seven P-Port clock (CLK)
cycles.
DRQ# Min Pulse Width (tDPW): The minimum duration that
DRQ# is deasserted following a DRQ acknowledgement (clear
of DMAVAL) is 110 ns in Async mode or five P-Port clock (CLK)
cycles in Sync mode.
Register Update-to-Read Holdoff (tURHO): Same status
registers are updated as side effect from accesses to other
registers. For example, clearing the DMAVAL field automatically
clears the associated endpoint buffer bit within the DRQ status
register. A holdoff time must elapse from the first register access
before the update is reflected in a subsequent read operation.
This holdoff time is identical to the tWRHO.
Same Register Write-to-Read Holdoff (tWRHO): A read of a
particular register must wait for a holdoff period following a write
operation to that same register address to ensure that valid
updated data is read. In Async mode, this holdoff time is 150 ns.
Document Number: 001-13805 Rev. *M
Page 67 of 78
CYWB022XX Family
S Port Interface AC Timing Parameters
SD/MMC/MMC+/CE-ATA Timing Parameters
For all conditions, SD/MMC data is driven and sampled on the rising edge of SD_CLK. Note that CE-ATA electrical and timing
parameters are equivalent to MMC.
Figure 59. SD/MMC/CE-ATA Timing Waveform – All Modes
tSDCLKH
tSDCLK
SD_CLK
tSDCLKL
tSDOS
tSDOH
tSDCKLZ
tSDCKHZ
SD_CMD/
SD_D0-D3
Output
SD_CMD/
SD_D0-D3
Input
tSDIH
tSDIS
Table 26. Common Timing Parameters for SD/MMC/CE-ATA – During Identification Mode
Parameter
SDFREQ
tSDCLK
Description
Min
0
Max
400
–
Units
kHz
µs
SD_CLK interface clock frequency
Clock period
2.5
1.0
1.0
tSDCLKH
tSDCLKL
Clock high time
–
µs
Clock low time
–
µs
Table 27. Common Timing Parameters for SD/MMC/CE-ATA – During Data Transfer Mode
Parameter
SDFREQ
tSDCLK
Description
Min
5
Max
48
200
60
3
Units
MHz
ns
SD_CLK interface clock frequency
Clock period
20.8
40
–
tSDCLKOD
tSCLKR
Clock duty cycle
%
Clock rise time
ns
tSCLKF
Clock fall time
–
3
ns
Table 28. Timing Parameters for SD – All Modes
Parameter
Description
Min
4
Max
–
Units
ns
tSDIS
Input setup time
Input hold time
tSDIH
2.5
7
–
ns
tSDOS
tSDOH
tSDCKHZ
tSDCKLZ
Output setup time
Output hold time
Clock to data High Z
Clock to data Low Z
–
ns
6
–
ns
–
18
–
ns
3
ns
Document Number: 001-13805 Rev. *M
Page 68 of 78
CYWB022XX Family
Table 29. Timing Parameters for MMC/CE-ATA – All Modes
Parameter Description
tSDIS
Min
4
Max
–
Units
ns
Input setup time
Input hold time
tSDIH
4
–
ns
tSDOS
Output setup time
Output hold time
Clock to data High Z
Clock to data Low Z
6
–
ns
tSDOH
6
–
ns
tSDCKHZ
tSDCKLZ
–
18
–
ns
3
ns
Minimum RESET# pulse width (tRPW): 5 ms when a crystal is
used as clock or 1 ms when an external clock is used.
Reset and Standby Timing Parameters
The Astoria reset mechanism and the standby mode are
described in this section.
Minimum WAKEUP pulse width (tWPW): 5 ms.
Minimum HIGH on RESET# and WAKEUP (tRH, TWH): The
WAKEUP and RESET# pins must be held HIGH for a minimum
of 5 ms.
Sleep Time (tSLP): The maximum time from deassertion of
WAKEUP to when Astoria enters low power state (sleep mode)
is 1 ms.
Reset Recovery Time (tRR): A minimum 1 ms reset recovery
time must be allowed before Astoria registers can be accessed
for read or write.
Wakeup Time (tWU): The minimum time from assertion of
WAKEUP pin (or initial power on with WAKEUP HIGH) to when
any register operation is conducted is 1 ms if an external clock
is present, or
5
ms if
a
crystal is used. The
CY_AN_MEM_PWR_MAGT_STAT.WAKEUP field can only be
polled after wakeup time following reset deassertion or WAKEUP
assertion.
Figure 60. Reset and Standby Timing Diagram
Core
Power-Down
VDD
(core)
VDDQ
(I/O)
XTALIN up & stable
before WAKEUP
asserted
XTALIN
tWPW
tWH
Standby
Mode
WAKEUP
Mandatory
tRH
Mandatory
Reset Pulse
Reset Pulse
Hard Reset
RESET#
Firmware Init
Complete
Firmware Init
Complete
Firmware Init
Complete
High-Z
tRPW
RESETOUT
tSLP
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘1’
Document Number: 001-13805 Rev. *M
Page 69 of 78
CYWB022XX Family
Table 30. Reset and Standby Timing Parameters
Parameter Description
tSLP Sleep time
Wakeup time from standby mode Clock on XTALIN
Conditions
Min
–
Max
1
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
tWU
1
–
Crystal on XTALIN-XTALOUT
5
–
tWH
WAKEUP high time
WAKEUP pulse width
RESET# high time
RESET# pulse width
5
–
tWPW
tRH
5
–
5
–
tRPW
Clock on XTALIN
1
–
Crystal on XTALIN-XTALOUT
5
–
tRP
RESET# recovery time
1
–
Figure61. ACTestLoadsandWaveforms(ExceptSDand MMC, SDandMMCarecomplywiththeSD/MMCspecification)
Document Number: 001-13805 Rev. *M
Page 70 of 78
CYWB022XX Family
Ordering Information
Astoria provides many options with multiple ordering part numbers as shown in the following table:
Optional Features
Clock Input
Frequencies
(MHz)
Ordering Code
Package Type
Status
FlexBoot™ USB Switch Turbo MTP
CYWB0220ABSX2-FDXIT 81-ball WLCSP (Pb-free)
CYWB0224ABM-BVXIES 100-ball VFBGA (Pb-free)
26
Sample
Sample
19.2, 24, 26, 48
CYWB0224ABS-BZXI
CYWB0224ABS-BVXI
CYWB0224ABS-BVXIT
CYWB0224ABS-BVXIES
CYWB0224ABSX-FDXI
CYWB0224ABSX-FDXIT
CYWB0226ABS-BVXI
CYWB0226ABS-BVXIT
CYWB0226ABSX-FDXI
CYWB0226ABSX-FDXIT
121-ball FBGA (Pb-free)
100-ball VFBGA (Pb-free)
100-ball VFBGA (Pb-free)
100-ball VFBGA (Pb-free)
81-ball WLCSP (Pb-free)
81-ball WLCSP (Pb-free)
100-ball VFBGA (Pb-free)
100-ball VFBGA (Pb-free)
81-ball WLCSP (Pb-free)
81-ball WLCSP (Pb-free)
19.2, 24, 26, 48 Production
19.2, 24, 26, 48 Production
19.2, 24, 26, 48 Production
19.2, 24, 26, 48
19.2, 26
Sample
Sample
19.2, 26
Production
19.2, 24, 26, 48 Production
19.2, 24, 26, 48 Production
19.2, 26
19.2, 26
Sample
Production
Ordering Code Definitions
CY WB XXXX ABS
X
X - XX
X
I
Temperature range:
I = Industrial = –40 °C to +85 °C
X = Pb-free
Package Type: XX = BV or BB or BZ or FD
BV = 100-ball VFBGA
BZ = 121-ball FBGA
FD = 81-ball WLCSP
Fixed value: X = 2
Fixed value
ABS = GPIF support
Base Part Number: XXXX = 0224 or 0226 or 0216 or 0220
Marketing Code: WB = West Bridge Astoria
Company ID: CY = Cypress
Document Number: 001-13805 Rev. *M
Page 71 of 78
CYWB022XX Family
Package Diagram
Figure 62. 100-ball VFBGA (6 × 6 × 1.0 mm) BZ100 Package Outline, 51-85209
51-85209 *D
100-ball VFBGA Package Outline Number
Revision
Date Released
02/07/2011
51-85209
*D
Document Number: 001-13805 Rev. *M
Page 72 of 78
CYWB022XX Family
Figure 63. 121-ball FBGA (10 × 10 × 1.20 mm) (0.30 Ball Diameter) Package Outline, 001-54471
001-54471 *C
121-ball FBGA Package Outline Number
Revision
Date Released
001-54471
*C
05/30/2011
Document Number: 001-13805 Rev. *M
Page 73 of 78
CYWB022XX Family
Figure 64. Astoria WLCSP (3.91 × 3.91× 0.55 mm) FN81B Package Outline, 001-45618
BOTTOM VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
SIDE VIEW
001-45618 *C
Astoria WLCSP Package Outline Number
Revision
Date Released
001-45618
*C
02/23/2012
Document Number: 001-13805 Rev. *M
Page 74 of 78
CYWB022XX Family
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CRAM
DMA
ECC
GPIF
MMC
MTP
PLL
cellular random access memory
direct memory access
error correction code
General purpose Interface
multimedia card
Unit of Measure
°C
degree Celsius
µA
µs
microampere
microsecond
milliampere
mA
Mbps
MHz
ms
ns
media transfer protocol
phase-locked loop
mega bytes per second
megahertz
millisecond
nanosecond
ohm
SD
secure digital
SD
secure digital
SDIO
SLC
secure digital input / output
single-level cell
pF
picofarad
SPI
serial peripheral interface
universal serial bus
V
volt
USB
VFBGA
WLCSP
very fine ball grid array
wafer level chip scale package
Document Number: 001-13805 Rev. *M
Page 75 of 78
CYWB022XX Family
Document History Page
Document Title: CYWB022XX Family, West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller
Document Number: 001-13805
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
866960 VSO / PSZ
See ECN New datasheet
*A
2208371
JYEE /
VSO
See ECN 1) Corrected the Pin name (R/B#) in Table 2, Updated I
to I
in Table 3,
SB1
SB3
Updated Table 5, Updated Figure 14 to Figure 18 (timing diagrams), In Table
6, moved “Interface Bandwidth” to first row, Updated Table 7, Updated Figure
22, Added Figure 23 (new), Updated Figure 24 to 26, Updated Table 8,
Updated Figure 27, Added Table 9 (Async SRAM mode Timing), Updated
Figure 29 - 31, Updated Table 10, Updated Figure 32 - 43, Updated Table 11,
Updated Table 12, Updated Figure 45, Updated Table 14, Added Table 16, and
21. Updated Figure 47.
2) Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the title,
Modified Feature list (same as Astoria Advance Information), Updated
Features to include “Integrated USB Switch”, Updated Figure 1, Updated USB
Interface (U-Port), Added Figure 2, Updated section 3.6, Updated Table 2,
Updated Figure 14, Added Table 4, Updated Table 5-6, Updated Figure 15-19,
Updated Table 7, Updated Figure 20-21, Updated Table 8, Updated Figure
22-27, Updated Table 9, Update Figure 28-29, Updated Table 10, Updated
Figure 30-32, Updated Table 11, Updated Figure 33-54, Updated Table 12,
Updated Figure 55, Updated Table 13-14, Updated Figure 56-58, Updated
Table 15-16, Added Table 17-18, Updated Table 19, Updated Figure 59, and
Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the order
information (section 9).
*B
2503171
VSO /
AESA
See ECN 1. “Features” - added 3.91x3.91 mm 81-ball WLCSP to Small footprint bullet.
2. “Processor Interface (P-Port)” - added “The P-Port of the WLCSP package
only supports PNAND and SPI interface” and “The 81-ball WLCSP package
only supports interrupt.”
3. “Clocking” - added “The 81-ball WLCSP only supports 19.2 and 26 MHz
external clock input.” and Tables 1 and 2
4. Table 4 - added the column of “Ball #”
5. Table 5 - added a new table for WLCSP pin assignment
6. Figure 13 - removed the grid line
7. Figure 14 - new ball map for WLCSP package
8. Table 14 - add 33ns for tRC and tWC timing for WLCSP package
9. Figure 55 - updated the SPI timing diagram
10. “Ordering Information” - added WLCSP package ordering code to the table
11. Add CYWB0224ABSX, CYWB0224ABMX CYWB0226ABSX,
CYWB0226ABMX.
*C
2521024
VSO /
AESA
See ECN 1. This version is final - Removed status “Preliminary”
2. Update the section of “Core Power Down Mode”
3. Note 3 of Table 6 has added the requirement of SSVDDQ and SNVDDQ in
SD/MMC modes
4. SNVDDQ in Table 6 added Note 3
5. Table 17, add parameter tWH
6. Figure 22 and Figure 27 have been updated
7. Table 18, add parameter tAVH
8. Figure 28 and Figure 29 have been updated
9. Table 20, the value of parameters “tPROG” and “tR” have been updated
10. Table 23, removed parameter of “tA”
11. Figure 58 I2C timing diagram has been updated
Document Number: 001-13805 Rev. *M
Page 76 of 78
CYWB022XX Family
Document History Page (continued)
Document Title: CYWB022XX Family, West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller
Document Number: 001-13805
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*D
2663942
VSO /
AESA
02/24/2009 1. Feature list - add (SP and Lite SP) to WLCSP
2. Update the section of “Clocking” (add description of “SP” and “Lite SP”)
3. Add Table 3
4. Add section of “Packages and Interface Options”
5. Add Table 5
6. Add “SP” to the title of Table 7
7. Add Table 8 (pin assignment for Lite SP)
8. Figure 14, change the color of AVDDQ
9. Add Figure 15 for Lite SP ball map
10. Remove some of note [2] in table 6.
11. Update the description of Note [2]
12. Update the table in “Order Information” section.
*E
*F
2905597
2920278
VSO
04/05/2010 Removed part CYWB0224ABM-BVXI. Updated package diagrams.
VSO /
AESA
04/21/2010 Added I
parameter in DC Specifications for All Voltage Supplies (Except
SB1
USB Switch).
Added Contents
Updated links in Sales, Solutions, and Legal Information.
*G
*H
2954592
3057588
ESH
ODC
06/17/10
Removed inactive parts from the ordering information table
10/13/2010 Removed references to MLC NAND flash.
Removed MLC NAND parts from Ordering Information.
Added Ordering Code Definitions.
*I
3164752
3191625
ANOP
ANOP
02/07/2011 In 'D3' row in Table 8, added ‘#’ to DACK in the 'SRAM Interface', 'ADM' and
'PNAND' columns.
In 'D4' row in Table 8, added ‘#’ to DRQ in the 'SRAM Interface', 'ADM' and
'PNAND' columns.
*J
03/09/2011 Added Table 18 (Page-read command sequence for large-block devices) and
Figure 40 (LBD mode address cycles)
Added Table 19 (Page-read command sequence for small-block devices) and
Figure 42 (SBD mode address cycles)
Updated Package Diagram.
*K
3465771
SIRK
12/22/2011 Changed status from Confidential to Final.
Updated Mass Storage Support (S-Port).
Updated Pin Assignments.
Updated Package Diagram.
*L
3539318
3665980
SIRK
AASI
03/01/2012 Updated Package Diagram (001-45618 from Rev *B to *C).
Moving document to external web.
*M
07/06/2012 Updated Features (Removed 100-ball BGA package related information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagram (Removed 100-ball BGA package related
information (spec 51-85107)).
Document Number: 001-13805 Rev. *M
Page 77 of 78
CYWB022XX Family
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13805 Rev. *M
Revised July 6, 2012
Page 78 of 78
West Bridge, Astoria, Antioch, and SLIM are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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