CYUSB3025-BZXI [CYPRESS]
USB Bus Controller, CMOS, PBGA121, FBGA-121;
| 型号： | CYUSB3025-BZXI |
| 厂家： | 
CYPRESS |
| 描述： | USB Bus Controller, CMOS, PBGA121, FBGA-121 时钟 静态存储器 外围集成电路 |
| 文件： | 总34页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYUSB302x
SD3™ USB and Mass Storage
Peripheral Controller
SD3™ USB and Mass Storage Peripheral Controller
■ Independent power domains for core and I/O
Features
■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
■ Latest-generation storage support
❐ SD3.0/SDXC – UHS1 SDR50 / DDR50 Master
❐ eMMC 4.4 Master
■ 5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
❐ SDIO 3.0 Master
Applications
■ USB integration
■ USB thumb drives
■ Card readers
❐ CertifiedUSB3.0andUSB2.0 peripheral: SuperSpeed (SS),
Hi-Speed (HS), and Full-Speed (FS) only)
❐ Thirty-two physical endpoints
❐ Integrated transceiver
❐ Accessory charger adaptor (ACA) support
■ Laptop with SD slots
■ SD slot in TV/STB
■ WIFI Dongles
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ USB SDIO Bridge
■ Raid on-Chip Controller
■ I2C master controller at 1 MHz
■ Selectable input clock frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
Logic Block Diagram
JTAG
Embedded
SRAm
(512 kB/
256 KB)
ARM926EJ-S
SSRX-
SSRX+
SS
Peripheral
SSTX-
SSTX+
D+
USB
EPs
GPIOs
HS/FS
Peripheral
FSLC[0]
FSLC[1]
D-
FSLC[2]
UART
CLKIN
SDIO/SD/MMC Controller
CLKIN_32
XTALIN
SPI
XTALOUT
I2S
I2C
S0-PORT
S1-PORT
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-55190 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2017
CYUSB302x
Contents
Functional Overview ........................................................3
USB Interface (U-Port) ................................................3
Mass-Storage Support (S-Port) ...................................3
I2C Interface ................................................................3
UART Interface ............................................................3
I2S Interface ................................................................3
SPI Interface ................................................................3
Boot Options ................................................................4
Reset ...........................................................................4
Clocking .......................................................................4
Power ..........................................................................5
Configuration Fuse ......................................................7
Digital I/Os ...................................................................7
EMI ..............................................................................7
System Level ESD ......................................................7
Pinout for BGA ..................................................................7
Pin Description for BGA ..................................................8
Pinout for WLCSP ...........................................................11
Pin Description for WLCSP ...........................................12
AC Timing Parameters ...................................................15
Storage Port Timing ..................................................15
I2C Interface Timing ..................................................18
Absolute Maximum Ratings ..........................................23
Operating Conditions .....................................................23
DC Specifications ...........................................................24
Reset Sequence ..............................................................26
Package Diagrams ..........................................................27
Ordering Information ......................................................28
Ordering Code Definitions .........................................28
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Errata ...............................................................................30
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support .......................34
Products ....................................................................34
PSoC® Solutions ......................................................34
Cypress Developer Community .................................34
Technical Support .....................................................34
Document Number: 001-55190 Rev. *L
Page 2 of 34
CYUSB302x
2
I C Interface
Functional Overview
SD3 has an I2C interface compatible with the I2C Bus
Specification Revision 3. Because SD3’s I2C interface is capable
of operating only as I2C master, it may be used to communicate
with other I2C slave devices. For example, SD3 may boot from
an EEPROM connected to the I2C interface, as a selectable boot
option.
SD3™ is a USB 3.0 SuperSpeed mass-storage controller
providing the latest SD/MMC support. SD3 complies with the SD
Specification, Version 3.0, and the MMC Specification, Version
4.41.
SD3 offers the following access paths among USB and mass
storage ports:
SD3’s I2C master controller also supports multi-master mode
functionality.
■ A USB-port (U-Port) supporting USB 3.0 peripheral
■ Two mass-storage ports (S0-Port and S1-Port) supporting
mass-storage devices. Following are the possible
configurations for the two mass-storage ports:
❐ SD and MMC
❐ SD and SD
❐ MMC and MMC
❐ SD and SDIO
❐ MMC and SDIO
❐ SDIO and SDIO
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock stretching
feature to enable slower devices to exercise flow control.
Combinations of these accesses can happen independently or
in an interleaved manner.
Both SCL and SDA signals of the I2C interface require external
pull-up resistors. These resistors must be connected to VIO5.
The SD3 complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0.
UART Interface
The UART interface of SD3 supports full-duplex communication.
It includes the signals noted in Table 1.
USB Interface (U-Port)
SD3 offers the following features:
Table 1. UART Interface Signals
■ Supports USB peripheral functionality compliant with the USB
3.0Specification Revision 1.0 and is backward-compatiblewith
the USB 2.0 Specification
Signal
TX
Description
Output signal
Input signal
Flow control
Flow control
■ Supports up to 16 IN and 16 OUT endpoints.
RX
■ Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device class to optimize mass-storage
access performance.
CTS
RTS
■ As a USB peripheral, SD3 supports UAS and Mass Storage
Class (MSC) peripheral classes.
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then SD3's UART only transmits data when the CTS
input is asserted. In addition to this, SD3's UART asserts the RTS
output signal, when it is ready to receive data.
■ When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Figure 1. USB Interface Signals
SD3
2
I S Interface
SD3 has an I2S port to support external audio codec devices.
SD3 functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). SD3 can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
VBATT
VBUS
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
Mass-Storage Support (S-Port)
SPI Interface
The SD3 storage interface port supports the following
specifications:
SD3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
■ SD Specification, Version 3.0
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 21 for details on the
modes) with the Start-Stop clock. This controller is a
■ Multimedia Card-System Specification, MMCA Technical
Committee, Version 4.4
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
■ SDIO Host controller compliant with SDIO Specification
Version 3.00
Document Number: 001-55190 Rev. *L
Page 3 of 34
CYUSB302x
Boot Options
Table 3. Crystal/Clock Frequency Selection
SD3 can load boot images from various sources, selected by the
configuration of the PMODE pins. The boot options for the SD3
are as follows:
Crystal/Clock
Frequency
FSLC[2]
FSLC[1]
FSLC[0]
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
19.2-MHz crystal
19.2-MHz input CLK
26-MHz input CLK
38.4-MHz input CLK
52-MHz input CLK
■ Boot from USB
■ Boot from I2C
■ Boot from eMMC on S0-Port
■ Boot from SPI
Table 2. Booting Options for SD3
PMODE[2:0] [1]
Boot From
S0-Port: eMMC
On failure, USB boot enabled
Table 4. Input Clock Specifications for SD3
Specification
FF0
FF1
FFF
0FF
0F1
Parameter
Phase noise
Description
Units
Min
–
Max
–75
USB Boot
I2C
On Failure, USB Boot is enabled
I2C only
100-Hz offset
1-kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
–
dB
dB
–
–104
–120
–128
–130
150
–
dB
–
dB
SPI
On Failure, USB Boot is enabled
–
dB
Maximumfrequency
deviation
–
ppm
Reset
A reset is initiated by asserting the Reset# pin on SD3. The
specific reset sequence and timing requirements are detailed in
Figure 4 on page 18 and Table 14 on page 26. All I/Os are
tristated during a hard reset.
Duty cycle
–
–
–
–
30
–
70
3
%
%
%
ns
Overshoot
Undershoot
Rise time/fall time
–
–3
3
–
Clocking
SD3 allows either a crystal to be connected between the XTALIN
and XTALOUT pins or an external clock to be connected at the
CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins
can be left unconnected if not used.
32-kHz Watchdog Timer Clock Input
SD3 includes a watchdog timer that can be used to interrupt the
core, automatically wake up SD3 in Standby mode, and reset the
core. The watchdog timer runs off a 32-kHz clock, which may
optionally be supplied from an external source on a dedicated
pin of SD3.
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
SD3 has an on-chip oscillator circuit that uses an external
19.2 MHz (±100 ppm) crystal (when the crystal option is used).
An appropriate load capacitance is required with a crystal. Refer
to the specification of the crystal used to determine the appro-
priate load capacitance. The FSLC[2:0] pins must be configured
appropriately to select the crystal option/clock frequency option.
The configuration options are shown in Table 3.
The watchdog timer can be disabled by firmware.
Requirements for the optional 32-kHZ clock input are listed in
Table 5.
Table 5. 32-kHz Clock Input Requirements
Parameter
Duty cycle
Min
40
–
Max
60
Units
%
Clock inputs to SD3 must meet the phase noise and jitter
requirements specified in Table 4.
Frequency deviation
Rise Time/fall Time
±200
200
ppm
ns
The input clock frequency is independent of the clock/data rate
of SD3 core or any of the device interfaces. The internal PLL
applies the appropriate clock multiply option depending on the
input frequency.
–
Note
1. F indicates Floating.
Document Number: 001-55190 Rev. *L
Page 4 of 34
CYUSB302x
Power
SD3 has the following main groups of power supply domains:
Power Modes
SD3 supports the following power modes:
■ IO_VDDQ: This refers to a group of independent supply
domains for digital I/Os. The voltage level on these supplies
are 1.8 V to 3.3 V. SD3 provides six independent supply
domains for digital I/Os listed as follows:
❐ S0VDDQ: S0-Port (for SD/MMC) I/O Power Supply Domain
❐ S1VDDQ: S1-Port (for SD/MMC) I/O Power Supply Domain
❐ S2VDDQ: S2-Port (GPIO) Power Supply Domain
❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these
pins support MMC’s high nibble data line - D[7:4] on S1-Port)
❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)
❐ CVDDQ: Clock Power Supply Domain
■ Normal mode: This is the full-functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (see Table 9 on page 15
for current consumption specifications).
The I/O power supplies (S0VDDQ, S1VDDQ, VIO4, and VIO5)
may be turned off when the corresponding interface is not in use.
S2VDDQ cannot be turned off at any time if the S2-Port is used
in the application.
■ SD3 supports four low-power modes (see Table 6 on page 5):
❐ Suspend mode with USB 3.0 PHY enabled (L1 mode)
❐ Suspend mode with USB 3.0 PHY disabled (L2 mode)
❐ Standby mode (L3 mode)
■ VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator
and other core analog circuits
❐ Core power-down mode (L4 mode)
❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-
ages for the USB 3.0 interface.
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through SD3’s internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Table 6. Entry and Exit Methods for Low-Power Modes
Low Power Mode
Characteristics
Methods of Entry
Methods of Exit
Suspend mode with
USB3.0PHYEnabled
(L1 mode)
■ The power consumption in this mode does ■ Firmware executing on the core can put ■ D+ transitioning to low or high
not exceed ISB1
SD3 into suspend mode. For example,
on USB suspend condition, firmware
may decide to put SD3 into suspend
mode
■ D– transitioning to low or high
■ Resume condition on SSRX +/-
■ Detection of VBUS
■ USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by the
USB 3.0specification).Thisoneblockalone
operateswithitsinternalclockwhileallother
clocks are shut down
■ Assertion of GPIO[17]
■ Assertion of RESET#
■ All I/Os maintain their previous state
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off individ-
ually
■ The states of the configuration registers,
buffer memory and all internal RAM are
maintained
■ All transactions must be completed before
SD3 enters Suspend mode (state of
outstanding transactions are not preserved)
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Document Number: 001-55190 Rev. *L
Page 5 of 34
CYUSB302x
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low Power Mode
Characteristics
Methods of Entry
Methods of Exit
Suspend mode with
USB3.0PHYdisabled
(L2 mode)
■ The power consumption in this mode does ■ Firmware executing on the core can put ■ D+ transitioning to low or high
not exceed ISB2
SD3 into suspend mode. For example,
on USB suspend condition, firmware
may decide to put SD3 into suspend
mode
■ D– transitioning to low or high
■ Resume condition on SSRX +/-
■ Detection of VBUS
■ USB 3.0 PHY is disabled and the USB
interface is in suspend mode
■ The clocks are shut off. The PLLs are
disabled
■ Assertion of GPIO[17]
■ All I/Os maintain their previous state
■ Assertion of RESET#
■ USB interface maintains the previous state
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off individ-
ually
■ The states of the configuration registers,
buffer memory, and all internal RAM are
maintained
■ All transactions must be completed before
SD3 enters Suspend mode (state of
outstanding transactions are not preserved)
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Standby Mode (L3
mode)
■ The power consumption in this mode does ■ Firmware executing on the core or
■ Detection of VBUS
■ Assertion of GPIO[17]
■ Assertion of RESET#
not exceed ISB3
external processor configures the appro-
priate register
■ All configuration register settings and
program/data RAM contents are preserved.
However, data in the buffers or other parts
of the data path, if any, is not guaranteed.
Therefore, the external processor should
take care that needed data is read before
putting SD3 into this Standby Mode
■ The program counter is reset after waking
up from Standby
■ GPIO pins maintain their configuration
■ Crystal oscillator is turned off
■ Internal PLL is turned off
■ USB transceiver is turned off
■ Core is powered down. Upon wakeup, the
core re-starts and runs the program stored
in the program/data RAM
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off individ-
ually
Core Power Down
Mode (L4 mode)
■ The power consumption in this mode does ■ Turn off VDD
■ Reapply VDD
not exceed ISB4
■ Assertion of RESET#
■ Core power is turned off
■ All buffer memory, configuration registers
andtheprogramRAMdonotmaintainstate.
It is necessary to reload the firmware on
exiting from this mode
■ In this mode, all other power domains can
be turned on/off individually
Document Number: 001-55190 Rev. *L
Page 6 of 34
CYUSB302x
Configuration Fuse
EMI
Fuse options are available for specific usage models. Contact
Cypress Applications/Marketing for details.
SD3 meets EMI requirements outlined by FCC 15B (USA) and
EN55022 (Europe) for consumer electronics. SD3 can tolerate
reasonable EMI, conducted by aggressor, outlined by these
specifications and continue to function as expected.
Digital I/Os
SD3 provides firmware controlled pull-up or pull-down resistors
internally on all digital I/O pins. The pins can be pulled high
through an internal 50-k resistor or can be pulled low through
an internal 10-k resistor to prevent the pins from floating. The
I/O pins may have the following states:
System Level ESD
SD3 has built-in ESD protection on the D+, D–, GND pins on the
USB interface. The ESD protection levels provided on these
ports are:
■ Tristated (High-Z)
■ ±2.2-KV human body model (HBM) based on JESD22-A114
Specification
■ Weak pull-up (through internal 50 k)
■ Pull down (through internal 10 k)
■ ±6-KV contact discharge and ±8-KV air gap discharge based
on IEC61000-4-2 level 3A
■ Hold (I/O hold its value) when in low power modes
■ ±8-KV contact discharge and ±15-KV air gap discharge based
All unused I/Os should be pulled high by using the internal
pull-up resistors. All unused outputs should be left floating. All
I/Os can be driven at full-strength, three-quarter strength,
half-strength, or quarter-strength. These drive strengths are
configured based on each interface.
on IEC61000-4-2 level 4C.
This protection ensures the device continues to function after
ESD events up to the levels stated.
The SuperSpeed USB signals (SSRX+, SSRX-, SSTX+, SSTX-)
and S0/S1_INS have up to ±2.2 KV HBM internal ESD
protection.
Pinout for BGA
Figure 2. SD3 BGA Ball Map (Top View)
1
2
3
4
5
6
7
8
9
10
11
U3VSSQ
U3RXVDDQ
SSRXM
SSRXP
SSTXP
SSTXM
VSS
DP
DM
NC
AV DD
A
B
C
D
E
F
G
H
J
VIO4
GPIO[54]
GPIO[50]
GPIO[47]
S0VDDQ
VSS
FSLC[0]
GPIO[55]
GPIO[51]
VSS
R_USB3
VDD
FSLC[1]
GPIO[57]
GPIO[53]
GPIO[49]
GPIO[41]
GPIO[30]
GPIO[31]
GPIO[34]
VSS
U3TXVDDQ
RESET#
GPIO[56]
GPIO[48]
GPIO[46]
GPIO[25]
GPIO[29]
GPIO[28]
GPIO[27]
VDD
CVDDQ
XTALIN
CLKIN_32
FSLC[2]
NC
VSS
OTG_ID
I2C_GPIO[58]
VDD
NC
VIO5
AV SS
XTALOUT
CLKIN
V SS
R_USB2
VSS
V DD
NC
GPIO[52]
S1VDDQ
GPIO[44]
GPIO[43]
GPIO[40]
GPIO[37]
VSS
I2C_GPIO[59]
V BATT
GPIO[0]
GPIO[3]
GPIO[6]
GPIO[8]
GPIO[12]
GPIO[ 11]
O[60]
V BUS
VDD
NC
NC
GPIO[45]
GPIO[42]
GPIO[39]
GPIO[36]
GPIO[33]
VSS
GPIO[2]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
V D D
GPIO[5]
GPIO[15]
GPIO[24]
GPIO[14]
GPIO[17]
N C
GPIO[1]
GPIO[22]
GPIO[26]
GPIO[16]
GPIO[23]
VSS
GPIO[4]
GPIO[7]
VSS
VDD
S2VDDQ
VDD
GPIO[38]
GPIO[35]
VSS
GPIO[9]
GPIO[13]
S2 V D D Q
GPIO[10]
VSS
K
L
VSS
GPIO[32]
Document Number: 001-55190 Rev. *L
Page 7 of 34
CYUSB302x
Pin Description for BGA
Table 7. Pin List
Pin
No.
Power
Domain
I/O
Name
Description
S2-PORT (GPIO)
F10
F9
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
NC
GPIO
GPIO
F7
GPIO
G10
G9
F8
GPIO
GPIO
GPIO
H10
H9
J10
J9
GPIO
GPIO
GPIO
GPIO
K11
L10
K10
K9
J8
GPIO
GPIO
GPIO
GPIO
GPIO
G8
J6
GPIO
GPIO
K8
K7
J7
GPIO
GPIO
GPIO
H7
G7
G6
K6
H8
G5
H6
K5
J5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
H5
G4
H4
L4
GPIO
PMODE[0]
PMODE[1]
PMODE[2]
No Connect
Active Low. Hardware Reset.
L8
C5
CVDDQ
I
RESET#
8b MMC
SD+GPIO
Configuration
GPIO
Configuration
Configuration
S0_SD0
S0_SD1
S0_SD2
S0_SD3
S0_SD4
S0_SD5
S0_SD6
S0_SD7
S0_CMD
S0_CLK
K2
J4
VI02
VI02
VI02
VI02
VI02
VI02
VI02
VI02
VI02
VI02
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
GPIO[38]
GPIO[39]
GPIO[40]
GPIO[41]
GPIO[42]
S0_SD0
S0_SD1
S0_SD2
S0_SD3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
K1
J2
J3
J1
GPIO
H2
H3
F4
G2
GPIO
GPIO
S0_CMD
S0_CLK
Document Number: 001-55190 Rev. *L
Page 8 of 34
CYUSB302x
Table 7. Pin List (continued)
Pin
No.
Power
I/O
Name
Description
S0_WP
Domain
G3
F3
F2
VI02
VI02
VI02
I/O
I/O
I/O
GPIO[43]
GPIO[44]
GPIO[45]
S0_WP
S0S1_INS
GPIO
GPIO
GPIO
S0S1_INS
GPIO
MMC0_RST_OUT
GPIO+
UART+I2S
UART+
SD+I2S
8b MMC
SD+UART
SD+SPI
SD+GPIO
GPIO
SPI+I2S
F5
E1
E5
E4
D1
D2
D3
D4
C1
C2
D5
VI03
VI03
VI03
VI03
VI03
VI03
VI03
VIO4
VIO4
VIO4
VIO4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
GPIO[54]
GPIO[55]
GPIO[56]
S1_SD0
S1_SD1
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
S1_SD0
S1_SD1
S1_SD0
S1_SD1
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
S1_SD0
S1_SD1
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
S1_SD0
S1_SD1
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_CLK
S1_SD2
GPIO
S1_SD3
GPIO
S1_CMD
S1_CLK
I2S_CLK
I2S_SD
I2S_SD
S1_WP
I2S_WS
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_WS
S1_SD4
S1_SD5
S1_SD6
S1_SD7
UART_RTS
UART_CTS
UART_TX
UART_RX
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
GPIO
I2S_CLK
I2S_SD
I2S_WS
GPIO
GPIO
MMC1_RS
T_OUT
C4
VIO4
I/O
GPIO[57]
GPIO
GPIO
GPIO
GPIO
I2S_MCLK
I2S_MCLK
I2S_MCLK
C9
A3
A4
A6
A5
NC
No Connect
U3RXVDDQ
U3RXVDDQ
U3TXVDDQ
U3TXVDDQ
I
SSRXM
SSRXP
SSTXM
SSTXP
USB 3.0 SuperSpeed Receive Minus
USB 3.0 SuperSpeed Receive Plus
USB 3.0 SuperSpeed Transmit Minus
USB 3.0 SuperSpeed Transmit Plus
I
O
O
VBATT/
VBUS
A9
I/O
I/O
D+
D-
USB (HS/FS) Data Plus
USB (HS/FS) Data Minus
VBATT/
VBUS
A10
A11
B2
C6
C7
B4
E6
D7
D6
NC
No Connect
FSLC[0]
XTALIN
CVDDQ
AVDD
I
FSLC[0]
XTALIN
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
I/O
AVDD
I/O
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
CVDDQ
CVDDQ
CVDDQ
CVDDQ
I
I
I
I
CLKIN_32
CLKIN_32
2
I C_GPIO[5
2
D9
VIO5
VIO5
I/O
I/O
SCL (Serial Clock) for I C Bus Interface
8]
2
I C_GPIO[5
2
D10
SDA (Serial Data) for I C Bus Interface
9]
E7
C10
B11
E8
NC
No Connect
No Connect
No Connect
No Connect
No Connect
Output only
NC
NC
NC
F6
NC
D11
E10
B10
A1
VIO5
O
O[60]
VBATT
VDD
U3VSSQ
VBUS
VSS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
E11
D8
H11
E2
S2VDDQ
VSS
Document Number: 001-55190 Rev. *L
Page 9 of 34
CYUSB302x
Table 7. Pin List (continued)
Pin
No.
Power
Domain
I/O
Name
Description
L9
G1
F1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
S2VDDQ
VSS
S0VDDQ
VSS
G11
E3
L1
S1VDDQ
VSS
B1
L6
VIO4
VSS
B6
B5
A2
C11
L11
A7
B7
C3
B8
E9
B9
F11
H1
L7
CVDDQ
U3TXVDDQ
U3RXVDDQ
VIO5
VSS
AVDD
AVSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
J11
L5
VDD
VDD
K4
L3
VSS
VSS
K3
L2
VSS
VSS
A8
VSS
Precision Resistors
VBUS/VBAT
T
C8
B3
I/O
I/O
R_usb2
R_usb3
Precision resistor for USB 2.0 (Connect a 6.04 k+/-1% resistor between this pin and GND)
Precision resistor for USB 3.0 (Connect a 200 +/-1% resistor between this pin and GND)
U3TXVDDQ
Document Number: 001-55190 Rev. *L
Page 10 of 34
CYUSB302x
Pinout for WLCSP
Figure 3. SD3 WLCSP Ball Map (Bottom View)[2]
12
11
10
9
8
7
6
5
4
3
2
1
VSS
VSS
SSRXM
SSTXM
FSLC[0]
AV SS
AV DD
DP
DM
A
B
U2AFEVSSQ
R_USB2
OTG_ID
V DD
V DD
TRST#
L_GPIO[55]
L_GPIO[56]
LVDDQ
SSRXP
R_USB3
U3VSSQ
SSTXP
FSLC[2]
CVDDQ
XTALIN
XTALOUT
CLKIN
SWDP
SWDM
TDO
U2 PLLV SS
Q
S1VDDQ
U3RXVDDQ
U3TXVDDQ
CLKIN_32
C
S1_GPIO[49] S1_GPIO[50]
L_GPIO[53]
S1_GPIO[51]
L_GPIO[54]
VDD
I2C_GPIO[58]
TMS
I2CVDDQ
TCK
I2C_GPIO[59]
VSS
D
E
F
RESET#
L_GPIO[57]
VSS
S1_GPIO[48]
S1_GPIO[52]
FSLC[1]
I2C_O[60]
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDD
P_GPIO[3]
P_GPIO[4]
P_GPIO[7]
V BATT
P_GPIO[1]
P_GPIO[6]
V BUS
S1_GPIO[46] S1_GPIO[47]
TDI
P_GPIO[0]
P_GPIO[2]
S0VDDQ
S0_GPIO[43] S0_GPIO[44] S0_GPIO[45]
VSS
P_GPIO[9]
G
VSS
S0_GPIO[40] S0_GPIO[41] S0_GPIO[42] S0_GPIO[39]
VSS
P_GPIO[20]
P_GPIO[18]
P_GPIO[14]
P_GPIO[12]
P_GPIO[8]
PVDDQ
H
J
S0VDDQ
S0_GPIO[38] S0_GPIO[37] S0_GPIO[36] P_GPIO[31] P_GPIO[27]
P_GPIO[25] P_GPIO[22]
P_GPIO[19]
INT#
P_GPIO[15]
P_GPIO[24]
P_GPIO[17]
P_GPIO[10]
P_GPIO[11]
P_GPIO[13]
P_GPIO[5]
VSS
S0_GPIO[35] S0_GPIO[34] S0_GPIO[33] P_GPIO[32] P_GPIO[28] P_GPIO[26]
VDD VSS VDD P_GPIO[30] P_GPIO[29] PVDDQ
P_GPIO[16]
P_GPIO[23]
P_GPIO[21]
VSS
K
L
PVDDQ
VSS
Note
2. No ball is populated at location A9.
Document Number: 001-55190 Rev. *L
Page 11 of 34
CYUSB302x
Pin Description for WLCSP
Table 8. Pin List
Power
Domain
Pin
I/O
Name
Description
P-Port
GPIO
F1
F2
G1
E3
F3
J1
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
VI01
CVDDQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
INT#
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
G2
G3
H2
G4
J2
GPIO
GPIO
GPIO
GPIO
GPIO
K2
H3
L2
H4
J3
GPIO
GPIO
GPIO
GPIO
GPIO
K6
L3
H5
J4
GPIO
GPIO
GPIO
GPIO
H6
K5
J5
GPIO
GPIO
GPIO
L6
K3
J6
GPIO
GPIO
GPIO
K7
J7
GPIO
GPIO
K8
L8
L9
J8
GPIO
GPIO
PMODE[0]
PMODE[1]
PMODE[2]
INT#
K9
K4
D8
I
RESET#
RESET#
S0-Port
8b MMC
S0_SD0
S0_SD1
S0_SD2
S0_SD3
S0_SD4
S0_SD5
S0_SD6
S0_SD7
SD+GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
K10
K11
K12
J9
VI02
VI02
VI02
VI02
VI02
VI02
VI02
VI02
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
GPIO[38]
GPIO[39]
GPIO[40]
S0_SD0
S0_SD1
S0_SD2
S0_SD3
GPIO
J10
J11
H8
GPIO
GPIO
H11
GPIO
Document Number: 001-55190 Rev. *L
Page 12 of 34
CYUSB302x
Table 8. Pin List (continued)
Power
Pin
I/O
Name
Description
S0_CMD
Domain
H10
H9
VI02
I/O
I/O
I/O
I/O
I/O
GPIO[41]
GPIO[42]
GPIO[43]
GPIO[44]
GPIO[45]
S0_CMD
S0_CLK
GPIO
GPIO
GPIO
GPIO
GPIO
VI02
S0_CLK
S0_WP
S0S1_INS
GPIO
G11
G10
G9
VI02
S0_WP
VI02
S0S1_INS
VI02
MMC0_RST_OUT
S1-Port
GPIO+UART
+I2S
UART+SPI+I
8b MMC
SD+UART
SD+SPI
SD+GPIO
GPIO
SD+I2S
2S
F11
F10
VI03
VI03
I/O
I/O
GPIO[46]
GPIO[47]
S1_SD0
S1_SD1
S1_SD0
S1_SD1
S1_SD0
S1_SD1
S1_SD0
S1_SD1
GPIO
GPIO
GPIO
GPIO
S1_SD0
S1_SD1
UART_RTS
UART_CTS
E11
D12
D11
E10
E9
VI03
VI03
VI03
VI03
VI03
VI04
VI04
VI04
VI04
VI04
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
GPIO[54]
GPIO[55]
GPIO[56]
GPIO[57]
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
S1_SD2
S1_SD3
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
S1_SD2
S1_SD3
S1_CMD
S1_CLK
S1_WP
UART_TX
UART_RX
I2S_CLK
I2S_SD
S1_CMD
S1_CLK
I2S_CLK
I2S_SD
S1_WP
I2S_WS
I2S_WS
D10
D9
S1_SD4
S1_SD5
S1_SD6
S1_SD7
UART_RTS
UART_CTS
UART_TX
UART_RX
GPIO
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_MCLK
GPIO
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
I2S_MCLK
GPIO
I2S_CLK
I2S_SD
I2S_WS
I2S_MCLK
B12
C12
E12
GPIO
GPIO
MMC1_RST
_OUT
GPIO
U-Port
USB OTG Identification
C3
A10
B10
A8
VBUS/VBATT
U3RXVDDQ
U3RXVDDQ
U3TXVDDQ
U3TXVDDQ
VBUS/VBATT
VBUS/VBATT
VBUS/VBATT
VBUS/VBATT
I
OTG_ID
SSRXM
SSRXP
SSTXM
SSTXP
DP
I
USB 3.0 SuperSpeed Receive Minus
USB 3.0 SuperSpeed Receive Plus
USB 3.0 SuperSpeed Transmit Minus
USB 3.0 SuperSpeed Transmit Plus
USB (HS/FS) Data Plus
I
O
B8
O
A4
I/O
I/O
I/O
I/O
A2
DM
USB (HS/FS) Data Minus
B4
SWDP
SWDM
USB (HS/FS) Switch Interface Data Plus
USB (HS/FS) Switch Interface Data Minus
Crystal/Clocks
B2
A7
B6
B5
F9
CVDDQ
AVDD
I
FSLC[0]
XTALIN
Frequency Select 0
I/O
I/O
I
Crystal Oscillator Input
AVDD
XTALOUT
FSLC[1]
Crystal Oscillator Output
CVDDQ
Frequency Select 1
Frequency Select 2
CVDDQ
CVDDQ
CVDDQ
I
I
I
FSLC[2]
CLKIN
B7
C5
C6
External Clock Input
32.76-kHz Clock Input for Watchdog Timer
Other
CLKIN_32
2
D6
D2
F8
C2
C1
D5
D3
E8
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I2C_VDDQ
I/O
I/O
I
I2C_GPIO[58]
I2C_GPIO[59]
TDI
SCL (Serial Clock) for I C Bus Interface
2
SDA (Serial Data) for I C Bus Interface
TDI (Test Data In) for JTAG Interface
TDO (Test Data Out) for JTAG Interface
TRST (Test Reset) for JTAG Interface
TMS (Test Mode Select) for JTAG Interface
TCK (Test Clock) for JTAG Interface
Charger Detect Output
O
TDO
O
TRST#
TMS
O
O
TCK
O
O[60]
Power
Document Number: 001-55190 Rev. *L
Page 13 of 34
CYUSB302x
Table 8. Pin List (continued)
Power
Domain
Pin
I/O
Name
Description
E2
B1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I/O
VBATT
VDD
USB Supply Voltage Input
A1
VDD
C9
E1
U3VSSQ
VBUS
U2PLLVSSQ
PVDDQ
VSS
GND
USB Supply Voltage Input
C4
H1
K1
USB2 Regulator GND
P-Port Supply Voltage Input
GND
L4
PVDDQ
VSS
P-Port Supply Voltage Input
L5
GND
L7
PVDDQ
VSS
P-Port Supply Voltage Input
L1
GND
J12
H12
G12
C11
F12
B11
A11
A12
C7
C8
C10
D4
A3
S0VDDQ
VSS
S0-Port Supply Voltage Input
GND
S0VDDQ
S1VDDQ
VSS
S0- Port Supply Voltage Input
S1-Port Supply Voltage Input
GND
LVDDQ
VSS
Low Performance Peripherals Supply Voltage Input
GND
VSS
GND
Clock Supply Voltage Input
USB3 1.2V Supply Voltage
USB3 1.2V Supply Voltage
I2C and JTAG Supply Voltage Input
GND
CVDDQ
U3TXVDDQ
U3RXVDDQ
I2C_VDDQ
U2AFEVSSQ
AVDD
AVSS
A5
Analog Supply Voltage Input
Analog GND
A6
F4
VDD
Core Supply Voltage Input
GND
D1
F5
VSS
VDD
Core Supply Voltage Input
GND
E4
VSS
F6
VDD
Core Supply Voltage Input
GND
E5
VSS
F7
VDD
Core Supply Voltage Input
GND
E6
VSS
D7
E7
VDD
Core Supply Voltage Input
GND
VSS
G6
L10
L12
H7
G7
L11
G8
G5
B3
VDD
Core Supply Voltage Input
Core Supply Voltage Input
Core Supply Voltage Input
GND
VDD
VDD
VSS
VSS
GND
VSS
GND
VSS
GND
VSS
GND
VBUS/VBATT
U3TXVDDQ
R_USB2
R_USB3
Precision Resistor for USB 2.0 (Connect a 6.04 k ± 1% resistor between this pin and GND)
Precision Resistor for USB 3.0 (Connect a 200 ± 1% resistor between this pin and GND)
B9
I/O
Document Number: 001-55190 Rev. *L
Page 14 of 34
CYUSB302x
AC Timing Parameters
Storage Port Timing
The S0-Port and S1-Port support the MMC Specification Version 4.4 and SD Specification Version 3.0.
Table 9 lists the timing parameters for S0-Port and S1-Port of SD3.
Table 9. S-Port Timing Parameters[3]
Parameter
Description
Min
Max
Units
MMC-20
MMC-26
MC-HS
tSDIS CMD
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
4.8
4.8
4.4
4.4
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
–
–
–
5
–
5
–
5
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
50
–
SDFREQ
Clock frequency
20
60
tSDCLKOD
Clock duty cycle
40
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
10
10
9
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
–
9
–
3
–
3
–
3
–
3
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
38.5
–
SDFREQ
Clock frequency
26
60
tSDCLKOD
Clock duty cycle
40
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
4
4
3
3
3
3
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Document Number: 001-55190 Rev. *L
Page 15 of 34
CYUSB302x
Table 9. S-Port Timing Parameters[3] (continued)
Parameter Description
tSDOH CMD
Min
3
Max
–
Units
ns
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
tSDOH DAT
tSCLKR
3
–
ns
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
19.2
–
–
ns
SDFREQ
tSDCLKOD
Clock frequency
52
60
MHz
%
Clock duty cycle
40
MMC-DDR52
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
4
0.56
3
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
–
2.58
3
–
–
2.5
3
–
–
2.5
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
19.2
–
SDFREQ
Clock frequency
52
55
tSDCLKOD
Clock duty cycle
45
SD-Default Speed (SDR12)
Host input setup time for CMD
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
24
24
2.5
2.5
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
–
–
–
5
–
5
–
5
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
40
–
SDFREQ
Clock frequency
25
60
tSDCLKOD
Clock duty cycle
40
SD-High-Speed(SDR25)
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
4
–
–
–
–
ns
ns
ns
ns
4
2.5
2.5
Document Number: 001-55190 Rev. *L
Page 16 of 34
CYUSB302x
Table 9. S-Port Timing Parameters[3] (continued)
Parameter Description
tSDOS CMD
Min
6
Max
–
Units
ns
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
6
–
ns
2
–
ns
2
–
ns
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
20
–
–
ns
SDFREQ
tSDCLKOD
Clock frequency
50
60
MHz
%
Clock duty cycle
40
SD-SDR50
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
1.5
1.5
2.5
2.5
3
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
–
–
–
3
–
0.8
0.8
–
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
10
–
SDFREQ
Clock frequency
100
60
tSDCLKOD
Clock duty cycle
40
SD-DDR50
tSDIS CMD
tSDIS DAT
tSDIH CMD
tSDIH DAT
tSDOS CMD
tSDOS DAT
tSDOH CMD
tSDOH DAT
tSCLKR
Host input setup time for CMD
Host input setup time for DAT
Host input hold time for CMD
Host input hold time for DAT
Host output setup time for CMD
Host output setup time for DAT
Host output hold time for CMD
Host output hold time for DAT
Clock rise time
4
0.92
2.5
2.5
6
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
–
–
–
3
–
0.8
0.8
–
–
–
2
tSCLKF
Clock fall time
–
2
tSDCK
Clock cycle time
20
–
SDFREQ
Clock frequency
50
55
tSDCLKOD
Clock duty cycle
45
Note
3. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *L
Page 17 of 34
CYUSB302x
2
I C Interface Timing
I2C Timing
Figure 4. I2C Timing Definition
Table 10. I2C Timing Parameters[4]
Parameter
Description
Min
Max
Units
I2C Standard Mode Parameters
fSCL
SCL clock frequency
0
4
100
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
4.7
4
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
–
Setup time for a repeated START condition
Data hold time
4.7
0
–
–
Data setup time
250
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
1000
300
–
tf
–
tSU:STO
tBUF
4
4.7
–
–
tVD:DAT
tVD:ACK
tSP
3.45
3.45
n/a
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
n/a
Note
4. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *L
Page 18 of 34
CYUSB302x
Table 10. I2C Timing Parameters[4] (continued)
Parameter
Description
Min
Max
Units
I2C Fast Mode Parameters
fSCL
SCL clock frequency
0
0.6
1.3
0.6
0.6
0
400
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
100
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus-free time between a STOP and START condition
Data valid time
300
300
–
tf
–
tSU:STO
tBUF
0.6
1.3
–
–
tVD:DAT
tVD:ACK
tSP
0.9
0.9
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ = 1.2V)
fSCL
SCL clock frequency
0
0.26
0.5
0.26
0.26
0
1000
–
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
HIGH period of the SCL
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
50
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
120
120
–
tf
–
tSU:STO
tBUF
0.26
0.5
–
–
tVD:DAT
tVD:ACK
tSP
0.45
0.55
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
Document Number: 001-55190 Rev. *L
Page 19 of 34
CYUSB302x
I2S Timing Diagram
Figure 5. I2S Transmit Cycle
tT
tTR tTF
tTH
tTL
SCK
tThd
SA,
WS (output)
tTd
Table 11. I2S Timing Parameters[5]
Parameter
Description
Min
Max
Units
ns
tT
I2S transmitter clock cycle
I2S transmitter cycle LOW period
Ttr
–
tTL
tTH
tTR
tTF
tThd
tTd
0.35 Ttr
–
–
ns
I2S transmitter cycle HIGH period
I2S transmitter rise time
0.35 Ttr
ns
–
–
0
–
0.15 Ttr
0.15 Ttr
–
ns
I2S transmitter fall time
ns
I2S transmitter data hold time
I2S transmitter delay time
ns
0.8tT
ns
Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
5. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *L
Page 20 of 34
CYUSB302x
SPI Timing Specification
Figure 6. SPI Timing
SSN
(output)
tssnh
tsck
tlag
tlead
SCK
(CPOL=0,
Output)
trf
twsck
twsck
SCK
(CPOL=1,
Output)
tsdi
thoi
LSB
MISO
(input)
MSB
MSB
td
tdis
tsdd
tdi
v
MOSI
(output)
LSB
SPI Master Timing for CPHA = 0
SSN
(output)
tssnh
tsck
tlag
tlead
trf
SCK
(CPOL=0,
Output)
twsck
twsck
SCK
(CPOL=1,
Output)
thoi
LSB
tsdi
MISO
(input)
MSB
MSB
tdis
tdi
tdv
MOSI
(output)
LSB
SPI Master Timing for CPHA = 1
Document Number: 001-55190 Rev. *L
Page 21 of 34
CYUSB302x
Table 12. SPI Timing Parameters[6]
Parameter Description
fop
Min
Max
Units
MHz
ns
Operating frequency
Cycle time
0
33
tsck
twsck
tlead
tlag
trf
30
–
Clock high/low time
SSN-SCK lead time
Enable lag time
13.5
1/2 tsck[7 ]-5
–
ns
1.5 tsck[7]+ 5
1.5 tsck[7]+5
ns
0.5
–
ns
Rise/fall time
8
5
5
–
–
–
–
–
ns
tsdd
tdv
Output SSN to valid data delay time
Output data valid time
Output data invalid
–
ns
–
ns
tdi
0
ns
tssnh
tsdi
thoi
tdis
Minimum SSN high time
Data setup time input
Data hold time input
Disable data output on SSN high
10
8
ns
ns
0
ns
0
ns
Notes
6. All parameters guaranteed by design and validated through characterization.
7. Depends on LAG and LEAD setting in the SPI_CONFIG register.
Document Number: 001-55190 Rev. *L
Page 22 of 34
CYUSB302x
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may shorten the useful life of the
device.
TA (ambient temperature under bias)
Industrial ................................................... –40 °C to +85 °C
Storage temperature ............................... –65 °C to +150 °C
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
supply voltage ............................................. 1.15 V to 1.25 V
Ambient temperature with
power supplied (Industrial) ....................... –40 °C to +85 °C
VBATT supply voltage ......................................... 3.2 V to 6 V
Supply voltage to ground potential
S2VDDQ, S1VDDQ, S0VDDQ, VIO4, CVDDQ
supply voltage ................................................. 1.7 V to 3.6 V
VDD, AVDDQ ................................................................. 1.25 V
S2VDDQ,S1VDDQ, S0VDDQ, VIO4, VIO5 ......................... 3.6 V
U3TXVDDQ, U3RXVDDQ ............................................. 1.25 V
DC input voltage to any input pin ......................... VCC + 0.3
VIO5 supply voltage ....................................... 1.15 V to 3.6 V
DC voltage applied to
outputs in High Z State ........................................ VCC + 0.3
(VCC is the corresponding I/O voltage)
Static discharge voltage ESD protection levels:
■ ±2.2-KV human body model (HBM) based on JESD22-A114
■ Additional ESD Protection levels on D+, D–, VBUS, GND pins
U-port and GPIO pins LPP-Port
■ ±6-KV contact discharge, ±8-KV air gap discharge based on
IEC61000-4-2 level 3A, ±8-KV contact discharge, and ±15-KV
air gap discharge based on IEC61000-4-2 level 4C
Latch-up current ................................................... > 200 mA
Maximum output short circuit current
for all I/O configurations. (Vout = 0 V) .................... –100 mA
Document Number: 001-55190 Rev. *L
Page 23 of 34
CYUSB302x
DC Specifications
Table 13. DC Specifications
Parameter
Description
Min
1.15
1.15
1.7
Max
1.25
1.25
3.6
3.6
3.6
3.6
6
Units
V
Notes
VDD
Core voltage supply
Analog voltage supply
1.2-V typical
1.2-V typical
AVDD
V
S0VDDQ
S1VDDQ
S2VDDQ
VIO4
SD/ MMC/ CF I/O power supply domain
SD/MMC I/O power supply domain
GPIO/ CF I/O power supply domain
GPIO/ I/O power supply domain
USB voltage supply
V
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
3.7-V typical
1.7
V
1.7
V
1.7
V
VBATT
3.2
V
VBUS
USB voltage supply
4.0
6
V
5-V typical
U3TXVDDQ
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass
capacitor is required on this
power supply.
U3RXVDDQ
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass
capacitor is required on this
power supply.
CVDDQ
VIO5
Clock voltage supply
I2C voltage supply
Input HIGH voltage 1
1.7
1.2
3.6
3.3
V
V
V
1.8-, 3.3-V typical
1.2-,1.8-, 2.5-, and 3.3-V typical
VIH1
0.625 × VCC
VCC + 0.3
For 2.0 V VCC 3.6 V (except
USB port).VCC is the corre-
sponding I/O voltage supply.
VIH2
Input HIGH voltage 2
VCC - 0.4
VCC + 0.3
V
For 1.7 V VCC 2.0 V
(except USB port). VCC is the
corresponding I/O voltage
supply.
VIL
Input LOW voltage
–0.3
0.25 × VCC
–
V
V
VCC is the corresponding I/O
voltage supply.
VOH
Output HIGH voltage
0.9 × VCC
IOH (max) = –100 µA tested at
quarterdrivestrength.VCCisthe
corresponding I/O voltage
supply.
VOL
Output LOW voltage
–
0.1 × VCC
V
IOL (min) = +100 µA tested at
quarterdrivestrength.VCCisthe
corresponding I/O voltage
supply.
IIX
Input leakage current for all pins except
SSTXP/SSXM/SSRXP/SSRXM
–1
1
µA
All I/O signals held at VDDQ
(For I/Os that have a
pull-up/down resistor connected,
the leakage current increases by
VDDQ/Rpu or VDDQ/RPD
IOZ
Output High-Z leakage current for all pins
except SSTXP/SSXM/SSRXP/SSRXM
–1
–
1
µA
All I/O signals held at VDDQ
ICC Core
Core and Analog Voltage Operating
Current
200
60
mA Total current through AVDD,
VDD
ICC USB
USB voltage supply operating current
–
mA
Document Number: 001-55190 Rev. *L
Page 24 of 34
CYUSB302x
Table 13. DC Specifications(continued)
Parameter
Description
Min
Max
Units
Notes
ISB1
Total suspend current during Suspend
Mode with USB 3.0 PHY enabled (L1
mode)
–
–
mA Core current: 1.5 mA
I/O current: 20 µA
USB current: 2 mA
For typical PVT (Typical silicon,
all power supplies at their
respective nominal levels at
25 C.)
ISB2
ISB3
ISB4
Total suspend current during Suspend
Mode with USB 3.0 PHYdisabled (L2
mode)
–
–
–
–
–
–
mA Core current: 250 µA
I/O current: 20 µA
USB current: 1.2 mA
For typical PVT (Typical silicon,
all power supplies at their
respective nominal levels at
25 C.)
Total Standby Current during Standby
Mode (L3 mode)
µA
µA
Core current: 60 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (Typical silicon,
all power supplies at their
respective nominal levels at
25 C.)
Total Standby Current during Core Power
Down Mode (L4 mode)
Core current: 0 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (Typical silicon,
all power supplies at their
respective nominal levels at
25 C.)
VRAMP
VN
Voltage Ramp Rate on Core and I/O
Supplies
0.2
–
50
100
20
V/ms Voltage ramp must be monotonic
Noise Level Permitted on VDD and I/O
Supplies
mV Max p-p noise level permitted on
all supplies except AVDD
VN_AVDD
Noise Level Permitted on AVDD Supply
–
mV Max p-p noise level permitted on
AVDD
Document Number: 001-55190 Rev. *L
Page 25 of 34
CYUSB302x
Reset Sequence
Table 14 provides the hard reset sequence requirements for SD3.
Table 14. Reset and Standby Timing Parameters
Parameter
tRPW
Definition
Conditions
Clock Input
Crystal Input
–
Min (ms)
Max (ms)
Minimum RESET# pulse width
1
1
5
1
5
–
–
–
–
–
tRH
tRR
Minimum high on RESET#
Reset Recovery Time (after which Boot loader begins
firmware download)
Clock Input
Crystal Input
–
tSBY
tWU
Time to enter Standby/Suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
1
Time to wakeup from standby
Clock Input
Crystal Input
–
1
5
5
–
–
–
tWH
Minimum time before Standby/Suspend source may be
reasserted
Figure 7. Reset Sequence
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
tRh
tRR
Mandatory
Reset Pulse
Hard Reset
RESET #
tWH
tWU
tRPW
tSBY
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
Document Number: 001-55190 Rev. *L
Page 26 of 34
CYUSB302x
Package Diagrams
Figure 8. 121-ball FBGA (10 × 10 × 1.20 mm) Package Outline, 001-54471
2X
0.10 C
E1
E
B
(datum B)
A1 CORNER
A
11 10
9
8
7
6
5
4
3
2
1
7
A1 CORNER
A
B
C
D
E
F
6
SD
D1
D
(datum A)
G
H
J
K
eD
L
2X
0.10 C
6
eE
TOP VIEW
SE
BOTTOM VIEW
0.20 C
DETAIL A
A1
0.08 C
C
121XØb
5
A
Ø0.15 M C A B
Ø0.08 M C
SIDE VIEW
DETAIL A
001-54471 *E
Figure 9. 131-ball WLCSP FB131/FN131 Package Outline, 001-62221
001-62221 *C
Document Number: 001-55190 Rev. *L
Page 27 of 34
CYUSB302x
Ordering Information
Table 15. Ordering Information
Ordering Code
CYUSB3023-FBXCT
CYUSB3025-BZXI
SD/eMMC SDIO Ports
SRAM (KB)
512
Package Type
1
2
131-ball WLCSP
121-ball BGA
512
Ordering Code Definitions
XXX
-
XX
X
X X
USB
CY
3
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = BZ or FB
BZ = 121-ball BGA
FB = 131-ball WLCSP
Marketing Part Number
Base Part Number for USB 3.0
Marketing Code: USB = USB Controller
Company ID: CY = Cypress
Document Number: 001-55190 Rev. *L
Page 28 of 34
CYUSB302x
Acronyms
Document Conventions
Table 16. Acronyms Used in this Document
Units of Measure
Acronym
ACA
Description
accessory charger adaptor
Table 17. Units of Measure
Symbol
°C
Unit of Measure
BGA
MMC
PLL
ball grid array
degree Celsius
Megabytes per second
mega hertz
microamperes
microseconds
milliamperes
milliseconds
nanoseconds
ohms
Mbps
MHz
µA
µs
multimedia card
phase locked loop
secure digital
SD
SDIO
SLC
secure digital input / output
single-level cell
mA
ms
ns
USB
universal serial bus
pF
pico Farad
V
volts
Document Number: 001-55190 Rev. *L
Page 29 of 34
CYUSB302x
Errata
This document describes the errata for the SD3, CYUSB3023-FBXCT, CYUSB3025-BZXI. Details include errata trigger conditions,
scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s datasheet for a
complete functional description. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
CYUSB3023-FBXCT
CYUSB3025-BZXI
Device Characteristics
SD3 USB and Mass Storage Peripheral Controller Qualification Status
Product Status: Sampling
SD3 USB and Mass Storage Peripheral Controller Errata Summary
The following table defines the errata applicability to available SD3 USB and Mass Storage Peripheral Controller family devices.
Items
Part Number
Silicon Revision
Fix Status
[1]. Turning off VIO1 during Normal, Suspend, and
Standby modes causes the FX3 to stop working.
CYUSB3023-FBXCT,
CYUSB3025-BZXI
ES
Workaround provided
[2]. USB enumeration failure in USB boot mode when CYUSB3023-FBXCT,
FX3 is self-powered. CYUSB3025-BZXI
ES
ES
Workaround provided
[3]. Bus collision is seen when the I2C block is used as CYUSB3023-FBXCT,
a master in the I2C Multi-master configuration. CYUSB3025-BZXI
Use FX3 in single-master
configuration
1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working.
❐ Problem Definition
Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the FX3 to stop working.
❐ Parameters Affected
N/A
❐ Trigger Conditions
This condition is triggered when the VIO1 is turned off during Normal, Suspend, and Standby modes.
❐ Scope Of Impact
FX3 stops working.
❐ Workaround
VIO1 must stay on during Normal, Suspend, and Standby modes.
❐ Fix Status
No fix. Workaround is required.
Document Number: 001-55190 Rev. *L
Page 30 of 34
CYUSB302x
2. USB enumeration failure in USB boot mode when FX3 is self-powered.
❐ Problem Definition
FX3 device may not enumerate in USB boot mode when it is self-powered. The bootloader is designed for bus power mode. It
does not make use of the VBUS pin on the USB connector to detect the USB connection and expect that USB bus is connected
to host if it is powered. If FX3 is not already connected to the USB host when it is powered, then it enters into low-power mode
and does not wake up when connected to USB host.
❐ Parameters Affected
N/A
❐ Trigger Conditions
This condition is triggered when FX3 is self-powered in USB boot mode.
❐ Scope Of Impact
Device does not enumerate
❐ Workaround
Reset the device after connecting to USB host.
❐ Fix Status
No fix. Workaround is required.
3. Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.
❐ Problem definition
2
When FX3 is used as a master in the I C multi-master configuration, there can be occasional bus collisions.
❐ Parameters affected
NA
❐ Trigger Conditions
2
This condition is triggered only when the FX3 I C block operates in Multi-master configuration.
❐ Scope Of Impact
2
2
The FX3 I C block can transmit data when the I C bus is not idle leading to bus collision.
❐ Workaround
Use FX3 as a single master.
❐ Fix Status
No fix.
Document Number: 001-55190 Rev. *L
Page 31 of 34
CYUSB302x
Document History Page
Document Title: CYUSB302x, SD3™ USB and Mass Storage Peripheral Controller
Document Number: 001-55190
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2761891
2823531
VSO
OSG
09/10/2009 New data sheet.
*A
12/08/2009 Added data sheet to the USB 3.0 EROS spec 001-51884.
No technical updates.
*B
3080927
OSG
11/08/2010 Changed status from Advance to Preliminary
Added the following sections: Power, Configuration Fuse, Digital I/Os, EMI,
System LevelESD, Absolute Maximum Ratings, AC Timing Parameters, Reset
Sequence. Added DC Specifications table
Updated Pin List
Updated block diagram
Updated part number
Updated package diagram
*C
*D
*E
3204393
3217917
3369042
OSG
OSG
OSG
03/23/2011 Added a reference to footnote 1 in Table 1.
04/06/2011 Changed values of R_USB2 and R_USB3
12/06/2011 Updated tRR and tRPW for crystal input
Added clarification regarding I and I
OZ
IX
Updated 121-ball FBGA package diagram
Added clarification regarding VCC in DC Specifications table
In Power Modes description, stated that S2VDDQ cannot be turned off at any
time if the S2-port is used in the application
Updated Absolute Maximum Ratings
Added requirement for by-pass capacitor on U3RX
and U3TX
VDDQ
VDDQ
Updated I2C interface tVD:ACK parameter for 1 MHz operation.
Changed datasheet status from Preliminary to Final.
*F
3649782
OSG
08/16/2012 Added note about the I2C controller support for clock stretching.
Updated Clocking and Hard Reset sections.
Modified V
min value.
BUS
Updated Rise/fall time max value.
*G
*H
3848148
4016006
OSG
GSZ
12/20/2012 Updated Package Diagrams:
spec 001-54471 – Changed revision from *C to *D.
06/04/2013 Updated Features.
Updated Applications.
Updated Logic Block Diagram.
Updated Functional Overview.
Updated Pin Description for BGA.
Added Pinout for WLCSP.
Added Pin Description for WLCSP.
Updated AC Timing Parameters
Updated Package Diagrams (Added Figure 9).
Updated Ordering Information (Updated part numbers).
*I
4131901
5460202
GSZ
09/23/2013 Changed status from Preliminary to Final.
Updated Package Diagrams:
spec 001-62221 – Changed revision from *B to *C.
Updated Ordering Information (Updated part numbers).
Updated to new template.
Completing Sunset Review.
*J
RAJV
10/14/2016 Updated Package Diagrams:
spec 001-54471 – Changed revision from *D to *E.
Added Errata.
Updated to new template.
*K
5765169 AESATMP9 06/06/2017 Updated logo and copyright.
Document Number: 001-55190 Rev. *L
Page 32 of 34
CYUSB302x
Document History Page(continued)
Document Title: CYUSB302x, SD3™ USB and Mass Storage Peripheral Controller
Document Number: 001-55190
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*L
5774759
GAYA
06/15/2017 Updated Errata.
Updated to new template.
Document Number: 001-55190 Rev. *L
Page 33 of 34
CYUSB302x
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-55190 Rev. *L
Revised June 15, 2017
Page 34 of 34
相关型号：
CYUSB3064-BZXC
Infineon EZ-USB™ CX3 enables USB 5 Gbps connectivity to any image sensor which is compliant with Mobile Industry Processor Interface (MIPI) Camera Serial Interface Type 2 (CSI-2) standard. Based on the proven EZ-USB™ FX3 Platform, EZ-USB™ CX3 includes a fully accessible ARM9 CPU and 512 KB SRAM that provides 200 MIPS of computational power. EZ-USB™ CX3 also supports Camera Control Interface (CCI) for image sensor configuration. EZ-USB™ CX3's multiple peripheral interfaces such as I²C, SPI, and UART can be programmed to support pan, tilt and zoom or other camera control functions.
INFINEON
CYUSB3064-BZXI
Infineon EZ-USB™ CX3 enables USB 5 Gbps connectivity to any image sensor which is compliant with Mobile Industry Processor Interface (MIPI) Camera Serial Interface Type 2 (CSI-2) standard. Based on the proven EZ-USB™ FX3 Platform, EZ-USB™ CX3 includes a fully accessible ARM9 CPU and 512 KB SRAM that provides 200 MIPS of computational power. EZ-USB™ CX3 also supports Camera Control Interface (CCI) for image sensor configuration. EZ-USB™ CX3's multiple peripheral interfaces such as I²C, SPI, and UART can be programmed to support pan, tilt and zoom or other camera control functions.
INFINEON
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