CYM9291PZ-117C [CYPRESS]
ZBT SRAM, 1MX36, 4.8ns, CMOS, ZIP-120;
| 型号： | CYM9291PZ-117C |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 1MX36, 4.8ns, CMOS, ZIP-120 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYM9291
ADVANCE INFORMATION
1M x 36 Pipelined NoBL™ SRAM Module
plastic surface mount packages on an epoxy laminate board
with pins. The modules are designed to be incorporated into
large memory arrays.
Features
• Operates at 133 MHz
• Uses 512K x 18 high-performance Pipelined NoBL™
synchronous SRAMs
• 2.5V data inputs/outputs
The module is configured as two banks, where each bank has
separate chip select controls. Separate clocks are provided for
every pair of SRAMs.
Multiple ground pins and on-board decoupling capacitors en-
sure high performance with maximum noise immunity.
Functional Description
The CYM9291 is a high-performance synchronous pipelined
NoBL memory module organized as 1M by 36 bits. These
modules are constructed from 512K x 18 NoBL SRAMs in
All components on the modules are surface mounted on a
multi-layer epoxy laminate (FR-4) substrate.
-
LogicBlockDiagram CYM9291
D[35:18]
D[17:0]
A[18:0]
SRAM2
D[15:0]
DP[1:0]
A18:0
ADV/LD
GND
OE
ADV/LD
OE
OE
MS0
D[35:0]
MS0
SRAM0
CLK
CS1
CS2
GND
VCC
A19
WE
CS3
BW[0]
BANK 0
A19
BW[1]
CEN
WE
CLK[0:1]
D[35:18]
D[17:0]
SRAM3
D[15:0]
DP[1:0]
A18:0
ADV/LD
OE
OE
MS0
A19
CS1
CS2
CS3
SRAM1
GND
BW[0]
BW[1]
CEN
CLK
BANK 1
WE
GND
NoBL is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 7, 2000
ADVANCE INFORMATION
CYM9291
Selection Guide
NoBL Pipelined Module
Part Number
Cache Size
1M x 36
SRAM’s Used
System Clock (MHz)
Data t
CDV
CYM9291PZ-133
CYM9291PZ-117
4 of 512K x 18(TQFP)
4 of 512K x 18(TQFP)
133
117
4.4 ns
4.8ns
1M x 36
2
ADVANCE INFORMATION
CYM9291
Pin Configuration
Dual Read-Out ZIP
Top View
1
3
2
4
6
8
GND
A1
GND
A0
Vcc2
Vcc2
5
A2
7
A3
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
9
GND
A5
A4
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
A6
A7
GND
A8
GND
A9
GND
GND
A11
A10
CC2
A12
V
V
A
CC2
13
GND
A14
A16
GND
A18
GND
A15
A17
GND
A19
MS[0]
GND
D0
WE
GND
D1
VCC2
VCC2
D
2
45
47
49
51
D3
GND
D5
D7
GND
D9
VCC2
D11
GND
CLK1
GND
D13
VCC2
D15
GND
D17
D19
GND
D4
D6
53
55
57
59
61
63
65
67
69
71
73
75
77
GND
D8
VCC2
58
D10
GND
CLK0
60
62
64
66
68
70
72
74
76
GND
D12
VCC2
D14
GND
D16
D18
78
80
GND
GND
79
D20
D22
D21
D23
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
GND
GND
D24
D25
VCC2
V
CC2
D26
D27
GND
D29
GND
D28
D30
D31
GND
D33
VCC2
D35
GND
ADV/LD
GND
GND
D32
VCC2
D34
GND
GND
GND
(MS[1])NC
OE
VCC2
VCC2
PD0(GND)
GND
PD1(GND)
GND
119
3
ADVANCE INFORMATION
CYM9291
Pin Definitions
Signal
Description
V
2.5V Supply
CC2
GND
A[19:0]
OE
Ground
Addresses from processor
Output Enable
WE
Write Enable
MS[0]
Chip Select for the module
Presence Detect output pins
Data lines from processor
Clock lines to the module
Advance Load Signal from processor
Signal not connected on module
Reserved for Depth expansion
Reserved
PD –PD
0
1
D[35:0]
CLK[0:1]
ADV/LD
NC
NC(Pin 113)
RSVD
Presence Detect Pins
PD
PD
0
1
CYM9291PZ - 1M x 36
GND
GND
4
ADVANCE INFORMATION
CYM9291
DC Input Voltage ........................................... –0.5V to +3.6V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature ................................. –55°C to +125°C
Ambient
Ambient Temperature
with Power Applied........................................... 0°C to +70°C
Range
Temperature
V
CC
Commercial
0°C to +70°C
2.5V ± 5%
Supply Voltage to Ground Potential .............. –0.3V to +3.6V
DC Voltage Applied to Outputs
in High Z State .............................................. –0.3V to +3.6V
Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Test Condition
Min.
1.7
Max.
V + 0.3
CC
Unit
V
V
IH
IL
V
–0.3
2.0
0.7
V
V
V
V
V
= Min. I = −1 mA
OH
V
OH
CC
CC
CC
V
= Min. I = 1 mA
0.2
V
OL
OL
I
V
Operating Supply Current
= Max., I
=0 mA, f=f
=1/t
RC
1680
mA
CC (9291)
CC
OUT
MAX
Capacitance[1]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
Address Input Capacitance
Control Input Capacitance
Input/Output Capacitance
Clock Capacitance
24
pF
A
A
V
= 2.5 V
CC
C
T = 25°C, f = 1 MHz,
24
16
6
pF
pF
pF
I
A
V
= 2.5 V
CC
C
T = 25°C, f = 1 MHz,
A
O
V
= 2.5 V
CC
C
T = 25°C, f = 1 MHz,
A
CLK
V
= 2.5 V
CC
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R=351W
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
Z =50W
0
3.0V
R =50W
L
5 pF
R=351W
GND
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(a)
(b)
5
ADVANCE INFORMATION
CYM9291
[2]
Switching Characteristics Over the Operating Range
133
117
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Unit
t
Clock Cycle Time
7.5
8.6
ns
MHz
ns
CYC
F
Maximum Operating Frequency
Clock HIGH
133
117
MAX
t
t
2.5
2.5
3
3
CH
CL
Clock LOW
ns
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
4.4
4.4
4.8
4.8
ns
ns
ns
ns
ns
ns
ns
CDV
EOV
DOH
CHZ
CLZ
[3, 5]
OE LOW to Output Valid
Data Output Hold After CLK Rise
2.3
2.3
0
2.3
2.3
0
[3, 4, 5]
Clock to High-Z
3. 8
3.8
3.8
3.8
[3, 4, 5]
Clock to Low-Z
[3, 4, 5]
OE HIGH to Output High-Z
EOHZ
EOLZ
[3, 4, 5]
OE LOW to Output Low-Z
Set-up Times
t
t
t
t
t
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
WE Set-Up Before CLK Rise
ADV/LD Set-Up Before CLK Rise
Chip Selects Set-Up
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
AS
DS
WES
ALS
CES
Hold Times
t
t
t
t
t
Address Hold After CLK Rise
Data Input Hold After CLK Rise
WE Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
AH
DH
WEH
ALH
CEH
ADV/LD Hold after CLK Rise
Chip Selects Hold After CLK Rise
Notes:
2. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loading shown in AC Test Load for 2.5V
devices.
3.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
4. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
5. This parameter is sampled and not 100% tested.
6
ADVANCE INFORMATION
CYM9291
Switching Waveforms
Read/Write/Deselect Timing
READ/WRITE/DESELECT Sequence
CLK
t
CENH
t
CENS
t
t
CL
t
CYC
CH
t
t
AH
AS
WA5
WA2
RA1
RA3
RA4
RA6
ADDRESS
WE
RA7
t
t
WS
WH
t
t
CEH
CES
MS[0]
t
t
t
t
DH
DS
CHZ
CHZ
t
DOH
t
t
CLZ
DOH
D2
In
Q4
Out
D5
In
Q1
Q3
Q6
Out
Q7
Data In/Out
Device
Out
Out
Out
t
CO
originally
deselected
All chip enables need to be active in order to select the device. Any chip enable can deselect the device.
RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X,
Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
7
ADVANCE INFORMATION
CYM9291
Switching Waveforms (continued)
Burst Timing
Burst Sequences
CLK
t
CYC
t
t
ALH
ALS
t
t
CL
CH
ADV/LD
ADDRESS
WE
t
t
AH
AS
RA1
WA2
RA3
t
t
WS
WH
t
t
WS
WH
BW
[3:0]
t
t
CES
CEH
MS[0]
t
t
CLZ
CHZ
t
t
DH
DOH
t
CLZ
Q3
Out
Data-
In/Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Q1+1
Out
D2+1
In
Out
Device
originally
deselected
t
CO
t
t
CO
DS
All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands
for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for
location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BW
input signals. Burst order determined by the state of the Mode input. OE held LOW.
[3:0]
= UNDEFINED
= DON’T CARE
8
ADVANCE INFORMATION
CYM9291
Switching Waveforms (continued)
OE Timing
OE
t
EOV
t
EOHZ
Three-state
I/O’s
t
EOLZ
Ordering Information
Speed (MHz)
Ordering Code
CYM9291PZ-133C
CYM9291PZ-117C
Package Name
Package Type
120-Pin ZIP
120-Pin ZIP
Description
Operating Range
133
117
PZxx
PZxx
Pipelined NoBL 1M x 36
Pipelined NoBL 1M x 36
Commercial
Document #: 38-01012-**
9
ADVANCE INFORMATION
CYM9291
Package Diagrams
PZ13: 120 Pin Dual Sided ZIP Module
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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