CYM1836P8-35C [CYPRESS]
128K x 32 Static RAM Module; 128K ×32静态RAM模块
| 型号： | CYM1836P8-35C |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 32 Static RAM Module |
| 文件： | 总8页 (文件大小：543K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYM1836
128K x 32 Static RAM Module
constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
lects (CS1, CS2, CS3, CS4) are used to independently enable
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
Features
• High-density 4-megabit SRAM module
• 32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
• High-speed CMOS SRAMs
— Access time of 15 ns
• Low active power
Writing to each byte is accomplished when the appropriate
Chip Select (CS) and Write Enable (WE) inputs are both
LOW. Data on the input/output pins (I/O) is written into the
memory location specified on the address pins (A0 through
A16).
— 2.6W (max.) at 20 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
Reading the device is accomplished by taking the Chip Select
(CS) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
— Max. height of 0.57 in.
• Small PCB footprint
— 0.78 sq. in.
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
• AvailableinSIMM, ZIPformat. SIMM suitableforvertical
or angled sockets.
Two pins (PD0 and PD1) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Functional Description
The CYM1836 is a high-performance 4-megabit static RAM
module organized as 128K words by 32 bits. This module is
Logic Block Diagram
Pin Configuration
ZIP/SIMM
Top View
PD −OPEN
0
PD −OPEN
1
A − A
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
0
16
PD
I/O
17
2
4
6
8
0
PD
1
OE
WE
0
I/O
8
I/O
9
I/O
10
I/O
I/O
1
2
3
I/O
V
10
12
14
16
18
20
22
24
26
28
30
32
I/O
11
CC
A
A
0
128K x 8
SRAM
I/O − I/O
7
0
7
A
1
4
4
4
4
A
8
A
2
A
9
4
I/O
12
I/O
CS
1
I/O
I/O
13
14
I/O
5
I/O
6
I/O
7
I/O
15
128K x 8
SRAM
GND
I/O − I/O
8
15
WE
A
15
A
14
CS
2
CS
1
CS
CS
CS
2
3
4
CS
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
4
CS
3
16
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
NC
A
128K x 8
SRAM
OE
I/O
GND
I/O − I/O
16
23
24
I/O
16
17
18
19
I/O
25
I/O
26
I/O
I/O
I/O
I/O
27
A
3
A
A
10
11
A
4
128K x 8
SRAM
I/O − I/O
A
5
24
31
A
12
A
13
V
CC
A
6
I/O
20
I/O
21
I/O
22
I/O
23
I/O
28
1836–1
I/O
I/O
29
30
I/O
31
GND
1836–2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 15, 1999
CYM1836
Selection Guide
1836–15
15
1836–20
20
1836–25
25
1836–30
30
1836–35
35
1836–45
45
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains preliminary information.
760
480
480
480
480
480
180
100
100
100
100
100
Maximum Ratings
Operating Range
Ambient
Temperature
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Range
VCC
Commercial
0°C to +70°C
5V ± 10%
Storage Temperature .................................–55°C to +125°C
Ambient Temperature with
Power Applied...............................................–10°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
1836–20, 25,
30, 35, 45
1836–15
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min. Max. Min. Max.
Unit
V
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
0.4
VCC
0.8
0.4
VCC
0.8
V
VIH
2.2
–0.5
–20
–20
2.2
–0.5
–20
–20
V
VIL
V
IIX
GND < VI < VCC
+20
+20
760
180
+20
+20
480
100
µA
µA
mA
mA
IOZ
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CS < VIL
ISB1
Automatic CS Power-Down
Current[1]
VCC = Max., CS > VIH,
Min. Duty Cycle = 100%
ISB2
Automatic CS Power-Down
Current[1]
VCC = Max., CS > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
60
28
mA
Shaded area contains preliminary information.
Capacitance[2]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance[3]
TA = 25°C, f = 1 MHz,
VCC = 5.0V
40/20
15
pF
pF
COUT
Output Capacitance
Notes:
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
2. Tested on a sample basis.
3. 20 pF on CS, 40 pF all others.
2
CYM1836
AC Test Loads and Waveforms
Ω
Ω
R1 481
R1 481
ALL INPUT PULSES
90%
10%
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
R2
255Ω
R2
255Ω
30 pF
5 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
1836–3
1836–4
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
3
CYM1836
Switching Characteristics Over the Operating Range[4]
1836–15
1836–20
1836–25
1836–30
1836–35
1836– 45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
15
3
20
3
25
3
30
3
35
3
45
3
ns
ns
Address to Data
Valid
15
20
25
30
35
45
tOHA
tACS
Output Hold from
Address Change
ns
ns
ns
ns
ns
ns
ns
CS LOW to Data
Valid
15
7
20
8
25
8
30
10
35
12
45
15
tDOE
OE LOW to Data
Valid
tLZOE
tHZOE
tLZCS
tHZCS
OE LOW to
Low Z
0
3
0
3
0
3
0
3
0
3
0
3
OE HIGH to High
Z
7
7
8
10
10
11
13
12
15
15
18
CS LOW to
Low Z[5]
CS HIGH to High
Z[5, 6]
10
WRITE CYCLE[7]
tWC
Write Cycle Time
15
12
20
15
25
15
30
18
35
20
45
25
ns
ns
tSCS
CS LOW to Write
End
tAW
tHA
tSA
Address Set-Up
to Write End
12
0
15
0
15
0
18
0
20
0
25
0
ns
ns
ns
Address Hold
from Write End
Address Set-Up
to Write Start
0
0
0
0
0
0
tPWE
tSD
WE Pulse Width
12
7
15
10
15
10
18
13
20
15
25
20
ns
ns
Data Set-Up to
Write End
tHD
Data Hold from
Write End
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
ns
ns
ns
tLZWE
tHZWE
WE HIGH to Low
Z
WE LOW to High
Z[6]
6
8
10
15
15
18
Shaded area contains preliminary information.
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.
6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4
CYM1836
Switching Waveforms
Read Cycle No.1[8, 9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1836–5
Read Cycle No. 2[8, 10]
t
CS
RC
t
ACS
OE
t
HZOE
t
DOE
t
HZCS
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCS
1836–6
Write Cycle No.1 (WE Controlled)[7]
t
WC
ADDRESS
CS
t
SCS
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
1836–7
Notes:
8. WE is HIGH for read cycle.
9. Device is continuously selected, CS = VIL and OE= VIL.
10. Address valid prior to or coincident with CS transition LOW.
5
CYM1836
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)[7, 11]
t
WC
ADDRESS
t
SA
t
SCS
CS
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
HZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
1836–8
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CSN
H
WE
X
OE
X
Input/Outputs
Mode
High Z
Deselect/Power-Down
L
H
L
Data Out
Data In
High Z
Read
L
L
X
Write
L
H
H
Deselect
6
CYM1836
Ordering Information[12]
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
64-Pin SIMM Module
15
CYM1836PM–15C
CYM1836PZ–15C
CYM1836PY–15C
CYM1836P8–15C
CYM1836PM–20C
CYM1836PZ–20C
CYM1836PY–20C
CYM1836P8–20C
CYM1836PM–25C
CYM1836PZ–25C
CYM1836PY–25C
CYM1836P8–25C
CYM1836PM–30C
CYM1836PZ–30C
CYM1836PY–30C
CYM1836P8–30C
CYM1836PM–35C
CYM1836PZ–35C
CYM1836PY–35C
CYM1836P8–35C
CYM1836PM–45C
CYM1836PZ–45C
CYM1836PY–45C
CYM1836P8–45C
PM03
PZ08
PM08
PM04
PM03
PZ08
PM08
PM04
PM03
PZ08
PM08
PM04
PM03
PZ08
PM03
PM04
PM03
PZ08
PM03
PM04
PM03
PZ08
PM03
PM04
Commercial
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
64-Pin SIMM Module
20
25
30
35
45
Commercial
Commercial
Commercial
Commercial
Commercial
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
64-Pin SIMM Module
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
64-Pin SIMM Module
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
64-Pin SIMM Module
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
64-Pin SIMM Module
64-Pin ZIP Module
64-Pin Gold SIMM Module
72-Pin Gold SIMM Module
Shaded area contains preliminary information.
Note:
12. 64-pin SIMM suitable for use in angled SIMM applications.
Document #: 38–M–00050–D
Package Diagrams
64-Pin SIMM Module PM03
3.855 MAX.
3.580/3.588
. 200 MAX.
124/.126 DIA.
2 PLCS
128KX8
128KX8
128KX8
128KX8
.595 MAX.
.135 REF.
.397/.403
.245/.255
.061/.063 R
.249/.251
PIN1
.075/.085
7
CYM1836
Package Diagrams (continued)
72-Pin Plastic SIMM Module PM04
64-Pin ZIP Module PZ08
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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