CYD36S18V18-167BBC [CYPRESS]
Dual-Port SRAM, 2MX18, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484;型号: | CYD36S18V18-167BBC |
厂家: | CYPRESS |
描述: | Dual-Port SRAM, 2MX18, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484 静态存储器 |
文件: | 总48页 (文件大小:938K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
FullFlex™ Synchronous
SDR Dual-Port SRAM
— Selectable LVTTL (3.3V), Extended HSTL
(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on
each port
Features
• True dual-ported memory allows simultaneous access
to the shared array from each port
— Burst counters for sequential memory access
— Mailbox with interrupt flags for message passing
— Dual Chip Enables for easy depth expansion
• Synchronous pipelined operation with SDR operation
on each port
— Single Data Rate (SDR) interface at 250 MHz
— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)
• Selectable pipeline or flow-through mode
• Selectable 1.5V or 1.8V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
Functional Description
The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,
9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static
RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two
ports are provided, allowing the array to be accessed simulta-
neously. Simultaneous access to a location triggers determin-
istic access control. For FullFlex72 these ports can operate
independently with 72-bit bus widths and each port can be
independently configured for two pipeline stages. Each port
can also be configured to operate in pipeline or flow-through
mode.
Advanced features include built-in deterministic access
control to manage address collisions during simultaneous
access to the same memory location, variable impedance
matching (VIM) to improve data transmission by matching the
output driver impedance to the line impedance, and echo
clocks to improve data transfer.
• Available in 484-ball PBGA Packages and 256-ball
FBGA packages
• FullFlex72 family
— 36-Mbit: 512K x 72 (CYD36S72V18)
— 18-Mbit: 256K x 72 (CYD18S72V18)
— 9-Mbit: 128K x 72 (CYD09S72V18)
— 4-Mbit: 64K x 72 (CYD04S72V18)
• FullFlex36 family
— 36-Mbit: 1M x 36 (CYD36S36V18)
— 18-Mbit: 512K x 36 (CYD18S36V18)
— 9-Mbit: 256K x 36 (CYD09S36V18)
— 4-Mbit: 128K x 36 (CYD04S36V18)
• FullFlex18 family
To reduce the static power consumption, chip enables can be
used to power down the internal circuitry. The number of
cycles of latency before a change in CE0 or CE1 will enable
or disable the databus matches the number of cycles of read
latency selected for the device. In order for a valid write or read
to occur, both chip enable inputs on a port must be active.
— 36-Mbit: 2M x 18 (CYD36S18V18)
— 18-Mbit: 1M x 18 (CYD18S18V18)
— 9-Mbit: 512K x 18 (CYD09S18V18)
— 4-Mbit: 256K x 18 (CYD04S18V18)
Each port contains an optional burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally.
Additional features of this device include a mask register and
• Built-in deterministic access control to manage
a mirror register to control counter increments and
address collisions
wrap-around, counter-interrupt (CNTINT) flags to notify that
the counter will reach the maximum value on the next clock
cycle, readback of the burst-counter internal address, mask
register address, and BUSY address on the address lines,
retransmit functionality, mailbox interrupt flags for message
passing, JTAG for boundary scan, and asynchronous Master
Reset (MRST). The logic block diagram in Figure 1 displays
these features.
— Deterministic flag output upon collision detection
— Collision detection on back-to-back clock cycles
— First Busy Address readback
• Advanced features for improved high-speed data
transfer and flexibility
— Variable Impedance Matching (VIM)
— Echo clocks
The FullFlex72 is offered in a 484-ball plastic BGA package.
The FullFlex36 and FullFlex18 are offered in a 256-ball fine
pitch BGA package.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-06082 Rev. *C
Revised October 11, 2005
PRELIMINARY
FullFlex
FTSEL
CQEN
PORTSTD[1:0]
FTSEL
L
R
CQEN
L
R
CONFIG Block
CONFIG Block
PORTSTD[1:0]
L
R
DQ [71:0]
R
DQ[71:0]
L
BE [7:0]
R
BE [7:0]
L
CE0
R
CE0
L
IO
Control
IO
Control
CE1
R
CE1
L
OE
R
OE
L
R/W
R
R/W
L
CQ1
CQ1
L
CQ1
R
R
R
CQ1
L
CQ0
CQ0
CQ0
L
CQ0
L
R
Dual Ported Array
VC_SEL
BUSY
Collision Detection Logic
BUSY
L
R
A [20:0]
A [20:0]
L
L
R
R
CNT/MSK
CNT/MSK
ADS
ADS
R
L
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
L
RET
R
CNTINT
L
CNTINT
R
C
L
C
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
ZQ0
ZQ0
L
R
ZQ1
ZQ1
L
R
RESET
LOGIC
MRST
READY
READY
LowSPD
L
L
R
LowSPD
R
Figure 1. FullFlex72 18-Mbit (CYD18S72V18) Block Diagram[1, 2, 3]
Notes:
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and the CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18,
and the CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and the CYD04S18V18 devices have 18 address bits. The
CYD09S72V18 and the CYD04S36V18 devices have 17 address bits. The CYD04S72V18 has 16 address bits.
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte
enables.
Document #: 38-06082 Rev. *C
Page 2 of 48
PRELIMINARY
FullFlex
FullFlex72 SDR 484-ball BGA Pinout (Top View)
20 21 22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC DQ61 DQ59 DQ57 DQ54 DQ51 DQ48 DQ45 DQ42 DQ39 DQ36 DQ36 DQ39 DQ42 DQ45 DQ48 DQ51 DQ54 DQ57 DQ59 DQ61 NC
A
B
C
L
L
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
R
R
R
DQ63 DQ62 DQ60 DQ58 DQ55 DQ52 DQ49 DQ46 DQ43 DQ40 DQ37 DQ37 DQ40 DQ43 DQ46 DQ49 DQ52 DQ55 DQ58 DQ60 DQ62 DQ63
L
L
L
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
R
R
R
R
DQ65 DQ64 VSS VSS DQ56 DQ53 DQ50 DQ47 DQ44 DQ41 DQ38 DQ38 DQ41 DQ44 DQ47 DQ50 DQ53 DQ56 VSS VSS DQ64 DQ65
L
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
R
R
[
DQ67 DQ66 VSS VSS VSS CQ1L CQ1L
LOW PORT ZQ0L BUSY CNTI PORT NC CQ1R CQ1R VSS VSS VSS DQ66 DQ67
4]
VSS
L
L
SPDL STD0
L
L
NTL STD1
L
R
R
D
E
F
DQ69 DQ68 VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI NC VSS VDDI DQ68 DQ69
OL OL OL OL OL OL OR OR OR OR OR
L
L
R
R
DQ71 DQ70 CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DQ70 DQ71
OL OL OL OL OL RE RE RE RE OR OR OR OR OR
L
L
R
R
A0L A1L RETL BE4L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE4R RETR A1R A0R
OL OL OR OR
G
H
J
L
R
A2L A3L WRP BE5L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE5R WRP A3R A2R
OL OL OR OR
L
R
A4L A5L READ BE6L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE6R READ A5R A4R
YL OL OL OR OR YR
[
A6L A7L ZQ1L BE7L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI BE7R ZQ1R A7R A6R
4]
[4]
K
L
RE
RE
OR
A8L A9L
CL
OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R
RE RE
A10L A11L VSS BE3L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE3R VSS A11R A10R
RE RE
M
N
A12L A13L ADSL BE2L VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE2R ADSR A13R A12R
OL RE RE
A14L A15L CNT BE1L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT A15R A14R
MSKL
OL
OL
OR
OR
MSK
R
P
R
T
[
[
[
[
[
A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R
7]
6]
6]
7]
NL
OL
OL
OR
OR
NR
[
A18L NC CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR NC A18R
5]
5]
STL
OL
OL
L
R
OR
OR
STR
DQ35 DQ34 R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DQ34 DQ35
U
V
L
L
NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR
R
R
DQ33 DQ32 FTSE VDDI NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DQ32 DQ33
LL OL OL OL OL OL OR OR OR OR OR OR LR
L
L
R
R
DQ31 DQ30 VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO DQ30 DQ31
[4]
L
L
EL STD1 NTR
R
R
STD0 SPDR
R
R
R
W
Y
DQ29 DQ28 VSS VSS DQ20 DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DQ20 TMS TCK DQ28 DQ29
L
L
L
L
L
L
R
R
R
R
R
R
DQ27 DQ26 DQ24 DQ22 DQ19 DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DQ19 DQ22 DQ24 DQ26 DQ27
AA
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
R
NC DQ25 DQ23 DQ21 DQ18 DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DQ18 DQ21 DQ23 DQ25 NC
AB
L
L
L
L
L
L
R
R
R
R
R
R
Notes:
4. Leaving this pin NC disables VIM
5. Leave this ball unconnected for CYD18S72V18, CYD09S72V18 and CYD04S72V18.
6. Leave this ball unconnected for CYD09S72V18 and CYD04S72V18
7. Leave this ball unconnected for CYD04S72V18
Document #: 38-06082 Rev. *C
Page 3 of 48
PRELIMINARY
FullFlex
FullFlex36 SDR 484-ball BGA Pinout (Top View)[8]
20 21 22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
NC
NC
NC
NC DQ33 DQ30 DQ27 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ27 DQ30 DQ33 NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
L
L
L
L
L
L
R
R
R
R
R
R
NC
NC
NC
NC
NC
NC
NC DQ34 DQ31 DQ28 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ28 DQ31 DQ34 NC
NC
NC
NC
L
L
L
L
L
L
R
R
R
R
R
R
NC VSS VSS NC DQ35 DQ32 DQ29 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ29 DQ32 DQ35 NC VSS VSS NC
L
L
L
L
L
L
R
R
R
R
R
R
[
NC VSS VSS VSS CQ1L CQ1L
LOW PORT ZQ0L BUSY CNTI PORT NC CQ1R CQ1R VSS VSS VSS NC
4]
VSS
SPDL STD0
L
L
NTL STD1
L
D
E
F
NC
NC
NC VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI NC VSS VDDI NC
OL OL OL OL OL OL OR OR OR OR OR
NC
NC
NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R NC
OL OL OL OL OL RE RE RE RE OR OR OR OR OR
A0L A1L RETL BE2L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R A0R
OL OL OR OR
G
H
J
L
R
A2L A3L WRP BE3L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R WRP A3R A2R
OL OL OR OR
L
R
A4L A5L READ NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC READ A5R A4R
YL OL OL OR OR YR
[
A6L A7L ZQ1L NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI NC ZQ1R A7R A6R
4]
[4]
K
L
RE
RE
OR
A8L A9L
CL
OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R
RE RE
A10L A11L VSS NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC VSS A11R A10R
RE RE
M
N
A12L A13L ADSL NC VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC ADSR A13R A12R
OL RE RE
A14L A15L CNT BE1L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT A15R A14R
MSKL
OL
OL
OR
OR
MSK
R
P
R
T
A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R
NL OL OL OR OR NR
A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R
STL OL OL OR OR STR
L
R
NC
NC
NC
NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NC
NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR
NC
NC
NC
U
V
NC FTSE VDDI NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE NC
LL OL OL OL OL OL OR OR OR OR OR OR LR
NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO NC
[4]
EL STD1 NTR
R
R
STD0 SPDR
R
W
Y
NC
NC
NC
NC VSS VSS NC DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 NC TMS TCK NC
NC
NC
NC
L
L
L
R
R
R
NC
NC
NC
NC
NC
NC
NC DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 NC
NC
NC
NC
NC
NC
NC
AA
L
L
L
R
R
R
NC DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 NC
AB
L
L
R
R
Note:
8. Use this pinout only for device CYD36S36V18 of the FullFlex36 famiy.
Document #: 38-06082 Rev. *C
Page 4 of 48
PRELIMINARY
FullFlex
FullFlex18 SDR 484-ball BGA Pinout (Top View)[9]
20 21 22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
NC
NC
NC
NC
NC
NC
NC DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
L
L
R
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 NC
NC
NC
NC
NC
NC
NC
NC
NC
L
L
L
R
R
R
NC VSS VSS NC
NC DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 NC
NC VSS VSS NC
L
L
L
R
R
R
[
NC VSS VSS VSS CQ1L CQ1L
LOW PORT ZQ0L BUSY CNTI PORT NC CQ1R CQ1R VSS VSS VSS NC
4]
VSS
SPDL STD0
L
L
NTL STD1
L
D
E
F
NC
NC
NC VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI NC VSS VDDI NC
OL OL OL OL OL OL OR OR OR OR OR
NC
NC
NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R NC
OL OL OL OL OL RE RE RE RE OR OR OR OR OR
A0L A1L RETL BE1L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R A0R
OL OL OR OR
G
H
J
L
R
A2L A3L WRP NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC WRP A3R A2R
OL OL OR OR
L
R
A4L A5L READ NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC READ A5R A4R
YL OL OL OR OR YR
[
A6L A7L ZQ1L NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI NC ZQ1R A7R A6R
4]
[4]
K
L
RE
RE
OR
A8L A9L
CL
OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R
RE RE
A10L A11L VSS NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC VSS A11R A10R
RE RE
M
N
A12L A13L ADSL NC VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC ADSR A13R A12R
OL RE RE
A14L A15L CNT NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC CNT A15R A14R
MSKL
OL
OL
OR
OR
MSK
R
P
R
T
A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R
NL OL OL OR OR NR
A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R
STL OL OL OR OR STR
L
R
A20L NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NC A20R
NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR
U
V
NC
NC FTSE VDDI NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE NC
LL OL OL OL OL OL OR OR OR OR OR OR LR
NC
NC
NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS TDI TDO NC
NC
[4]
EL STD1 NTR
R
R
STD0 SPDR
R
W
Y
NC
NC
NC
NC VSS VSS NC
NC
NC
NC
NC
NC
NC
NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC
NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC
NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC
NC
NC
NC
NC
NC
NC
NC TMS TCK NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AA
AB
Note:
9. Use this pinout only for device CYD36S18V18 of the FullFlex18 famiy.
Document #: 38-06082 Rev. *C
Page 5 of 48
PRELIMINARY
FullFlex
FullFlex36 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R
A
B
C
D
E
F
DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R
[4]
DQ34L DQ35L
RETL
WRPL
CE0L
INTL
CQ1L
CQ1L VC_SEL TRST
MRST ZQ0R
VTTL VSS
CQ1R
CQ1R
INTR
RETR DQ35R DQ34R
A0L
A2L
A1L
A3L
VREF FTSELL LOWSP
DL
VSS
VTTL
LOWSP FTSELR VREF
DR
WRPR
CE0R
A1R
A3R
A0R
A2R
CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R
A4L
A5L
CNINTL BE3L VDDIOL
[4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIOR BE3R CNINTR
VSS VDDIOR BE2R BUSYR
A5R
A4R
A6L
A7L
BUSYL
CL
BE2L
ZQ0L
A7R
A6R
G
H
J
A8L
A9L
VTTL VCORE
VSS
VSS
VCORE VTTL
CR
A9R
A8R
A10L
A12L
A14L
A11L
A13L
A15L
VSS PORTST VCORE
D1L
VCORE PORTST VSS
D1R
A11R
A13R
A15R
A10R
A12R
A14R
A16R
OEL
BE1L VDDIOL
VSS VDDIOR BE1R
OER
K
L
ADSL
BE0L VDDIOL
VSS VDDIOR BE0R
ADSR
[11]
[11]
A16L A17L
[10]
R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R
M
N
P
R
T
[4]
[4]
[10]
A18L
NC
CNTMS VREF PORTST READYL ZQ1L
KL D0L
VTTL
TMS
VTTL ZQ1R
READY PORTST VREF CNTMS
NC
A18R
R
D0R
KR
DQ16L DQ17L CNTENL CNTRST CQ0L
L
CQ0L
DQ5L
DQ4L
TCK
TDO
DQ1R
DQ0R
TDI
CQ0R
CQ0R CNTRST CNTEN DQ17R DQ16R
R
R
DQ15L DQ13L DQ11L
DQ9L
DQ7L
DQ3L
DQ2L
DQ1L
DQ0L
DQ3R
DQ2R
DQ5R
DQ4R
DQ7R
DQ6R
DQ9R DQ11R DQ13R DQ15R
DQ14L DQ12L DQ10L
DQ8L
DQ6L
DQ8R DQ10R DQ12R DQ14R
Notes:
10. Leave this ball unconnected for CYD09S36V18 and CYD04S36V18.
11. Leave this ball unconnected for CYD04S36V18.
Document #: 38-06082 Rev. *C
Page 6 of 48
PRELIMINARY
FullFlex
FullFlex18 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
DQ17L DQ16L DQ13L DQ12L
DQ9L
DQ9R DQ12R DQ13R DQ16R DQ17R
NC
NC
NC
A
B
C
D
E
F
NC
NC
NC
NC
NC
RETL
WRPL
CE0L
CNINTL
BUSYL
CL
NC
DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R
[4]
NC
NC
RETR
WRPR
CE0R
CNINTR
BUSYR
CR
NC
NC
NC
NC
INTL
CQ1L
CQ1L VC_SEL TRST
MRST ZQ0R
VTTL VSS
CQ1R
CQ1R
INTR
A0L
A1L
A3L
A5L
VREF FTSELL LOWSP
DL
VSS
VTTL
LOWSP FTSELR VREF
DR
A1R
A3R
A5R
A7R
A9R
A11R
A13R
A15R
A17R
A0R
A2R
A4R
A6R
A8R
A10R
A12R
A14R
A16R
A2L
CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R
A4L
NC
NC
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIOR
VSS VDDIOR
NC
NC
[4]
A6L
A7L
A9L
A11L
A13L
A15L
A17L
ZQ0L
G
H
J
A8L
VTTL VCORE
VSS
VSS
VCORE VTTL
A10L
A12L
A14L
A16L
VSS PORTST VCORE
D1L
VCORE PORTST VSS
D1R
OEL
BE1L VDDIOL
VSS VDDIOR BE1R
OER
K
L
ADSL
BE0L VDDIOL
VSS VDDIOR BE0R
ADSR
R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR
M
N
P
R
T
[13]
[12]
[4]
[4]
[12]
[13]
A18L
A19L
CNTMS VREF PORTST READYL ZQ1L
KL D0L
VTTL
TMS
VTTL ZQ1R
READY PORTST VREF CNTMS A19R
A18R
R
D0R
KR
NC
NC
NC
NC
NC
NC
CNTENL CNTRST CQ0L
L
CQ0L
DQ5L
DQ4L
TCK
TDO
DQ1R
DQ0R
TDI
CQ0R
CQ0R CNTRST CNTEN
NC
NC
NC
NC
NC
NC
R
R
NC
NC
DQ6L
DQ2L
DQ3L
DQ1L
DQ0L
DQ2R
DQ3R
DQ5R
DQ4R
DQ6R
DQ7R
NC
NC
NC
DQ8L
DQ7L
DQ8R
NC
Notes:
12. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18.
13. Leave this ball unconnected for CYD04S18V18.
Document #: 38-06082 Rev. *C
Page 7 of 48
PRELIMINARY
FullFlex
Table 1. Selection Guide
-250[14, 15]
-200[14]
200
3.3
TBD
TBD
-167[14]
167
4.0
TBD
TBD
-133[14]
133
4.5
TBD
TBD
Unit
MHz
ns
mA
mA
fMAX
250
2.64
TBD
TBD
Max. Access Time (Clock to Data)
Typical Operating Current ICC
Typical Standby Current for ISB3 (Both Ports CMOS Level)
Pin Definitions
Left Port
0L–A20L
DQ0L–DQ71L
BE0L–BE7L
Right Port
A0R–A20R
DQ0R–DQ71R
BE0R–BE7R
Description
A
Address Inputs.[1]
Data Bus Input/Output.[2]
Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array.
BUSYL
BUSYR
Port Busy Output. When there is an address match and both chip enables are active
for both ports, an external BUSY signal is asserted on the fifth clock cycles from when
the collision occurs.
CL
CR
Clock Signal. Maximum clock input rate is fMAX
.
CE0L
CE1L
CQENL
CQ0L
CE0R
CE1R
CQENR
CQ0R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.
Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal
Output for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for
FullFlex18 devices.
CQ0L
CQ1L
CQ1L
CQ0R
CQ1R
CQ1R
Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted
Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock
Signal Output for DQ[8:0] for FullFlex18 devices.
Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal
Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9]
for FullFlex18 devices.
Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted
Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock
Signal Output for DQ[17:9] forFullFlex18 devices.
VIM Output Impedance Matching Input. To use, connect a calibrating resistor
between ZQ and ground. The resistor must be five times larger than the intended line
impedance driven by the dual-port. Assert HIGH to disable Variable Impedance
Matching.
[16]
[16]
ZQ[1:0]L
ZQ[1:0]R
OEL
INTL
OER
INTR
Output Enable Input. This asynchronous signal must be asserted LOW to enable the
DQ data pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INTL is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL
LowSPDR
Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation
at less than 100 MHz, assert this pin LOW.
[17]
[17]
PORTSTD[1:0]L
PORTSTD[1:0]R
Port Clock/Address/Control/Data/Echo Clock/ I/O Standard Select Input. Assert
these pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS,
and HIGH/HIGH for 1.8V LVCMOS, respectively. Connect these pins to a VTTL supply.
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the
dual-port memory array.
Notes:
14. SDR mode with two pipeline stages.
15. 250 MHz for HSTL and 1.8V LVCMOS I/O standards only
16. Leaving pins K3, K20 of the 484-ball BGA package and pin C10 of the 256-ball BGA package disables VIM.
17. For FullFlex72, pins D14 and W9 have an internal pull-down resistor.
Document #: 38-06082 Rev. *C
Page 8 of 48
PRELIMINARY
FullFlex
Pin Definitions (continued)
Left Port
READYL
Right Port
READYR
Description
Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable
Impedance Matching circuits have completed calibration. This is a wired OR capable
output.
CNT/MSKL
ADSL
CNTENL
CNTRSTL
CNTINTL
CNT/MSKR
ADSR
CNTENR
CNTRSTR
CNTINTR
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW one cycle before the
unmasked portion of the counter is incremented to all “1s”.
WRPL
RETL
WRPR
RETR
Port Counter Wrap Input. When the burst counter reaches the maximum count, on
the next counter increment WRP can be set LOW to load the unmasked counter bits
to 0 or set HIGH to load the counter with the value stored in the mirror register.
Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for
repeated access to the same segment of memory.
VREFL
VDDIOL
VREFR
VDDIOR
FTSELR
Port External HSTL I/O Reference Input.
Port Data I/O Power Supply.
FTSELL
Port Flow-Through Mode Select Input. Assert this pin LOW to select Flow-Through
mode. Assert this pin HIGH to select Pipeline mode.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A
MRST operation is required at power-up. This pin must be driven by a VDDIOL refer-
enced signal.
VC_SEL
TMS
Core Power Supply Select. Assert this pin LOW to select 1.8V Core operation. Assert
this pin HIGH to select 1.5V Core operation. This pin must be driven by a VTTL refer-
enced signal.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V
LVCMOS.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers. Operation for LVTTL or 2.5V LVCMOS.
TRST
TCK
JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.
JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Operation for LVTTL or 2.5V LVCMOS.
VSS
VCORE
VTTL
Ground Inputs.
Device Core Power Supply.
LVTTL Power Supply.
Selectable I/O Standard
Table 2. Port Standard Selection
The FullFlex families of devices also offer the option of
choosing one of four port standards for the device. Each port
can independently select standards from single-ended HSTL
class I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V
LVCMOS. The selection of the standard is determined by the
PORTSTD pins for each port. These pins should be connected
to either an LVTTL or 2.5V LVCMOS power suppy. This will
determine the input clock, address, control, data, and Echo
clock standard for each port as shown in Table 2.
PORTSTD1
VSS
PORTSTD0
VSS
I/O Standard
LVTTL
HSTL
2.5V LVCMOS
1.8V LVCMOS
VSS
VTTL
VTTL
VTTL
VSS
VTTL
Operating mode with different IO standards combined with
different core power supply will result in different maximum
speed as shown in Table 3.
Document #: 38-06082 Rev. *C
Page 9 of 48
PRELIMINARY
FullFlex
clock in the address and control signals for a read operation.
The dual-port retransmits the input clocks relative to the data
output. The buffered clocks are provided on the CQ1/CQ1 and
CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each
clock is associated with half the data bits. The output clock will
match the corresponding ports I/O configuration.
Table 3. Speed vs. I/O Standard and Pipeline Stages
Maximum
Core
Latency
Speed (MHz) Voltage (V)
I/O Standard
HSTL/1.8V LVCMOS
LVTTL/2.5V LVCMOS
HSTL/LVTTL
2.5V LVCMOS
1.8V LVCMOS
Cycles
250[15]
200
200
1.8
1.8
1.5
2
2
2
To enable Echo clock outputs, tie CQEN HIGH. To disable
Echo clock outputs, tie CQEN LOW.
Input Clock
Data Out
Clocking
Separate clocks synchronize the operations on each port.
Each port has one clock input C. In this mode, all the transac-
tions on the address, control, and data will be on the C rising
edge. All transactions on the address, control, data input,
output, and byte enables will occur on the C rising edge.
Echo Clock
Echo Clock
Figure 2. SDR Echo Clock Delay
Table 4. Data Pin Assignment
Deterministic Access Control
BE Pin Name
BE[7]
Data Pin Name
DQ[71:63]
DQ[62:54]
DQ[53:45]
DQ[44:36]
DQ[35:27]
DQ[26:18]
DQ[17:9]
Deterministic Access Control is provided for ease of design.
The circuitry detects when both ports are accessing the same
location and provides an external BUSY flag to the port on
which data may be corrupted. The collision detection logic
saves the address in conflict (Busy Address) to a readable
register. In the case of multiple collisions, the first Busy
address will be written to the Busy Address register.
If both ports are accessing the same location at the same time
and only one port is doing a write, if tCCS is met, then the data
being written to and read from the address is valid data. For
example, if the right port is reading and the left port is writing
and the left ports clock meets tCCS, then the data being read
from the address by the right port will be the old data. In the
same case, if the right ports clock meets tCCS, then the data
being read out of the address from the right port will be the new
data. In the above case, if tCCS is violated by the either ports
clock with respect to the other port and the right port gets the
external BUSY flag, the data from the right port is corrupted.
Table 5 shows the tCCS timing that must be met to guarantee
the data.
BE[6]
BE[5]
BE[4]
BE[3]
BE[2]
BE[1]
BE[0]
DQ[8:0]
Selectable Pipeline/Flow-Through Mode
To meet data rate and throughput requirements, the FullFlex
families offer selectable pipeline or flow-through mode. Echo
clocks are not supported in flow-through mode and the DLL
must be disabled.
Flow-Through mode is selected by the FTSEL pin. Strapping
this pin HIGH selects pipeline mode. Strapping this pin LOW
selects flow-through mode.
Table 6 shows that, in the case of the left port writing and the
right port reading, when an external BUSY flag is asserted on
the right port, the data read out of the device will not be
guaranteed.
DLL
The FullFlex familes of devices have an on-chip DLL. Enabling
the DLL reduces the clock to data valid time allowing more
set-up time for the receiving device. For operation below
100 MHz, the DLL must be disabled. This is selectable by
strapping LowSPD low. For information on DLL lock and reset
time, please see the Master Reset section below.
The value in the busy address register can be read back to the
address lines. The required input control signals for this
function are shown in Table 9. The value in the busy address
register will be read out to the address lines tCA after the same
amount of latency as a data read operation. After an initial
address match, the address under contention is saved in the
busy address register. All following address matches cause
the BUSY flag to be generated, however, none of the
addresses are saved into the busy address register. Once a
busy readback is performed, the address of the first match
which happens at least two clocks cycles after the busy
readback, is saved into the busy address register.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make providing accurate clock trees extremely
difficult. To counter this problem, the FullFlex families incor-
porate Echo Clocks. Echo Clocks are enabled on a per port
basis. The dual-port receives input clocks that are used to
Table 5. tCCS Timing for All Operating Modes
Port A—Early Arriving Port Port B—Late Arriving Port
tCCS
Mode
Active Edge
Mode
Active Edge
Unit
C Rise to Opposite C Rise Set-up Time for Non-corrupt Data
SDR
C
SDR
C
tCYC(min) – 1
ns
Document #: 38-06082 Rev. *C
Page 10 of 48
PRELIMINARY
FullFlex
Table 6. Deterministic Access Control Logic
Left Port Right Port Left Clock
Right Clock
BUSYL
BUSYR
Description
Read
Write
Read
Read
X
>tCCS
0
X
0
>tCCS
0
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
H
H
H
H
H
L
No Collision
Read OLD Data
Read NEW Data
Read OLD Data
Data Not Guaranteed
Read NEW Data
Data Not Guaranteed
Read NEW Data
Read OLD Data
Read NEW Data
Data Not Guaranteed
Read OLD Data
Data Not Guaranteed
Array Data Corrupted
Array Stores Right Port Data
Array Stores Left Port Data
<tCCS
0
<tCCS
H
L
Read
Write
Write
Write
>tCCS
0
<tCCS
0
>tCCS
0
H
H
H
H
H
H
L
0
<tCCS
0
0
>–tCCS & <tCCS
>tCCS
0
H
L
>tCCS
Table 8. Variable Impedance Matching Operation
RQ Connection Output Configuration
Variable Impedance Matching (VIM)
Each port contains a Variable Impedance Matching circuit to
set the impedance of the I/O driver to match the impedance of
the on-board traces. The impedance is set for all outputs
except JTAG and is done on a per port basis. To take
advantage of the VIM feature, connect a calibrating resistor
(RQ) that is five times the value of the intended line impedance
from the ZQ pin to VSS. The output impedance is then
adjusted to account for drifts in supply voltage and temper-
ature every 1024 clock cycles. If a port’s clock is suspended,
the VIM circuit will retain its last setting until the clock is
restarted where it will then resume periodic adjustment. In the
case of a significant change in device temperature or supply
voltage, the recalibration period is multiples of 1024 clock
cycles. A Master Reset will initialize the VIM circuitry. Table 7
shows the VIM parameters and Table 8 describes the VIM
operation modes.
100Ω - 275Ω to VSS Output Driver Impedance = RQ/5 ±
15% at Vout = VDDIO/2
ZQ to VDDIO
VIM Disabled. Rout < 20Ω at Vout =
VDDIO/2
Address Counter and Mask Register Operations[1]
Each port of the FullFlex family contains a programmable burst
address counter. The burst counter contains four registers: a
counter register, a mask register, a mirror register, and a busy
address register.
The counter register contains the address used to access the
RAM array. It is changed only by the master reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
In order to disable VIM, the ZQ pin must be connected to
VDDIO of the relative supply for the I/Os before a Master
Reset.
The mask register value affects the Counter Increment and
Counter Reset operations by preventing the corresponding
bits of the counter register from changing. It also affects the
counter interrupt output (CNTINT). The mask register is only
changed by Mask Reset, Mask Load, and MRST. The Mask
Load operation loads the value of the address bus into the
mask register. The mask register defines the counting range
of the counter register. It divides the counter register into two
or three consecutive regions. Zero or more “0s” define the
masked region and one or more “1s” define the unmasked
portion of the counter register. The counter register may only
be divided into up to three regions. The region containing the
least significant bits must be no more than two bits. Bits one
and zero may be “10” respectively, masking the least signif-
icant counter bit and causing the counter to increment by two
instead of one. If bits one and zero are “00”, the two least
significant bits are masked and the counter will increment by
four instead of one. For example, in the case of a 256Kx72
Table 7. Variable Impedance Matching Parameters
Parameter
RQ Value
Min. Max.
Unit
Ω
Tolerance
± 2%
100
275
Output Impedance
Reset Time
Update Time
20
55
Ω
± 15%
N/A
N/A
N/A 1024 Cycles
N/A 1024 Cycles
Document #: 38-06082 Rev. *C
Page 11 of 48
PRELIMINARY
FullFlex
configuration, a mask register value of 003FC divides the
mask register into three regions. With bit 0 being the least
significant bit and bit 17 being the most significant bit, the two
least significant bits are masked, the next eight bits are
unmasked, and the remaining bits are masked.
The mirror register is used to reload the counter register on
retransmit operations (see “retransmit” below) and wrap
functions (see “counter increment” below). The last value
loaded into the counter register is stored in the mirror register.
The mirror register is only changed by master reset (MRST),
Counter Reset, and Counter Load.
Table 9 summarizes the operations of these registers and the
required input control signals. All signals except MRST are
synchronized to the ports clock.
Counter Load Operation[1]
The address counter and mirror registers are both loaded with
the address value presented on the address lines. This value
ranges from 0 to 1FFFFF.
Mask Load Operation[1]
The mask register is loaded with the address value presented
on the address bus. This value ranges from 0 to 1FFFFF
though not all values permit correct increment operations.
Permitted values are in the form of 2n–1, 2n–2, or 2n–4. The
counter register can only be segmented in up to three regions.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s”, one or more “1s”, and
the least significant two bits can be “11”, “10”, or “00”. Thus
1FFFFE, 07FFFF, and 003FFC are permitted values but
02FFFF, 003FFA, and 07FFE4 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. The address will be valid tCA after the
selected number of latency cycles configured by FTSEL. The
data bus (DQ) is tri-stated on the cycle that the address is
presented on the address lines. Figure 3 shows a block
diagram of the operation.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. The address will be valid tCA after the selected
number of latency cycles configured by FTSEL. The data bus
(DQ) is tri-stated on the cycle that the address is presented on
the address lines. Figure 3 shows a block diagram of the
operation.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0”. All masked bits remain unchanged. A mask reset
followed by a counter reset will reset the counter and mirror
registers to 00000.
Mask Reset Operation
The mask register is reset to all “1s”, which unmasks every bit
of the burst counter.
Document #: 38-06082 Rev. *C
Page 12 of 48
PRELIMINARY
FullFlex
Table 9. Burst Counter and Mask Register Control Operation (Any Port) [18, 19]
C
MRST CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
X
L
X
X
X
X
X
Master Reset Reset address counter to all 0s, mask register
to all 1s, and BUSY address to all 0’s.
H
L
H
X
X
X
Counter Reset Reset counter and mirror unmasked portion to
all 0s.
H
H
L
L
X
L
X
L
X
X
Mask Reset
Reset mask register to all 1s.
H
H
Counter Load Load burst counter and mirror with external
address value presented on address lines.
H
H
L
L
L
X
Mask Load
Load mask register with value presented on the
address lines.
H
H
H
H
H
H
L
L
H
H
L
Retransmit
Load counter with value in the mirror register
H
Counter
Internally increment address counter value.
Increment
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
L
Counter Hold Constantly hold the address value for multiple
clock cycles.
Counter
Read out counter internal value on address
lines.
Readback
L
Mask
Read out mask register value on address lines.
Readback
L
H
Busy Address Read out last busy address
Readback
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
X
L
Reserved
Reserved
Reserved
Reserved
Reserved
L
H
L
H
L
H
H
H
L
Notes:
18. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
19. Counter operation and mask register operation is independent of chip enables.
Document #: 38-06082 Rev. *C
Page 13 of 48
PRELIMINARY
FullFlex
Increment Operation[1]
loaded. When the burst counter reaches its maximum value
set by the mask register, it wraps back to the initial value stored
in the mirror register as long as WRP is deasserted. The
unmasked counter bits will be loaded with “0” If WRP is
asserted. If the counter is configured to continuously be in
increment mode, it increments once again to the maximum
value and wraps back to the value initially stored in the mirror
register as long as WRP is deasserted. While RET is asserted
low, the counter will continue to wrap back to the value in the
mirror register independent of the state of WRP.
Once the address counter is initially loaded with an external
address, the counter can internally increment the address
value and address the entire memory array. Only the
unmasked bits of the counter register are incremented. In
order for a counter bit to change, the corresponding bit in the
mask register must be “1”. If the two least significant bits of the
mask register are “11”, the burst counter will increment by one.
If the two least significant bits are “10”, the burst counter will
increment by two, and if they are “00”, the burst counter will
increment by four. If all unmasked counter bits are incre-
mented to “1” and WRP is deasserted, the next increment will
wrap the counter back to the initially loaded value. The cycle
before an increment will result in the unmasked counter bits
being “1s”, a counter interrupt flag (CNTINT) is asserted if the
counter is continuously incrementing. The next increment will
cause the counter to reach its maximum value and the second
increment will return the counter register to its initial value
which was stored in the mirror register when WRP is
deasserted. When WRP is asserted, the second increment
after CNTINT is asserted will load the unmasked counter bits
with “0”. The example shown in Figure 4 shows an example of
the CYDD36S18V18 device with the mask register loaded with
a mask value of 00007F unmasking the seven least significant
bits. Setting the mask register to this value allows the counter
to access the entire memory space. The address counter is
then loaded with an initial value of 000005 assuming WRP is
deasserted. The masked bits, the seventh address through the
twenty-first address, do not increment in an increment
operation. The counter address will start at address 000005
and will increment its internal address value until it reaches the
mask register value of 00007F. The counter wraps around the
memory block to location 000005 at the next count. CNTINT
is issued when the counter reaches the maximum –1 count.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock
cycle before an increment operation that results in the
unmasked portion of the counter register being all “1s”. It is
deasserted by counter reset, counter load, mask reset, mask
load, and MRST.
Counting by Two
When the two least significant bits of the mask register are
“10,” the counter increments by two.
Counting by Four
When the two least significant bits of the mask register are
“00”, the counter increments by four.
Mailbox Interrupts
The upper two memory locations can be used for message
passing and permit communications between ports. Table 10
shows the interrupt operation for both ports. The highest
memory location is the mailbox for the right port and the
maximum address – 1 is the mailbox for the left port.
When one port Writes to the other port’s mailbox, the INT flag
of the port that the mailbox belongs to is asserted LOW. The
INT flag remains asserted until the mailbox location is read by
the other port. When a port reads its mailbox, the INT flag is
deasserted high after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
Table 10 shows that in order to set the INTR flag, a Write
operation by the left port to address 1FFFFF will assert INTR
LOW. A valid Read of the 1FFFFF location by the right port will
reset INTR HIGH after one cycle of latency with respect to the
right port’s clock. At least one byte enable has to be activated
to set or reset the mailbox interrupt.
Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Retransmit
Retransmit allows repeated access to the same block of
memory without the need to reload the initial address. An
internal mirror register stores the address counter value last
Document #: 38-06082 Rev. *C
Page 14 of 48
PRELIMINARY
FullFlex
CNT/MSK
CNTEN
A
Decode
Logic
CNTRST
RET
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
C
Load/Increment
21
21
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
21
Wrap
Register
21
21
21
From
Mask
From
Counter
Bit 0
and 1
+1
+2
+4
Wrap
Wrap
To
1
0
Detect
21
1
0
Counter
Figure 3. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06082 Rev. *C
Page 15 of 48
PRELIMINARY
FullFlex
CNTINT
H
Example:
Load
Counter-Mask
0
0
0s
1
1
1
1
1
1
1
0
Register = 00007F
220 219
26 25 24 23 22 21 20
Unmasked Address
27
Masked Address
Mask
Register
LSB
Load
Address
H
L
X
X
Xs
Xs
Xs
0
0
0
0
1
0
1
X
Counter = 000005
220 219
26 25 24 23 22 21 20
Address
Counter
LSB
27
27
27
Max
Address
Value
X
X
1
1
1
1
1 1
1
X
220 219
26 25 24 23 22 21 20
Max + 1
Address
Value
H
X
X
0
0
0
0
1
0
1
X
220 219
26 25 24 23 22 21 20
Figure 4. Programmable Counter-Mask Register Operation[1, 23]
Table 10.Interrupt Operation Example[1, 19, 20, 21, 22]
Left Port
A0L–21L
Right Port
A0R–21R
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
R/WL
CEL
L
INTL
X
R/WR
CER
X
INTR
L
H
X
X
L
X
X
H
Max. Address
X
H
L
X
X
X
L
X
X
X
L
H
L
L
X
Max. Address
Max. Address–1
X
Reset Left INTL Flag
Max. Address–1
X
Master Reset
to four outputs may be connected together. For faster
pull-down of the signal, connect a 250 Ohm resistor to VSS. If
the DLL and VIM circuits are disabled for a port, the port will
be operational within five clock cycles. However, the READY
will be asserted within 160 clock cycles.
The FullFlex family of Dual-Ports undergo a complete reset by
asserting MRST. The MRST can be asserted asynchronously
to the clocks and must remain asserted for at least tRS. Once
asserted MRST deasserts READY, initializes the internal burst
counters, internal mirror registers, and internal Busy
Addresses to zero, and initializes the internal mask register to
all “1s”. All mailbox interrupts (INT), Busy Address Outputs
(BUSY), and burst counter interrupts (CNTINT) are
deasserted upon master reset. Releasing MRST also signifies
that the power supplies and all port clocks are stable. This
begins calibration of the DLL and VIM circuits. READY will be
asserted within 1024 clock cycles. READY is a wired OR
capable output with a strong pull-up and weak pull-down. Up
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates
using JEDEC-standard 3.3V or 2.5V I/O logic levels depending
on the VTTL power supply. It is composed of four input
connections and one output connection required by the test
logic defined by the standard.
Notes:
20. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and
0
1
can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.
21. OE is “Don’t Care” for mailbox operation.
22. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
23. The “X” in this diagram represents the counter upper bits.
Document #: 38-06082 Rev. *C
Page 16 of 48
PRELIMINARY
FullFlex
Table 11.Identification Register Definitions
Table 12.Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Part Number
CYD36S72V18
CYD36S36V18
CYD36S18V18
CYD18S72V18
CYD18S36V18
CYD18S18V18
CYD09S72V18
CYD09S36V18
CYD09S18V18
CYD04S72V18
CYD04S36V18
CYD04S18V18
Configuration
512Kx72
1024Kx36
2048Kx36
256Kx72
512Kx36
1024Kx18
128Kx72
256Kx36
1024Kx18
64Kx72
Value
Bit Size
0C022069h
0C023069h
0C024069h
0C025069h
0C026069h
0C027069h
0C028069h
0C029069h
0C02A069h
0C02B069h
0C02C069h
0C02D069h
4
1
32
n[24]
128Kx36
256Kx18
Table 13.Instruction Identification Codes
Instruction Code
EXTEST
Description
0000
1111
1011
0111
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
IDCODE
HIGHZ
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers
to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note:
24. Details of the boundary scan length can be found in the BSDL file for the device.
Document #: 38-06082 Rev. *C
Page 17 of 48
PRELIMINARY
FullFlex
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. For user guide-
Range
Commercial
Ambient Temperature
VCORE
lines, not tested.)
0°C to +70°C
1.8V ± 100 mV
Storage Temperature ................................ –65°C to + 150°C
1.5V ± 80 mV
Ambient Temperature with
Industrial
–40°C to +85°C
1.8V ± 100 mV
1.5V ± 80 mV
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential.............. –0.5V to + 4.1V
Power Supply Requirements
DC Voltage Applied to
Outputs in High-Z State......................–0.5V to VCORE + 0.5V
Min.
Typ.
Max.
3.6V
2.7V
1.9V
1.9V
3.6V
2.7V
0.95V
DC Input Voltage............................... –0.5V to VCORE + 0.5V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage...........................................> 2200V
(JEDEC JESD8-6, JESD8-B)
LVTTL VDDIO
2.5V LVCMOS VDDIO
HSTL VDDIO
1.8V LVCMOS VDDIO
3.3V VTTL
3.0V
2.3V
1.4V
1.7V
3.0V
2.3V
0.68V
3.3V
2.5V
1.5V
1.8V
3.3V
2.5V
0.75V
Latch-up Current.....................................................> 200 mA
2.5V VTTL
HSTL VREF
Electrical Characteristics Over the Operating Range
-250[15]
-200
Parameter
VOH
Description
Configuration
Min.
Typ. Max.
Min.
2.4 [25]
Typ. Max. Unit
Output HIGH Voltage
LVTTL
2.4[25]
V
(VCORE=Min., IOH=-8 mA)
(VCORE=Min., IOH=-4 mA)
(VCORE=Min., IOH=-4 mA)
(VCORE=Min., IOH=-6 mA)
(VCORE=Min., IOH=-4 mA)
HSTL (DC)[26] VDDIO – 0.4[25]
HSTL (AC)[26] VDDIO – 0.5[25]
2.5V LVCMOS
1.8V LVCMOS VDDIO – 0.45[25]
LVTTL
VDDIO – 0.4[25]
VDDIO – 0.5[25]
1.7[25]
V
V
V
V
1.7[25]
VDDIO – 0.45[25]
VOL
Output HIGH Voltage
0.4[25]
0.4[25]
V
(VCORE=Min., IOL= 8 mA)
(VCORE=Min., IOL= 4 mA)
(VCORE=Min., IOL= 4 mA)
(VCORE=Min., IOL= 6 mA)
(VCORE=Min., IOL= 4 mA)
Input HIGH Voltage
HSTL (DC)[26]
HSTL (AC)[26]
2.5V LVCMOS
1.8V LVCMOS
0.4[25]
0.5[25]
0.7[25]
0.2[25]
0.4[25]
0.5[25]
0.7[25]
0.2[25]
VDDI
O +
0.3
V
V
V
V
V
VIH
LVTTL
2
VDDIO
+ 0.3
2
HSTL (DC)[26]
VREF + 0.1
VDDIO
+ 0.3
VREF + 0.1
VDDI
O +
0.3
V
HSTL (AC)[26]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VREF + 0.2
1.7
VREF + 0.2
1.7
V
V
V
V
V
1.26
–0.3
–0.3
1.26
–0.3
–0.3
VIL
Input LOW Voltage
0.8
VREF
– 0.1
VREF
– 0.2
0.8
VREF
– 0.1
VREF
– 0.2
HSTL (DC)[26]
HSTL (AC)[26]
V
2.5V LVCMOS
1.8V LVCMOS
0.7
0.36
0.7
0.36
V
V
Document #: 38-06082 Rev. *C
Page 18 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-250[15]
-200
Parameter
Description
Configuration
Min.
Typ. Max.
Min.
Typ. Max. Unit
READY
Output HIGH Voltage
LVTTL
2.7[25]
2.7[25]
V
VOH
(VCORE = Min., IOH = –24 mA)
(VCORE = Min., IOH = –12 mA) HSTL (DC)[26] VDDIO – 0.4[25]
(VCORE = Min., IOH = –12 mA) HSTL (AC)[26] VDDIO – 0.5[25]
VDDIO – 0.4[25]
VDDIO – 0.5[25]
2.0[25]
V
V
V
V
(VCORE = Min., IOH = –15 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –12 mA) 1.8V LVCMOS VDDIO – 0.45[25]
2.0[25]
VDDIO – 0.45[25]
READY
VOL
Output HIGH Voltage
LVTTL
0.4[25]
0.4[25]
V
(VCORE = Min., IO = 0.12 mA)
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS
(VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS
Output Leakage Current
HSTL (DC)
HSTL (AC)
0.4[25]
0.5[25]
0.7[25]
0.2[25]
10
0.4[25]
0.5[25]
0.7[25]
0.2[25]
10
V
V
V
V
µA
µA
IOZ
IIX1
–10
–10
–10
–10
Input Leakage Current Except
TDI, TMS, MRST
10
10
IIX2
IIX3
Input Leakage Current TDI,
TMS, MRST
Input Leakage Current
PORTSTD, DDRON,
VC_SEL
–300
–10
10
–300
–10
10
µA
300
300 µA
ICC
Operating Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
(VCORE = Max.,IOUT = 0 mA)
Outputs Disabled
64Kx72
128Kx36
256x18
Notes:
25. These parameters are met with VIM disabled.
26. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed.
Document #: 38-06082 Rev. *C
Page 19 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-250[15]
Typ. Max.
-200
Parameter
Description
Configuration
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max. Unit
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
ISB1
Standby Current
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
ISB2
Standby Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
ISB3
Standby Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
(Both Ports CMOS Level)
CEL and CER ≥ VCORE – 0.2V,
f = 0
64Kx72
128Kx36
256x18
Document #: 38-06082 Rev. *C
Page 20 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-250[15]
Typ. Max.
-200
Parameter
Description
Configuration
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max. Unit
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
ISB4
Standby Current
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
Electrical Characteristics Over the Operating Range
-167
-133
Parameter
VOH
Description
Configuration
Min.
2.4[25]
Typ. Max.
Min.
Typ. Max. Unit
Output HIGH Voltage
LVTTL
2.4 [25]
V
(VCORE = Min., IOH = –8 mA)
(VCORE = Min., IOH = –4 mA) HSTL (DC) VDDIO – 0.4[25]
(VCORE = Min., IOH = –4 mA) HSTL (AC) VDDIO – 0.5[25]
VDDIO – 0.4[25]
VDDIO – 0.5[25]
1.7[25]
V
V
V
V
(VCORE = Min., IOH = –6 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –4 mA) 1.8V LVCMOS VDDIO – 0.45[25]
1.7[25]
VDDIO – 0.45[25]
VOL
Output HIGH Voltage
LVTTL
0.4[25]
0.4[25]
V
(VCORE = Min., IOH = –8 mA)
(VCORE = Min., IOH = –4 mA) HSTL (DC)
(VCORE = Min., IOH = –4 mA) HSTL (AC)
(VCORE = Min., IOH = –6 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –4 mA) 1.8V LVCMOS
0.4[25]
0.5[25]
0.7[25]
0.2[25]
VDDIO
+ 0.3
VDDIO
+ 0.3
0.4[25]
0.5[25]
0.7[25]
0.2[25]
VDDIO
+ 0.3
VDDIO
+ 0.3
V
V
V
V
V
VIH
Input HIGH Voltage
Input LOW Voltage
LVTTL
2
2
HSTL (DC)
VREF + 0.1
VREF + 0.1
V
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VREF + 0.2
1.7
VREF + 0.2
1.7
V
V
V
V
V
1.26
–0.3
–0.3
1.26
–0.3
–0.3
VIL
0.8
VREF–
0.1
0.8
VREF–
0.1
HSTL (DC)
HSTL (AC)
VREF–
0.2
VREF–
0.2
V
2.5V LVCMOS
1.8V LVCMOS
0.7
0.36
0.7
0.36
V
V
Document #: 38-06082 Rev. *C
Page 21 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-167
-133
Parameter
Description
Configuration
Min.
Typ. Max.
Min.
Typ. Max. Unit
READY
Output HIGH Voltage
LVTTL
2.7[25]
2.7[25]
V
VOH
(VCORE = Min., IOH = –24 mA)
(VCORE = Min., IOH = –12 mA) HSTL (DC)[26] VDDIO – 0.4[25]
(VCORE = Min., IOH = –12 mA) HSTL (AC)[26] VDDIO – 0.5[25]
VDDIO – 0.4[25]
VDDIO – 0.5[25]
2.0[25]
V
V
V
V
(VCORE = Min., IOH = –15 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –12 mA) 1.8V LVCMOS VDDIO – 0.45[25]
2.0[25]
VDDIO – 0.45[25]
READY
VOL
Output HIGH Voltage
LVTTL
0.4[25]
0.4[25]
V
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min., IOL = 0.12 mA) HSTL (DC)
(VCORE = Min., IOL = 0.12 mA) HSTL (AC)
(VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS
(VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS
Output Leakage Current
0.4[25]
0.5[25]
0.7[25]
0.2[25]
10
0.4[25]
0.5[25]
0.7[25]
0.2[25]
10
V
V
V
V
µA
µA
IOZ
IIX1
–10
–10
–10
–10
Input Leakage Current
Except TDI,
10
10
TMS, MRST
IIX2
IIX3
Input Leakage Current TDI,
TMS, MRST
Input Leakage Current
PORTSTD, DDRON,
VC_SEL
–300
–10
10
–300
–10
10
µA
µA
300
300
ICC
Operating Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
(VCORE = Max., IOUT = 0 mA)
Outputs Disabled
64Kx72
128Kx36
256x18
Document #: 38-06082 Rev. *C
Page 22 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-167
-133
Parameter
ISB1
Description
Configuration
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max.
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max. Unit
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
ISB2
Standby Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
ISB3
Standby Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
(Both Ports CMOS Level)
CEL andCER ≥ VCORE–0.2V,
f = 0
64Kx72
128Kx36
256x18
Document #: 38-06082 Rev. *C
Page 23 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-167
-133
Parameter
ISB4
Description
Configuration
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024x18
128Kx72
256Kx36
512x18
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max.
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max. Unit
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
Standby Current
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
64Kx72
128Kx36
256x18
Table 14.Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
10
12
Unit
pF
pF
[27]
CIN
TA = °C, f = MHz,
VCORE = 3 dV[28]
[27, 29]
COUT
AC Test Load and Waveforms
V T H = 1 .5 V fo r L V T T L
V T H = 5 0 % V D D IO fo r 2 .5 V C M O S
V T H = 5 0 % V D D IO fo r 1 .8 V C M O S
= 0 V
V
R E F
V
R E F
5 0 O h m
5 0 O h m
O u tp u t
R E A D Y Z Q
T e s t P o in t
R = 2 5 0 O h m
V T H
D e v ic e u n d e r
te s t
C
= 1 0 p F
R Q = 2 5 0 O h m
Figure 5. Output Test Load for LVTTL/CMOS
V T H
=
5 0 % V D D I O
5 0 O h m
V
=
E F
0 . 7 5 V
R
V
R
E F
5 0 O h m
O u t p u t
R E A D Y Z Q
R = 2 5 0 O h m
T e s t P o i n t
V T H
C = 1 0 p F f o r S D R
D e v i c e u n d e r
t e s t
R Q = 2 5 0 O h m
Figure 6. Output Test Load for HSTL
Notes:
27. Capacitance for the 36M x18 device is 20 pF, capacitance for all other 36M or x18 devices is 12 pF.
28. Input and Output switch from 0V to 3V or from 3V to 0V.
29. C also references to C
.
out
I/O
Document #: 38-06082 Rev. *C
Page 24 of 48
PRELIMINARY
FullFlex
Switching Characteristics Over the Operating Range
Table 15.SDR Mode with DLL Enabled (LOWSPD-HIGH)[32]
-250[15}
-200
Max.
-167
Max.
-133
Min.
Parameter
Description
Min.
100
Max.
250
Min.
100
Min.
100
Max. Unit
133 MHz
f
MAX (PIPELINED) Maximum Operating Frequency
200
167
100
for Pipelined mode
Maximum Operating Frequency
[33]
fMAX
100
77
66.7
55.6 MHz
10.00 ns
ns
(FLOW-THROUGH) for Flow-through mode
tCYC (PIPELINED) C Clock Cycle Time for Pipelined 4.00
10.00
5.00
10.00
6.00
10.00
7.00
mode
tCYC
C Clock Cycle Time for
10.00
45
13.00
15.00
18.00
(FLOW-THROUGH) Flow-through mode
tCKD C Clock Duty Time
tSD
tHD
55
45
55
45
55
45
55
%
ns
ns
ns
Data Input Set-up Time to C Rise 1.20[31]
Data Input Hold Time after C Rise 0.50[31]
1.50[31]
0.50[31]
1.50
1.70[31]
0.50[31]
1.70
1.80[31]
0.50[31]
1.80
tSAC
Address & Control Input Setup
1.20
Time to C Rise
tHAC
tOE
Address & Control Input Hold
Time after C Rise
Output Enable to Data Valid
OE to Low Z
0.50
0.50
0.60
0.70
ns
3.40[31]
4.40[31]
5.00[31]
5.50[31] ns
ns
[30]
tOLZ
tOHZ
tCD1
1.00
1.00
1.00
1.00
[30]
OE to High Z
1.00[31] 3.40[31] 1.00[31] 4.40[31] 1.00[31] 5.00[31] 1.00[31] 5.50[31] ns
C Rise to DQ Valid for
Flow-through Mode
(LowSPD = 1)
7.20
9.00
11.00
13.00 ns
4.50[31] ns
13.00 ns
tCD2
C Rise to DQ Valid for Pipelined
2.64[31]
3.30[31]
4.00[31]
mode
(LowSPD = 1)
tCA1
tCA2
tDC
tCCQ
tCQHQV
C Rise to Address Readback
7.20
4.00
9.00
5.00
11.00
6.00
Valid for flow-through mode
C Rise to Address Readback
Valid for pipelined mode
DQ Output Hold after C Rise
C Rise to CQ Rise
7.50
ns
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
2.64
0.70[31]
3.30
0.76[31]
4.00
0.80[31]
4.50
Echo Clock (CQ) High to Output
0.90[31] ns
Valid
tCQHQX
Echo Clock (CQ) High to Output –0.66
Hold
–0.72
1.00
1.00
–0.76
1.00
1.00
–0.90
1.00
1.00
ns
13.00 ns
ns
[30]
tCKHZ1
C Rise to DQ Output High Z in
1.00
7.20
9.00
11.00
Flow-Through Mode
[30]
tCKLZ1
C Rise to DQ Output Low Z in
Flow-Through Mode
1.00
[30]
tCKHZ2
C Rise to DQ Output High Z in
1.00[31] 2.64[31] 1.00[31] 3.30[31] 1.00[31] 4.00[31] 1.00[31] 4.50[31] ns
Pipelined Mode
[30]
tCKLZ2
C Rise to DQ Output Low Z in
Pipelined Mode
1.00
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
tAC
Address Output Hold after C Rise 1.00
Notes:
30. Parameters specified with the load capacitance in Figure 5 and Figure 6.
31. For the x18 devices, add 200 ps to this parameter in the table above.
32. Test conditions assume a signal transition time of 2 V/ns.
33. Flow-Through Mode operates at this frequency regardless of DLL being enabled or disabled
Document #: 38-06082 Rev. *C
Page 25 of 48
PRELIMINARY
Table 15.SDR Mode with DLL Enabled (LOWSPD-HIGH)[32] (continued)
FullFlex
-250[15}
-200
Max.
-167
Max.
-133
Min.
Parameter
tCKHZA1
Description
Min.
Max.
Min.
Min.
Max. Unit
13.00 ns
[30]
C Rise to Address Output High Z 1.00
7.20
1.00
9.00
1.00
11.00
1.00
for Flow-Through Mode
[30]
tCKHZA2
C Rise to Address Output High Z 1.00
for Pipelined Mode
C Rise to Address Output Low Z 1.00
C Rise to CNTINT Low
C Rise to CNTINT High
C Rise to INT Low
4.00
1.00
5.00
1.00
6.00
1.00
7.50
ns
[30]
tCKLZA
tSCINT
tRCINT
tSINT
1.00
1.00
1.00
0.50
0.50
1.00
1.00
1.00
1.00
0.50
0.50
1.00
1.00
1.00
1.00
0.50
0.50
1.00
ns
ns
ns
ns
ns
ns
1.00
1.00
0.50
0.50
1.00
2.64
2.64
6.00
6.00
2.64
3.30
3.30
7.00
7.00
3.30
4.00
4.00
8.00
8.00
4.00
4.50
4.50
8.50
8.50
4.50
tRINT
tBSY
C Rise to INT High
C Rise to BUSY Valid
Table 16. SDR Mode with DLL Disabled (LOWSPD-LOW)[32]
-100
Parameter
Description
Min.
Max.
Unit
f
MAX (PIPELINED)
Maximum Operating Frequency for Pipelined mode
100
55.6
10.00
MHz
MHz
ns
ns
%
fMAX (FLOW-THROUGH)[33] Maximum Operating Frequency for Flow-through mode
tCYC (PIPELINED)
C Clock Cycle Time for Pipelined mode
C Clock Cycle Time for Flow-through mode
C Clock Duty Time
Data Input Set-up Time to C Rise
Data Input Hold Time after C Rise
Address & Control Input Setup Time to C Rise
Address & Control Input Hold Time after C Rise
Output Enable to Data Valid
OE to Low Z
OE to High Z
C Rise to DQ Valid for Flow-through Mode (LowSPD = 0)
C Rise to DQ Valid for Pipelined mode (LowSPD = 0)
C Rise to Address Readback Valid for flow-through mode
C Rise to Address Readback Valid for pipelined mode
DQ Output Hold after C Rise
7.00
18.00
45
tCYC (FLOW-THROUGH)
tCKD
tSD
tHD
55
1.80[31]
0.50[31]
1.80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSAC
tHAC
tOE
tOLZ
tOHZ
tCD1
tCD2
tCA1
tCA2
tDC
tCCQ
tCQHQV
tCQHQX
tCKHZ1
tCKLZ1
0.70
5.50[31]
[30]
1.00
[30]
1.00[31] 5.50[31]
13.00
6.00[31]
13.00
7.50
1.00
1.00
C Rise to CQ Rise
6.00
Echo Clock (CQ) High to Output Valid
Echo Clock (CQ) High to Output Hold
C Rise to DQ Output High Z in Flow-through Mode
C Rise to DQ Output Low Z in Flow-Through Mode
C Rise to DQ Output High Z in Pipelined Mode
C Rise to DQ Output Low Z in Pipelined Mode
Address Output Hold after C Rise
C Rise to Address Output High Z for Flow-Through mode
C Rise to Address Output High Z for Pipelined mode
C Rise to Address Output Low Z
0.90[31]
–0.90
1.00
1.00
[30]
13.00
[30]
tCKHZ2
1.00[31] 6.00[31]
[30]
[30]
tCKLZ2
tAC
tCKHZA1
tCKHZA2
tCKLZA
tSCINT
tRCINT
1.00
1.00
[30]
[30]
1.00
1.00
1.00
1.00
1.00
13.00
7.50
[30]
C Rise to CNTINT Low
C Rise to CNTINT High
4.50
4.50
Document #: 38-06082 Rev. *C
Page 26 of 48
PRELIMINARY
Table 16. SDR Mode with DLL Disabled (LOWSPD-LOW)[32]
FullFlex
-100
Parameter
Description
Min.
0.50
0.50
1.00
Max.
Unit
ns
ns
tSINT
tRINT
tBSY
C Rise to INT Low
C Rise to INT High
C Rise to BUSY Valid
8.50
8.50
4.50
ns
Master Reset Timing
-250[15]
-200
-167
-133
Parameter
tPUP
tRS
Description
Power-Up Time
Master Reset Pulse Width
Master Reset Recovery Time
Master Reset to Outputs Inactive/Hi Z
Master Reset Release to Port Ready
C Rise to Port Ready
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ms
cycles
cycles
ns
1
5
5
1
5
5
1
5
5
1
5
5
tRSR
tRSF
tRDY
10
1024
8
10
1024
9.5
10
1024
11
10
[34]
[35]
1024 cycles
13
tCORDY
ns
Table 17.JTAG Timing
-250[15]
-200
-167
-133
Parameter
Description
JTAG TAP Controller Frequency
TCK Cycle Time
TCK High Time
Min.
Max.
20
Min.
Max.
20
Min.
Max.
20
Min.
Max.
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fJTAG
tTCYC
tTH
50
20
20
10
10
10
10
50
20
20
10
10
10
10
50
20
20
10
10
10
10
50
20
20
10
10
10
10
tTL
TCK Low Time
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
tJXZ
TMS Set-up to TCK Rise
TMS Hold to TCK Rise
TDI Set-up to TCK Rise
TDI Hold to TCK Rise
TCK Low to TDO Valid
TCK Low to TDO Invalid
TCK Low to TDO High Z
TCK Low to TDO Active
10
10
10
10
0
0
0
0
15
15
15
15
15
15
15
15
tJZX
Notes:
34. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250-Ohm resistor to VSS.
35. Add this propagation delay after t
for all Master Reset Operations.
RDY
Document #: 38-06082 Rev. *C
Page 27 of 48
PRELIMINARY
FullFlex
Switching Waveforms
JTAG Timing
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Master Reset[34]
~
V
CORE
t
t
RS
PUP
~
~
MRST
C
t
t
RDY
CORDY
~
~
READY
t
RSF
All Address
& Data
t
RSR
All Other
Inputs
~
Document #: 38-06082 Rev. *C
Page 28 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ Cycle for Pipelined Mode
t
CYC
C
CE
OE
t
t
HAC
SAC
R/W
A
A
A
A
A
A
A
A
n
n+1
x
n+2
n
n+3
n+4
n+5
n+6
2 pipeline stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+4
x-1
n+1
n+2
n+3
DQ
t
DC
t
CD2
WRITE Cycle for Pipelined and Flow-Through Modes
t
CYC
C
CE
R/W
A
A
A
A
A
A
A
n+6
A
n
n+1
n+2
n+3
n+4
n+5
2 pipeline stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+6
n
n+1
n+2
n+3
n+4
n+5
DQ
tSD tHD
Document #: 38-06082 Rev. *C
Page 29 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ with Address Counter Advance for Pipelined Mode
t
CYC
C
A
A
n
Internal
A
A
n+1
A
A
n
n+2
n+3
Address
ADS
CNTEN
DQ
DQ
DQ
DQ
DQ
n+1
x-1
x
n
DQ
DQ
n+3
n+2
READ with Address Counter Advance for Flow-Through Mode
tCYC
C
tSAC tHAC
A
An
ADS
CNTEN
DQ
tSAC tHAC
tCD1
DQx
DQn
DQn + 1
DQn + 2
DQn + 3
DQn + 4
tDC
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ W ITH COUNTER
Document #: 38-06082 Rev. *C
Page 30 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Port-to-Port WRITE–READ for Pipelined Mode
t
CYC
Left Port
C
L
A
AL
n
R/WL
DQL
DQ
n
Right Port
t
CCS
C
R
t
CYC
AR
A
n
R/WR
DQR
t
t
SAC HAC
DQ
n
t
t
DC
CD2
Chip Enable READ for Pipelined Mode
t
CYC
C
CE0
CE1
R/W
A
t
t
SAC HAC
A
A
A
A
A
A
A
n+6
n
n+1
n+2
n+3
n+4
n+5
DQ
DQ
DQ
n+3
n
t
t
DC
t
CD2
CKLZ2
Document #: 38-06082 Rev. *C
Page 31 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
OE Controlled WRITE for Pipelined Mode
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
tOHZ
DQ
x+1
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x-1
x
n
n+1
n+2
OE Controlled WRITE for Flow-Through Mode
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
tOHZ
DQ
x+2
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x
x+1
n
n+1
n+2
Document #: 38-06082 Rev. *C
Page 32 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Byte-Enable READ for Pipelined Mode
tCYC
C
A
A
A
A
n
n+1
n+2
n+3
A
R/W
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
tCKLZ2
tCKHZ2
DQn+1(63:71)
DQ
63:71
DQn+1(54:62)
DQ
DQ
DQ
54:62
DQn+2(45:53)
DQn+2(36:44)
45:53
36:44
DQn+1(27:35)
DQ
DQ
27:35
DQn+2(18:26)
18:26
DQn+3(9:17)
DQ
9:17
0:8
DQn+3(0:8)
DQ
Document #: 38-06082 Rev. *C
Page 33 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Port-to-Port WRITE-to-READ for Flow-Through Mode
CL
R/WL
tSAC
tHAC
tHD
NO MATCH
AL
MATCH
tSD
VALID
DQL
tCCS
CR
tCD1
R/W R
tHAC
tSAC
NO MATCH
AR
MATCH
tCD1
DQR
VALID
VALID
tDC
tDC
Busy Address Readback for Pipelined and Flow-Through Modes[36]
t
CYC
~
~
C
Internal
Address
Amatch+2
Amatch+3
Amatch+4
BUSY
~
~
CNTEN
ADS
~
~
External
Address
Amatch
tAC
tCA
Note:
36. A
is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy
match
Address Readback.”
Document #: 38-06082 Rev. *C
Page 34 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read Cycle for Flow-Through Mode
tCYC
C
CE0
CE1
tSAC tHAC
BEn
R/W
tSAC
tHAC
A
An
An + 1
An + 2
An + 3
tCKHZ1
tCD1
tDC
DQ
DQn
DQn + 1
tOHZ
DQn + 2
tCKLZ1
tDC
tOLZ
OE
tOE
READ-to-WRITE for Pipelined Mode (OE = VIL)[37,38,39]
tCYC
tCL
C
tCH
A
A
x
A
A
n+2
n
A
R/W
DQ
n+1
tSAC tHAC
tSAC tHAC
t
CKLZ2
DQ
DQ
DQ
x
DQ
x-2
tCD2
x-1
DQ
n+2
DQ
n+1
n
tDC
tCKHZ2
tSD tHD
Notes:
37. When OE = V , the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data.
IL
38. Two dummy writes should be issued to accomplish bus turnaround. The 3rd instruction is the first valid write.
39. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption.
Document #: 38-06082 Rev. *C
Page 35 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ-to-WRITE for Pipelined Mode (OE Controlled)[40,41]
tCYC
C
A
A
A
A
A
A
A
n+3
x
x+1
x+2
n
n+1
n+2
A
tSAC tHAC
R/W
OE
DQ
tOHZ
tSD tHD
DQ
DQ
x
DQ
DQ
DQ
DQ
DQ
n+3
x-2
x-1
n
n+1
n+2
Notes:
40. OE should be deasserted and t
allowed to elapse before the first write operation is issued.
OHZ
41. Any write scheduled to complete after OE is deasserted will be preempted.
Document #: 38-06082 Rev. *C
Page 36 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read-to-Write-to-Read for Flow-Through Mode (OE = LOW)
tCYC
C
tSAC tHAC
CE0
CE1
BEn
R/W
tSAC
tHAC
A
An
An + 1
An + 2
An + 2
An + 3
An + 4
tSD
tHD
DQIN
DQn + 2
tCD1
tCD1
tCD1
tCD1
DQn
tDC
DQOUT
DQn + 1
DQn + 3
tCKHZ1
tCKLZ1
tDC
READ
NOP
WRITE
READ
Document #: 38-06082 Rev. *C
Page 37 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read-to-Write-to-Read for Flow-Through Mode (OE Controlled)
tCYC
C
tHAC
tSAC
CE0
CE1
BEn
tHAC
tSAC
R/W
A
An
An + 1
An + 2
tHD
An + 3
An + 4
An + 5
tSD
DQIN
DQn + 2
DQn + 3
tOE
tCD1
tCD1
tDC
tCD1
DQOUT
DQn
DQn + 4
tDC
tCKLZ1
tOHZ
OE
READ
WRITE
READ
Document #: 38-06082 Rev. *C
Page 38 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Violates tCCS. (Flag Both
Ports)
Port A
C
A
R/W
BUSY
C
tBSY
tBSY
< tCCS
Port B
A
R/W
tBSY
tBSY
BUSY
BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Meets tCCS. (Flag Losing
Port)
Losing Port
C
A
R/W
tccs
tBSY
BUSY
tBSY
Winning Port
C
A
Match
R/W
BUSY
Document #: 38-06082 Rev. *C
Page 39 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read with Echo Clock for Pipelined and Flow-Through Modes (CQEN = HIGH)
C
t
t
HAC
SAC
R/W
A
A
A
A
A
A
A
A
n
n+1
n+2
n+3
n+4
n+5
n+6
CQ0
CQ0
CQ1
t
CCQ
CQ1
DQ
t
CQHQX
t
CQHQV
DQ
DQ
DQ
DQ
DQ
n+4
DQ
DQ
x
n
n+1
n+2
n+3
x-1
Document #: 38-06082 Rev. *C
Page 40 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Mailbox Interrupt Output
tCYC
C
L
AMAX
AL
R/WL
DQL
INTR
tSINT
tRINT
C
R
AMAX
AR
R/WR
DQMAX
DQR
Document #: 38-06082 Rev. *C
Page 41 of 48
PRELIMINARY
FullFlex
Ordering Information
512K
×
72 (36 Mbit) 1.8V Synchronous CYD36S72V18 Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
200 CYD36S72V18-200BBC
167 CYD36S72V18-167BBC
CYD36S72V18-167BBI
133 CYD36S72V18-133BBC
CYD36S72V18-133BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
256K
×
72 (18 Mbit) 1.8V Synchronous CYD18S72V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
250 CYD18S72V18-250BBC
200 CYD18S72V18-200BBC
CYD18S72V18-200BBI
167 CYD18S72V18-167BBC
CYD18S72V18-167BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
128K
×
72 (9 Mbit) 1.8V Synchronous CYD09S72V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
250 CYD09S72V18-250BBC
200 CYD09S72V18-200BBC
CYD09S72V18-200BBI
167 CYD09S72V18-167BBC
CYD09S72V18-167BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
64K
× 72 (4 Mbit) 1.8V Synchronous CYD04S72V18 Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
250 CYD04S72V18-250BBC
200 CYD04S72V18-200BBC
CYD04S72V18-200BBI
167 CYD04S72V18-167BBC
CYD04S72V18-167BBI
BY484
BY484
BY484
BY484
BY484
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
1024K
×
36 (36 Mbit) 1.8V Synchronous CYD36S36V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
200 CYD36S36V18-200BBC
167 CYD36S36V18-167BBC
CYD36S36V18-167BBI
133 CYD36S36V18-133BBC
CYD36S36V18-133BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
Document #: 38-06082 Rev. *C
Page 42 of 48
PRELIMINARY
FullFlex
Ordering Information (continued)
512K
×
36 (18 Mbit) 1.8V Synchronous CYD18S36V18 Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
250 CYD18S36V18-250BBC
200 CYD18S36V18-200BBC
CYD18S36V18-200BBI
167 CYD18S36V18-167BBC
CYD18S36V18-167BBI
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
256K
×
36 (9 Mbit) 1.8V Synchronous CYD09S36V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
Package Type
250 CYD09S36V18-250BBC
200 CYD09S36V18-200BBC
CYD09S36V18-200BBI
167 CYD09S36V18-167BBC
CYD09S36V18-167BBI
BB256
BB256
BB256
BB256
BB256
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
128K
× 36 (4 Mbit) 1.8V Synchronous CYD04S36V18 Dual-Port SRAM
Speed
Package
Operating
(MHz)
Ordering Code
Name
Package Type
Range
250 CYD04S36V18-250BBC
200 CYD04S36V18-200BBC
CYD04S36V18-200BBI
167 CYD04S36V18-167BBC
CYD04S36V18-167BBI
BB256
BB256
BB256
BB256
BB256
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
2048K
×
18 (36 Mbit) 1.8V Synchronous CYD36S18V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
200 CYD36S18V18-200BBC
167 CYD36S18V18-167BBC
CYD36S18V18-167BBI
133 CYD36S18V18-133BBC
CYD36S18V18-133BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
1024K
×
18 (18 Mbit) 1.8V Synchronous CYD18S18V18 Dual-Port SRAM
Package
Speed
Operating
Range
MHz)
Ordering Code
Name
Package Type
250 CYD18S18V18-250BBC
200 CYD18S18V18-200BBC
CYD18S18V18-200BBI
167 CYD18S18V18-167BBC
CYD18S18V18-167BBI
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
Document #: 38-06082 Rev. *C
Page 43 of 48
PRELIMINARY
FullFlex
Ordering Information (continued)
512K
×
18 (9 Mbit) 1.8V Synchronous CYD09S18V18 Dual-Port SRAM
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
BB256
BB256
Package Type
250 CYD09S18V18-250BBC
200 CYD09S18V18-200BBC
CYD09S18V18-200BBI
167 CYD09S18V18-167BBC
CYD09S18V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256K
×
18 (4 Mbit) 1.8V Synchronous CYD04S18V18 Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
BB256
BB256
Package Type
250 CYD04S18V18-250BBC
200 CYD04S18V18-200BBC
CYD04S18V18-200BBI
167 CYD04S18V18-167BBC
CYD04S18V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
Document #: 38-06082 Rev. *C
Page 44 of 48
PRELIMINARY
FullFlex
Package Diagrams
256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES
ꢀ0.05
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
51-85108-*F
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.70 MAX.
A
Document #: 38-06082 Rev. *C
Page 45 of 48
PRELIMINARY
FullFlex
Package Diagrams (continued)
256 FBGA (19 x 19 x 1.7 mm) BW256C
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.50 (256 X)
1
3
PIN A1 CORNER
13
13
1
9
11
15
15
11
9
8
5
5
3
7
7
12
14
16
16
14
12
2
6
10
10
6
2
4
8
4
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
1.00 (REF)
-B-
15.00 (REF)
19.00 +/- 0.10
-A-
0.15(4X)
Package Weight - 1.1 grams
Jedec Outline - Design Guide 4.14
-C-
SEATING PLANE
001-00915-*A
Document #: 38-06082 Rev. *C
Page 46 of 48
PRELIMINARY
FullFlex
Package Diagrams (continued)
484-ball PBGA (23 mm x 23 mm x 2.03 mm) BY484
Ø0.50~Ø0.70(484X)
PIN #1 CORNER
9
1
11
7
3
1
3
5
7
9
21
20 22
13
5
11
13 15 17 19
10 12 14 16 18
21
17 15
19
2
4
6
8
22 20 18 16 14 12 10
8
6
4
2
Ø1.00(3X) REF.
A
B
A
B
C
C
D
E
D
E
F
F
G
H
J
G
H
J
K
K
L
L
M
N
P
M
N
P
R
R
T
T
U
V
U
V
W
Y
W
Y
AA
AB
AA
AB
1.00
-B-
21.00
3.20*45°(4x)
20.00 REF.
-A-
23.00 0.20
0.20(4X)
30° TYP.
Package Weight - 2.0 grams
Jedec Outline - Design Guide 4.14
-C-
SEATING PLANE
51-85218-**
FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are
trademarks of their respective holders.
Document #: 38-06082 Rev. *C
Page 47 of 48
PRELIMINARY
FullFlex
Document History Page
Document Title: FullFlex™ Synchronous SDR Dual-Port SRAM
Document Number: 38-06082
Issue
Date
302411 See ECN
Orig. of
Change
YDT
REV.
**
ECN NO.
Description of Change
New data sheet
*A
334036 See ECN
YDT
Corrected typo on page 1
Reproduced PDF file to fix formatting errors
*B
395800 See ECN
SPN
Added statement about no echo clocks for flow-through mode
Updated electrical characteristics
Added note 16 and 17 (1.5V timing)
Added note 33 (timing for x18 devices)
Updated input edge rate (note 34)
Updated table 5 on deterministic access control logic
Added description of busy readback in deterministic access control section
Changed dummy write descriptions
Updated ZQ pins connection details
Updated note 24, B0 to BE0
Added power supply requirements to MRST and VC_SEL
Added note 4 (VIM disable)
Updated supply voltage to ground potential to 4.1V
Updated parameters on table 15
Updated and added parameters to table 16
Updated x72 pinout to SDR only pinout
Updated 484 PBGA pin diagram
Updated the pin definition of MRST
Updated the pin definition of VC_SEL
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated minimum VOH value for the 1.8V LVCMOS configuration
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added Note 33
Added Note 34
Removed Notes 15 and 17
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Removed -100 Speed bin from Table.1 Selection Guide
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD18S18V18 parts
Updated the Package Type for the CYD18S36V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow-Through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Updated Figure 5 and Figure 6
Updated Electrical Characteristics for READY VOH and READY V
Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-Through Mode
*C
402238 SEE ECN
KGH
Updated AC Test Load and Waveforms
Included FullFlex36 SDR 484-ball BGA Pinout (Top View)
Included FullFlex18 SDR 484-ball BGA Pinout (Top View)
Included Timing Parameter tCORDY
Document #: 38-06082 Rev. *C
Page 48 of 48
相关型号:
CYD36S18V18-167BBI
Dual-Port SRAM, 2MX18, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S18V18-167BGC
Dual-Port SRAM, 2MX18, 11ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S18V18-167BGXC
Dual-Port SRAM, 2MX18, 4ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484
CYPRESS
CYD36S18V18-200BBC
Dual-Port SRAM, 2MX18, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S18V18-200BGC
Dual-Port SRAM, 2MX18, 9ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S36V18-133BBI
Dual-Port SRAM, 1MX36, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S36V18-167BBI
Dual-Port SRAM, 1MX36, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
CYD36S36V18-167BBXI
Dual-Port SRAM, 1MX36, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484
CYPRESS
CYD36S36V18-167BGC
Dual-Port SRAM, 1MX36, 11ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
CYPRESS
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