CYD18S72V-100BBI [CYPRESS]
FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM; FLEx72 3.3V 64K / 128K / 256K X 72同步双端口RAM
| 型号： | CYD18S72V-100BBI |
| 厂家： | 
CYPRESS |
| 描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| 文件： | 总26页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
FLEx72™ 3.3V 64K/128K/256K x 72
Synchronous Dual-Port RAM
Functional Description
Features
• True dual-ported memory cells that allow simultaneous
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location
in memory. The result of writing to the same location by more
than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal set-up and
hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
access of the same memory location
• Synchronous pipelined operation
• Family of 4-Mbit, 9-Mbit and 18-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
—Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 484-ball FBGA (1 mm pitch)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
The CYD18S72V device have limited features. Please see
“Address Counter and Mask Register Operations[16]” on
page 6 for details.
• Seamless Migration to Next Generation Dual Port
Family
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details
Table 1. Product Selection Guide
Density
4-Mbit
9-Mbit
18-Mbit
(64K x 72)
CYD04S72V
167
(128K x 72)
(256K x 72)
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
CYD09S72V
CYD18S72V
167
4.0
270
133
5.0
410
4.0
225
484-ball FBGA
484-ball FBGA
484-ball FBGA
23mm x 23mm
23mm x 23mm
23mm x 23mm
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-06069 Rev. *D
Revised June 23, 2004
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
.
Logic Block Diagram[1]
FTSEL
L
FTSEL
R
CONFIG Block
CONFIG Block
PORTST[1:0]
L
PORTST[1:0]
R
DQ [71:0]
R
DQ[71:0]
L
BE [7:0]
R
BE [7:0]
L
CE0
CE0
R
L
L
IO
Control
IO
Control
CE1
CE1
R
OE
R
OE
L
R/W
R/W
R
L
Dual Ported Array
Arbitration Logic
BUSY
BUSY
L
R
A [17:0]
A [17:0]
L
L
R
R
CNT/MSK
CNT/MSK
ADS
ADS
R
L
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
L
RET
R
CNTINT
L
CNTINT
R
C
L
C
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
MRST
READY
RESET
LOGIC
READY
L
R
LowSPD
R
LowSPD
L
Note:
1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
Document #: 38-06069 Rev. *D
Page 2 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Pin Configuration
484-ball BGA
Top View
CYD04S72V / CYD09S72V / CYD18S72V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
DQ6
DQ5
DQ5
DQ5
DQ5
DQ4
DQ4
DQ4
DQ3
DQ3
DQ3
DQ3
DQ4
DQ4
DQ4
DQ5
DQ5
DQ5
DQ5
DQ6
NC
A
1L
9L
7L
4L
1L
8L
5L
2L
9L
6L
6R
9R
2R
5R
8R
1R
4R
7R
9R
1R
DQ6
3L
DQ6
2L
DQ6
0L
DQ5
8L
DQ5
5L
DQ5
2L
DQ4
9L
DQ4
6L
DQ4
3L
DQ4
0L
DQ3
7L
DQ3
7R
DQ4
0R
DQ4
3R
DQ4
6R
DQ4
9R
DQ5
2R
DQ5
5R
DQ5
8R
DQ6
0R
DQ6
2R
DQ6
3R
B
C
DQ6
5L
DQ6
4L
VSS
VSS
DQ5
6L
DQ5
3L
DQ5
0L
DQ4
7L
DQ4
4L
DQ4
1L
DQ3
8L
DQ3
8R
DQ4
1R
DQ4
4R
DQ4
7R
DQ5
0R
DQ5
3R
DQ5
6R
VSS
VSS
DQ6
4R
DQ6
5R
DQ6
7L
DQ6
6L
VSS
VSS
VSS
NC
NC
REV
LOW
SPD
POR
TST
NC
BUS
[2, 5]
CNTI
POR
TST
REV
NC
NC
VSS
VSS
VSS
DQ6
6R
DQ6
7R
[2, 5]
[2, 5]
[2,4]
L
[2, 5]
[2,4]
R
[2, 5]
[2, 5]
YL
NTL
[10]
[2,4]
L
D0L
[2,4]
D1L
[2, 5]
D
DQ6
9L
DQ6
8L
VDD
IOL
VSS
CE0
VSS
VDD
IOL
VDD
IOL
VDD
IOL
VDDI VDDI
VTT
L
VTT
L
VTTL VDDI
OR
VDD
IOR
VDD
IOR
VDD
IOR
NC
VSS
CE0
VDD
IOR
DQ6
8R
DQ6
9R
OL
OL
E
F
DQ7
1L
DQ7
0L
CE1
VDD
IOL
VDD
IOL
VDD
IOL
VDD
IOL
VDDI
OL
VCO
RE
VCO
RE
VCO
RE
VCO
RE
VDDI
OR
VDD
IOR
VDD
IOR
VDD
IOR
VDD
IOR
CE1
DQ7
0R
DQ7
1R
[8]
L
[9]
L
[9]
R
[8]
R
A0L
A1L
RET
BE4
L
VDD
IOL
VDD
IOL
VRE
[2, 4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VRE
[2, 4]
VDD
IOR
VDD
IOR
BE4
R
RET
A1R
A0R
[2,3]
L
[2,3]
R
FL
FR
G
H
A2L
A4L
A3L
A5L
WRP
BE5
L
VDD
IOL
VDD
IOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
IOR
VDD
IOR
BE5
R
WRP
A3R
A5R
A2R
A4R
[2,3]
L
[2,3]
R
REA
BE6
L
VDD
IOL
VDD
IOL
VDD
IOR
VDD
IOR
BE6
R
REA
DYL
[2, 5]
DYR
[2, 5]
J
A6L
A8L
A7L
A9L
NC
CL
BE7
L
VTT
L
VCO
RE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCO
RE
VDD
IOR
BE7
R
NC
CR
A7R
A9R
A6R
A8R
K
L
OEL
VTT
L
VCO
RE
VCO
RE
VTT
L
OER
A10L A11L
REV
BE3
L
VTT
L
VCO
RE
VCO
RE
VTT
L
BE3
R
REV
A11
R
A10
R
[2,4]
L
[2,4]
R
M
N
A12L A13L ADS
BE2
L
VDD
IOL
VCO
RE
VCO
RE
VTT
L
BE2
R
ADS
A13
R
A12
R
[9]
L
[9]
R
A14L A15L CNT/
MSK
BE1
L
VDD
IOL
VDD
IOL
VDD
IOR
VDD
IOR
BE1
R
CNT/
MSK
A15
R
A14
R
[8]
L
[8]
R
P
R
T
A16L A17L
CNT
BE0
L
VDD
IOL
VDD
IOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
IOR
VDD
IOR
BE0
R
CNT
A17
A16
[6]
[7]
ENL
[9]
ENR
[9]
R
R
[7]
[6]
A18L
[2,5]
NC
CNT
RST
INTL
VDD
IOL
VDD
IOL
VRE
VRE
VDD
IOR
VDD INTR CNT
NC
A18
FL
FR
IOR
RST
R
[8]
L
[2, 4]
[2, 4]
[8]
[2,5]
R
DQ3
5L
DQ3
4L
R/W
L
REV
VDD
IOL
VDD
IOL
VDD
IOL
VDD
IOL
VDDI
OL
VCO
RE
VCO
RE
VCO
RE
VCO
RE
VDDI
OR
VDD
IOR
VDD
IOR
VDD
IOR
VDD
IOR
REV
R/W
R
DQ3
4R
DQ3
5R
[2,4]
L
[2,4]
R
U
V
DQ3
3L
DQ3
2L
FTS
VDD
IOL
NC
VDD
IOL
VDD
IOL
VDD
IOL
VDDI VTTL
OL
VTT
L
VTT
L
VDDI VDDI
VDD
IOR
VDD
IOR
VDD
IOR
TRS
VDD
IOR
FTS
DQ3
2R
DQ3
3R
[2,5]
T
ELL
[2,3]
OR
OR
ELR
[2,3]
DQ3
1L
DQ3
0L
VSS
VSS
MRS
T
VSS
NC
NC
REV
POR
TST
CNTI
BUS
[2, 5]
NC
POR
TST
LOW
SPD
REV
NC
NC
VSS
TDI
TDO
TCK
DQ3
0R
DQ3
1R
[2, 5]
[2, 5]
[2,4]
L
[2, 5]
[2,4]
R
[2, 5]
[2, 5]
NTR
[10]
YR
[2,4]
R
D1R
[2, 5]
D0R
[2,4]
W
Y
DQ2
9L
DQ2
8L
VSS
DQ2
0L
DQ1
7L
DQ1
4L
DQ1
1L
DQ8
L
DQ5
L
DQ2
L
DQ2
R
DQ5
R
DQ8
R
DQ1
1R
DQ1
4R
DQ1
7R
DQ2
0R
TMS
DQ2
8R
DQ2
9R
DQ2
7L
DQ2
6L
DQ2
4L
DQ2
2L
DQ1
9L
DQ1
6L
DQ1
3L
DQ1
0L
DQ7
L
DQ4
L
DQ1
L
DQ1
R
DQ4
R
DQ7
R
DQ1
0R
DQ1
3R
DQ1
6R
DQ1
9R
DQ2
2R
DQ2
4R
DQ2
6R
DQ2
7R
A
A
NC
DQ2
5L
DQ2
3L
DQ2
1L
DQ1
8L
DQ1
5L
DQ1
2L
DQ9
L
DQ6
L
DQ3
L
DQ0
L
DQ0
R
DQ3
R
DQ6
R
DQ9
R
DQ1
2R
DQ1
5R
DQ1
8R
DQ2
1R
DQ2
3R
DQ2
5R
NC
A
B
2. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales
3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for a 64K x 72 configuration.
7. Leave this ball unconnected for 128K x 72 and 64K x72 configurations.
8. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO.
9. These balls are not applicable for CYD18S72V device. They need to be tied to VSS.
10. These balls are not applicable for CYD18S72V device. They need to be no connected.
Document #: 38-06069 Rev. *D
Page 3 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Pin Definitions
Left Port
Right Port
Description
Address Inputs.
A0L–A17L
A0R–A17R
Byte Enable Inputs. Asserting these signals enables Read and Write opera-
BE0L–BE7L
BE0R–BE7R
tions to the corresponding bytes of the memory array.
[2,5]
[2,5]
Port Busy Output. When the collision is detected, a BUSY is asserted.
BUSYL
BUSYR
Input Clock Signal.
CL
CR
[9]
[9]
Active Low Chip Enable Input.
CE0L
CE0R
[8]
[8]
Active High Chip Enable Input.
CE1L
CE1R
Data Bus Input/Output.
DQ0L–DQ71L
OEL
DQ0R–DQ71R
OER
Output Enable Input. This asynchronous signal must be asserted LOW to
enable the DQ data pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications
between ports. The upper two memory locations can be used for message
passing. INTL is asserted LOW when the right port writes to the mailbox location
of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
INTL
INTR
Port Low Speed Select Input. When operating at less than 100 MHz, the
[2,4]
[2,4]
LowSPDL
LowSPDR
LowSPD disables the port DLL.
[2,4,5]
[2,4,5]
Port Address/Control/Data I/O Standard Select Input.
PORTSTD[1:0]L
R/WL
PORTSTD[1:0]R
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read
from the dual port memory array.
Port Ready Output. This signal will be asserted when a port is ready for normal
[2,5]
[2,5]
READYL
READYR
operation.
[8]
[8]
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
CNT/MSKL
CNT/MSKR
[9]
[9]
ADSL
ADSR
[9]
[9]
CNTENL
CNTENR
[8]
[8]
CNTRSTL
CNTRSTR
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
[10]
[10]
CNTINTL
CNTINTR
portion of the counter is incremented to all “1s”.
Port Counter Wrap Input. After the burst counter reaches the maximum count,
if WRP is low, the unmasked counter bits will be set to 0. If high, the counter
will be loaded with the value stored in the mirror register.
Port Counter Retransmit Input. Counter control input.
[2,3]
[2,3]
WRPL
WRPR
[2,3]
[2,3]
RETL
RETR
Flow-Through Select. Use this pin to select Flow-Through mode. When is
[2,3]
[2,3]
FTSELL
FTSELR
de-asserted, the device is in pipelined mode.
[2,5]
[2,5]
Port External High-Speed IO Reference Input.
VREFL
VREFR
Port IO Power Supply.
VDDIOL
VDDIOR
REV[2,4]
REV[2,4]
Reserved pins for future features.
L
R
Master Reset Input. MRST is an asynchronous input signal and affects both
MRST
ports. A master reset operation is required at power-up.
TRST[2,5]
TMS
JTAG Reset Input.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state
machine. State machine transitions occur on the rising edge of TCK.
Document #: 38-06069 Rev. *D
Page 4 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Pin Definitions (continued)
Left Port
Right Port
Description
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
TDI
registers.
JTAG Test Clock Input.
TCK
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK.
TDO is normally three-stated except when captured data is shifted out of the
JTAG TAP.
TDO
Ground Inputs.
VSS
VCORE
VTTL
Core Power Supply.
LVTTL Power Supply.
Master Reset
write operation by the left port to address 3FFFF will assert
INTR LOW. At least one byte has to be active for a write to
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INTR HIGH. At least one byte has to be
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port. Table 2.shows that in order to set the INTR flag, a
Table 2. Interrupt Operation Example [1, 11, 12, 13]
Left Port
Right Port
Function
R/WL
CEL
A0L–17L
INTL
R/WR
CER
A0R–17R
INTR
Set Right INTR Flag
L
L
3FFFF
X
X
X
X
L
Reset Right INTR Flag
Set Left INTL Flag
X
X
H
X
X
L
X
X
X
L
H
L
L
L
X
3FFFF
3FFFE
X
H
X
X
Reset Left INTL Flag
3FFFE
H
X
Note:
11. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of
0
1
the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0 or BE7 must be LOW.
Document #: 38-06069 Rev. *D
Page 5 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Table 3. Address Counter and Counter Mask Register Control Operation (Any Port) [14,15 ]
CLK
MRST CNT/MSK CNTRST ADS CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
H
Operation undefined
Note:
14. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
15. Counter operation and mask register operation is independent of chip enables.
Address Counter and Mask Register Operations[16]
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
This section describes the features only apply to 4Mbit and
9Mbit devices, not to 18Mbit device. Each port have a
programmable burst address counter. The burst counter
contains three registers: a counter register, a mask register,
and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Counter Load Operation
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1)
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
Document #: 38-06069 Rev. *D
Page 6 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
will wrap the counter back to the initially loaded value. If an
Retransmit
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[17] An increment that results
in one or more of the unmasked bits of the counter being “0”
will de-assert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values,
but 1F0FF, 003FC, and 00000 are not.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
x72 devices as a 144-bit single port SRAM in which the
counter of one port counts even addresses and the counter of
the other port counts odd addresses. This even-odd address
scheme stores one half of the 144-bit data in even memory
locations, and the other half in odd memory locations.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Notes:
16. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF.
The CYD18S72V has 18 address bits and a maximum address value of 3FFFF.
17. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06069 Rev. *D
Page 7 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
17
Wrap
Register
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Wrap
To
1
0
Detect
17
1
0
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06069 Rev. *D
Page 8 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1 1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 18]
IEEE 1149.1 Serial Boundary Scan (JTAG)[19]
Boundary Scan Hierarchy for FLEx72 Family
Internally, the CYD04S72V and CYD09S72V have two DIEs
while CYD18S72V have four DIEs. Each DIE contains all the
circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain
of each DIE is connected serially to form the scan chain of the
FLEx72 family as shown in Figure 3. TMS and TCK are
connected in parallel to each DIE to drive all 4 TAP controllers
in unison. In many cases, each DIE will be supplied with the
same instruction. In other cases, it might be useful to supply
different instructions to each DIE. One example would be
testing the device ID of one DIE while bypassing the others.
Each pin of FLEx72 family is typically connected to multiple
DIEs. For connectivity testing with the EXTEST instruction, it
is desirable to check the internal connections between DIEs
as well as the external connections to the package. This can
be accomplished by merging the netlist of the devices with the
netlist of the user’s circuit board. To facilitate boundary scan
testing of the devices, Cypress provides the BSDL file for each
DIE, the internal netlist of the device, and a description of the
device scan chain. The user can use these materials to easily
integrate the devices into the board’s boundary scan
environment. Further information can be found in the Cypress
application note Using JTAG Boundary Scan For System In a
Package (SIP) Dual-Port SRAMs.
The FLEx72 incorporates an IEEE 1149.1 serial boundary
scan test access port (TAP). The TAP controller functions in a
manner that does not conflict with the operation of other
devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
FLEx72 family and may be performed while the device is
operating. An MRST must be performed on the FLEx72 after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the FLEx72 in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
Notes:
18. The “X” in this diagram represents the counter upper bits.
19. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document #: 38-06069 Rev. *D
Page 9 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
18 Mbit
4 Mbit/9 Mbit
TDO
TDO
TDO
D4
TDO
TDO
D2
D2
TDI
TDI
TDI
TDO
D3
TDO
D1
TDO
D1
TDI
TDI
TDI
TDI
TDI
Figure 3. Scan Chain
Table 4. Identification Register Definitions
Instruction Field
Revision Number(31:28)
Cypress Device(27:12)
Value
0h
C002h
Description
Reserved for version number
Defines Cypress DIE number for CYD18S72V and
CYD09S72V.
C001h
034h
1
Defines Cypress DIE number for CYD04S72V
Allows unique identification of FLEx72 family device vendor
Indicates the presence of an ID register
Cypress JDEC ID(11:1)
ID Register Presence (0)
Table 5. Scan Registers Sizes
Register Name
Instruction
Bit Size
4
Bypass
1
Identification
Boundary Scan
32
n [20]
Table 6. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
Code
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note:
20. See details in the device BSDL files
Document #: 38-06069 Rev. *D
Page 10 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
DC Input Voltage .............................. –0.5V to VDD + 0.5V[22]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
Maximum Ratings [21]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground Potential.............. –0.5V to + 4.6V
Ambient
DC Voltage Applied to
Range
Temperature
VDD
VCORE
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
Commercial
0°C to +70°C
3.3V
1.8V
± 165 mV ± 100 mV
Industrial
–40°C to +85°C
3.3V
1.8V
± 165 mV ± 100mV
Electrical Characteristics Over the Operating Range
-167
-133
-100
Parameter
VOH
Description
Output HIGH Voltage (VDD = Min., IOH= –4.0
Part No.
Min. Typ. Max. Min. Typ. Max. Min.
Typ
Max Unit
2.4
2.4
2.0
2.4
2.0
V
mA)
VOL
Output LOW Voltage (VDD = Min., IOL= +4.0
mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS,
0.4
0.4
0.4
V
VIH
VIL
IOZ
IIX1
2.0
V
V
µA
µA
0.8
10
10
0.8
10
10
0.8
10
10
–10
–10
–10
–10
-10
-10
MRST
IIX2
ICC
Input Leakage Current TDI, TMS, MRST
–0.1
1.0
300
–0.1
1.0
300
-0.1
1.0
mA
mA
Operating Current
CYD04S72V
225
225
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
CYD09S72V
CYD18S72V
410
90
580
115
315
450
mA
mA
ISB1
ISB2
ISB3
ISB4
ISB5
ICORE
Standby Current
CYD04S72V
90
160
55
115
210
75
(Both Ports TTL Level)
CYD09S72V
CEL and CER ≥ VIH, f = fMAX
Standby Current
CYD04S72V
CYD09S72V
160
55
210
75
mA
mA
mA
mA
mA
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports CYD04S72V
CMOS Level) CEL and CER
DD – 0.2V, f = 0
≥
CYD09S72V
V
Standby Current
CYD04S72V
CYD09S72V
160
210
160
210
75
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Operating Current
CYD18S72V
75
0
(VDDIO=Max,Iout=0mA,f=0)
Outputs Disabled
Core Operating Current for (VDD = Max.,IOUT
0
0
0
0
0
= 0 mA), Outputs Disabled
Capacitance [23]
Part#
Parameter
CIN
COUT
CIN
COUT
Description
Input Capacitance
Output Capacitance
Input Capacitance
Output Capacitance
Test Conditions
Max.
20
Unit
CYD04S72V
TA = 25°C, f = 1 MHz,
pF
pF
pF
pF
CYD09S72V
V
DD = 3.3V
10[24]
40
CYD18S72V
20
Note:
21. The voltage on any input or I/O pin can not exceed the power pin during power-up.
22. Pulse width < 20 ns.
23.
C
also references C
OUT I/O
Document #: 38-06069 Rev. *D
Page 11 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590 Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435 Ω
VTH = 1.5V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
-133
-100
CYD04S72V
CYD04S72V
CYD09S72V
CYD09S72V
CYD18S72V
CYD18S72V
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max
Min.
Max
Unit
fMAX2
Maximum Operating
167
133
133
100
MHz
Frequency
tCYC2
tCH2
tCL2
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock Rise Time
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.4
3.4
10
4.5
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[25]
tR
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
[25]
tF
Clock Fall Time
tSA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
Address Set-up Time
Address Hold Time
Byte Select Set-up Time
Byte Select Hold Time
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
2.2
1.0
2.2
1.0
NA
NA
2.2
1.0
2.2
1.0
NA
NA
NA
NA
NA
2.7
1.0
2.7
1.0
NA
NA
2.7
1.0
2.7
1.0
NA
NA
NA
NA
NA
R/W Hold Time
Input Data Set-up Time
Input Data Hold Time
ADS Set-up Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
Document #: 38-06069 Rev. *D
Page 12 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
-167
-133
-100
CYD04S72V
CYD04S72V
CYD09S72V
CYD09S72V
CYD18S72V
CYD18S72V
Parameter
tHRST
tSCM
Description
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Min.
0.6
2.3
Max.
Min.
0.6
2.5
Max.
Min.
NA
NA
Max
Min.
NA
NA
Max
Unit
ns
ns
tHCM
0.6
0.6
NA
NA
ns
ns
ns
ns
ns
tOE
4.0
4.4
5.5
5.5
[26, 27]
tOLZ
tOHZ
0
0
0
0
0
0
0
0
[26, 27]
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
5.5
5.0
NA
NA
5.5
5.2
NA
NA
tCD2
tCA2
tCM2
ns
ns
Clock to Mask Register
Readback Valid
tDC
Data Output Hold After Clock
HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
1.0
1.0
1.0
1.0
ns
[26, 27]
tCKHZ
tCKLZ
tSINT
tRINT
tSCINT
tRCINT
0
4.0
4.0
6.7
6.7
5.0
5.0
0
4.4
4.4
7.5
7.5
5.7
5.7
0
4.7
4.7
7.5
7.5
NA
NA
0
5.0
5.0
10
10
NA
NA
ns
ns
ns
ns
ns
ns
[26, 27]
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
5.7
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
Master Reset Set-up Time
Master Reset Recovery Time
5.0
6.0
5.0
5.0
6.0
5.0
5.0
6.0
5.0
5.0
8.5
5.0
cycles
ns
cycles
ns
tRSS
tRSR
tRSF
Master Reset to Outputs
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
Inactive
tRSCNTINT
Master Reset to Counter
Interrupt Flag Reset Time
ns
Notes:
24. Except INT and CNTINT which are 20pF
25. Except JTAG signal (tr and tf < 10ns max)
26. This parameter is guaranteed by design, but is not production tested
27. Test conditions used are Load 2
Document #: 38-06069 Rev. *D
Page 13 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
JTAG Timing Characteristics
CYD04S72V
CYD09S72V
CYD18S72V
-167/-133/-100
Parameter
Description
Maximum JTAG TAP Controller Frequency
Min.
Max.
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
fJTAG
tTCYC
tTH
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
100
40
40
10
10
10
10
tTL
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
30
ns
ns
0
Switching Waveforms
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-06069 Rev. *D
Page 14 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Master Reset
MRST
tRS
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
CNTINT
INT
TDO
Read Cycle[11, 28, 29, 30, 31]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE7
R/W
tSW
tSA
tHW
tHA
ADDRESS
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
DATAOUT
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes:
28. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
29. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
30. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
31. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document #: 38-06069 Rev. *D
Page 15 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Bank Select Read[32, 33]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Read-to-Write-to-Read (OE = LOW)[31, 34, 35, 36, 37]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+2
tSD tHD
Dn+2
An+3
ADDRESS
DATAIN
tSA
tHA
tCD2
tDC
tCKHZ
Qn
DATAOUT
WRITE
NO OPERATION
READ
Notes:
32. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
33. ADS = CNTEN= BE0 – BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
34. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
35. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
36. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
37. CE = BE0 – BE7 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06069 Rev. *D
Page 16 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[31, 34, 36, 37]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Read with Address Counter Advance[36]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06069 Rev. *D
Page 17 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance [37]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
ADDRESS
Document #: 38-06069 Rev. *D
Page 18 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Counter Reset [38, 39]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
D0
tSD
DATAIN
tCD2
tCD2
[51]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
READ
COUNTER
RESET
WRITE
ADDRESS 0
READ
READ
ADDRESS Am
ADDRESS 0
ADDRESS 1
ADDRESS An
Notes:
38. CE = BE0 – BE7= LOW; CE = MRST = CNT/MSK = HIGH.
0
1
39. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06069 Rev. *D
Page 19 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[40, 41, 42, 43]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A17
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
ADDRESS
Notes:
40. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
41. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
42. Address in input mode. Host can drive address bus after t
.
CKHZ
43. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06069 Rev. *D
Page 20 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[44, 45, 46]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
L_PORT
An
ADDRESS
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
An
ADDRESS
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes:
44. CE = OE = ADS = CNTEN = BE0 – BE7 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
45. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data will be Read out.
CCS
46. If t
If t
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock.
CCS
CCS
CYC2
CD2
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CYC2
CD2
Document #: 38-06069 Rev. *D
Page 21 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Switching Waveforms (continued)
Counter Interrupt and Retransmit[47, 48, 49, 50, 51]
tCYC2
tCH2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
1FFFE
tSCINT
1FFFC
Last_Loaded
1FFFD
1FFFF
tRCINT
Last_Loaded +1
CNTINT
Notes:
47. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
48. CNTINT is always driven.
49. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
50. The mask register assumed to have the value of 1FFFFh.
51. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06069 Rev. *D
Page 22 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Mailbox Interrupt Timing[52,53,54,55,56]
tCYC2
tCH2
tCL2
CLKL
tSA tHA
3FFFF
L_PORT
An+1
An
An+2
ADDRESS
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
Am+1
3FFFF
Am+3
Am+4
ADDRESS
Table 7. Read / Write and Enable Operation (Any Port) [1,14,57,58,59]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
DQ0 – DQ71
Operation
X
H
X
X
High-Z
Deselected
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
Deselected
Write
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes:
52. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
53. Address “1FFFF” is the mailbox location for R_Port.
54. L_Port is configured for Write operation, and R_Port is configured for Read operation.
55. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
56. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
57. OE is an asynchronous input signal.
58. When CE changes state, deselection and Read happen after one cycle of latency.
59. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document #: 38-06069 Rev. *D
Page 23 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Ordering Information
256K
× 72 (18Mb) 3.3V Synchronous CYD18S72V Dual-Port SRAM
Speed
Ordering Code
Package
Package Type
Operating Range
Commercial
Commercial
Industrial
(MHz)
Name
133
100
CYD18S72V-133BBC
CYD18S72V-100BBC
CYD18S72V-100BBI
BB484
BB484
BB484
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
128K
×
72 (9Mb) 3.3V Synchronous CYD09S72V Dual-Port SRAM
167
CYD09S72V-167BBC
CYD09S72V-133BBC
CYD09S72V-133BBI
BB484
BB484
BB484
484-ball Grid Array
Commercial
Commercial
Industrial
23mm x 23mm with 1.0mm pitch (FBGA)
133
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
64K x 72 (4Mb) 3.3 Synchronous CYD04S72V Dual-Port SRAM
167
CYD04S72V-167BBC
CYD04S72V-133BBC
CYD04S72V-133BBI
BB484
BB484
BB484
484-ball Grid Array
Commercial
Commercial
Industrial
23mm x 23mm with 1.0mm pitch (FBGA)
133
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
484-ball Grid Array
23mm x 23mm with 1.0mm pitch (FBGA)
Document #: 38-06069 Rev. *D
Page 24 of 26
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Package Diagram
484-ball FBGA (23 mm × 23 mm × 1.9 mm) BB484
51-85124-*D
FLEx72 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-06069 Rev. *D
Page 25 of 26
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYD04S72V
CYD09S72V
CYD18S72V
PRELIMINARY
Document History Page
Document Title: FLEx72™ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
Document Number: 38-06069
Issue
Date
06/17/03
Orig. of
REV.
**
*A
ECN NO.
125859
128707
Change Description of Change
SPN
SPN
New Data Sheet
08/01/03
Added -133 speed bin
Updated spec values for ICC, tHA, HB, HW, HD
t
t
t
Added new parameter ICC1
Added bank select read and read to write to read (OE=low) timing diagrams
*B
128997
09/18/03
SPN
Updated spec values for tOE, OHZ, CH2, CL2, HA, HB, HW, HD, CC, SB5, SA,
tSB, SW, SD, CD2
Updated read to write (OE=low) timing diagram
t
t
t
t
t
t
t
I
I
t
t
t
t
Updated Master Reset values for tRS, tRSR, RSF
t
Updated pinout
Updated VCORE voltage range
*C
*D
129936
233830
09/30/03
See ECN
SPN
Updated Package Diagram
Updated tCD2 value on first page
Removed Preliminary Status
WWZ
Added 4M and 9M x72 devices into the datasheet with updated pinout, pin
description table, power table, and timing table.
Changed the title and Added back Preliminary status to reflect the addition
of 4M and 9M devices.
Removed FLEX72-E word from the document.
Added counter related functions for 4M and 9M.
Removed standard JTAG description.
Updated block diagram.
Updated pinout with FTSEL and one more PORTSTD pins per port.
Updated tRSF of CYD18S72V value.
Document #: 38-06069 Rev. *D
Page 26 of 26
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