CYD18S36V18-200BBAC [CYPRESS]
Dual-Port SRAM, 512KX36, 3.3ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256;
| 型号： | CYD18S36V18-200BBAC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 512KX36, 3.3ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256 时钟 静态存储器 内存集成电路 |
| 文件： | 总52页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FullFlex
FullFlex™ Synchronous SDR Dual Port SRAM
Features
Functional Description
■ True dual port memory enables simultaneous access to the
shared array from each port
The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,
9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static
RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two
ports are provided, enabling simultaneous access to the array.
Simultaneous access to a location triggers deterministic access
control. For FullFlex72 these ports operate independently with
72-bit bus widths and each port is independently configured for
two pipelined stages. Each port is also configured to operate in
pipelined or flow through mode.
■ Synchronous pipelined operation with Single Data Rate (SDR)
operation on each port
❐ SDR interface at 200 MHz
❐ Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)
■ Selectable pipelined or flow-through mode
■ 1.5V or 1.8V core power supply
The advanced features include the following:
■ Commercial and Industrial temperature
■ IEEE 1149.1 JTAG boundary scan
■ Built in deterministic access control to manage address colli-
sions during simultaneous access tothesamememorylocation
■ Variable Impedance Matching (VIM) to improve data trans-
mission by matching the output driver impedance to the line
impedance
■ Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and
x18) packages
■ FullFlex72 family
■ Echo clocks to improve data transfer
❐ 36 Mbit: 512K x 72 (CYD36S72V18)
❐ 18 Mbit: 256K x 72 (CYD18S72V18)
❐ 9 Mbit: 128K x 72 (CYD09S72V18)
❐ 4 Mbit: 64K x 72 (CYD04S72V18)
To reduce the static power consumption, chip enables power
down the internal circuitry. The number of latency cycles before
a change in CE0 or CE1 enables or disables the databus
matches the number of cycles of read latency selected for the
device. For a valid write or read to occur, activate both chip
enable inputs on a port.
■ FullFlex36 family
❐ 36 Mbit: 1M x 36 (CYD36S36V18)
❐ 18 Mbit: 512K x 36 (CYD18S36V18)
❐ 9 Mbit: 256K x 36 (CYD09S36V18)
❐ 4 Mbit: 128K x 36 (CYD04S36V18)
❐ 2 Mbit: 64K x 36 (CYD02S36V18)
Each port contains an optional burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally.
Additional device features include a mask register and a mirror
register to control counter increments and wrap around. The
counter interrupt (CNTINT) flags notify the host that the counter
reaches maximum count value on the next clock cycle. The host
reads the burst counter internal address, mask register address,
and busy address on the address lines. The host also loads the
counter with the address stored in the mirror register by using the
retransmit functionality. Mailbox interrupt flags are used for
message passing, and JTAG boundary scan and asynchronous
Master Reset (MRST) are also available. The Logic Block
Diagram on page 2 shows these features.
■ FullFlex18 family
❐ 36 Mbit: 2M x 18 (CYD36S18V18)
❐ 18 Mbit: 1M x 18 (CYD18S18V18)
❐ 9 Mbit: 512K x 18 (CYD09S18V18)
❐ 4 Mbit: 256K x 18 (CYD04S18V18)
■ Built in deterministic access control to manage address colli-
sions
❐ Deterministic flag output upon collision detection
❐ Collision detection on back-to-back clock cycles
❐ First Busy Address readback
The FullFlex72 is offered in a 484-Ball plastic BGA package. The
FullFlex36 and FullFlex18 are available in 256-Ball fine pitch
BGA package.
■ Advanced features for improved high speed data transfer and
flexibility
❐ Variable Impedance Matching (VIM)
❐ Echo clocks
❐ Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V
LVCMOS, or 2.5V LVCMOS IO on each port
❐ Burst counters for sequential memory access
❐ Mailbox with interrupt flags for message passing
❐ Dual Chip Enables for easy depth expansion
Cypress Semiconductor Corporation
Document Number: 38-06082 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 15, 2008
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FullFlex
Logic Block Diagram
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]
FTSEL
L
FTSEL
CQEN
R
CQEN
L
R
CONFIG Block
CONFIG Block
PORTSTD[1:0]
PORTSTD[1:0]
L
R
DQ [71:0]
R
DQ[71:0]
L
BE [7:0]
0
R
BE [7:0]
R
L
CE
CE
0
L
CE1
OE
IO
Control
IO
Control
CE1
R
L
OE
R
L
R/
W
R/
W
L
R
CQ1
L
CQ1
CQ1
CQ0
R
CQ1
CQ0
L
R
R
L
CQ0
CQ0
L
R
Dual Port Array
BUSY
Collision Detection Logic
BUSY
L
R
A [20:0]
A [20:0]
L
R
CNT/MSK
CNT/MSK
L
R
ADS
ADS
L
R
CNTEN
CNTEN
L
R
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
RET
R
L
CNTINT
L
CNTINT
R
C
C
L
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
ZQ0
ZQ0
ZQ1
R
L
ZQ1
R
L
RESET
LOGIC
MRST
READY
READY
L
R
LowSPD
LowSPD
R
L
Notes
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and
CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits.
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.
Document Number: 38-06082 Rev. *H
Page 2 of 52
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FullFlex
Figure 1. FullFlex72 SDR 484-Ball BGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22
DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R DNU
DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R
A
B
C
DQ65L DQ64L VSS
DQ67L DQ66L VSS
VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS
VSS DQ64R DQ65R
VSS DQ66R DQ67R
VSS VSS CQ1L CQ1L VSS LOWS PORTS ZQ0L BUSYL CNTIN PORTS DNU CQ1R CQ1R VSS VSS
D
E
F
[4]
PDL
TD0L
TL
TD1L
DQ69L DQ68L VDDIO VSS
L
VSS VDDIO VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO DNU
VSS VDDIO DQ68R DQ69R
R
L
L
L
L
L
R
R
R
R
DQ71L DQ70L CE1L CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R CE1R DQ70R DQ71R
L
L
L
L
L
E
E
E
E
R
R
R
R
R
A0L
A2L
A4L
A6L
A8L
A10L
A1L
RETL BE4L VDDIO VDDIO VREFL VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VREFR VDDIO VDDIO BE4R RETR A1R
A0R
A2R
A4R
A6R
A8R
G
H
J
L
L
R
R
A3L WRPL BE5L VDDIO VDDIO VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIO VDDIO BE5R WRPR A3R
L
L
R
R
A5L READY BE6L VDDIO VDDIO VSS
VSS VDDIO VDDIO BE6R READY A5R
L
L
L
R
R
R
A7L
A9L
ZQ1L BE7L VTTL VCOR VSS
VSS VCOR VDDIO BE7R ZQ1R A7R
[4, 5]
K
L
[4, 5]
E
E
R
CL
OEL
VTTL VCOR VSS
E
VSS VCOR VTTL OER
E
CR
A9R
A11L
VSS
BE3L VTTL VCOR VSS
E
VSS VCOR VTTL BE3R VSS
E
A11R A10R
M
N
P
R
T
A12L A13L ADSL BE2L VDDIO VCOR VSS
VSS VCOR VTTL BE2R ADSR A13R A12R
E
L
E
A14L A15L CNT/M BE1L VDDIO VDDIO VSS
SKL
VSS VDDIO VDDIO BE1R CNT/M A15R A14R
L
L
R
R
SKR
A16L A17L CNTEN BE0L VDDIO VDDIO VSS
VSS VDDIO VDDIO BE0R CNTEN A17R A16R
[7] [8]
[8]
[7]
L
L
L
R
R
R
A18L
[6]
DNU CNTRS INTL VDDIO VDDIO VREFL VSS
TL
VSS VREFR VDDIO VDDIO INTR CNTRS DNU A18R
[6]
L
L
R
R
TR
DQ35L DQ34L R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN R/WR DQ34R DQ35R
U
V
W
L
L
L
L
L
E
E
E
E
R
R
R
R
R
R
DQ33L DQ32L FTSEL VDDIO DNU VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL DQ32R DQ33R
L
L
L
L
L
L
R
R
R
R
R
R
R
DQ31L DQ30L VSS MRST VSS CQ0L CQ0L DNU PORTS CNTIN BUSYR ZQ0R PORTS LOWS VSS CQ0R CQ0R VSS
TDI
TDO DQ30R DQ31R
[4]
TD1R
TR
TD0R PDR
DQ29L DQ28L VSS
VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS
TCK DQ28R DQ29R
Y
DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R
DNU DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R DNU
AA
AB
Notes
4. Leave this ball unconnected to disable VIM.
5. This ball is applicable only for 36 Mbit and DNU for 18 Mbit and lower densities.
6. Leave this Ball unconnected for CYD18S72V18, CYD09S72V18, and CYD04S72V18.
7. Leave this Ball unconnected for CYD09S72V18 and CYD04S72V18.
8. Leave this Ball unconnected for CYD04S72V18.
Document Number: 38-06082 Rev. *H
Page 3 of 52
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FullFlex
Figure 2. FullFlex36 SDR 484-Ball BGA Pinout (Top View)[9]
10 11 12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
DNU
DNU
DNU
DNU
DNU DQ33L DQ30L DQ27L DQ24L DQ21L DQ18L DQ18R DQ21R DQ24R DQ27R DQ30R DQ33R DNU
DNU DQ34L DQ31L DQ28L DQ25L DQ22L DQ19L DQ19R DQ22R DQ25R DQ28R DQ31R DQ34R DNU
DNU DQ35L DQ32L DQ29L DQ26L DQ23L DQ20L DQ20R DQ23R DQ26R DQ29R DQ32R DQ35R DNU
DNU
DNU
VSS
VSS
DNU
DNU
VSS
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
A
B
C
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VSS
VSS
DNU
VSS
VSS
VSS CQ1L CQ1L VSS LOWS PORTS ZQ0L BUSYL CNTIN PORTS DNU CQ1R CQ1R VSS
[4]
D
E
F
PDL
TD0L
TL
TD1L
DNU
DNU
A0L
A2L
A4L
A6L
A8L
DNU VDDIO VSS
L
VSS VDDIO VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO DNU
VSS VDDIO DNU
R
DNU
DNU
A0R
A2R
A4R
A6R
A8R
L
R
R
R
R
L
L
L
L
DNU CE1L CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R CE1R DNU
L
L
R
R
R
E
E
E
E
L
L
L
R
R
A1L
RETL BE2L VDDIO VDDIO VREFL VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VREFR VDDIO VDDIO BE2R RETR A1R
G
H
J
L
L
R
R
A3L WRPL BE3L VDDIO VDDIO VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIO VDDIO BE3R WRPR A3R
L
L
R
R
A5L READY DNU VDDIO VDDIO VSS
VSS VDDIO VDDIO DNU READY A5R
L
L
L
R
R
R
A7L
A9L
ZQ1L DNU VTTL VCOR VSS
VSS VCOR VDDIO DNU ZQ1R A7R
[4]
K
L
[4]
E
E
R
CL
OEL
VTTL VCOR VSS
E
VSS VCOR VTTL OER
E
CR
A9R
A10L
A11L
VSS
DNU VTTL VCOR VSS
E
VSS VCOR VTTL DNU
E
VSS
A11R A10R
M
N
P
R
T
A12L A13L ADSL DNU VDDIO VCOR VSS
VSS VCOR VTTL DNU ADSR A13R A12R
E
L
E
A14L A15L CNT/M BE1L VDDIO VDDIO VSS
SKL
VSS VDDIO VDDIO BE1R CNT/M A15R A14R
L
L
R
R
SKR
A16L A17L CNTEN BE0L VDDIO VDDIO VSS
VSS VDDIO VDDIO BE0R CNTEN A17R A16R
L
L
L
R
R
R
A18L A19L CNTRS INTL VDDIO VDDIO VREFL VSS
TL
VSS VREFR VDDIO VDDIO INTR CNTRS A19R A18R
TR
L
L
R
R
DNU
DNU
DNU
DNU R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN R/WR DNU
DNU
DNU
DNU
U
V
W
L
L
R
R
R
E
E
E
E
L
L
L
R
R
R
DNU FTSEL VDDIO DNU VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL DNU
L
L
R
R
R
R
L
L
L
L
R
R
R
DNU
VSS MRST VSS CQ0L CQ0L DNU PORTS CNTIN BUSYR ZQ0R PORTS LOWS VSS CQ0R CQ0R VSS
TDI
TDO
DNU
[4]
TD1R
TR
TD0R PDR
DNU
DNU
DNU
DNU
DNU
DNU
VSS
DNU
DNU
VSS
DNU
DNU
DNU DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DNU
DNU DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DNU
DNU DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DNU
TMS
DNU
DNU
TCK
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
Y
AA
AB
Note
9. Use this pinout only for device CYD36S36V18 of the FullFlex36 family.
Document Number: 38-06082 Rev. *H
Page 4 of 52
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FullFlex
Figure 3. FullFlex18 SDR 484-Ball BGA Pinout (Top View)[10]
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU DQ15L DQ12L DQ9L DQ9R DQ12R DQ15R DNU
DNU DQ16L DQ13L DQ10L DQ10R DQ13R DQ16R DNU
DNU DQ17L DQ14L DQ11L DQ11R DQ14R DQ17R DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VSS
VSS
DNU
DNU
VSS
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
A
B
C
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VSS
VSS
DNU
VSS
VSS
DNU
DNU
DNU
DNU
DNU
DNU
VSS CQ1L CQ1L VSS
LOWS PORTS ZQ0L BUSYL CNTIN PORTS DNU CQ1R CQ1R VSS
[4]
D
E
F
PDL
TD0L
TL
TD1L
DNU
DNU
A0L
A2L
A4L
A6L
A8L
DNU VDDIO VSS
L
VSS VDDIO VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO DNU
VSS VDDIO DNU
R
DNU
DNU
A0R
A2R
A4R
A6R
A8R
L
R
R
R
R
L
L
L
L
DNU CE1L CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R CE1R DNU
L
L
R
R
R
E
E
E
E
L
L
L
R
R
A1L
RETL BE1L VDDIO VDDIO VREFL VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VREFR VDDIO VDDIO BE1R RETR A1R
G
H
J
L
L
R
R
A3L WRPL DNU VDDIO VDDIO VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIO VDDIO DNU WRPR A3R
L
L
R
R
A5L READY DNU VDDIO VDDIO VSS
VSS VDDIO VDDIO DNU READY A5R
L
L
L
R
R
R
A7L
A9L
ZQ1L DNU VTTL VCOR VSS
VSS VCOR VDDIO DNU ZQ1R A7R
[4]
K
L
[4]
E
E
R
CL
OEL
VTTL VCOR VSS
E
VSS VCOR VTTL OER
E
CR
A9R
A10L
A11L
VSS
DNU VTTL VCOR VSS
E
VSS VCOR VTTL DNU
E
VSS
A11R A10R
M
N
P
R
T
A12L A13L ADSL DNU VDDIO VCOR VSS
VSS VCOR VTTL DNU ADSR A13R A12R
E
L
E
A14L A15L CNT/M DNU VDDIO VDDIO VSS
SKL
VSS VDDIO VDDIO DNU CNT/M A15R A14R
L
L
R
R
SKR
A16L A17L CNTEN BE0L VDDIO VDDIO VSS
VSS VDDIO VDDIO BE0R CNTEN A17R A16R
L
L
L
R
R
R
A18L A19L CNTRS INTL VDDIO VDDIO VREFL VSS
TL
VSS VREFR VDDIO VDDIO INTR CNTRS A19R A18R
TR
L
L
R
R
A20L
DNU
DNU
DNU R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN R/WR DNU A20R
U
V
W
L
L
R
R
R
E
E
E
E
L
L
L
R
R
R
DNU FTSEL VDDIO DNU VDDIO VDDIO VDDIO VDDIO VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL DNU
DNU
DNU
L
L
R
R
R
R
L
L
L
L
R
R
R
DNU
VSS MRST VSS CQ0L CQ0L DNU PORTS CNTIN BUSYR ZQ0R PORTS LOWS VSS CQ0R CQ0R VSS
TDI
TDO
DNU
[4]
TD1R
TR
TD0R PDR
DNU
DNU
DNU
DNU
DNU
DNU
VSS
DNU
DNU
VSS
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU
DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU
DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
TMS
DNU
DNU
TCK
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
Y
AA
AB
Note
10. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.
Document Number: 38-06082 Rev. *H
Page 5 of 52
[+] Feedback
FullFlex
Figure 4. FullFlex36 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ32L
DQ30L
DQ28L
DQ26L
DQ24L
DQ22L
DQ20L
DQ18L
DQ18R
DQ20R
DQ22R
DQ24R
DQ26R
DQ28R
DQ30R
DQ32R
A
B
C
D
E
F
DQ33L
DQ34L
A0L
DQ31L
DQ35L
A1L
DQ29L
RETL
WRPL
CE0L
CNTINTL
BUSYL
CL
DQ27L
INTL
DQ25L
CQ1L
DQ23L
CQ1L
DQ21L
DNU
DQ19L
TRST
VTTL
VCORE
VSS
DQ19R
MRST
VTTL
VCORE
VSS
DQ21R
DQ23R
CQ1R
DQ25R
CQ1R
DQ27R
INTR
DQ29R
RETR
WRPR
CE0R
CNTINTR
BUSYR
CR
DQ31R
DQ35R
A1R
DQ33R
DQ34R
A0R
[4]
ZQ0R
VREFL
CE1L
BE3L
BE2L
VTTL
FTSELL LOWSPDL
VSS
VSS
LOWSPD FTSELR
R
VREFR
CE1R
BE3R
BE2R
VTTL
A2L
A3L
VDDIOL
VDDIOL
VDDIOL
VSS
VDDIOL
VSS
VDDIOR VDDIOR VDDIOR
A3R
A2R
A4L
A5L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
VDDIOR
VCORE
A5R
A4R
[4]
A6L
A7L
ZQ0L
VSS
VSS
VSS
VSS
A7R
A6R
G
H
J
A8L
A9L
VCORE
VSS
VSS
VSS
VSS
A9R
A8R
A10L
A12L
A14L
A11L
A13L
A15L
VSS
PORTSTD VCORE
1L
VSS
VSS
VSS
VSS
VCORE PORTSTD
1R
VSS
A11R
A13R
A15R
A10R
A12R
A14R
OEL
BE1L
BE0L
VDDIOL
VDDIOL
VDDIOL
VSS
VSS
VSS
VSS
VDDIOR
VDDIOR
BE1R
BE0R
OER
K
L
ADSL
R/WL
VSS
VSS
VSS
VSS
ADSR
R/WR
[13]
[12]
[12]
[13]
A16L
A17L
CQENL
VDDIOL
VDDIOL
DNU
VCORE
VTTL
TMS
VCORE
VTTL
TDO
VDDIOR VDDIOR VDDIOR
CQENR
A17R
A16R
M
N
P
R
T
[11]
[11]
A18L
DNU
CNT/MSK VREFL PORTSTD READYL
DNU
TDI
READYR PORTSTD VREFR CNT/MSK
DNU
A18R
L
0L
0R
R
DQ16L
DQ15L
DQ14L
DQ17L
DQ13L
DQ12L
CNTENL CNTRSTL
CQ0L
CQ0L
DQ5L
DQ4L
TCK
CQ0R
DQ5R
DQ4R
CQ0R
CNTRSTR CNTENR
DQ17R
DQ13R
DQ12R
DQ16R
DQ15R
DQ14R
DQ11L
DQ10L
DQ9L
DQ8L
DQ7L
DQ6L
DQ3L
DQ2L
DQ1L
DQ0L
DQ1R
DQ0R
DQ3R
DQ2R
DQ7R
DQ6R
DQ9R
DQ8R
DQ11R
DQ10R
Notes
11. Leave this ball unconnected for CYD09S36V18, CYD04S36V18, and CYD02S36V18.
12. Leave this ball unconnected for CYD04S36V18 and CYD02S36V18.
13. Leave this ball unconnected for CYD02S36V18.
Document Number: 38-06082 Rev. *H
Page 6 of 52
[+] Feedback
FullFlex
Figure 5. FullFlex18 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DNU
DNU
DNU
DQ17L
DQ16L
DQ13L
DQ12L
DQ9L
DQ9R
DQ12R
DQ13R
DQ16R
DQ17R
DNU
DNU
DNU
A
B
C
D
E
F
DNU
DNU
A0L
DNU
DNU
A1L
DNU
RETL
WRPL
CE0L
CNTINTL
BUSYL
CL
DNU
INTL
DQ15L
CQ1L
DQ14L
CQ1L
DQ11L
DNU
DQ10L
TRST
VTTL
VCORE
VSS
DQ10R
MRST
VTTL
VCORE
VSS
DQ11R
DQ14R
CQ1R
DQ15R
CQ1R
DNU
INTR
VREFR
CE1R
DNU
DNU
RETR
WRPR
CE0R
CNTINTR
BUSYR
CR
DNU
DNU
A1R
DNU
DNU
A0R
[4]
ZQ0R
VREFL
CE1L
DNU
FTSELL LOWSPDL
VSS
VSS
LOWSPD FTSELR
R
A2L
A3L
VDDIOL
VDDIOL
VDDIOL
VSS
VDDIOL
VSS
VDDIOR VDDIOR VDDIOR
A3R
A2R
A4L
A5L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
VDDIOR
VCORE
A5R
A4R
[4]
A6L
A7L
DNU
ZQ0L
VSS
VSS
VSS
VSS
DNU
A7R
A6R
G
H
J
A8L
A9L
VTTL
VCORE
VSS
VSS
VSS
VSS
VTTL
A9R
A8R
A10L
A12L
A14L
A16L
A11L
A13L
A15L
A17L
VSS
PORTSTD VCORE
1L
VSS
VSS
VSS
VSS
VCORE PORTSTD
1R
VSS
A11R
A13R
A15R
A17R
A10R
A12R
A14R
A16R
OEL
BE1L
BE0L
VDDIOL
VDDIOL
VDDIOL
VSS
VSS
VSS
VSS
VDDIOR
VDDIOR
BE1R
BE0R
OER
K
L
ADSL
R/WL
VSS
VSS
VSS
VSS
ADSR
R/WR
CQENL
VDDIOL
VDDIOL
DNU
VCORE
VTTL
TMS
VCORE
VTTL
TDO
VDDIOR VDDIOR VDDIOR
CQENR
M
N
P
R
T
[15]
[14]
[14]
[15]
A18L
A19L
CNT/MSK VREFL PORTSTD READYL
DNU
TDI
READYR PORTSTD VREFR CNT/MSK A19R
A18R
L
0L
0R
R
DNU
DNU
DNU
DNU
DNU
DNU
CNTENL CNTRSTL
CQ0L
CQ0L
DQ5L
DQ4L
TCK
CQ0R
DQ5R
DQ4R
CQ0R
CNTRSTR CNTENR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ6L
DQ7L
DQ2L
DQ3L
DQ1L
DQ0L
DQ1R
DQ0R
DQ2R
DQ3R
DQ6R
DQ7R
DNU
DNU
DNU
DNU
DNU
DQ8L
DQ8R
Notes
14. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18.
15. Leave this ball unconnected for CYD04S18V18.
Document Number: 38-06082 Rev. *H
Page 7 of 52
[+] Feedback
FullFlex
Selection Guide
Parameter
–200
200
–167
167
Unit
MHz
ns
[17]
fMAX
Maximum Access Time (Clock to Data)
Typical Operating Current ICC
3.3
4.0
800[16]
210[16]
700[16]
210[16]
mA
mA
Typical Standby Current for ISB3 (Both Ports CMOS Level)
Pin Definitions
Left Port
A[20:0]L
Right Port
A[20:0]R
Description
Address Inputs.[1]
DQ[71:0]L
BE[7:0]L
DQ[71:0]R
BE[7:0]R
Data Bus Input and Output.[2]
Byte Select Inputs.[3] Asserting these signals enables read and write operations to the corresponding
bytes of the memory array.
BUSYL
BUSYR
Port Busy Output. When there is an address match and both chip enables are active for both ports,
an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs.
CL
CR
Clock Signal. Maximum clock input rate is fMAX
.
CE0L
CE1L
CQENL
CQ0L
CE0R
CE1R
CQENR
CQ0R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.
Echo Clock Signal Output for DQ[35:0] for FullFlex72 Devices. Echo Clock Signal Output for
DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices.
CQ0L
CQ0R
Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 Devices. Inverted Echo Clock
Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[8:0] for
FullFlex18 devices.
CQ1L
CQ1L
CQ1R
CQ1R
Echo Clock Signal Output for DQ[71:36] for FullFlex72 Devices. Echo Clock Signal Output for
DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for FullFlex18 devices.
Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 Devices. Inverted Echo Clock
Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[17:9]
forFullFlex18 devices.
ZQ[1:0]L
ZQ[1:0]R
VIM Output Impedance Matching Input.[18] To use, connect a calibrating resistor between ZQ and
ground. The resistor must be five times larger than the intended line impedance driven by the dual
port. Assert HIGH or leave DNU to disable VIM.
OEL
INTL
OER
INTR
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins
during read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two
memory locations are used for message passing. INTL is asserted LOW when the right port writes to
the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
LowSPDL
LowSPDR
Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less than
100 MHz, assert this pin LOW.
Notes
16. For 18 Mbit x72 commercial configuration only, refer to Electrical Characteristics on page 18 for complete information.
17. SDR mode with two pipelined stages.
18. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices.
Document Number: 38-06082 Rev. *H
Page 8 of 52
[+] Feedback
FullFlex
Pin Definitions (continued)
Left Port
Right Port
Description
PORTSTD[1:0] PORTSTD[1:0] Port Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert these pins
[19]
[19]
LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and HIGH/HIGH for 1.8V
LVCMOS, respectively. These pins are driven by VTTL referenced levels.
L
R
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the dual port memory
array.
READYL
READYR
Port DLL Ready Output. This signal is asserted LOW when the DLL and Variable Impedance
Matching circuits complete calibration. This is a wired OR capable output.
CNT/MSKL
ADSL
CNT/MSKR
ADSR
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
CNTENL
CNTRSTL
CNTINTL
CNTENR
CNTRSTR
CNTINTR
Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked portion
of the counter is incremented to all “1s”.
WRPL
RETL
WRPR
RETR
Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next counter
increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load the counter
with the value stored in the mirror register.
Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for repeated access
to the same segment of memory.
VREFL
VREFR
VDDIOR
FTSELR
Port External HSTL IO Reference Input. This pin is left DNU when HSTL is not used.
Port Data IO Power Supply.
VDDIOL
FTSELL
Port Flow through Mode Select Input. Assert this pin LOW to select Flow through mode. Assert
this pin HIGH to select Pipelined mode.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required at
power up. This pin is driven by a VDDIOL referenced signal.
TMS
TDI
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine
transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS.
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers. Operation for
LVTTL or 2.5V LVCMOS.
TRST
TCK
JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.
JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally tri-stated
except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5V LVCMOS.
VSS
Ground Inputs.
VCORE
VTTL
Device Core Power Supply.
LVTTL Power Supply.
Note
19. PORTSTD[1:0] and PORTSTD[1:0] have internal pull down resistors.
L
R
Document Number: 38-06082 Rev. *H
Page 9 of 52
[+] Feedback
FullFlex
LowSPD pins are used to reset the DLLs for a single port
independent of all other circuitry. MRST is used to reset all DLLs
on the chip. For more information on DLL lock and reset time,
see Master Reset on page 17.
Selectable IO Standard
The FullFlex device families offer the option to choose one of the
four port standards for the device. Each port independently
selects standards from single ended HSTL class I, single ended
LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The selection of the
standard is determined by the PORTSTD pins for each port.
These pins must be connected to an LVTTL power suppy. This
determines the input clock, address, control, data, and Echo
clock standard for each port as shown in Table 1.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make it extremely difficult to provide accurate clock
trees. To counter this problem, the FullFlex families incorporate
Echo Clocks. Echo Clocks are enabled on a per port basis. The
dual port receives input clocks that are used to clock in the
address and control signals for a read operation. The dual port
retransmits the input clocks relative to the data output. The
buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0
outputs. Each port has a pair of Echo clocks. Each clock is
associated with half the data bits. The output clock matches the
corresponding ports IO configuration.
Table 1. Port Standard Selection
PORTSTD1
VSS
PORTSTD0
VSS
I/O Standard
LVTTL
VSS
VTTL
HSTL
VTTL
VSS
2.5V LVCMOS
1.8V LVCMOS
VTTL
VTTL
To enable echo clock outputs, tie CQEN HIGH. To disable echo
clock outputs, tie CQEN LOW.
Clocking
Figure 6. SDR Echo Clock Delay
Separate clocks synchronize the operations on each port. Each
port has one clock input C. In this mode, all the transactions on
the address, control, and data are on the C rising edge. All trans-
actions on the address, control, data input, output, and byte
enables occur on the C rising edge.
Input Clock
Data Out
Echo Clock
Echo Clock
Table 2. Data Pin Assignment
BE Pin Name
BE[7]
Data Pin Name
DQ[71:63]
DQ[62:54]
DQ[53:45]
DQ[44:36]
DQ[35:27]
DQ[26:18]
DQ[17:9]
Deterministic Access Control
BE[6]
Deterministic Access Control is provided for ease of design. The
circuitry detects when both ports access the same location and
provides an external BUSY flag to the port on which data is
corrupted. The collision detection logic saves the address in
conflict (Busy Address) to a readable register. In the case of
multiple collisions, the first busy address is written to the busy
address register.
BE[5]
BE[4]
BE[3]
BE[2]
BE[1]
If both ports access the same location at the same time and only
one port is doing a write, if tCCS is met, then the data written to
and read from the address is valid data. For example, if the right
port is reading and the left port is writing and the left ports clock
meets tCCS, then the data read from the address by the right port
is the old data. In the same case, if the right ports clock meets
BE[0]
DQ[8:0]
Selectable Pipelined or Flow through Mode
To meet data rate and throughput requirements, the FullFlex
families offer selectable pipelined or flow through mode. Echo
clocks are not supported in flow through mode and the DLL must
be disabled.
t
CCS, then the data read out of the address from the right port is
the new data. In the above case, if tCCS is violated by the either
ports clock with respect to the other port and the right port gets
the external BUSY flag, the data from the right port is corrupted.
Table 3 on page 11 shows the tCCS timing that must be met to
guarantee the data.
Flow through mode is selected by the FTSEL pin. Strapping this
pin HIGH selects pipelined mode. Strapping this pin LOW selects
flow through mode.
Table 4 on page 11 shows that, in the case of the left port writing
and the right port reading, when an external BUSY flag is
asserted on the right port, the data read out of the device is not
guaranteed.
DLL
The FullFlex familes of devices have an on-chip DLL. Enabling
the DLL reduces the clock to data valid (tCD) time enabling more
setup time for the receiving device. For operation below
100 MHz, the DLL must be disabled. This is selectable by
strapping LowSPD low.
The value in the busy address register is read back to the
address lines. The required input control signals for this function
are shown in Table 7 on page 13. The value in the busy address
register is read out to the address lines tCA after the same
amount of latency as a data read operation. After an initial
address match, the BUSY flag is asserted and the address under
contention is saved in the busy address register. All the following
Whenever the operating frequency is altered beyond the Clock
Input Cycle to Cycle Jitter specification, reset the DLL, followed
by 1024 clocks before any valid operation.
Document Number: 38-06082 Rev. *H
Page 10 of 52
[+] Feedback
FullFlex
address matches enable to generate the BUSY flag. However,
none of the addresses are saved into the busy address register.
When a busy readback is performed, the address of the first
match that happens at least two clocks cycles after the busy
readback is saved into the busy address register.
Table 3. tCCS Timing for All Operating Modes
Port A—Early Arriving Port Port B—Late Arriving Port
tCCS
Unit
Mode
Active Edge
Mode
Active Edge
C Rise to Opposite C Rise Setup Time for Non Corrupt Data
SDR
C
SDR
C
tCYC(min) – 0.5
ns
Table 4. Deterministic Access Control Logic
Left Port
Read
Right Port Left Clock
Right Clock
BUSYL
BUSYR
Description
Read
Read
X
X
0
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
No Collision
Write
>tCCS
0
Read OLD Data
>tCCS
0
Read NEW Data
<tCCS
Read OLD Data
Data Not Guaranteed
Read NEW Data
0
<tCCS
H
L
Data Not Guaranteed
Read NEW Data
Read
Write
Write
>tCCS
0
0
>tCCS
0
H
H
H
H
H
H
L
Read OLD Data
<tCCS
Read NEW Data
Data Not Guaranteed
Read OLD Data
0
<tCCS
H
L
Data Not Guaranteed
Array Data Corrupted
Array Stores Right Port Data
Array Stores Left Port Data
Write
0
0
>–tCCS & <tCCS
L
>tCCS
0
L
H
L
>tCCS
H
Table 5. Variable Impedance Matching Parameters
Variable Impedance Matching
Parameter
RQ Value
Min Max
Unit
Ω
Tolerance
± 2%
Each port contains a Variable Impedance Matching circuit to set
the impedance of the IO driver to match the impedance of the
on-board traces. The impedance is set for all outputs except
JTAG and is done by port. To take advantage of the VIM feature,
connect a calibrating resistor (RQ) that is five times the value of
the intended line impedance from the ZQ[1:0][18] pin to VSS. The
output impedance is then adjusted to account for drifts in supply
voltage and temperature every 1024 clock cycles. If a port’s clock
is suspended, the VIM circuit retains its last setting until the clock
is restarted. On restart, it then resumes periodic adjustment. In
the case of a significant change in device temperature or supply
voltage, recalibration happens every 1024 clock cycles. A Master
Reset initializes the VIM circuitry. Table 5 shows the VIM param-
eters and Table 6 describes the VIM operation modes.
100 275
Output Impedance
Reset Time
20
55
Ω
± 15%
N/A
N/A 1024 Cycles
N/A 1024 Cycles
Update Time
N/A
Table 6. Variable Impedance Matching Operation
RQ Connection Output Configuration
100Ω - 275Ω to VSS Output Driver Impedance = RQ/5 ± 15%
at Vout = VDDIO/2
ZQ to VDDIO
VIM Disabled. Rout < 20Ω at Vout =
VDDIO/2
To disable VIM, connect the ZQ pin to VDDIO of the relative
supply for the IOs before a Master Reset.
Document Number: 38-06082 Rev. *H
Page 11 of 52
[+] Feedback
FullFlex
Address Counter and Mask Register Operations [1]
Counter Load Operation [1]
Each port of the FullFlex family contains a programmable burst
address counter. The burst counter contains four registers: a
counter register, a mask register, a mirror register, and a busy
address register.
The address counter and mirror registers are loaded with the
address value presented on the address lines. This value ranges
from 0 to 1FFFFF.
Mask Load Operation [1]
The counter register contains the address used to access the
RAM array. It is changed only by the Master Reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
The mask register is loaded with the address value presented on
the address bus. This value ranges from 0 to 1FFFFF though not
all values permit correct increment operations. Permitted values
are in the form of 2n–1, 2n–2, or 2n–4. The counter register is only
segmented up to three regions. From the most significant bit to
the least significant bit, permitted values have zero or more 0s,
one or more 1s, and the least significant two bits are 11, 10, or
00. Thus 1FFFFE, 07FFFF, and 003FFC are permitted values
but 02FFFF, 003FFA, and 07FFE4 are not.
The mask register value affects the Counter Increment and
Counter Reset operations by preventing the corresponding bits
of the counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is only changed by
Mask Reset, Mask Load, and MRST. The Mask Load operation
loads the value of the address bus into the mask register. The
mask register defines the counting range of the counter register.
The mask register is divided into two or three consecutive
regions. Zero or more 0s define the masked region and one or
more 1s define the unmasked portion of the counter register. The
counter register may be divided up to three regions. The region
containing the least significant bits must be no more than two 0s.
Bits one and zero may be 10 respectively, masking the least
significant counter bit and causing the counter to increment by
two instead of one. If bits one and zero are 00, the two least
significant bits are masked and the counter increments by four
instead of one. For example, in the case of a 256Kx72 configu-
ration, a mask register value of 003FC divides the mask register
into three regions. With bit 0 being the least significant bit and bit
17 being the most significant bit, the two least significant bits are
masked, the next eight bits are unmasked, and the remaining bits
are masked.
Counter Readback Operation
The internal value of the counter register is read out on the
address lines. The address is valid tCA after the selected number
of latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 15 shows a block diagram of this
logic.
Mask Readback Operation
The internal value of the mask register is read out on the address
lines. The address is valid tCA after the selected number of
latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 15 shows a block diagram of the
operation.
The mirror register reloads a counter register on retransmit
operations (see Retransmit on page 14) and wrap functions (see
Counter Interrupt on page 14 below). The last value loaded into
the counter register is stored in the mirror register. The mirror
register is only changed by master reset (MRST), counter reset,
and counter load.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
‘0’. All masked bits remain unchanged. A mask reset followed by
a counter reset resets the counter and mirror registers to 00000.
Mask Reset Operation
Table 7 on page 13 summarizes the operations of these registers
and the required input control signals. All signals except MRST
are synchronized to the ports clock.
The mask register is reset to all 1s, that unmasks every bit of the
burst counter.
Document Number: 38-06082 Rev. *H
Page 12 of 52
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FullFlex
Table 7. Burst Counter and Mask Register Control Operations
[20, 21]
The burst counter and mask register control operation for any port follows.
C
MRST CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
X
L
X
X
X
X
X
Master Reset
Reset address counter to all 0s, mask register to all
1s, and busy address to all 0s.
H
H
H
L
L
H
L
X
X
L
X
X
L
X
X
X
Counter Reset
Mask Reset
Reset counter and mirror unmasked portion to all 0s.
Reset mask register to all 1s.
H
H
Counter Load
Load burst counter and mirror with external address
value presented on address lines.
H
H
L
L
L
X
Mask Load
Retransmit
Load mask register with value presented on the
address lines.
H
H
H
H
H
H
L
L
H
H
L
Load counter with value in the mirror register.
Internally increment address counter value.
H
Counter
Increment
H
H
H
H
H
H
H
H
H
L
H
H
Counter Hold
Constantly hold the address value for multiple clock
cycles.
Counter
Readback
Read out counter internal value on address lines.
H
H
H
H
L
L
H
H
L
H
L
Mask Readback Read out mask register value on address lines.
H
Busy Address
Readback
Read out first busy address after last busy address
readback.
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
X
L
Reserved
Reserved
Reserved
Reserved
Reserved
H
H
H
H
L
H
L
H
L
H
H
H
L
Notes
20. “X” = Don’t Care, “H” = HIGH, “L” = LOW.
21. Counter operation and mask register operation is independent of chip enables.
Document Number: 38-06082 Rev. *H
Page 13 of 52
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FullFlex
Increment Operation[1]
Retransmit
After the address counter is initially loaded with an external
address, the counter can internally increment the address value
and address the entire memory array. Only the unmasked bits of
the counter register are incremented. For a counter bit to
change, the corresponding bit in the mask register must be 1. If
the two least significant bits of the mask register are 11, the burst
counter increments by one. If the two least significant bits are 10,
the burst counter increments by two, and if they are 00, the burst
counter increments by four. If all unmasked counter bits are
incremented to 1 and WRP is deasserted, the next increment l
wraps the counter back to the initially loaded value. The cycle
before the increment that results in all unmasked counter bits to
become 1s, a counter interrupt flag (CNTINT) is asserted if the
counter is incremented again. This increment causes the counter
to reach its maximum value and the next increment returns the
counter register to its initial value that was stored in the mirror
register if WRP is deasserted. If WRP is asserted, the unmasked
portion of the counter is filled with 0 instead. The example shown
in Figure 8 on page 16 shows an example of the
CYDD36S18V18 device with the mask register loaded with a
mask value of 00007F unmasking the seven least significant bits.
Setting the mask register to this value enables the counter to
access the entire memory space. The address counter is then
loaded with an initial value of 000005 assuming WRP is
deasserted. The masked bits, the seventh address through the
twenty-first address, do not increment in an increment operation.
The counter address starts at address 000005 and increments
its internal address value until it reaches the mask register value
of 00007F. The counter wraps around the memory block to
location 000005 at the next count. CNTINT is issued when the
counter reaches the maximum –1 count.
Retransmit enables repeated access to the same block of
memory without the need to reload the initial address. An internal
mirror register stores the address counter value last loaded.
While RET is asserted low, the counter continues to wrap back
to the value in the mirror register independent of the state of
WRP.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock cycle
before an increment operation that results in the unmasked
portion of the counter register being all 1s. It is deasserted by
counter reset, counter load, mask reset, mask load, and MRST.
Counting by Two
When the two least significant bits of the mask register are 10,
the counter increments by two.
Counting by Four
When the two least significant bits of the mask register are 00,
the counter increments by four.
Mailbox Interrupts
Use the upper two memory locations for message passing and
permit communications between ports. Table 8 on page 16
shows the interrupt operation for both ports. The highest memory
location is the mailbox for the right port and the maximum
address – 1 is the mailbox for the left port.
When one port writes to the other port’s mailbox, the INT flag of
the port that the mailbox belongs to is asserted LOW. The INT
flag remains asserted until the mailbox location is read by the
other port. When a port reads its mailbox, the INT flag is
deasserted high after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
Hold Operation
The value of all three registers is constantly maintained
unchanged for an unlimited number of clock cycles. This
operation is useful in applications where wait states are needed
or when address is available a few cycles ahead of data in a
shared bus interface.
As shown in Table 8 on page 16, to set the INTR flag, a write
operation by the left port to address 1FFFFF asserts INTR LOW.
A valid read of the 1FFFFF location by the right port resets INTR
HIGH after one cycle of latency with respect to the right port’s
clock. You must activate at least one byte enable to set or reset
the mailbox interrupt.
Document Number: 38-06082 Rev. *H
Page 14 of 52
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FullFlex
Figure 7. Counter, Mask, and Mirror Logic Block Diagram
Figure 7 shows the counter, mask, and mirror logic block diagram. [1]
CNT/MSK
CNTEN
A
Decode
Logic
CNTRST
RET
MRST
A
C
Mask
Register
Counter/
Address
Register
RAM
Array
Address
Decode
Load/Increment
20
20
From
Address
Lines
Counter
Mirror
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
Register
20
Wrap
20
20
20
From
Mask
Bit 0
and 1
From
Counter
+1
Wrap
Detect
Wrap
To
1
0
+2
+4
20
1
0
Counter
Document Number: 38-06082 Rev. *H
Page 15 of 52
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FullFlex
Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted
Figure 8 shows the programmable counter-mask operation with WRP deasserted. [1, 25]
CNTINT
Example:
Load
Counter-Mask
Register = 00007F
H
0
0
0s
1
1
1
1
1
1
1
0
220 219
Masked Address
26 25 24 23 22 21 20
27
Mask
Register
LSB
Unmasked Address
Load
Address
Counter = 000005
H
L
X
X
Xs
Xs
Xs
0
0
0
0
1
0
1
X
X
220 219
26 25 24 23 22 21 20
Address
Counter
LSB
27
27
27
Max
Address
Value
X
X
1
1
1
1
1 1
1
220 219
26 25 24 23 22 21 20
Max + 1
Address
Value
H
X
X
0
0
0
0
1
0
1
X
220 219
26 25 24 23 22 21 20
Table 8. Interrupt Operation Example
Table 8 shows the interrupt operation example. [1, 20, 22, 23, 24]
Left Port
Function
Right Port
A0R–20R
X
R/WL
CEL
L
A0L–20L
INTL
X
R/WR
CER
X
INTR
L
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
L
X
X
H
Max Address
X
H
L
X
X
X
L
Max Address
H
X
X
L
L
Max Address–1
X
X
X
Reset Left INTL Flag
L
Max Address–1
H
X
X
Notes
22. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is
0
1
deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge.
23. OE is “Don’t Care” for mailbox operation.
24. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
25. The “X” in this diagram represents the counter’s upper bits.
Document Number: 38-06082 Rev. *H
Page 16 of 52
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FullFlex
Master Reset
Table 9. JTAG IDCODE Register Definitions
The FullFlex family of Dual Ports undergoes a complete reset
when MRST is asserted. MRST must be driven by VDDIOL refer-
enced levels. The MRST is asserted asynchronously to the
clocks and must remain asserted for at least tRS. When asserted
MRST deasserts READY, initializes the internal burst counters,
internal mirror registers, and internal busy addresses to zero. It
also initializes the internal mask register to all 1s. All mailbox
interrupts (INT), busy address outputs (BUSY), and burst
counter interrupts (CNTINT) are deasserted upon master reset.
Additionally, do not release MRST until all power supplies
including VREF are fully ramped and all port clocks and mode
select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD)
are valid and stable. This begins calibration of the DLL and VIM
circuits. READY is asserted within 1024 clock cycles. READY is
a wired OR capable output with a strong pull up and weak pull
down. Up to four outputs may be connected together. For faster
pull down of the signal, connect a 250 Ohm resistor to VSS. If
the DLL and VIM circuits are disabled for a port, the port is opera-
tional within five clock cycles. However, the READY is asserted
within 160 clock cycles.
Part Number
CYD36S72V18
CYD36S36V18
CYD36S18V18
CYD18S72V18
CYD18S36V18
CYD18S18V18
CYD09S72V18
CYD09S36V18
CYD09S18V18
CYD04S72V18
CYD04S36V18
CYD04S18V18
CYD02S36V18
Configuration
512Kx72
1024Kx36
2048Kx36
256Kx72
512Kx36
1024Kx18
128Kx72
256Kx36
512Kx18
64Kx72
Value
0C026069h (x2)
0C023069h
0C024069h
0C025069h
0C026069h
0C027069h
0C028069h
0C029069h
0C02A069h
0C02B069h
0C02C069h
0C02D069h
0C030069h
128Kx36
256Kx18
64Kx36
IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 10.Scan Registers Sizes
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels depending on the
VTTL power supply. It is composed of four input connections and
one output connection required by the test logic defined by the
standard.
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary Scan
32
n[26]
Table 11.Instruction Identification Codes
Instruction
EXTEST
Code
0000
1111
1011
0111
Description
Captures the input and output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a
High-Z state.
CLAMP
0100
1000
Controls boundary to 1 or 0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
RESERVED
Captures the input and output ring contents. Places BSR between TDI and TDO.
All other Other combinations are reserved. Do not use other than the mentioned combinations.
codes
Note
26. Details of the boundary scan length is found in the BSDL file for the device.
Document Number: 38-06082 Rev. *H
Page 17 of 52
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FullFlex
Maximum Ratings
Operating Range
Ambient
Temperature
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Range
VCORE
Commercial
0°C to +70°C
1.8V ± 100 mV
1.5V ± 80 mV
Storage Temperature................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Industrial
–40°C to +85°C
1.8V ± 100 mV
1.5V ± 80 mV
Supply Voltage to Ground Potential...............–0.5V to + 4.1V
DC Voltage Applied to
Outputs in High-Z State ...................... –0.5V to VDDIO + 0.5V
Power Supply Requirements
Min
Typ
3.3V
2.5V
1.5V
1.8V
3.3V
2.5V
Max
3.6V
2.7V
1.9V
1.9V
3.6V
2.7V
DC Input Voltage ................................ –0.5V to VDDIO + 0.5V
Output Current into Outputs (LOW)............................ 20 mA
Static Discharge Voltage........................................... > 2200V
(JEDEC JESD8-6, JESD8-B)
LVTTL VDDIO
2.5V LVCMOS VDDIO
HSTL VDDIO
3.0V
2.3V
1.4V
1.7V
3.0V
2.3V
1.8V LVCMOS VDDIO
3.3V VTTL
Latch-up Current..................................................... > 200 mA
2.5V VTTL
HSTL VREF
0.68V 0.75V 0.95V
Electrical Characteristics
Over the Operating Range
All Speed Bins
Typ
Unit
Parameter
Description
Configuration
Min
Max
VOH
Output HIGH Voltage
(VDDIO = Min, IOH = –8 mA)
LVTTL
2.4[27]
V
(VDDIO = Min, IOH = –4 mA)
(VDDIO = Min, IOH = –4 mA)
(VDDIO = Min, IOH = –6 mA)
(VDDIO = Min, IOH = –4 mA)
HSTL (DC)[28]
HSTL (AC)[28]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VDDIO – 0.4[27]
VDDIO – 0.5[27]
1.7[27]
V
V
V
V
V
VDDIO – 0.45[27]
VOL
Output HIGH Voltage
0.4[27]
(VDDIO = Min, IOL = 8 mA)
(VDDIO = Min, IOL = 4 mA)
(VDDIO = Min, IOL = 4 mA)
(VDDIO = Min, IOL = 6 mA)
(VDDIO = Min, IOL = 4 mA)
Input HIGH Voltage
HSTL(DC)[28]
HSTL (AC)[28]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
HSTL(DC)[28]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
0.4[27]
0.5[27]
0.7[27]
V
V
V
V
V
V
V
V
V
V
V
V
0.45[27]
VIH
2
VREF + 0.1
1.7
VDDIO + 0.3
VDDIO + 0.3
0.65 x VDDIO
–0.3
VIL
Input LOW Voltage
0.8
VREF – 0.1
0.7
HSTL(DC)[28]
2.5V LVCMOS
1.8V LVCMOS
–0.3
0.35 x VDDIO
Notes
27. These parameters are met with VIM disabled.
28. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are
measured with 1V/ns input edge rates
Document Number: 38-06082 Rev. *H
Page 18 of 52
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FullFlex
Electrical Characteristics
Over the Operating Range (continued)
All Speed Bins
Typ
Unit
Parameter
Description
Configuration
Min
Max
Output HIGH Voltage
(VDDIO = Min, IOH = –24 mA)
LVTTL
2.7[27]
V
READY
VOH
(VDDIO = Min, IOH = –12 mA)
(VDDIO = Min, IOH = –12 mA)
(VDDIO = Min, IOH = –15 mA)
(VDDIO = Min, IOH = –12 mA)
Output HIGH Voltage
HSTL(DC)[28]
HSTL (AC)[28]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VDDIO – 0.4[27]
VDDIO – 0.5[27]
2.0[27]
V
V
V
V
VDDIO – 0.45[27]
0.4[27]
V
READY VOL (VDDIO = Min, IO = 0.12 mA)
(VDDIO = Min, IOL = 0.12 mA)
(VDDIO = Min, IOL = 0.12 mA)
(VDDIO = Min, IOL = 0.15 mA)
(VDDIO = Min, IOL = 0.08 mA)
HSTL(DC)[28]
HSTL (AC)[28]
2.5V LVCMOS
1.8V LVCMOS
0.4[27]
0.5[27]
0.7[27]
0.45[27]
10
V
V
V
V
IOZ
IIX1
Output Leakage Current
–10
–10
μA
μA
Input Leakage Current Except
TDI, TMS, MRST, PORTSTD
10
IIX2
IIX3
Input Leakage Current TDI,
TMS, MRST
–300
–10
10
μA
μA
Input Leakage Current
PORTSTD
300
Document Number: 38-06082 Rev. *H
Page 19 of 52
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FullFlex
Electrical Characteristics
Over the Operating Range
–200
Typ
512Kx72 Com. 1440
Ind. N/A
1024Kx36 Com. 1180
Ind. N/A
2048Kx18 Com. 1130
–167
Typ
–133
Parameter
ICC
Description
Operating Current
(VCORE = Max,IOUT = 0 mA)
Outputs Disabled
Configuration
Unit
Max
1800
N/A
1500
N/A
1430
N/A
980
1030
800
860
770
830
790
830
640
670
660
690
740
770
590
600
610
620
Max
1620
1730
1350
1470
1290
1410
880
930
720
780
690
750
700
740
570
600
580
610
650
680
520
530
530
550
Typ
1120
1170
930
980
890
940
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Max
1430
1550
1220
1330
1160
1280
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1280
1330
1050
1110
1000
1060
700
730
570
590
540
570
560
580
470
490
480
500
540
550
450
460
460
470
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Ind.
256Kx72 Com.
Ind.
N/A
800
820
640
670
610
640
640
660
540
550
550
570
620
630
510
520
530
540
512Kx36 Com.
Ind.
1024Kx18 Com.
Ind.
128Kx72 Com.
Ind.
256Kx36 Com.
Ind.
512Kx18 Com.
Ind.
64Kx72
Com.
Ind.
128Kx36 Com.
Ind.
256Kx18 Com.
Ind.
64Kx36
Com.
Ind.
Document Number: 38-06082 Rev. *H
Page 20 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
–200
Typ
512Kx72 Com. 1000
–167
Max
–133
Parameter
ISB1
Description
Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
Configuration
Unit
Max
1250
N/A
1140
N/A
1110
N/A
630
680
570
630
560
610
490
540
440
470
460
480
450
480
400
410
410
420
Typ
920
970
820
880
810
860
460
490
410
440
410
430
360
380
340
360
350
370
340
350
320
330
320
330
Typ
830
880
740
790
730
780
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Max
1060
1170
960
1080
940
1050
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1160
1260
1050
1160
1030
1140
580
630
530
580
520
570
450
490
400
430
410
440
400
430
360
370
370
380
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Ind.
1024Kx36 Com.
Ind.
N/A
910
N/A
890
N/A
500
530
460
480
450
470
400
420
380
390
390
410
380
390
360
360
370
370
2048Kx18 Com.
Ind.
256Kx72 Com.
Ind.
512Kx36 Com.
Ind.
1024Kx18 Com.
Ind.
128Kx72 Com.
Ind.
256Kx36 Com.
Ind.
512Kx18 Com.
Ind.
64Kx72
Com.
Ind.
128Kx36 Com.
Ind.
256Kx18 Com.
Ind.
64Kx36
Com.
Ind.
Document Number: 38-06082 Rev. *H
Page 21 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
–200
Typ
512Kx72 Com. 1300
Ind. N/A
1024Kx36 Com. 1090
Ind. N/A
2048Kx18 Com. 1040
–167
Typ
–133
Parameter
ISB2
Description
Standby Current
(One Port TTL or CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Configuration
Unit
Max
1570
N/A
1330
N/A
1270
N/A
790
840
670
730
640
690
630
670
530
560
530
560
580
610
480
500
490
500
Max
1410
1520
1210
1330
1160
1270
710
760
610
670
580
640
560
610
470
500
480
510
510
550
420
440
430
450
Typ
1020
1070
870
920
830
880
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Max
1260
1370
1100
1210
1050
1160
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1160
1210
980
1030
930
980
580
610
490
520
470
490
460
480
400
430
410
430
440
450
380
390
390
400
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Ind.
256Kx72 Com.
Ind.
N/A
650
680
550
570
520
550
520
550
460
480
460
480
500
510
440
450
440
450
512Kx36 Com.
Ind.
1024Kx18 Com.
Ind.
128Kx72 Com.
Ind.
256Kx36 Com.
Ind.
512Kx18 Com.
Ind.
64Kx72
Com.
Ind.
128Kx36 Com.
Ind.
256Kx18 Com.
Ind.
64Kx36
Com.
Ind.
Document Number: 38-06082 Rev. *H
Page 22 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
All Speed Bins
Typ Max
Parameter
ISB3
Description
Configuration
Com.
Unit
Standby Current
512Kx72
1024Kx36
2048Kx18
256Kx72
512Kx36
1024Kx18
128Kx72
256Kx36
512Kx18
64Kx72
410
460
410
460
410
460
210
230
210
230
210
230
150
170
150
170
150
170
130
140
130
140
130
140
590
700
590
700
590
700
300
350
300
350
300
350
200
220
200
220
200
220
150
170
150
170
150
170
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Both Ports CMOS Level)
CEL and CER ≥ VCORE – 0.2V, f = 0
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
128Kx36
256Kx18
Com.
Ind.
Com.
Ind.
Table 12.Capacitance
Signals
Packages
CYD18S72V18
CYD09S72V18
CYD04S72V18
CYD18S36V18
CYD09S36V18
CYD04S36V18
CYD02S36V18
CYD18S18V18
CYD09S18V18
CYD04S18V18
CYD36S72V18
CYD36S36V18
CYD36S18V18
OE
12 pF
10 pF
10 pF
12 pF
18 pF
10 pF
20 pF
16 pF
16 pF
20 pF
30 pF
16 pF
BE, DQ
All other signals
Document Number: 38-06082 Rev. *H
Page 23 of 52
[+] Feedback
FullFlex
AC Test Load and Waveforms
Figure 9. Output Test Load for LVTTL/CMOS
V T H = 1 .5 V fo r L V T T L
V T H = 5 0 % V D D IO fo r 2 . 5 V C M O S
V T H = 5 0 % V D D IO fo r 1 . 8 V C M O S
V
= N C
R E F
V
R E F
5 0 O h m
5 0 O h m
O u tp u t
T e s t P o in t
R = 2 5 0 O h m
V T H
R E A D Y
Z Q
D e v ic e u n d e r
te s t
C
= 1 0 p F
R Q = 2 5 0 O h m
Figure 10. Output Test Load for HSTL
V T H
=
5 0 % V D D I O
V
=
E F
0 . 7 5 V
R
V
R
E F
5 0 O h m
5 0 O h m
O u t p u t
R E A D Y Z Q
R = 2 5 0 O h m
T e s t P o i n t
V T H
C = 1 0 p F f o r S D R
D e v i c e u n d e r
t e s t
R Q = 2 5 0 O h m
Figure 11. HSTL Input Waveform
Document Number: 38-06082 Rev. *H
Page 24 of 52
[+] Feedback
FullFlex
Switching Characteristics Over the Operating Range
Table 13.SDR Mode, Signals Affected by DLL
DLL ON (LOWSPD=1)[31]
DLL OFF
(LOWSPD=0)
Description
[31]
Parameter
–200
–167
–133
Max
Unit
Min
Max
Min
Max
Min
Min
Max
[34]
[34]
tCD2
C Rise to DQ Valid for Pipelined
Mode
3.30
4.00
4.50
6.00
ns
[30, 33]
[30, 33]
[30, 33]
[30, 33]
tCCQ
C Rise to CQ Rise
1.00
3.30[33]
1.00
1.00
4.00[33]
1.00
1.00
4.50[33]
1.00
1.00
6.00[33]
ns
ns
[29, 34]
tCKHZ2
C Rise to DQ Output High Z in 1.00
Pipelined Mode
3.30
4.00
4.50
6.00
[30, 33]
[30, 33]
[30, 33]
[30, 33]
[29, 34]
tCKLZ2
C Rise to DQ Output Low Z in
Pipelined Mode
1.00
1.00
1.00
1.00
ns
Table 14.SDR Mode
Parameter
–200
–167
–133
Description
Unit
Min
Max
Min
Max
Min
Max
fMAX
Maximum Operating Frequency for Pipelined Mode 100
200
100
167
100
133
MHz
(PIPELINED)
f
MAX (FLOW
Maximum Operating Frequency for Flow Through
Mode
77
66.7
55.6
MHz
ns
THROUGH)
tCYC
(PIPELINED)
C Clock Cycle Time for Pipelined Mode
5.00
10.00
6.00
10.00
7.00
10.00
[33]
[33]
[33]
tCYC (FLOW X C Clock Cycle Time for Flow Through Mode
THROUGH)
13.00
15.00
18.00
ns
[33]
[33]
[33]
tCKD
tSD
C Clock Duty Time
45
55
45
55
45
55
%
Data Input Setup Time HSTL
to C Rise
1.50
1.70
1.80
ns
[30, 33]
[30, 33]
[30, 33]
1.8V LVCMOS
2.5V LVCMOS 3.3V
LVTTL
1.75
1.95
2.05
ns
[30, 33]
[30, 33]
[30, 33]
[32]
tHD
Data Input Hold Time after C Rise
0.5
0.5
0.5
ns
ns
tSAC
Address and Control HSTL
Input Setup Time to C 1.8V LVCMOS
Rise
1.50
1.70
1.80
[30, 32,
[30, 32,
[30, 32,
33]
33]
33]
2.5V LVCMOS 3.3V
LVTTL
1.75
1.95
2.05
ns
[30, 32,
[30, 32,
[30, 32,
33]
33]
33]
[32]
tHAC
tOE
Address and Control Input Hold Time after C Rise 0.50
Output Enable to Data Valid
0.60
0.70
ns
ns
4.40
5.00
5.50
[30,33]
[30,33]
[30,33]
[29]
tOLZ
OE to Low Z
1.00
1.00
1.00
ns
Notes
29. Parameters specified with the load capacitance in Figure 9 and Figure 10.
30. For the x18 devices, add 200 ps to this parameter in Table 14.
31. Test conditions assume a signal transition time of 2 V/ns.
32. Add 300 ps to this timing for 36M devices.
33. Add 15% to this parameter if a VCORE of 1.5V is used.
34. This parameter assumes input clock cycle to cycle jitter of ± 0ps.
Document Number: 38-06082 Rev. *H
Page 25 of 52
[+] Feedback
FullFlex
Table 14.SDR Mode (continued)
–200
Max
–167
Max
–133
Parameter
Description
Unit
Min
Min
Min
Max
[29]
tOHZ
tCD1
tCA1
tCA2
OE to High Z
1.00
4.40
1.00
5.00
1.00
5.50
ns
ns
ns
ns
[30, 33]
[30, 33]
[30, 33]
C Rise to DQ Valid for Flow Through Mode
(LowSPD = 1)
9.00
11.00
13.00
[30, 33]
[30, 33]
[30, 33]
CRisetoAddressReadbackValidforFlowThrough
Mode
9.00[33]
5.00[33]
11.00[33]
6.00[33]
13.00
[33]
C Rise to Address Readback Valid for Pipelined
Mode
7.50[33]
[34]
tDC
DQ Output Hold after C Rise
Clock Input Cycle to Cycle Jitter
Echo Clock (CQ) High HSTL
1.00
1.00
1.00
ns
ps
ns
tJIT
+/- 200
0.70[30]
+/- 200
0.80[30]
+/- 200
0.90[30]
[34]
[34]
tCQHQV
to Output Valid
1.8V LVCMOS
2.5V LVCMOS 3.3V
LVTTL
0.80[30]
0.90[30]
1.00[30]
ns
ns
ns
ns
tCQHQX
Echo Clock (CQ) High HSTL
to Output Hold 1.8V LVCMOS
–0.70
–0.85
–0.80
–0.95
1.00
–0.90
–1.05
1.00
2.5V LVCMOS 3.3V
LVTTL
[29]
tCKHZ1
C Rise to DQ Output High Z in Flow Through Mode 1.00
9.00
11.00
13.00
[30, 33]
[30, 33]
[30, 33]
[29]
tCKLZ1
tAC
tCKHZA1
C Rise to DQ Output Low Z in Flow Through Mode 1.00
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
ns
Address Output Hold after C Rise
1.00
[29]
[29]
C Rise to Address Output High Z for Flow Through 1.00
Mode
9.00[33]
5.00[33]
11.00
13.00
[33]
[33]
tCKHZA2
C Rise to Address Output High Z for Pipelined Mode 1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
6.00[33]
1.00
1.00
1.00
1.00
0.50
0.50
1.00
7.50[33]
ns
ns
ns
ns
ns
ns
ns
[29]
tCKLZA
tSCINT
tRCINT
tSINT
C Rise to Address Output Low Z
C Rise to CNTINT Low
C Rise to CNTINT High
C Rise to INT Low
1.00
1.00
1.00
0.50
0.50
1.00
3.30[33]
3.30[33]
7.00[33]
7.00[33]
3.30[33]
4.00[33]
4.00[33]
8.00[33]
8.00[33]
4.00[33]
4.50[33]
4.50[33]
8.50[33]
8.50[33]
4.50[33]
tRINT
C Rise to INT High
tBSY
C Rise to BUSY Valid
Document Number: 38-06082 Rev. *H
Page 26 of 52
[+] Feedback
FullFlex
Table 15.Master Reset Timing
Parameter
–200
–167
–133
Description
Unit
Min
1
Max
Min
1
Max
Min
1
Max
tPUP
tRS
Power Up Time
ms
cycles
cycles
ns
Master Reset Pulse Width
5
5
5
tRSR
tRSF
tRDY
Master Reset Recovery Time
Master Reset to Outputs Inactive/Hi Z
Master Reset Release to Port Ready
C Rise to Port Ready
5
5
5
15
18
22.50
[35]
[36]
1024
9.5[33]
1024
11[33]
1024
13[33]
cycles
ns
tCORDY
Table 16.JTAG Timing
Parameter
–200
–167
–133
Description
Unit
Min
Max
Min
Max
Min
Max
fJTAG
tTCYC
tTH
JTAG TAP Controller Frequency
TCK Cycle Time
20
20
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
20
20
10
10
10
10
50
20
20
10
10
10
10
50
20
20
10
10
10
10
TCK High Time
tTL
TCK Low Time
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
tJXZ
TMS Setup to TCK Rise
TMS Hold to TCK Rise
TDI Setup to TCK Rise
TDI Hold to TCK Rise
TCK Low to TDO Valid
TCK Low to TDO Invalid
TCK Low to TDO High Z
TCK Low to TDO Active
TCK Low to TDO Active
10
10
10
0
0
0
15
15
15
15
15
15
15
15
15
tJZX
tJZX
.
Notes
35. READY is a wired OR capable output with a weak pull down. For a decreased falling delay, connect a 250-Ω resistor to VSS.
36. Add this propagation delay after t for all Master Reset Operations
RDY
Document Number: 38-06082 Rev. *H
Page 27 of 52
[+] Feedback
FullFlex
Switching Waveforms
Figure 12. JTAG Timing
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Figure 13. Master Reset [35]
~
V
CORE
t
t
RS
PUP
~
~
MRST
C
t
t
RDY
CORDY
~
~
READY
t
RSF
All Address
& Data
t
RSR
All Other
Inputs
~
Document Number: 38-06082 Rev. *H
Page 28 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 14. READ Cycle for Pipelined Mode
t
CYC
C
CE
OE
t
t
HAC
SAC
R/W
A
A
A
A
A
A
A
n+6
A
n
n+1
x
n+2
n
n+3
n+4
n+5
2 Pipelined stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+4
x-1
n+1
n+2
n+3
DQ
t
DC
t
CD2
Figure 15. WRITE Cycle for Pipelined and Flow Through Modes
t
CYC
C
CE
R/W
A
A
A
A
A
A
A
n+6
A
n
n+1
n+2
n+3
n+4
n+5
2 Pipelined stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+6
n
n+1
n+2
n+3
n+4
n+5
DQ
tSD tHD
Document Number: 38-06082 Rev. *H
Page 29 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 16. READ with Address Counter Advance for Pipelined Mode
t
CYC
C
A
A
n
Internal
Address
A
A
n+1
A
A
n
n+2
n+3
ADS
CNTEN
DQ
DQ
DQ
DQ
DQ
n+1
x-1
x
n
DQ
DQ
n+2
n+3
Figure 17. READ with Address Counter Advance for Flow Through Mode
tCYC
C
tSAC tHAC
A
An
ADS
CNTEN
DQ
tSAC tHAC
tCD1
DQx
DQn
DQn + 1
DQn + 2
DQn + 3
DQn + 4
tDC
READ EXTERNAL ADDRESS
READ W ITH COUNTER
COUNTER HOLD
READ W ITH COUNTER
Document Number: 38-06082 Rev. *H
Page 30 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 18. Port-to-Port WRITE–READ for Pipelined Mode
t
CYC
Left Port
C
L
A
A
n
L
R/WL
DQ
DQ
L
n
Right Port
t
CCS
C
R
t
CYC
A
R
A
n
R/WR
t
t
SAC HAC
DQ
R
DQ
n
t
t
DC
CD2
Figure 19. Chip Enable READ for Pipelined Mode
t
CYC
C
CE0
CE1
R/W
A
t
t
SAC HAC
A
A
A
A
A
A
A
n+6
n
n+1
n+2
n+3
n+4
n+5
DQ
DQ
DQ
n+3
n
t
t
DC
t
CD2
CKLZ2
Document Number: 38-06082 Rev. *H
Page 31 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 20. OE Controlled WRITE for Pipelined Mode
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
tOHZ
DQ
x+1
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x-1
x
n
n+1
n+2
Figure 21. OE Controlled WRITE for Flow Through Mode
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
tOHZ
DQ
x+2
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x
x+1
n
n+1
n+2
Document Number: 38-06082 Rev. *H
Page 32 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 22. Byte-Enable READ for Pipelined Mode
tCYC
C
A
A
A
A
A
n
n+1
n+2
n+3
R/W
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
tCKLZ2
tCKHZ2
DQn+1(63:71)
DQ
63:71
54:62
DQn+1(54:62)
DQ
DQ
DQ
DQn+2(45:53)
45:53
36:44
DQn+2(36:44)
DQn+1(27:35)
DQ
DQ
27:35
18:26
DQn+2(18:26)
DQn+3(9:17)
DQ
DQ
9:17
0:8
DQn+3(0:8)
Document Number: 38-06082 Rev. *H
Page 33 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 23. Port-to-Port WRITE-to-READ for Flow Through Mode
CL
R/W L
AL
tSAC
tHAC
NO MATCH
MATCH
tSD
tHD
VALID
DQL
tCCS
CR
tCD1
R/W R
tHAC
tSAC
NO MATCH
AR
MATCH
tCD1
DQR
VALID
VALID
tDC
tDC
Document Number: 38-06082 Rev. *H
Page 34 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 24. Busy Address Readback for Pipelined and Flow Through Modes, CNT/MSK = RET = LOW[37]
t
CYC
~
~
C
Internal
Address
Amatch+2
Amatch+3
Amatch+4
BUSY
~
~
CNTEN
ADS
~
~
External
Address
Amatch
Pipelined
tAC
tCA2
External
Address
~
Amatch
Flow through
tAC
tCA1
Figure 25. Read Cycle for Flow Through Mode
tCYC
C
CE0
CE1
tSAC
tHAC
BEn
R/W
A
tSAC
tHAC
An
An + 1
An + 2
An + 3
tCKHZ1
tCD1
tDC
DQ
OE
DQn
DQn + 1
DQn + 2
tDC
tCKLZ1
tOLZ
tOHZ
tOE
Note
37. A
is the matching address that is reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy Address
match
Readback.”
Document Number: 38-06082 Rev. *H
Page 35 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 26. READ-to-WRITE for Pipelined Mode (OE = VIL)[38, 39, 40]
tCYC
tCL
C
A
tCH
A
A
x
A
A
n+2
n
n+1
tSAC tHAC
tSAC tHAC
R/W
DQ
t
CKLZ2
DQ
DQ
DQ
x
DQ
x-2
x-1
DQ
n+2
DQ
n+1
n
tDC
tCD2
tCKHZ2
tSD tHD
Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled)[41, 42]
tCYC
C
A
A
A
A
A
A
A
A
n+3
x
x+1
x+2
n
n+1
n+2
tSAC tHAC
R/W
OE
tOHZ
tSD tHD
DQ
x
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x-2
x-1
n
n+1
n+2
Notes
38. When OE = V , the last read operation is enabled to complete before the DQ bus is tri-stated and the user is enabled to drive write data.
IL
39. Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write.
40. Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption.
41. OE is deasserted and t
enabled to elapse before the first write operation is issued.
OHZ
42. Any write scheduled to complete after OE is deasserted is pre-empted.
Document Number: 38-06082 Rev. *H
Page 36 of 52
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FullFlex
Switching Waveforms (continued)
Figure 28. Read-to-Write-to-Read for Flow Through Mode (OE = LOW)
tCYC
C
tSAC tHAC
CE0
CE1
BEn
tSAC
tHAC
R/W
A
An
An + 1
An + 2
An + 2
An + 3
An + 4
tSD
tHD
DQIN
DQn + 2
tCD1
tCD1
tCD1
tCD1
DQn
tDC
DQOUT
DQn + 1
DQn + 3
tCKHZ1
tCKLZ1
tDC
READ
NOP
W RITE
READ
Document Number: 38-06082 Rev. *H
Page 37 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 29. Read-to-Write-to-Read for Flow Through Mode (OE Controlled)
tCYC
C
tHAC
tSAC
CE0
CE1
BEn
tHAC
tSAC
R/W
A
An
An + 1
An + 2
tHD
An + 3
An + 4
An + 5
tSD
DQIN
DQn + 2
DQn + 3
tOE
tCD1
tCD1
tDC
tCD1
DQOUT
DQn
DQn + 4
tDC
tCKLZ1
tOHZ
OE
READ
W RITE
READ
Document Number: 38-06082 Rev. *H
Page 38 of 52
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FullFlex
Switching Waveforms (continued)
Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow Through Modes, Clock Timing Violates tCCS
.
(Flag Both Ports)
Port A
C
A
R/W
BUSY
C
tBSY
tBSY
< tCCS
Port B
A
R/W
tBSY
tBSY
BUSY
Figure 31. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow Through Modes, Clock Timing Meets tCCS
(Flag Losing Port)
.
Losing Port
C
A
R/W
tccs
tBSY
BUSY
tBSY
Winning Port
C
A
Match
R/W
BUSY
Document Number: 38-06082 Rev. *H
Page 39 of 52
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FullFlex
Switching Waveforms (continued)
Figure 32. Read with Echo Clock for Pipelined Mode (CQEN = HIGH)
C
tSAC
tHAC
R/W
An
An+1
An+2
An+3
An+4
An+5
An+6
A
CQ0
CQ0
CQ1
tCCQ
CQ1
DQ
tCQHQX
tCQHQV
DQn
DQn+1
DQn+2
DQn+3
DQn+4
DQx-1
DQx
Document Number: 38-06082 Rev. *H
Page 40 of 52
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FullFlex
Switching Waveforms (continued)
Figure 33. Mailbox Interrupt Output
t
CYC
C
L
A
MAX
A
L
R/WL
DQ
L
INT
R
t
SINT
t
RINT
C
R
A
MAX
A
R
R/WR
DQ
MAX
DQ
R
Document Number: 38-06082 Rev. *H
Page 41 of 52
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FullFlex
Ordering Information
512K
×
72 (36 Mbit) 1.8V/1.5V Synchronous CYD36S72V18 Dual Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
200 CYD36S72V18-200BGXC
CYD36S72V18-200BGC
167 CYD36S72V18-167BGXC
CYD36S72V18-167BGC
CYD36S72V18-167BGXI
CYD36S72V18-167BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
133 CYD36S72V18-133BGXC
CYD36S72V18-133BGC
CYD36S72V18-133BGXI
CYD36S72V18-133BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
256K
× 72 (18 Mbit) 1.8V/1.5V Synchronous CYD18S72V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD18S72V18-200BGXC
CYD18S72V18-200BGC
CYD18S72V18-200BGXI
CYD18S72V18-200BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
167 CYD18S72V18-167BGXC
CYD18S72V18-167BGC
CYD18S72V18-167BGXI
CYD18S72V18-167BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
128K
× 72 (9 Mbit) 1.8V/1.5V Synchronous CYD09S72V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD09S72V18-200BGXC
CYD09S72V18-200BGC
CYD09S72V18-200BGXI
CYD09S72V18-200BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
167 CYD09S72V18-167BGXC
CYD09S72V18-167BGC
CYD09S72V18-167BGXI
CYD09S72V18-167BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
Document Number: 38-06082 Rev. *H
Page 42 of 52
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Ordering Information (continued)
64K
×
72 (4 Mbit) 1.8V/1.5V Synchronous CYD04S72V18 Dual Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
200 CYD04S72V18-200BGXC
CYD04S72V18-200BGC
CYD04S72V18-200BGXI
CYD04S72V18-200BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
167 CYD04S72V18-167BGXC
CYD04S72V18-167BGC
CYD04S72V18-167BGXI
CYD04S72V18-167BGI
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218 484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
1024K
× 36 (36 Mbit) 1.8V/1.5V Synchronous CYD36S36V18 Dual Port SRAM
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
200 CYD36S36V18-200BGXC
CYD36S36V18-200BGC
167 CYD36S36V18-167BGXC
CYD36S36V18-167BGC
CYD36S36V18-167BGXI
CYD36S36V18-167BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
133 CYD36S36V18-133BGXC
CYD36S36V18-133BGC
CYD36S36V18-133BGXI
CYD36S36V18-133BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
512K
× 36 (18 Mbit) 1.8V/1.5V Synchronous CYD18S36V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD18S36V18-200BBAXC
CYD18S36V18-200BBAC
CYD18S36V18-200BBAXI
CYD18S36V18-200BBAI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD18S36V18-167BBAXC
CYD18S36V18-167BBAC
CYD18S36V18-167BBAXI
CYD18S36V18-167BBAI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Document Number: 38-06082 Rev. *H
Page 43 of 52
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FullFlex
Ordering Information (continued)
256K
×
36 (9 Mbit) 1.8V/1.5V Synchronous CYD09S36V18 Dual Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
200 CYD09S36V18-200BBXC
CYD09S36V18-200BBC
CYD09S36V18-200BBXI
CYD09S36V18-200BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD09S36V18-167BBXC
CYD09S36V18-167BBC
CYD09S36V18-167BBXI
CYD09S36V18-167BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
128K
× 36 (4 Mbit) 1.8V/1.5V Synchronous CYD04S36V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD04S36V18-200BBXC
CYD04S36V18-200BBC
CYD04S36V18-200BBXI
CYD04S36V18-200BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD04S36V18-167BBXC
CYD04S36V18-167BBC
CYD04S36V18-167BBXI
CYD04S36V18-167BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
64K
× 36 (2 Mbit) 1.8V/1.5V Synchronous CYD02S36V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD02S36V18-200BBXI
167 CYD02S36V18-167BBXI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
Document Number: 38-06082 Rev. *H
Page 44 of 52
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Ordering Information (continued)
2048K
×
18 (36 Mbit) 1.8V/1.5V Synchronous CYD36S18V18 Dual Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
200 CYD36S18V18-200BGXC
CYD36S18V18-200BGC
167 CYD36S18V18-167BGXC
CYD36S18V18-167BGC
CYD36S18V18-167BGXI
CYD36S18V18-167BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
133 CYD36S18V18-133BGXC
CYD36S18V18-133BGC
CYD36S18V18-133BGXI
CYD36S18V18-133BGI
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
1024K
× 18 (18 Mbit) 1.8V/1.5V Synchronous CYD18S18V18 Dual Port SRAM
Package
Diagram
Speed
MHz)
Operating
Range
Ordering Code
Package Type
200 CYD18S18V18-200BBAXC
CYD18S18V18-200BBAC
CYD18S18V18-200BBAXI
CYD18S18V18-200BBAI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD18S18V18-167BBAXC
CYD18S18V18-167BBAC
CYD18S18V18-167BBAXI
CYD18S18V18-167BBAI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17mm with 1.0 mm pitch
512K
× 18 (9 Mbit) 1.8V/1.5V Synchronous CYD09S18V18 Dual Port SRAM
Package
Diagram
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
200 CYD09S18V18-200BBXC
CYD09S18V18-200BBC
CYD09S18V18-200BBXI
CYD09S18V18-200BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD09S18V18-167BBXC
CYD09S18V18-167BBC
CYD09S18V18-167BBXI
CYD09S18V18-167BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Document Number: 38-06082 Rev. *H
Page 45 of 52
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FullFlex
Ordering Information (continued)
256K
×
18 (4 Mbit) 1.8V or 1.5V Synchronous CYD04S18V18 Dual Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Package Type
Diagram
200 CYD04S18V18-200BBXC
CYD04S18V18-200BBC
CYD04S18V18-200BBXI
CYD04S18V18-200BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
167 CYD04S18V18-167BBXC
CYD04S18V18-167BBC
CYD04S18V18-167BBXI
CYD04S18V18-167BBI
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108 256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Document Number: 38-06082 Rev. *H
Page 46 of 52
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FullFlex
Package Diagrams
Figure 34. 256-Ball FBGA (17 x 17 mm), 51-85108
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES
ꢀ0.05
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.70 MAX.
A
51-85108-*F
Document Number: 38-06082 Rev. *H
Page 47 of 52
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FullFlex
Package Diagrams
Figure 35. 484-Ball PBGA (23 mm x 23 mm x 2.03 mm), 51-85218
Ø0.50~Ø0.70(484X)
PIN #1 CORNER
9
1
2
11
7
3
1
3
5
7
9
21
20 22
13
5
11
13 15 17 19
10 12 14 16 18
21
17 15
19
2
4
6
8
22 20 18 16 14 12 10
8
6
4
Ø1.00(3X) REF.
A
B
A
B
C
C
D
E
D
E
F
F
G
H
J
G
H
J
K
K
ꢁ
ꢁ
M
N
P
M
N
P
R
R
T
T
U
V
U
V
W
Y
W
Y
AA
AB
AA
AB
1.00
ꢀBꢀ
21.00
3.20*45°(4x)
20.00 REF.
ꢀAꢀ
23.00 0.20
0.20(4X)
30° TYP.
Package Weight ꢀ 2.0 grams
Jedec Outline ꢀ Design Guide 4.14
ꢀCꢀ
SEATING PꢁANE
51-85218-**
Document Number: 38-06082 Rev. *H
Page 48 of 52
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Package Diagrams
Figure 36. 484-Ball PBGA (27 mm x 27 mm x 2.33 mm), 001-07825
001-07825-**
Document Number: 38-06082 Rev. *H
Page 49 of 52
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FullFlex
Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
Submission Orig. of
REV.
ECN NO.
Description of Change
Date
Change
**
302411
334036
See ECN
See ECN
YDT
New data sheet
*A
YDT
Corrected typo on page 1
Reproduced PDF file to fix formatting errors
*B
395800
See ECN
SPN
Added statement about no echo clocks for flow through mode
Updated electrical characteristics
Added note 16 and 17 (1.5V timing)
Added note 33 (timing for x18 devices)
Updated input edge rate (note 34)
Updated table 5 on deterministic access control logic
Added description of busy readback in deterministic access control section
Changed dummy write descriptions
Updated ZQ pins connection details
Updated note 24, B0 to BE0
Added power supply requirements to MRST and VC_SEL
Added note 4 (VIM disable)
Updated supply voltage to ground potential to 4.1V
Updated parameters on table 15
Updated and added parameters to table 16
Updated x72 pinout to SDR only pinout
Updated 484 PBGA pin diagram
Updated the pin definition of MRST
Updated the pin definition of VC_SEL
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated minimum VOH value for the 1.8V LVCMOS configuration
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added Notes 33 and 34Removed Notes 15 and 17
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Removed -100 Speed bin from Table.1 Selection Guide
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD18S18V18 parts
Updated the Package Type for the CYD18S36V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Updated Figure 5 and Figure 6
Updated Electrical Characteristics for READY VOH and READY V
Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode
Document Number: 38-06082 Rev. *H
Page 50 of 52
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FullFlex
Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
Submission Orig. of
REV.
ECN NO.
Description of Change
Updated AC Test Load and Waveforms
Date
Change
*C
402238
SEE ECN
KGH
Included FullFlex36 SDR 484-Ball BGA Pinout (Top View)
Included FullFlex18 SDR 484-Ball BGA Pinout (Top View)
Included Timing Parameter tCORDY
*D
458131
SEE ECN
YDT
Changed ordering information with Pb-free part numbers
Removed VC_SEL
Added IO and core voltage adders
Removed references to bin drop for LVTTL/2.5V LVCMOS and 1.5V core modes
Updated Cin and Cout
Updated ICC, ISB1, ISB2 and ISB3 tables
Updated busy address read back timing diagram
Added HTSL input waveform
Removed HSTL (AC) from DC tables
Added 484-ball 27 mmx27 mmx2.33 mm PBGA package
*E
470031
SEE ECN
YDT
Changed VOL of 1.8V LVCMOS to 0.45V
Updated tRSF
VREF is DNU when HSTL is not used
Formatted pin description table
Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts
Changed 36Mx72 JTAG IDCODE
*F
500001
627539
SEE ECN
SEE ECN
YDT
QSL
DLL Change, added Clock Input Cycle to Cycle Jitter
Modified DLL description
Changed Input Capacitance Table
Changed tCCS number
Added note 31
*G
change all NC to DNU
corrected switching waveform for (CQEN = High) from both Pipeline and Flow
through mode to only pipeline mode
Modified master reset description
Modified switching characteristics tables, extracted signals effected by the DLL
into one table and combine all other signals into one table
updated package name
Added footnote for tHD, tHAC and tSAC
changed note 26 description
Document Number: 38-06082 Rev. *H
Page 51 of 52
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Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
Submission Orig. of
REV.
ECN NO.
Description of Change
Date
Change
*H
2505003
See ECN
VKN/
Modified footnote #1
AESA Removed 250 MHz speed bin
Added 2-Mbit part and it’s related information
Changed ball name ZQ1 to DNU for 18M and lesser density devices
Added 256-Ball (17 x 17 mm) BGA package for 18M
Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level
For 1.8V LVCMOS level, Changed VIH(min) from 1.26V to 0.65 times VDDIO and
Changed VIL(max) from 0.36V to 0.35 times VDDIO
Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote# 32)
Updated Ordering Information table
Sales, Solutions, and Legal Information
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closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06082 Rev. *H
Revised May 15, 2008
Page 52 of 52
FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
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