CYD04S72V_11 [CYPRESS]
FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM; FLEx72 3.3 V 64 K / 128 K / 256的K× 72同步双端口RAM
| 型号： | CYD04S72V_11 |
| 厂家： | 
CYPRESS |
| 描述： | FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM |
| 文件： | 总30页 (文件大小：887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYD04S72V
CYD09S72V
CYD18S72V
FLEx72™ 3.3 V 64 K/128 K/256 K × 72
Synchronous Dual-Port RAM
Features
Functional Description
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal set-up and hold time.
■ Synchronous pipelined operation
■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18-micron complmentary metal oxide semiconductor
(CMOS) for optimum speed and power
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter will increment the address internally (more
details to follow). The internal write pulse width is independent of
the duration of the R/W input signal. The internal write pulse is
self-timed to allow the shortest possible cycle times.
■ High-speed clock to data access
■ 3.3 V low power
❐ Active as low as 225 mA (typ)
❐ Standby as low as 55 mA (typ)
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
■ IEEE 1149.1-compatible joint test action group (JTAG)
boundary scan
■ 484-ball fine-pitch ball grid array (FBGA) (1-mm pitch)
■ Pb-free packaging available
The CYD18S72V device have limited features. Please see
Table 3 on page 8 for details.
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
Seamless Migration to Next-Generation Dual-Port
Family
■ Counter readback on address lines
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details
■ Mask register readback on address lines
■ Dual chip enables on both ports for easy depth expansion
■ Seamless migration to next generation dual-port family
Table 1. Product Selection Guide
.
4-Mbit
9-Mbit
18-Mbit
Density
(64K x 72)
CYD04S72V
167
(128K x 72)
(256K x 72)
Part number
CYD09S72V
CYD18S72V
Max. speed (MHz)
133
4.4
133
5.0
Max. access time—clock to data (ns)
Typical operating current (mA)
Package
4.0
225
350
410
484-ball FBGA
23 mm x 23 mm
484-ball FBGA
23 mm x 23 mm
484-ball FBGA
23 mm x 23 mm
Cypress Semiconductor Corporation
Document Number : 38-06069 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 25, 2011
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CYD04S72V
CYD09S72V
CYD18S72V
Logic Block Diagram[1]
FTSEL
L
FTSEL
R
CONFIG Block
CONFIG Block
PORTST[1:0]
L
PORTST[1:0]
R
DQ [71:0]
R
DQ[71:0]
L
BE [7:0]
BE [7:0]
R
L
CE0
CE1
CE0
R
L
IO
Control
IO
Control
CE1
R
L
OE
OE
R
L
R/W
R/W
R
L
Dual-Ported Array
Arbitration Logic
BUSY
BUSY
L
R
A [17:0]
A [17:0]
L
R
CNT/MSK
CNT/MSK
L
R
ADS
ADS
L
R
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
RET
R
L
CNTINT
L
CNTINT
R
C
C
L
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
MRST
READY
LowSPD
RESET
LOGIC
READY
L
R
R
LowSPD
L
Note
1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
Document Number : 38-06069 Rev. *L
Page 2 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Contents
Pin Configuration .............................................................4
Pin Definitions ..................................................................5
Master Reset ...............................................................7
Mailbox Interrupts ........................................................7
Address Counter and Mask Register Operations.........8
Counter Reset Operation ............................................8
Counter Load Operation ..............................................8
Counter Increment Operation ......................................9
Counter Hold Operation ..............................................9
Counter Interrupt .........................................................9
Counter Readback Operation ......................................9
Retransmit ...................................................................9
Mask Reset Operation .................................................9
Mask Load Operation ..................................................9
Mask Readback Operation ..........................................9
Counting by Two .........................................................9
IEEE 1149.1 Serial Boundary Scan (JTAG) ...................11
Performing a TAP Reset ...........................................11
Performing a Pause/Restart ......................................11
Boundary Scan Hierarchy for FLEx72 Family ...........11
Maximum Ratings............................................................13
Operating Range .............................................................13
Electrical Characteristics Over the Operating Range .13
Capacitance .....................................................................14
AC Test Load and Waveforms .......................................14
Switching Characteristics Over the Operating Range 14
JTAG Timing Characteristics ........................................16
Switching Waveforms ....................................................16
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagram ............................................................27
Acronyms ........................................................................28
Document Conventions .................................................28
Units of Measure .......................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC Solutions .........................................................30
Document Number : 38-06069 Rev. *L
Page 3 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Pin Configuration
484-ball BGA
Top View
CYD04S72V/CYD09S72V/CYD18S72V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R NC
A
DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R
B
C
DQ65L DQ64L VSS
DQ67L DQ66L VSS
VSS
VSS
DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R
VSS
VSS
VSS DQ64R DQ65R
VSS DQ66R DQ67R
[2, 5]
[2, 5]
[2, 5]
[2, 5]
[2, 5]
VSS NC
NC
VSS LOWSP PORTS NC
BUSYL CNTINT PORTS NC NC
NC
VSS
NC
[2,4]
[2, 5]
DL
TD0L
L
TD1L
D
E
[2,4]
[10]
[2, 4]
DQ69L DQ68L VDDIOL VSS
VSS VDDIOL VDDIO VDDIO VDDIOL VDDIOL VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIOR
VSS VDDIOR DQ68R DQ69R
L
L
R
R
R
[8]
[9]
[9]
[8]
DQ71L DQ70L CE1L
CE0L
VDDIOL VDDIOL VDDIO VDDIO VDDIOL VCORE VCOREVCORE VCORE VDDIO VDDIO VDDIO VDDIOR VDDIOR CE0R
CE1R DQ70R DQ71R
F
G
H
J
L
L
R
R
R
[2,3]
[2,3
A0L
A2L
A4L
A6L
A8L
A1L RETL
BE4L VDDIOL VDDIOL VREFL VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VREFR VDDIOR VDDIOR BE4R RETR
A1R
A3R
A0R
A2R
A4R
A6R
A8R
[2, 4]
[2, 4]
]
[2,
[2,
A3L WRPL
BE5L VDDIOL VDDIOL VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIOR VDDIOR BE5R WRPR
3]
3]
A5L READYL BE6L VDDIOL VDDIOL VSS
[2, 5]
VSS VDDIOR VDDIOR BE6R READYR A5R
[2, 5]
[2,5]
[2,5]
A7L
A9L
NC
BE7L
OEL
VTTL VCORE VSS
VTTL VCORE VSS
VTTL VCORE VSS
VSS VCORE VDDIOR BE7R NC
A7R
A9R
K
L
CL
VSS VCORE VTTL
VSS VCORE VTTL
VSS VCORE VTTL
OER
CR
A10L A11L
VSS
BE3L
BE3R
VSS
A11R A10R
A13R A12R
M
N
P
R
T
[9]
[9]
A12L A13L ADSL
BE2L VDDIOL VCORE VSS
BE2R ADSR
A14L A15L CNT/MS BE1L VDDIOL VDDIOL VSS
VSS VDDIOR VDDIOR BE1R CNT/MS A15R A14R
[8]
[8]
KL
KR
A16L A17L CNTENL BE0L VDDIOL VDDIOL VSS
VSS VDDIOR VDDIOR BE0R CNTENR A17R A16R
[6]
[7]
[9]
[9]
[7]
[6]
A18L
[2,5]
NC CNTRST INTL VDDIOL VDDIOL VREFL VSS
VSS VREFR VDDIOR VDDIOR INTR CNTRST NC
A18R
[2,5]
[8]
[2, 4]
[2, 4]
[8]
L
R
[2,4
DQ35L DQ34L R/WL
REVL VDDIOL VDDIOL VDDIO VDDIO VDDIOL VCORE VCOREVCORE VCORE VDDIO VDDIO VDDIO VDDIOR VDDIOR REVR
R/WR DQ34R DQ35R
[2,4]
]
L
L
R
R
R
U
V
[2,
DQ33L DQ32L FTSELL VDDIOL
NC VDDIOL VDDIO VDDIO VDDIOL VTTL VTTL VTTL VDDIO VDDIO VDDIO VDDIO VDDIOR TRST VDDIOR FTSELR DQ32R DQ33R
[2,3]
5]
[2,3]
L
R
R
R
R
[2, 5]
[2, 5]
[2,
[2, 5]
[2, 5]
[2, 5]
DQ31L DQ30L VSS
DQ29L DQ28L VSS
MRST
VSS
VSS NC
NC
REVL PORTS CNTINT BUSYR NC
PORTS LOWSP VSS NC
NC
VSS
TDI
TDO DQ30R DQ31R
4]
[2, 5]
[2,4]
TD1R
R
TD0R DR
W
[2, 4]
[10]
[2,4]
DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS
TCK DQ28R DQ29R
Y
DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R
NC DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R NC
AA
AB
Notes
2. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for a 64K x 72 configuration.
7. Leave this ball unconnected for 128K x 72 and 64K x72 configurations.
8. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO.
9. These balls are not applicable for CYD18S72V device. They need to be tied to VSS.
10. These balls are not applicable for CYD18S72V device. They need to be no connected.
Document Number : 38-06069 Rev. *L
Page 4 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Pin Definitions
Left Port
Right Port
Description
A0L–A17L
A0R–A17R
Address inputs.
BE0L–BE7L
BE0R–BE7R
Byte enable inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
[11,12]
[11,12]
BUSYL
BUSYR
Port busy output. When the collision is detected, a BUSY is asserted.
Input clock signal.
CL
CR
[13]
[13]
CE0L
CE0R
Active low chip enable input.
[14]
[14]
CE1L
CE1R
Active high chip enable input.
DQ0L–DQ71L
OEL
DQ0R–DQ71R
OER
Data bus input/output.
Output enable input. This asynchronous signal must be asserted LOW to enable the
DQ data pins during Read operations.
INTL
INTR
Mailbox interrupt flag output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INTL is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
[11,15]
[11,15]
LowSPDL
LowSPDR
Port low speed select input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
[11,15
[11,15
PORTSTD[1:0]L
PORTSTD[1:0]R
Port address/control/data i/o standard select input.
]
]
R/WL
R/WR
Read/write enable input. Assert this pin LOW to write to, or HIGH to Read from the
dual-port memory array.
[11,12]
[11,12]
READYL
READYR
Port ready output. This signal will be asserted when a port is ready for normal
operation.
[14]
[14]
CNT/MSKL
CNT/MSKR
Port counter/mask select input. Counter control input.
Port counter address load strobe input. Counter control input.
Port counter enable input. Counter control input.
Port counter reset input. Counter control input.
[13]
[13]
ADSL
ADSR
[13]
[13]
[14]
CNTENL
CNTENR
[14]
CNTRSTL
CNTRSTR
[16]
[16]
CNTINTL
CNTINTR
Port counter interrupt output. This pin is asserted LOW when the unmasked portion
of the counter is incremented to all “1s”.
[11,17]
[11,17]
WRPL
WRPR
Port counter wrap input. After the burst counter reaches the maximum count, if WRP
is low, the unmasked counter bits will be set to 0. If high, the counter will be loaded with
the value stored in the mirror register.
[11,17]
[12,17]
RETL
RETR
Port counter retransmit input. Counter control input.
[11,17]
[11,17]
FTSELL
FTSELR
Flow-through select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
[11,15]
[11,15]
VREFL
VREFR
Port external high-speed io reference input.
Notes
11. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
12. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
13. These balls are not applicable for CYD18S72V device. They need to be tied to VSS.
14. These balls are not applicable for CYD18S72V device. They need to be tied to VDDIO.
15. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
16. These balls are not applicable for CYD18S72V device. They need to be no connected.
17. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales
Document Number : 38-06069 Rev. *L
Page 5 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Pin Definitions (continued)
Left Port
Right Port
Description
VDDIOL
VDDIOR
Port IO power supply.
REV[18,19]
REV[18,19]
Reserved pins for future features.
L
R
MRST
Master reset input. MRST is an asynchronous input signal and affects both ports. A
master reset operation is required at power-up.
TRST[18,20]
TMS
JTAG reset input.
JTAG test mode select input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
TDI
JTAG test data input. Data on the TDI input will be shifted serially into selected
registers.
TCK
TDO
JTAG test clock input.
JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground inputs.
[21]
VCORE
Core power supply.
LVTTL power supply.
VTTL
Notes
18. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
19. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales
20. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
21. This family of Dual-Ports does not use V
, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E™, will use V
of 1.5 V or 1.8
CORE
CORE
V. Please contact local Cypress FAE for more information
Document Number : 38-06069 Rev. *L
Page 6 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
operation by the left port to address 3FFFF will assert INTR LOW.
At least one byte has to be active for a write to generate an
interrupt. A valid Read of the 3FFFF location by the right port will
reset INTR HIGH. At least one byte has to be active in order for
a read to reset the interrupt. When one port writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to is
asserted LOW.
Master Reset
The FLEx72 family devices undergo a complete reset by taking
the MRST input LOW. MRST input can switch asynchronously to
the clocks. MRST initializes the internal burst counters to zero,
and the counter mask registers to all ones (completely
unmasked). MRST also forces the mailbox interrupt (INT) flags
and the Counter Interrupt (CNTINT) flags HIGH. MRST must be
performed on the FLEx72 family devices after power-up.
The INT is reset when the owner (port) of the mailbox reads the
contents of the mailbox. The interrupt flag is set in a flow-thru
mode (i.e., it follows the clock edge of the writing port). Also, the
flag is reset in a flow-thru mode (i.e., it follows the clock edge of
the reading port)
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18 Mbit device
as an example. The highest memory location, 3FFFF is the
mailbox for the right port and 3FFFE is the mailbox for the left
port. Table 2.shows that in order to set the INTR flag, a write
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Table 2. Interrupt Operation Example [22, 23, 24, 25]
Left Port
Function
Right Port
R/WL
CEL
A0L–17L
3FFFF
X
INTL
X
R/WR
CER
X
A0R–17R
X
INTR
L
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
L
X
X
H
L
X
H
L
X
X
L
3FFFF
3FFFE
X
H
X
X
L
L
X
Reset Left INTL Flag
L
3FFFE
H
X
X
X
Notes
22. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
23. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
0
1
can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
24. OE is “Don’t Care” for mailbox operation.
25. At least one of BE0 or BE7 must be LOW.
Document Number : 38-06069 Rev. *L
Page 7 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Table 3. Address Counter and Counter Mask Register Control Operation (Any Port) [26,27]
CLK MRST CNT/MSK CNTRST ADS CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask register
to all 1s
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s
H
Load counter with external address value presented
on address lines
H
H
H
H
H
H
H
H
H
L
H
H
H
L
Counter Readback Read out counter internal value on address lines
Counter Increment Internally increment address counter value
H
Counter Hold
Constantly hold the address value for multiple clock
cycles
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s
H
Load mask register with value presented on the
address lines
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address lines
H
Operation undefined
Address Counter and Mask Register Operations[28]
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
This section describes the features only apply to 4 Mbit and 9
Mbit devices, not to 18 Mbit device. Each port has a program-
mable burst address counter. The burst counter contains three
registers: a counter register, a mask register, and a mirror
register.
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH transition
of that port’s clock signal. This will Read/Write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and will loop
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
“0.” All masked bits remain unchanged. A Mask Reset followed
by a Counter Reset will reset the counter and mirror registers to
00000, as will master reset (MRST).
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset
operations, and by the MRST.
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Notes
26. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
27. Counter operation and mask register operation is independent of chip enables.
28. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF. The
CYD18S72V has 18 address bits and a maximum address value of 3FFFF.
Document Number : 38-06069 Rev. *L
Page 8 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1,” the next increment will wrap the
counter back to the initially loaded value. If an Increment results
in all the unmasked bits of the counter being “1s,” a counter
interrupt flag (CNTINT) is asserted. The next Increment will
return the counter register to its initial value, which was stored in
the mirror register. The counter address can instead be forced to
loop to 00000 by externally connecting CNTINT to CNTRST.[29]
An increment that results in one or more of the unmasked bits of
the counter being “0” will de-assert the counter interrupt flag. The
example in Figure 2 shows the counter mask register loaded with
a mask value of 0003Fh unmasking the first 6 bits with bit “0” as
the LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask register
to this value allows the counter to access the entire memory
space. The address counter is then loaded with an initial value
of 8h. The base address bits (in this case, the 6th address
through the 16th address) are loaded with an address value but
do not increment once the counter is configured for increment
operation. The counter address will start at address 8h. The
counter will increment its internal address value till it reaches the
mask register value of 3Fh. The counter wraps around the
memory block to location 8h at the next count. CNTINT is issued
when the counter reaches its maximum value.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n–1 or 2n–2. From
the most significant bit to the least significant bit, permitted
values have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1 shows
a block diagram of the operation.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the x72
devices as a 144-bit single port SRAM in which the counter of
one port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 144-bit data in even memory locations, and the
other half in odd memory locations.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCA2 after the next rising edge of the port’s clock. If address
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1 shows
a block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
Note
29. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document Number : 38-06069 Rev. *L
Page 9 of 30
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CYD09S72V
CYD18S72V
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[30]
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
17
From
Increment
Logic
Mask
Register
17
Wrap
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Detect
Wrap
1
0
17
1
0
To
Counter
Note
30. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
Document Number : 38-06069 Rev. *L
Page 10 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Figure 2. Programmable Counter-Mask Register Operation[31, 32]
CNTINT
Example:
Load
Counter-Mask
Register = 3F
H
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1 1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
IEEE 1149.1 Serial Boundary Scan (JTAG)[33]
registers. The circuity and operation of the DIE boundary scan
are described in detail below. The scan chain of each DIE is
connected serially to form the scan chain of the FLEx72 family
as shown in Figure 3. TMS and TCK are connected in parallel to
each DIE to drive all 4 TAP controllers in unison. In many cases,
each DIE will be supplied with the same instruction. In other
cases, it might be useful to supply different instructions to each
DIE. One example would be testing the device ID of one DIE
while bypassing the others.
The FLEx72 incorporates an IEEE 1149.1 serial boundary scan
test access port (TAP). The TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1-compliant
TAPs.
The
TAP
operates
using
JEDEC-standard 3.3 V I/O logic levels. It is composed of three
input connections and one output connection required by the test
logic defined by the standard.
Each pin of FLEx72 family is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs as well
as the external connections to the package. This can be
accomplished by merging the netlist of the devices with the
netlist of the user’s circuit board. To facilitate boundary scan
testing of the devices, Cypress provides the BSDL file for each
DIE, the internal netlist of the device, and a description of the
device scan chain. The user can use these materials to easily
integrate the devices into the board’s boundary scan
environment. Further information can be found in the Cypress
application note Using JTAG Boundary Scan with the
FLEx18/72TM Dual-Port SRAMs.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
FLEx72 family and may be performed while the device is
operating. An MRST must be performed on the FLEx72 after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain will output the next bit in the chain twice. For example, if
the value expected from the chain is 1010101, the device will
output a 11010101. This extra bit will cause some testers to
report an erroneous failure for the FLEx72 in a scan test.
Therefore the tester should be configured to never enter the
PAUSE-DR state.
Boundary Scan Hierarchy for FLEx72 Family
Internally, the CYD04S72V and CYD09S72V have two DIEs
while CYD18S72V has four DIEs. Each DIE contains all the
circuitry required to support boundary scan testing. The circuitry
includes the TAP, TAP controller, instruction register, and data
Notes
31. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
32. The “X” in this diagram represents the counter upper bits.
33. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document Number : 38-06069 Rev. *L
Page 11 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Figure 3. Scan Chain
18 Mbit
4 Mbit/9 Mbit
TDO
TDO
TDO
D4
TDI
TDO
D2
TDI
TDO
D2
TDI
TDO
D3
TDI
TDO
D1
TDI
TDO
D1
TDI
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Revision number(31:28)
Cypress device(27:12)
Value
0h
Description
Reserved for version number
C002h
Defines Cypress DIE number for CYD18S72V and
CYD09S72V
C001h
034h
1
Defines Cypress DIE number for CYD04S72V
Allows unique identification of FLEx72 family device vendor
Indicates the presence of an ID register
Cypress JDEC ID(11:1)
ID register presence (0)
Table 5. Scan Registers Sizes
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary scan
32
n[34]
Table 6. Instruction Identification Codes
Instruction
EXTEST
Code
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO
Places the BYR between TDI and TDO
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO
Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state
Controls boundary to 1/0. Places BYR between TDI and TDO
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO
Resets the non-boundary scan logic. Places BYR between TDI and TDO
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above
Note
34. See details in the device BSDL files.
Document Number : 38-06069 Rev. *L
Page 12 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Maximum Ratings[35]
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage...........................................> 2000 V
(JEDEC JESD22-A114-2000B)
(Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested)
Latch-up current .....................................................> 200 mA
Storage temperature............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Operating Range
Ambient
[36]
Range
VDD
VCORE
Supply voltage to ground potential ..............–0.5 V to + 4.6 V
Temperature
DC Voltage Applied to
Outputs in High-Z state........................ –0.5 V to VDD + 0.5 V
DC input voltage............................. –0.5 V to VDD + 0.5 V[37]
Commercial 0 °C to +70 °C 3.3 V ± 165 mV 1.8 V ± 100 mV
Industrial –40 °C to +85 °C 3.3 V ± 165 mV 1.8 V ± 100mV
Electrical Characteristics Over the Operating Range
–167
–133
Typ
–
–100
Typ
–
Parameter
Description
Part No.
Unit
Min
Typ
Max Min
Max
Min
Max
VOH
Output HIGH voltage (VDD = Min., IOH
–4.0 mA)
=
2.4
–
–
2.4
–
2.4
–
V
VOL
Output LOW voltage (VDD = Min., IOL= +4.0
mA)
–
–
0.4
–
–
0.4
–
–
0.4
V
VIH
VIL
IOZ
IIX1
Input HIGH voltage
Input LOW voltage
Output leakage current
2.0
–
–
–
–
–
–
2.0
–
–
–
–
–
–
2.0
–
–
–
–
–
–
V
V
0.8
10
10
0.8
10
10
0.8
10
10
–10
–10
–10
–10
–10
–10
A
A
Input leakage current except TDI, TMS,
MRST
IIX2
ICC
Input leakage current TDI, TMS, MRST
–0.1
–
225
–
1.0
300
–
–0.1
–
1.0
–
–0.1
–
–
1.0
–
mA
mA
Operating current
(VDD = Max.,IOUT = 0 mA),
outputs disabled
CYD04S72V
CYD09S72V
CYD18S72V
CYD04S72V
CYD09S72V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
350
410
500
580
–
–
–
–
315
–
450
–
mA
mA
ISB1
ISB2
ISB3
ISB4
ISB5
Standby current
(both ports TTL level)
CEL and CER VIH, f = fMAX
90
–
115
–
105
266
55
150
380
75
–
–
Standby current
(one port TTL level)
CEL | CER VIH, f = fMAX
CYD04S72V
CYD09S72V
–
–
160
–
210
–
–
–
–
–
–
–
–
–
mA
mA
mA
mA
mA
Standby current (both ports CYD04S72V
–
–
55
–
75
–
–
–
–
–
–
–
–
–
CMOS level) CEL and CER
VDD – 0.2V, f = 0
CYD09S72V
Standby current
(one port CMOS level)
CEL | CER VIH, f = fMAX
CYD04S72V
CYD09S72V
–
–
160
–
210
–
–
–
–
–
–
–
–
75
0
224
320
75
Operating current (VDDIO CYD18S72V
= Max, Iout = 0 mA, f = 0)
outputs disabled
–
–
–
–
–
–
[36]
ICORE
Core operating current for (VDD = Max.,
–
0
0
–
0
0
–
0
I
OUT = 0 mA), outputs disabled
Notes
35. The voltage on any input or I/O pin can not exceed the power pin during power-up.
36. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E™, will use VCORE of 1.5 V or
1.8 V. Please contact local Cypress FAE for more information.
37. Pulse width < 20 ns.
Document Number : 38-06069 Rev. *L
Page 13 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Capacitance[38]
Part#
Parameter
Description
Input capacitance
Test Conditions
Max
Unit
pF
CYD04S72V CIN
CYD09S72V
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V
20
10[39]
40
COUT
Output capacitance
Input capacitance
Output capacitance
pF
CYD18S72V CIN
COUT
pF
20
pF
AC Test Load and Waveforms
3.3 V
Z0 = 50
R = 50
OUTPUT
R1 = 590
OUTPUT
C = 5 pF
C = 10 pF
R2 = 435
VTH = 1.5 V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0 V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
–167
–133
–100
CYD18S72V
Parameter
Description
CYD04S72V
CYD09S72V
CYD18S72V
Unit
Min
–
Max
167
–
Min
–
Max
133
–
Min
–
Max
133
–
Min
–
Max
100
–
fMAX2
tCYC2
tCH2
Maximum operating frequency
Clock cycle time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.7
2.7
–
7.5
3.0
3.0
–
7.5
3.4
3.4
–
10
Clock HIGH time
–
–
–
4.5
4.5
–
–
tCL2
Clock LOW time
–
–
–
–
[40]
tR
Clock rise time
2.0
2.0
–
2.0
2.0
–
2.0
2.0
–
3.0
3.0
–
[40]
tF
Clock fall time
–
–
–
–
tSA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
tHD
Address set-up time
Address hold time
Byte select set-up time
Byte select hold time
Chip enable set-up time
Chip enable hold time
R/W set-up time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.2
1.0
2.2
1.0
NA
NA
2.2
1.0
2.2
1.0
2.7
1.0
2.7
1.0
NA
NA
2.7
1.0
2.7
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W hold time
–
–
–
–
Input data set-up time
Input data hold time
–
–
–
–
–
–
–
–
Notes
38. C
also references C
I/O.
OUT
39. Except INT and CNTINT which are 20 pF.
40. Except JTAG signal (t and t < 10 ns max).
R
F
Document Number : 38-06069 Rev. *L
Page 14 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Characteristics Over the Operating Range (continued)
–167
–133
–100
Parameter
Description
CYD04S72V
CYD09S72V
CYD18S72V
CYD18S72V
Unit
Min
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
–
Max
–
Min
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
–
Max
–
Min
NA
NA
NA
NA
NA
NA
NA
NA
–
Max
–
Min
NA
NA
NA
NA
NA
NA
NA
NA
–
Max
–
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
tHCM
tOE
ADS set-up time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADS hold time
–
–
–
–
CNTEN set-up time
CNTEN hold time
–
–
–
–
–
–
–
–
CNTRST set-up time
CNTRST hold time
CNT/MSK set-up time
CNT/MSK hold time
Output enable to data valid
OE to Low Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4.0
–
4.4
–
5.5
–
5.5
–
[41, 42]
tOLZ
0
0
0
0
[41, 42]
tOHZ
OE to High Z
0
4.0
4.0
4.0
4.0
0
4.4
4.4
4.4
4.4
0
5.5
5.0
NA
NA
0
5.5
5.2
NA
NA
tCD2
tCA2
tCM2
Clock to data valid
Clock to counter address valid
–
–
–
–
–
–
–
–
Clock to mask register readback
valid
–
–
–
–
tDC
Data output hold after clock
HIGH
1.0
–
1.0
–
1.0
–
1.0
–
ns
[41, 42]
tCKHZ
Clock HIGH to output High Z
Clock HIGH to output Low Z
Clock to INT set time
0
4.0
4.0
6.7
6.7
5.0
5.0
0
4.4
4.4
7.5
7.5
5.7
5.7
0
4.7
4.7
7.5
7.5
NA
NA
0
5.0
5.0
10
ns
ns
ns
ns
ns
ns
[41, 42]
tCKLZ
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
tSINT
tRINT
Clock to INT reset time
10
tSCINT
tRCINT
Clock to CNTINT set time
Clock to CNTINT reset time
NA
NA
Port to Port Delays
tCCS
Clock to clock skew
5.2
–
6.0
–
5.7
–
8.0
–
ns
Master Reset Timing
tRS
Master reset pulse width
5.0
6.0
5.0
–
–
–
5.0
6.0
5.0
–
–
–
5.0
6.0
5.0
–
–
–
5.0
8.5
5.0
–
–
–
cycles
ns
tRSS
Master reset set-up time
tRSR
Master reset recovery time
Master Reset to outputs inactive
–
–
–
–
cycles
ns
tRSF
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
tRSCNTINT
Master reset to counter interrupt
flag reset time
–
–
–
–
ns
Notes
41. This parameter is guaranteed by design, but is not production tested.
42. Test conditions used are Load 2.
Document Number : 38-06069 Rev. *L
Page 15 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
JTAG Timing Characteristics
CYD04S72V
CYD09S72V
CYD18S72V
Parameter
Description
Unit
–167/–133/–100
Min
Max
10
–
fJTAG
tTCYC
tTH
Maximum JTAG TAP controller frequency
TCK clock cycle time
–
100
40
40
10
10
10
10
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock HIGH time
–
tTL
TCK clock LOW time
–
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS set-up to TCK clock rise
TMS hold after TCK clock rise
TDI set-up to TCK clock rise
TDI hold after TCK clock rise
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
–
–
–
30
–
0
Switching Waveforms
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document Number : 38-06069 Rev. *L
Page 16 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 4. Master Reset
tRS
MRST
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
CNTINT
INT
TDO
Figure 5. Read Cycle[43, 44, 45, 46, 47]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE7
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes
43. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
0
1
can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
44. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
45. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
46. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
47. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document Number : 38-06069 Rev. *L
Page 17 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 6. Bank Select Read[48, 49]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Figure 7. Read-to-Write-to-Read (OE = LOW)[47, 50, 51, 52, 53]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+2
tSD tHD
Dn+2
An+3
ADDRESS
DATAIN
tSA
tHA
tCD2
tDC
tCKHZ
Qn
DATAOUT
WRITE
NO OPERATION
READ
Notes
48. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx72 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
49. ADS = CNTEN = BE0 – BE7 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
50. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
51. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
52. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
53. CE = BE0 – BE7 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document Number : 38-06069 Rev. *L
Page 18 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 8. Read-to-Write-to-Read (OE Controlled)[54, 55, 56, 57]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Figure 9. Read with Address Counter Advance[56]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Notes
54. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
55. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
56. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH
0
1
57. CE = BE0 – BE7 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document Number : 38-06069 Rev. *L
Page 19 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 10. Write with Address Counter Advance [58]
t
CYC2
t
t
CH2
CL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Note
58. CE = BE0 – BE7 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document Number : 38-06069 Rev. *L
Page 20 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 11. Counter Reset [59, 60]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
tSD
DATAIN
D0
tCD2
tCD2
[72]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS An
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS Am
Notes
59. CE = BE0 – BE7 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
60. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document Number : 38-06069 Rev. *L
Page 21 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 12. Readback State of Address Counter or Mask Register[61, 62, 63, 64]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A17
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
EXTERNAL
ADDRESS
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Notes
61. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
62. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
63. Address in input mode. Host can drive address bus after t
.
CKHZ
64. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document Number : 38-06069 Rev. *L
Page 22 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 13. Left_Port (L_Port) Write to Right_Port (R_Port) Read[65, 66, 67]
tCYC2
tCL2
tCH2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
ADDRESS
An
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes
65. CE = OE = ADS = CNTEN = BE0 – BE7 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
66. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data will be Read out.
CCS
67. If t
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If
CCS
CYC2
CD2
t
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CCS
CYC2
CD2
Document Number : 38-06069 Rev. *L
Page 23 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Switching Waveforms (continued)
Figure 14. Counter Interrupt and Retransmit[68, 69, 70, 71, 72]
tCYC2
tCL2
tCH2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
1FFFE
tSCINT
1FFFC
Last_Loaded
1FFFD
1FFFF
tRCINT
Last_Loaded +1
CNTINT
Figure 15. Mailbox Interrupt Timing[73, 74, 75, 76, 77]
tCYC2
tCL2
tCH2
CLKL
tSA tHA
3FFFF
L_PORT
ADDRESS
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
ADDRESS
Am+1
3FFFF
Am+3
Am+4
Notes
68. CE = OE = BE0 – BE7 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
69. CNTINT is always driven.
70. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
71. The mask register assumed to have the value of 1FFFFh.
72. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
73. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
74. Address “1FFFF” is the mailbox location for R_Port.
75. L_Port is configured for Write operation, and R_Port is configured for Read operation.
76. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
77. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
Document Number : 38-06069 Rev. *L
Page 24 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Table 7. Read/Write and Enable Operation (Any Port) [78, 79, 80, 81, 82]
Inputs
Outputs
DQ0 – DQ71
High-Z
Operation
OE
CLK
CE0
CE1
R/W
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
X
DOUT
High-Z
Read
H
X
Outputs disabled
Notes
78. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
79. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
80. OE is an asynchronous input signal.
81. When CE changes state, deselection and Read happen after one cycle of latency.
82. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document Number : 38-06069 Rev. *L
Page 25 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Ordering Information
Speed
(MHz)
Ordering Code
Package Name
Package Type
Operating Range
256K × 72 (18-Mbit) 3.3 V Synchronous CYD18S72V Dual-Port SRAM
133
100
CYD18S72V-133BBC
CYD18S72V-133BBI
CYD18S72V-100BBC
CYD18S72V-100BBI
BB484
BB484
BB484
BB484
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
Commercial
Industrial
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
Commercial
Industrial
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
128K
× 72 (9-Mbit) 3.3 V Synchronous CYD09S72V Dual-Port SRAM
133
CYD09S72V-133BBC
BB484
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
Commercial
Commercial
64K x 72 (4-Mbit) 3.3 V Synchronous CYD04S72V Dual-Port SRAM
167
CYD04S72V-167BBC
BB484
484-ball Ball Grid Array
23 mm × 23 mm with 1.0-mm pitch (FBGA)
Ordering Code Definitions
CY D XX 72 V - XXX BB
S
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type:
BB = 484-ball BGA
Speed Grade: XXX = 100 MHz / 133 MHz / 167 MHz
V = 3.3 V
72 = Width: × 72
S = Sync
XX = Density: 04 = 4 Mb; 09 = 9 Mb; 18 = 18 Mb
D = Dual Port SRAM
CY = Cypress Device
Document Number : 38-06069 Rev. *L
Page 26 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Package Diagram
51-85124 *G
Document Number : 38-06069 Rev. *L
Page 27 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Acronyms
Acronym
CMOS
FBGA
Description
Complementary metal oxide semiconductor
fine-pitch ball grid array
joint test action group
JTAG
OE
Output enable
RAM
Random access memory
Document Conventions
Units of Measure
Symbol
ns
Unit of Measure
nano seconds
Volts
V
µA
mA
mV
mW
MHz
pF
micro Amperes
milli Amperes
milli Volts
milli Watts
Mega Hertz
pico Farad
degree Celcius
Watts
°C
W
Document Number : 38-06069 Rev. *L
Page 28 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Document History Page
Document Title: CYD04S72V / CYD09S72V / CYD18S72V FLEx72™ 3.3 V 64 K/128 K/256 K × 72 Synchronous Dual-Port
RAM
Document Number: 38-06069
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
125859
128707
06/17/03
08/01/03
SPN
New Data Sheet
*A
SPN
Added -133 speed bin
Updated spec values for ICC, tHA, HB, HW, HD
t
t
t
Added new parameter ICC1
Added bank select read and read to write to read (OE=low) timing diagrams
*B
128997
09/18/03
SPN
Updated spec values for tOE, tOHZ, CH2, CL2, HA, HB, HW, HD, CC, SB5, SA,
tSB, SW, SD, CD2
Updated read to write (OE=low) timing diagram
Updated Master Reset values for tRS, RSR, RSF
t
t
t
t
t
t
I
I
t
t
t
t
t
t
Updated pinout
Updated VCORE voltage range
*C
*D
129936
233830
09/30/03
See ECN
SPN
Updated package diagram
Updated tCD2 value on first page
Removed Preliminary status
WWZ
Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout,
pin description table, power table, and timing table
Changed title
Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices
Removed FLEx72-E from the document
Added counter related functions for 4 Mbit and 9 Mbit
Removed standard JTAG description
Updated block diagram
Updated pinout with FTSEL and one more PORTSTD pins per port
Updated tRSF of CYD18S72V value
*E
*F
288892
327355
See ECN
See ECN
WWZ
AEQ
Change pinout D15 from REV[2,4] to VSS to reflect SC pin removal
Changed pinout K3 from NC to NC[2,5]
Changed pinout K20 from NC to NC[2,5]
Changed pinout D15 from VSS to NC
Changed pinout D8 and M3 from REVL[2,4] to VSS
Changed pinout M20 and W15 from REVR[2,4] to VSS
*G
*H
345735
360316
See ECN
See ECN
PCX
YDT
VREF Pin Definition Updated
Added Pb-Free Part Ordering Informations
Added note for VCORE
Changed notes for PORTSTD to VSS
Changed ICC, ISB1, ISB2 and ISB4 number for CYD09S72V per PE request
*I
460454
See ECN
07/01/10
YDT
AJU
Changed CYDxxS72AV to CYDxxS72V (rev. A not implemented)
*J
2898491
Removed inactive parts from Ordering Information.
Updated Packaging Information
*K
*L
3110296 12/14/2010
3265044 05/25/2011
ADMU
ADMU
Updated Ordering Information.
Added Ordering Code Definitions.
Updates link to Application note.
Removed obsolete part information.
Notes updated across datasheet as per template.
Added Acronyms and Units of measure table.
Document Number : 38-06069 Rev. *L
Page 29 of 30
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CYD04S72V
CYD09S72V
CYD18S72V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-06069 Rev. *L
Revised May 25, 2011
Page 30 of 30
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