CYD01S36V_08 [CYPRESS]
FLEx36⑩ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM; FLEx36⑩ 3.3V 32K / 64K / 128K / 256K / 512 ×36同步双端口RAM
| 型号： | CYD01S36V_08 |
| 厂家： | 
CYPRESS |
| 描述： | FLEx36⑩ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| 文件： | 总28页 (文件大小：623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
Features
Functional Description
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. A particular port can write to a certain location while
another port is reading that location. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow for
minimal setup and hold time.
■ Synchronous pipelined operation
■ Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18 micron CMOS for optimum speed and power
■ High-speed clock to data access
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
■ 3.3V low power
❐ Active as low as 225 mA (typ.)
❐ Standby as low as 55 mA (typ.)
■ Mailbox function for message passing
■ Global master reset
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible JTAG boundary scan
■ 256 Ball FBGA (1-mm pitch)
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Operations[19]
on page 5 for details.
■ Counter readback on address lines
■ Mask register readback on address lines
■ Dual Chip Enables on both ports for easy depth expansion
■ Seamless migration to next-generation dual-port family
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Table 1. Product Selection Guide
1 Mbit
2 Mbit
4 Mbit
9 Mbit
18 Mbit
Density
(32K x 36)
CYD01S36V
167
(64K x 36)
CYD02S36V
167
(128K x 36)
(256K x 36)
(512K x 36)
Part Number
CYD04S36V
CYD09S36V
CYD18S36V
Max. Speed (MHz)
167
4.0
167
4.0
133
5.0
Max. Access Time – Clock to Data
(ns)
4.0
4.4
Typical Operating Current (mA)
Package
225
225
225
270
315
256 FBGA
256 FBGA
256 FBGA
256 FBGA
256 FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 12, 2008
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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Logic Block Diagram[1]
FTSEL
L
FTSEL
R
CONFIG Block
CONFIG Block
PORTSTD[1:0]
PORTSTD[1:0]
L
R
DQ [35:0]
R
DQ [35:0]
L
BE [3:0]
BE [3:0]
R
L
CE0
CE1
CE0
R
L
IO
Control
IO
Control
CE1
R
L
OE
OE
R
L
R/W
R/W
R
L
Dual Ported Array
Arbitration Logic
BUSY
BUSY
L
R
A [18:0]
A [18:0]
L
R
CNT/MSK
CNT/MSK
L
R
ADS
ADS
L
R
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
RET
R
L
CNTINT
L
CNTINT
R
C
C
L
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
MRST
READY
LowSPD
RESET
LOGIC
READY
L
R
R
LowSPD
L
Note
1. 18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has
15 address bits.
Document Number: 38-06076 Rev. *F
Page 2 of 28
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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Pin Configurations
Figure 1. Pin Diagram - 256-Ball FBGA (Top View)
CYD01S36V/CYD02S36V/CYD04S36V/CYD09S36V/CYD18S36V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ32L
DQ30L
DQ28L
DQ26L
DQ24L
DQ22L
DQ20L
DQ18L
DQ18R
DQ20R
DQ22R
DQ24R
DQ26R
DQ28R
DQ30R
DQ32R
A
B
C
D
E
F
DQ33L
DQ34L
A0L
DQ31L
DQ35L
A1L
DQ29L
DQ27L
INTL
DQ25L
DQ23L
DQ21L
DQ19L
DQ19R
MRST
VTTL
VCORE
VSS
DQ21R
DQ23R
DQ25R
DQ27R
INTR
DQ29R
DQ31R
DQ35R
A1R
DQ33R
DQ34R
A0R
NC
[2,5]
NC
[2,5]
NC
[2,5]
NC
[2,5]
NC
[2,5]
RETL [2,3]
REVL [2,4] TRST [2,5]
RETR [2,3]
WRPR [2,3]
CE0R [11]
LOWSPDL
[2,4]
LOWSPDR
[2,4]
WRPL
[2,3]
VREFL
[2,4]
FTSELL
[2,3]
FTSELR
[2,3]
VREFL
[2,4]
VSS
VDDIOL
VSS
VTTL
VCORE
VSS
VSS
VDDIOR
VSS
A2L
A3L
CE0L [11]
CE1L [10]
BE3L
VDDIOL
VDDIOL
VDDIOL
VSS
VDDIOR
VSS
VDDIOR
VDDIOR
VDDIOR
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CE1R [10]
BE3R
A3R
A2R
CNTINTL
[12]
CNTINTR
[12]
A4L
A5L
A5R
A4R
BUSYR
[2,5]
BUSYL
[2,5]
REVL
[2,3]
A6L
A7L
BE2L
VSS
VSS
VSS
VSS
VSS
VSS
BE2R
A7R
A6R
G
H
J
A8L
A9L
CL
VTTL
VCORE
VCORE
VDDIOL
VDDIOL
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VTTL
CR
A9R
A8R
PORTSTD1
L[2,4]
PORTSTD1
R[2,4]
A10L
A12L
A14L
A11L
A13L
VSS
OEL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OER
A11R
A13R
A10R
A12R
A14R
BE1L
BE0L
VSS
VSS
VSS
VSS
VSS
VSS
BE1R
BE0R
K
L
A15L
[6]
ADSL
[11]
ADSR
[11]
A15R
[6]
VSS
VSS
VSS
VSS
VSS
VSS
A16L
[7]
A17L
[8]
A17R
[8]
A16R
[7]
R/WL
REVL [2,4]
VDDIOL
VDDIOL
VCORE
VTTL
TMS
VCORE
VTTL
TDO
VDDIOR
VDDIOR
REVR [2,4]
R/WR
M
N
P
R
T
CNT/MSKL
[10]
READYL
[2,5]
READYR
[2,5]
CNT/MSKR
[10]
A18L
[9]
A19L
[2,5]
VREFL
[2,4]
PortSTD0L
[2,4]
REVL
[2,3]
REVR
[2,3]
PortSTD0R
[2,4]
VREFR
[2,4]
A18R
[9]
A19R [2,5]
DQ17R
CNTENL
[11]
CNTRSTL
[10]
CNTRSTR
[10]
CNTENR
[11]
NC
[2,5]
NC
[2,5]
NC
[2,5]
NC
[2,5]
DQ16L
DQ15L
DQ14L
DQ17L
DQ13L
DQ12L
TCK
DQ3L
DQ2L
TDI
DQ16R
DQ15R
DQ14R
DQ11L
DQ10L
DQ9L
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
DQ1L
DQ0L
DQ1R
DQ0R
DQ3R
DQ2R
DQ5R
DQ4R
DQ7R
DQ6R
DQ9R
DQ8R
DQ11R
DQ10R
DQ13R
DQ12R
Notes
2. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for 32K x 36configuration.
7. Leave this ball unconnected for a 64K x 36, 32K x 36 configurations.
8. Leave this ball unconnected for a 128K x 36, 64K x 36 and 32K x 36 configurations.
9. Leave this ball unconnected for a 256K x 36, 128K x 36, 64K x 36, and 32K x 36 configurations.
10. These balls are not applicable for CYD18S36V device. They need to be tied to VDDIO.
11. These balls are not applicable for CYD18S36V device. They need to be tied to VSS.
12. These balls are not applicable for CYD18S36V device. They need to be no connected.
Document Number: 38-06076 Rev. *F
Page 3 of 28
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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Pin Definitions
Left Port
Right Port
A0R–A18R
Description
A0L–A18L
Address Inputs.
BE0L–BE3L
BE0R–BE3R
Byte Enable Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
[2,5]
[2,5]
BUSYL
BUSYR
Port Busy Output. When the collision is detected, a BUSY is asserted.
Input Clock Signal.
CL
CR
[11]
[11]
CE0L
CE0R
Active Low Chip Enable Input.
[10]
[10]
CE1L
CE1R
Active High Chip Enable Input.
DQ0L–DQ35L
OEL
DQ0R–DQ35R
OER
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An interrupt
to a port is deasserted HIGH when it reads the contents of its mailbox.
[2,4]
[2,4]
LowSPDL
LowSPDR
Port Low Speed Select Input.
[2,4]
[2,4]
PORTSTD[1:0]L
R/WL
PORTSTD[1:0]R
R/WR
Port Address/Control/Data IO Standard Select Inputs.
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
[2,5]
[2,5]
READYL
READYR
Port Ready Output. This signal is asserted when a port is ready for normal operation.
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
[10]
[10]
CNT/MSKL
CNT/MSKR
[11]
[11]
ADSL
ADSR
[11]
[11]
CNTENL
CNTENR
[10]
[10]
CNTRSTL
CNTRSTR
Port Counter Reset Input. Counter control input.
[12]
[12]
CNTINTL
CNTINTR
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of
the counter is incremented to all “1s”.
[2,3]
[2,3]
WRPL
WRPR
Port Counter Wrap Input. The burst counter wrap control input.
Port Counter Retransmit Input. Counter control input.
[2,3]
[2,3]
RETL
RETR
[2,3]
[2,3]
FTSELL
FTSELR
Flow-Through Select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
[2,4]
[2,4]
VREFL
VDDIOL
VREFR
VDDIOR
Port External High-Speed IO Reference Input.
Port IO Power Supply.
[2, 3, 4]
[2, 3, 4]
REVL
REVR
Reserved pins for future features.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. A
maser reset operation is required at power up.
TRST[2,5]
TMS
JTAG Reset Input.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
TCK
TDO
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
[13]
VCORE
VTTL
Core Power Supply.
LVTTL Power Supply for JTAG IOs
Document Number: 38-06076 Rev. *F
Page 4 of 28
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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Master Reset
Address Counter and Mask Register
Operations[19]
The FLEx36 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx36 family devices after
power up.
This section describes the features only apply to 1Mbit, 2 Mbit,
4 Mbit and 9 Mbit devices. It does not apply to 18Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Mailbox Interrupts
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.l
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CYD18S36V. The
highest memory location, 7FFFF is the mailbox for the right port
and 7FFFE is the mailbox for the left port. Table 2 shows that to
set the INTR flag, a Write operation by the left port to address
7FFFF asserts INTR LOW. At least one byte must be active for a
Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active in order for a Read to reset the interrupt. When
one port Writes to the other port’s mailbox, the INT of the port
that the mailbox belongs to is asserted LOW. The INT is reset
when the owner (port) of the mailbox Reads the contents of the
mailbox. The interrupt flag is set in a flow-thru mode (i.e., it
follows the clock edge of the writing port). Also, the flag is reset
in a flow-thru mode (i.e., it follows the clock edge of the reading
port).
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3 on page 6 summarizes the operation of these registers
and the required input control signals. The MRST control signal
is asynchronous. All the other control signals in Table 3 on page
6 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins must be left open.
Table 2. Interrupt Operation Example [1, 14, 15, 16, 17, 18]
Left Port
Function
Right Port
R/WL
CEL
L
A0L–18L
7FFFF
X
INTL
X
R/WR
CER
X
A0R–18R
X
INTR
L
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
L
X
X
H
X
H
L
X
X
L
7FFFF
7FFFE
X
H
X
X
L
L
X
Reset Left INTL Flag
L
7FFFE
H
X
X
X
Notes
13. This family of Dual-Ports does not use V
, and these pins are internally NC. The next generation Dual-Port family, the FLEx36-E™, uses V
of 1.5V or 1.8V.
CORE
CORE
Please contact local Cypress FAE for more information.
14. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
0
1
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
15. OE is “Don’t Care” for mailbox operation.
16. At least one of BE0, BE1, BE2, or BE3 must be LOW.
17. A17x is a NC for CYD04S36V, therefore the Interrupt Addresses are 1FFFF and 1FFFE. A17x and A16x are NC for CYD02S36V, therefore the Interrupt Addresses
are FFFF and FFFE; A17x, A16x and A15x are NC for CYD01S36V, therefore the Interrupt Addresses are 7FFF and 7FFE.
18. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
19. This section describes the CYD09S36V, CYD04S36V, CYD02S36V, and CYD01S36V which have 18, 17, 16 and 15 address bits.
Document Number: 38-06076 Rev. *F
Page 5 of 28
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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This Read’s or Write’s one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
“0.” All masked bits remain unchanged. A Mask Reset followed
by a Counter Reset resets the counter and mirror registers to
00000, as does master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 20]
CLK MRST CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantlyholdtheaddressvalueformultiple
clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
H
Operation undefined
Note
20. Counter operation and mask register operation is independent of chip enables.
Document Number: 38-06076 Rev. *F
Page 6 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 2 on page 8 shows a
block diagram of the operation.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1,” the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being “1s,” a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT to CNTRST.[21] An increment that
results in one or more of the unmasked bits of the counter being
“0” de-asserts the counter interrupt flag. The example in Figure
3 on page 9 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB
and bit “16” as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
once the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value till it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment opera-
tions. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
7FFFF, 003FE, and 00001 are permitted values, but 7F0FF,
003FC, and 00000 are not.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid tCM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 2 on page 8 shows a
block diagram of the operation.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the x36
devices as a 72-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 72-bit data in even memory locations, and the
other half in odd memory locations.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
Note
21. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document Number: 38-06076 Rev. *F
Page 7 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Figure 2. Counter, Mask, and Mirror Logic Block Diagram[1]
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
Register
17
Wrap
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Detect
Wrap
To
1
0
17
1
0
Counter
Document Number: 38-06076 Rev. *F
Page 8 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Figure 3. Programmable Counter-Mask Register Operation[1, 22]
CNTINT
Example:
Load
Counter-Mask
Register = 3F
H
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
IEEE 1149.1 Serial Boundary Scan (JTAG)[23]
Boundary Scan Hierarchy for 9-Mbit and 18-Mbit
Devices
The FLEx36 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V IO logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Internally, the devices have multiple DIEs. Each DIE contains all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below.
The scan chain for 9-Mbit and 18-Mbit devices uses a hierar-
chical approach as shown in Figure 4 on page 10 and Figure 5
on page 10. TMS and TCK are connected in parallel to each DIE
to drive all 2- or 4-TAP controllers in unison. In many cases, each
DIE is supplied with the same instruction. In other cases, it might
be useful to supply different instructions to each DIE. One
example would be testing the device ID of one DIE while
bypassing the rest.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
Each pin of the devices is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This can be accom-
plished by merging the netlist of the devices with the netlist of the
user’s circuit board. To facilitate boundary scan testing of the
devices, Cypress provides the BSDL file for each DIE, the
internal netlist of the device, and a description of the device scan
chain. The user can use these materials to easily integrate the
devices into the board’s boundary scan environment. Further
information can be found in the Cypress application note Using
JTAG Boundary Scan For System in a Package (SIP) Dual-Port
SRAMs.
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester must be configured to never enter the PAUSE-DR state.
Notes
22. The “X” in this diagram represents the counter upper bits.
23. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document Number: 38-06076 Rev. *F
Page 9 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Figure 4. Scan Chain for 18-Mbit Device
TDO
TDO
D4
TDI
TDO
D2
TDI
TDO
D3
TDI
TDO
D1
TDI
TDI
Figure 5. Scan Chain for 9-Mbit Device
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Value
Description
0h
Reserved for version number.
C002h
C001h
C092h
034h
1
Defines Cypress part number for CYD04S36V, CYD09S36V and CYD18S36V
Defines Cypress part number for CYD02S36V
Defines Cypress part number for CYD01S36V
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Table 5. Scan Register Sizes
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary Scan
32
n[24]
Note
24. See details in the device BSDL files.
Document Number: 38-06076 Rev. *F
Page 10 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Table 6. Instruction Identification Codes
Instruction Code
EXTEST
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Document Number: 38-06076 Rev. *F
Page 11 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
Maximum Ratings
Exceeding maximum ratings[25] may shorten the useful life of the
device. User guidelines are not tested.
Latch-up Current.....................................................> 200 mA
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
Ambient
Temperature
[13]
Range
VDDIO/VTTL
VCORE
DC Voltage Applied to
Commercial 0°C to +70°C 3.3V±165 mV 1.8V±100 mV
Outputs in High-Z State .......................... –0.5V to VDD +0.5V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[26]
Industrial
–40°C to +85°C 3.3V±165 mV 1.8V±100 mV
Electrical Characteristics Over the Operating Range
-167
-133
-100
Parameter
Description
Unit
Min Typ. Max Min Typ. Max Min Typ. Max
VOH
VOL
VIH
VIL
Output HIGH Voltage (VDD = Min, IOH= –4.0 mA)
Output LOW Voltage (VDD = Min, IOL= +4.0 mA)
Input HIGH Voltage
2.4
2.4
2.4
V
V
V
V
0.4
0.4
0.4
2.0
2.0
2.0
Input LOW Voltage
0.8
0.8
10
10
0.8
IOZ
IIX1
IIX2
ICC
Output Leakage Current
–10
–10
–1.0
10 –10
10 –10
0.1 –1.0
–10
–10
10 μA
10 μA
0.1 mA
mA
Input Leakage Current Except TDI, TMS, MRST
Input Leakage Current TDI, TMS, MRST
0.1 –1.0
225 300
Operating Current for
CYD01S36V
225 300
(VDD = Max.,IOUT = 0 mA), Outputs CYD02S36V/
Disabled
CYD04S36V
CYD09S36V
CYD18S36V
mA
450 600
370 540
410 580
mA
mA
315 450
[27]
ISB1
Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
90 115
160 210
90
160 210
55 75
115
[27]
ISB2
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
mA
mA
mA
[27]
ISB3
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
55
75
[27]
ISB4
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
160 210
160 210
75
ISB5
Operating Current (VDDIO = Max, CYD18S36V
Iout = 0 mA, f = 0) Outputs Disabled
75 mA
mA
[13]
ICORE
Core Operating Current for (VDD = Max, IOUT = 0
mA), Outputs Disabled
0
0
0
0
0
0
Capacitance
Part Number
Parameter[28]
CIN
Description
Test Conditions
Max
Unit
CYD01S36/
CYD02S36V/
CYD04S36V
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
13
pF
COUT
CIN
Output Capacitance
Input Capacitance
Output Capacitance
10
22
10[29]
pF
pF
pF
CYD09S36V
COUT
Notes
25. The voltage on any input or IO pin cannot exceed the power pin during power up.
26. Pulse width < 20 ns.
27. I
, I
, I
and I
are not applicable for CYD18S36V because it cannot be powered down by using chip enable pins.
SB1 SB2 SB3
SB4
28. C
also references C .
OUT
IO
29. Except INT and CNTINT which are 20 pF.
Document Number: 38-06076 Rev. *F
Page 12 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Capacitance (continued)
Part Number
CYD18S36V
Parameter[28]
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
40
Unit
pF
CIN
COUT
20
pF
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590 Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435 Ω
VTH = 1.5V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
-133
-100
CYD18S36V
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
CYD01S36V
CYD02S36V
CYD18S36V
CYD04S36V
Parameter
Description
Unit
CYD09S36V
Min
Max
Min
Max
Min
Max
Min
Max
fMAX2
tCYC2
tCH2
Maximum Operating Frequency
Clock Cycle Time
167
133
133
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.4
3.4
10.0
4.5
Clock HIGH Time
tCL2
Clock LOW Time
4.5
[30]
tR
Clock Rise Time
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
[30]
tF
Clock Fall Time
tSA
Address Setup Time
Address Hold Time
Byte Select Setup Time
Byte Select Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.2
1.0
2.2
1.0
NA
NA
2.2
1.0
2.2
1.0
NA
NA
NA
NA
2.7
1.0
2.7
1.0
NA
NA
2.7
1.0
2.7
1.0
NA
NA
NA
NA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
tHCN
Note
30. Except JTAG signals (t and t < 10 ns [max.]).
r
f
Document Number: 38-06076 Rev. *F
Page 13 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Characteristics Over the Operating Range (continued)
-167
-133
CYD01S36V
-100
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
CYD02S36V
Parameter
Description
CYD18S36V
CYD18S36V
Unit
CYD04S36V
CYD09S36V
Min
2.3
0.6
2.3
0.6
Max
Min
2.5
0.6
2.5
0.6
Max
Min
NA
NA
NA
NA
Max
Min
NA
NA
NA
NA
Max
tSRST
tHRST
tSCM
tHCM
tOE
CNTRST Setup Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNTRST Hold Time
CNT/MSK Setup Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
4.4
4.4
5.5
5.5
[31, 32]
tOLZ
0
0
0
0
0
0
0
0
[31, 32]
tOHZ
OE to High Z
4.0
4.4
4.0
4.0
4.4
4.4
4.4
4.4
5.5
5.0
NA
NA
5.5
5.2
NA
NA
tCD2
tCA2
tCM2
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback
Valid
tDC
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
1.0
0
1.0
0
1.0
0
1.0
0
ns
ns
ns
ns
ns
ns
ns
[31, 32]
tCKHZ
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
[31, 32]
tCKLZ
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
tSINT
10.0
10.0
NA
tRINT
Clock to INT Reset Time
tSCINT
tRCINT
Clock to CNTINT Set Time
Clock to CNTINT Reset time
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
5.7
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
5.0
6.0
5.0
5.0
6.0
5.0
5.0
6.0
5.0
5.0
8.5
5.0
cycles
ns
tRS
Master Reset Setup Time
tRSR
tRSF
tRSINT
Master Reset Recovery Time
Master Reset to Outputs Inactive
cycles
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
ns
JTAG Timing
167/133/100
Parameter
Description
Unit
Min
Max
10
fJTAG
tTCYC
tTH
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
MHz
ns
100
40
40
TCK Clock HIGH Time
ns
tTL
TCK Clock LOW Time
ns
tTMSS
TMS Setup to TCK Clock Rise
TMS Hold After TCK Clock Rise
10
ns
tTMSH
10
ns
Notes
31. This parameter is guaranteed by design, but it is not production tested.
32. Test conditions used are Load 2.
Document Number: 38-06076 Rev. *F
Page 14 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
JTAG Timing (continued)
167/133/100
Unit
Parameter
Description
Min
10
Max
tTDIS
TDI Setup to TCK Clock Rise
TDI Hold After TCK Clock Rise
ns
ns
ns
ns
tTDIH
tTDOV
tTDOX
10
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
30
0
JTAG Switching Waveform
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Switching Waveforms
Figure 6. Master Reset
tRS
MRST
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
tRSINT
CNTINT
INT
TDO
Document Number: 38-06076 Rev. *F
Page 15 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 7. Read Cycle[14, 33, 34, 35, 36]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE3
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes
33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
34. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
35. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
36. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document Number: 38-06076 Rev. *F
Page 16 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 8. Bank Select Read[37, 38]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Figure 9. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+2
tSD tHD
Dn+2
An+3
ADDRESS
DATAIN
tSA
tHA
tCD2
tDC
tCKHZ
Qn
DATAOUT
READ
NO OPERATION
WRITE
Notes
37. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
38. ADS = CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
39. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
40. During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
41. CE = OE = BE0 – BE3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
42. CE = BE0 – BE3 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
0
1
(labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Document Number: 38-06076 Rev. *F
Page 17 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 10. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Figure 11. Read with Address Counter Advance[41]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document Number: 38-06076 Rev. *F
Page 18 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 12. Write with Address Counter Advance [42]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Document Number: 38-06076 Rev. *F
Page 19 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 13. Counter Reset [43, 44]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
tSD
DATAIN
D0
tCD2
tCD2
[45]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS An
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS Am
Notes
43. CE = BE0 – BE3 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
44. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
45. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value
Document Number: 38-06076 Rev. *F
Page 20 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 14. Readback State of Address Counter or Mask Register[46, 47, 48, 49]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
EXTERNAL
ADDRESS
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Notes
46. CE = OE = BE0 – BE3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
47. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
48. Address in input mode. Host can drive address bus after t
.
CKHZ
49. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document Number: 38-06076 Rev. *F
Page 21 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 15. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52]
tCYC2
tCL2
tCH2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
ADDRESS
An
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes
50. CE = OE = ADS = CNTEN = BE0 – BE3 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
51. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data is Read out.
CCS
52. If t
< minimum specified value, then R_Port Reads the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If t
>
CCS
CYC2
CD2
CCS
minimum specified value, then R_Port Reads the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CYC2
CD2
Document Number: 38-06076 Rev. *F
Page 22 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 16. Counter Interrupt and Retransmit[17, 45, 53, 54, 55, 56]
tCYC2
tCL2
tCH2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFE
tSCINT
3FFFC
Last_Loaded
3FFFD
3FFFF
tRCINT
Last_Loaded +1
CNTINT
Notes
53. CE = OE = BE0 – BE3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
54. CNTINT is always driven.
55. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
56. The mask register assumed to have the value of 3FFFFh.
Document Number: 38-06076 Rev. *F
Page 23 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms (continued)
Figure 17. MailBox Interrupt Timing[57, 58, 59, 60, 61]
tCYC2
tCL2
tCH2
CLKL
tSA tHA
7FFFF
L_PORT
ADDRESS
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
ADDRESS
Am+1
7FFFF
Am+3
Am+4
Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 62, 63, 64]
Inputs
Outputs
DQ0 – DQ35
High-Z
Operation
OE
CLK
CE0
CE1
R/W
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes
57. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
58. Address “7FFFF” is the mailbox location for R_Port of the 9-Mbit device.
59. L_Port is configured for Write operation, and R_Port is configured for Read operation.
60. At least one byte enable (BE0 – BE3) is required to be active during interrupt operations.
61. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
62. OE is an asynchronous input signal.
63. When CE changes state, deselection and Read happen after one cycle of latency.
64. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document Number: 38-06076 Rev. *F
Page 24 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Ordering Information
512K
×
36 (18-Mbit) 3.3V Synchronous CYD18S36V Dual-Port SRAM
Package
Speed(
MHz)
Operating
Range
Ordering Code
Package Type
Name
133 CYD18S36V-133BBC
CYD18S36V-133BBI
BB256B
BB256B
BB256B
BB256B
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Industrial
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Industrial
100 CYD18S36V-100BBC
CYD18S36V-100BBI
256K
×
36 (9-Mbit) 3.3V Synchronous CYD09S36V Dual-Port SRAM
Package
Speed(
MHz)
Operating
Range
Ordering Code
Package Type
Name
BB256
BB256
BB256
167 CYD09S36V-167BBC
133 CYD09S36V-133BBC
CYD09S36V-133BBI
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
128K
×
36 (4-Mbit) 3.3V Synchronous CYD04S36V Dual-Port SRAM
Package
Speed(
MHz)
Operating
Range
Ordering Code
Package Type
Name
BB256
BB256
BB256
167 CYD04S36V-167BBC
133 CYD04S36V-133BBC
CYD04S36V-133BBI
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
64K
× 36 (2-Mbit) 3.3V Synchronous CYD02S36V Dual-Port SRAM
Speed(
MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
167 CYD02S36V-167BBC
133 CYD02S36V-133BBC
CYD02S36V-133BBI
BB256
BB256
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
32K
× 36 (1-Mbit) 3.3V Synchronous CYD01S36V Dual-Port SRAM
Speed(
MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
167 CYD01S36V-167BBC
133 CYD01S36V-133BBC
CYD01S36V-133BBI
BB256
BB256
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
Document Number: 38-06076 Rev. *F
Page 25 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Package Diagrams
Figure 18. 256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES
ꢀ0.05
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.70 MAX.
A
51-85108-*F
Document Number: 38-06076 Rev. *F
Page 26 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Package Diagrams (continued)
Figure 19. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
+0.10
Ø0.50 (256X)
ꢀ0.05
PIN 1 CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
23.00 0.10
0.20(4X)
SEATING PꢁANE
JEDEC MOꢀ192
51-85201-*A
C
Document Number: 38-06076 Rev. *F
Page 27 of 28
[+] Feedback
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document History Page
Document Title: CYD01S36V CYD02S36V/CYD04S36V CYD09S36V/CYD18S36V FLEx36™ 3.3V 32K/64K/128K/256K/512 x
36 Synchronous Dual-Port RAM
Document Number: 38-06076
Orig. of
Change
REV.
ECN NO.
Description of Change
**
232012
244232
WWZ
New data sheet
Changed pinout
*A
WWZ
Changed FTSEL# to FTSEL in the block diagram
*B
313156
YDT
Changed pinout D10 from NC to VSS to reflect test mode pin swap, C10 from rev[2,4] to VSS
to reflect SC removal.
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added CYD01S36V to data sheet
Added ISB5 and changed IIX2
*C
*D
321033
327338
YDT
AEQ
Added CYD18S36V-133BBI to the Ordering Information Section
Change Pinout C10 from VSS to NC[2,5]
Change Pinout G5 from VDDIOL to REVL[2,3]
*E
*F
365315
YDT
Added note for VCORE
Removed preliminary status
2193427
NXR/AESA Changed tCD2 and tOE Spec from 4ns to 4.4ns for -167.
Template Update.
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06076 Rev. *F
Revised March 12, 2008
Page 28 of 28
FLEx36 and FLEx36-E are trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products
and company names mentioned in this document may be the trademarks of their respective holders.
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